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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
ICS557-03  
Description  
Features  
The ICS557-03 is a spread spectrum clock generator that  
supports PCI-Express Gen 1 and Ethernet requirements.  
The device is used for PC or embedded systems to  
substantially reduce electromagnetic interference (EMI).  
The device provides two differential (HCSL) spread  
spectrum outputs. The spread type and amount are  
configured via select pin. Using IDT’s patented  
Phase-Locked Loop (PLL) techniques, the device takes a  
25 MHz crystal input and produces two pairs of differential  
outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock  
frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.  
• Packaged in 16-pin TSSOP  
• RoHS 5 (green) or RoHS 6 (green and lead free)  
compliant packaging  
• Supports HCSL or LVDS output levels  
• Operating voltage of 3.3 V  
• Input frequency of 25 MHz  
• Jitter 60 ps (cycle-to-cycle)  
• Spread Spectrum capability  
• Industrial and commercial temperature ranges  
• For PCIe Gen2 applications, see the 5V41065  
• For PCIe Gen3 applications, see the 5V41235  
Block Diagram  
VDD  
2
SS1:SS0  
2
CLK0  
CLK0  
Control  
Logic  
S1:S0  
2
Phase Lock Loop  
CLK1  
CLK1  
X1/ICLK  
Clock  
Buffer/  
25 MHz  
Crystal  
crystal or clock  
Oscillator  
X2  
2
GND  
Optional tuning crystal  
capacitors  
Rr(IREF)  
OE  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
1
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
Output Select Table 1 (MHz)  
Pin Assignment  
S1  
0
S0  
0
CLK(1:0), CLK(1:0)  
1
2
3
4
5
6
7
8
VDDXD  
CLK0  
16  
15  
14  
13  
12  
11  
10  
9
S0  
S1  
25M  
100M  
125M  
200M  
0
1
SS0  
X1/ICLK  
X2  
CLK0  
1
0
1
1
GNDODA  
VDDODA  
CLK1  
Spread Selection Table 2  
OE  
SS1 SS0  
Spread%  
No Spread  
Down -0.5  
Down -0.75  
No Spread  
GNDXD  
SS1  
CLK1  
IREF  
0
0
1
1
0
1
0
1
16-pin (173 mil) TSSOP  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin  
Type  
Pin Description  
1
2
3
4
5
6
S0  
S1  
Input Select pin 0. See Table1. Internal pull-up resistor.  
Input Select pin 1. See Table 1. Internal pull-up resistor.  
Input Spread Select pin 0. See Table 2. Internal pull-up resistor.  
SS0  
X1/ICLK  
X2  
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.  
Output Crystal connection. Leave unconnected for clock input.  
OE  
Input Output enable. Tri-states outputs and device is not shut down. Internal  
pull-up resistor.  
7
8
9
GNDXD  
SS1  
Power Connect to ground.  
Input Spread Select pin 1. See Table 2. Internal pull-up resistor.  
IREF  
Output Precision resistor attached to this pin is connected to the internal current  
reference.  
10  
11  
12  
13  
14  
15  
16  
CLK1  
CLK1  
Output HCSL complimentary clock output 1.  
Output HCSL true clock output 1.  
VDDODA  
GNDODA  
CLK0  
Power Connect to voltage supply +3.3 V for output driver and analog circuits  
Power Connect to ground.  
Output HCSL complimentary clock output 0.  
Output HCSL true clock output 0.  
CLK0  
VDDXD  
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
2
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
Applications Information  
External Components  
A minimum number of external components are required for  
proper operation.  
Output Structures  
6*IREF  
IREF  
=2.3 mA  
Decoupling Capacitors  
Decoupling capacitors of 0.01 μF should be connected  
between each VDD pin and the ground plane, as close to  
the VDD pin as possible. Do not share ground vias between  
components. Route power from power source through the  
capacitor pad and then into ICS pin.  
Crystal  
See Output Termination  
Sections - Pages 3 ~ 5  
A 25 MHz fundamental mode parallel resonant crystal  
should be used. This crystal must have less than 300 ppm  
of error across temperature in order for the ICS557-03 to  
meet PCI Express specifications.  
RR 475  
Ω
General PCB Layout Recommendations  
Crystal Capacitors  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
Crystal capacitors are connected from pins X1 to ground  
and X2 to ground to optimize the accuracy of the output  
frequency.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
C = Crystal’s load capacitance in pF  
L
Crystal Capacitors (pF) = (C - 8) * 2  
L
2. No vias should be used between decoupling capacitor  
and VDD pin.  
For example, for a crystal with a 16 pF load cap, each  
external crystal cap would be 16 pF. (16-8)*2=16.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
Current Source (Iref) Reference Resistor - R  
R
If board target trace impedance (Z) is 50Ω, then R = 475Ω  
(1%), providing IREF of 2.32 mA. The output current (I ) is  
R
OH  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the ICS557-03.This includes signal traces  
just underneath the device, or on layers adjacent to the  
ground plane layer used by the device.  
equal to 6*IREF.  
Output Termination  
The PCI-Express differential clock outputs of the ICS557-03  
are open source drivers and require an external series  
resistor and a resistor to ground. These resistor values and  
their allowable locations are shown in detail in the  
PCI-Express Layout Guidelines section.  
The ICS557-03 can also be configured for LVDS compatible  
voltage levels. See the LVDS Compatible Layout  
Guidelines section.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
3
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
PCI-Express Layout Guidelines  
Common Recommendations for Differential Routing  
Dimension or Value Unit  
L1 length, Route as non-coupled 50 ohm trace.  
L2 length, Route as non-coupled 50 ohm trace.  
L3 length, Route as non-coupled 50 ohm trace.  
RS  
RT  
0.5 max  
0.2 max  
0.2 max  
33  
inch  
inch  
inch  
ohm  
ohm  
49.9  
Differential Routing on a Single PCB  
Dimension or Value Unit  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
Differential Routing to a PCI Express Connector  
L4 length, Route as coupled microstrip 100 ohm differential trace.  
L4 length, Route as coupled stripline 100 ohm differential trace.  
Dimension or Value Unit  
0.25 to 14 max inch  
0.225 min to 12.6 max inch  
PCI-Express Device Routing  
L1  
L2  
L4  
RS  
RS  
L4’  
L1’  
L2’  
RT  
RT  
PCI-Express  
Load or  
Connector  
ICS557-03  
Output  
L3’ L3  
Clock  
Typical PCI-Express (HCSL) Waveform  
700 mV  
0
500 ps  
500 ps  
tOR  
tOF  
0.525 V  
0.175 V  
0.525 V  
0.175 V  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
4
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
LVDS Compatible Layout Guidelines  
Alternative Termination for LVDS and other Common Differential Signals  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
LVDS Device Routing  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Typical LVDS Waveform  
1325 mV  
1000 mV  
500 ps  
500 ps  
tOR  
tOF  
1250 mV  
1150 mV  
1250 mV  
1150 mV  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
5
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress  
ratings only. Functional operation of the device at these or any other conditions above those indicated in the  
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for  
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
Item  
Supply Voltage, VDDXD, VDDODA  
All Inputs and Outputs  
Rating  
7 V  
-0.5 V to VDD+0.5 V  
0 to +70° C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
Storage Temperature  
-40 to +85° C  
-65 to +150° C  
125°C  
Junction Temperature  
Soldering Temperature  
260°C  
ESD Protection (Input)  
2000 V min. (HBM)  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C  
Parameter  
Symbo  
l
Conditions  
Min.  
Typ.  
Max.  
Units  
Supply Voltage  
Input High Voltage  
V
2.97  
2.0  
3.3  
3.63  
V
V
1
V
S0, S1, OE, ICLK, SS0, SS1  
S0, S1, OE, ICLK, SS0, SS1  
0 < Vin < VDD  
VDD +0.3  
IH  
1
Input Low Voltage  
Input Leakage Current  
V
I
VSS-0.3  
-5  
0.8  
5
V
IL  
2
μA  
mA  
mA  
pF  
pF  
nH  
kΩ  
kΩ  
IL  
Operating Supply Current  
I
50Ω, 2 pF  
OE =Low  
78  
44  
7
DD  
I
DDOE  
Input Capacitance  
Output Capacitance  
Pin Inductance  
C
Input pin capacitance  
Output pin capacitance  
IN  
C
6
OUT  
L
5
PIN  
Output Resistance  
Pull-up Resistor  
R
CLK outputs  
3.0  
OUT  
R
S0, S1, OE, SS0, SS1  
100  
PU  
1. Single edge is monotonic when transitioning through region.  
2. Inputs with pull-ups/-downs are not included.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
6
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
AC Electrical Characteristics - CLKOUT, HCSL  
Unless stated otherwise, VDD=3.3 V 10%, Ambient Temperature -40 to +85° C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
mV  
Output Frequency  
Output High Voltage  
HCSL termination  
200  
850  
27  
1,2  
1,2  
V
660  
-150  
250  
700  
0
OH  
Output Low Voltage  
Crossing Point  
V
mV  
OL  
Absolute  
350  
550  
mV  
1,2  
Voltage  
Crossing Point  
Voltage  
Variation over all edges  
140  
mV  
1,2,4  
1,3  
Jitter, Cycle-to-Cycle  
80  
33  
ps  
kHz  
ps  
Modulation Frequency  
Spread spectrum  
30  
31.5  
332  
344  
1,2  
Rise Time  
t
From 0.175 V to 0.525 V  
From 0.525 V to 0.175 V  
At crossing point Voltage  
175  
175  
700  
700  
50  
OR  
1,2  
Fall Time  
t
ps  
OF  
Skew between outputs  
ps  
1,3  
Duty Cycle  
45  
55  
%
5
Output Enable Time  
All outputs  
12  
us  
5
Output Disable Time  
All outputs  
12  
us  
Power-up Time  
t
From power-up VDD=3.3 V  
Settling period after spread change  
3.0  
3.0  
3.5  
3.5  
ms  
ms  
STABLE  
Spread Change Time  
t
SPREAD  
1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).  
2 Measurement taken from a single-ended waveform.  
3 Measurement taken from a differential waveform.  
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.  
5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
7
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
AC Electrical Characteristics - CLKOUT, LVDS  
Unless stated otherwise, VDD=3.3 V 10%, Ambient Temperature -40 to +85° C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
mV  
Output Frequency  
Differential Output Voltage  
Offset Voltage  
LVDS termination  
100  
454  
V
247  
OD  
V
1.125  
1.375  
50  
V
OS  
∆V  
mV  
|Change to V |  
OD  
OD  
∆V  
50  
mV  
|Change to V |  
OS  
OS  
1,3  
Jitter, Cycle-to-Cycle  
80  
33  
4
ps  
Modulation Frequency  
Spread spectrum  
30  
1
31.5  
kHz  
V/ns  
1,3  
Slew Rate, Rise  
t
Measured from 150 mV from  
crossing point voltage  
SLR  
1,3  
Slew Rate, Fall  
t
Measured from 150 mV from  
crossing point voltage  
1
4
V/ns  
SLF  
Skew between outputs  
At crossing point Voltage  
50  
55  
ps  
%
1,3  
Duty Cycle  
45  
5
Output Enable Time  
All outputs  
12  
µs  
µs  
ms  
ms  
5
Output Disable Time  
All outputs  
12  
Power-up Time  
t
From power-up VDD=3.3 V  
Settling period after spread change  
3
3
3.5  
3.5  
STABLE  
Spread Change Time  
t
SPREAD  
1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).  
2 Measurement taken from a single-ended waveform.  
3 Measurement taken from a differential waveform.  
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.  
5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.  
Electrical Characteristics - Differential Phase Jitter  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Notes  
Jitter, Phase  
tjphasePLL  
PCIe Gen 1  
-
-
86  
ps (p-p)  
1, 2  
Note 1: Guaranteed by design and characterization, not 100% tested in production.  
Note 2: See http://www.pcisig.com for complete specs.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
8
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
Still air  
1 m/s air flow  
3 m/s air flow  
78  
70  
68  
37  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
θ
θ
JA  
JA  
Thermal Resistance Junction to Case  
θ
JC  
Marking Diagram (ICS557G-03LF)  
Marking Diagram (ICS557GI-03LF)  
16  
9
16  
9
557GI03L  
######  
YYWW  
557G03LF  
######  
YYWW  
1
8
1
8
Notes:  
1. ###### is the lot code.  
2. YYWW is the last two digits of the year, and the week number that the part was assembled.  
3. “LF” designates Pb (lead) free package.  
4. “I” designates industrial temperature range.  
5. Bottom marking: (origin). Origin = country of origin of not USA.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
9
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches*  
16  
Symbol  
Min  
--  
Max  
1.20  
0.15  
1.05  
0.30  
0.20  
5.1  
Min  
--  
0.002  
0.032  
0.007  
Max  
0.047  
0.006  
0.041  
0.012  
A
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
4.90  
E1  
E
INDEX  
AREA  
C
D
E
0.0035 0.008  
0.193 0.201  
0.252 BASIC  
0.169 0.177  
0.0256 Basic  
6.40 BASIC  
1
2
E1  
e
4.30  
0.65 Basic  
4.50  
D
L
0.45  
0.75  
0.018  
0.030  
a
0°  
8°  
0°  
8°  
aaa  
--  
0.10  
--  
0.004  
A
A2  
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
aaa C  
Ordering Information  
Part / Order Number  
Marking  
See Page 8  
Shipping Packaging  
Tubes  
Package  
Temperature  
0 to +70° C  
0 to +70° C  
-40 to +85° C  
-40 to +85° C  
557G-03LF  
557G-03LFT  
557GI-03LF  
557GI-03LFT  
16-pin TSSOP  
16-pin TSSOP  
16-pin TSSOP  
16-pin TSSOP  
Tape and Reel  
Tubes  
See Page 8  
Tape and Reel  
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
10  
ICS557-03  
REV U 112111  
ICS557-03  
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE  
PCIE SSCG  
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