5V41065--Datasheet/数据表在线中文翻译

DATASHEET

2 OUTPUT PCIE GEN1/2 SYNTHESIZER

IDT5V41065

Recommended Applications

Features/Benefits

2 Output synthesizer for PCIe Gen1/2 and Ethernet

• 16-pin TSSOP and QFN packages; small board footprint

• Spread-spectrum capable; reduces EMI

General Description

• Outputs can be terminated to LVDS; can drive a wider

variety of devices

The IDT5V41065 is a PCIe Gen2 compliant spread

spectrum capable clock generator. The device has 2

differential HCSL outputs and can be used in

• 25 MHz, 125 MHz and 200 MHz output frequencies;

TSSOP only

communication or embedded systems to substantially

reduce electro-magnetic interference (EMI). The spread

amount and output frequency are selectable via select pins.

The IDT5V41065 can also supply 25 MHz, 125 MHz and

200 MHz outputs for applications such as Ethernet.

• 100MHz and 200MHz output frequencies; VFQFPN

package

• OE control pin; greater system power management

• Spread% and frequency pin selection; no software

required to configure device

• Industrial temperature range available; supports

demanding embedded applications

Output Features

• 2 - 0.7V current mode differential HCSL output pairs

• For PCIe Gen3 applications, see the 5V41235

Key Specifications

• Cycle-to-cycle jitter < 100 ps

• Output-to-output skew < 50 ps

• PCIe Gen2 phase jitter < 3.0ps RMS

Block Diagram

VDD

SS1:SS0

S1:S0

CLK0

Control

Logic

Phase Lock Loop

CLK1

X1/ICLK

Clock

Buffer/

Crystal

Oscillator

25 MHz

crystal or clock

GND

Optional tuning crystal

capacitors

Rr(IREF)

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Pin Assignment

VDDXD

CLK0

16 15 14 13

SS0

X1/ICLK

CLK0

SS0

X1/CLK 3

X2 4

12 GNDODA

11 VDDODA

10 CLK1

GNDODA

VDDODA

CLK1

5V41065

CLK1#

GNDXD

SS1

CLK1

IREF

16-pin VFQFPN

16-pin (173 mil) TSSOP

Output Select Table 1 (MHz)–TSSOP only

Output/Spread Select Table 3 - VFQFPN Only

SS1 SS0

Output

100MHz

200MHz

100MHz

Spread%

-0.5

CLK(1:0), CLK(1:0)

25M

100M

125M

200M

-0.5

No spread

Reserved

100MHz

200MHz

-1

Spread Selection Table 2–TSSOP only

Reserved

SS1 SS0

Spread%

No Spread

Down -0.5

Down -0.75

No Spread

100MHz

200MHz

-1.5

Reserved

200MHz

No spread

Reserved

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Pin Descriptions

VFQFPN TSSOP

Pin Pin

Number Number

Name

Type

Pin Description

Input Select pin 0. See Table1. Internal pull-up resistor.

Input Select pin 1. See Table 1. Internal pull-up resistor.

SS0

X1/ICLK

Input Spread Select pin 0. See Table 2. Internal pull-up resistor.

Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.

Output Crystal connection. Leave unconnected for clock input.

Input Output enable. Tri-states outputs and device is not shut down. Internal

pull-up resistor.

GNDXD

SS1

Power Connect to ground.

Input Spread Select pin 1. See Table 2. Internal pull-up resistor.

IREF

Output Precision resistor attached to this pin is connected to the internal current

reference.

CLK1

Output HCSL complementary clock output 1.

Output HCSL true clock output 1.

VDDODA

GNDODA

CLK0

Power Connect to voltage supply +3.3 V for output driver and analog circuits

Power Connect to ground.

Output HCSL complementary clock output 0.

Output HCSL true clock output 0.

CLK0

VDDXD

Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.

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Applications Information

External Components

A minimum number of external components are required for

proper operation.

Output Structures

6*IREF

IREF

=2.3 mA

Decoupling Capacitors

Decoupling capacitors of 0.01F should be connected

between each VDD pin and the ground plane, as close to

the VDD pin as possible. Do not share ground vias between

components. Route power from power source through the

capacitor pad and then into ICS pin.

Crystal

See Output Termination

Sections - Pages 3 ~ 5

A 25 MHz fundamental mode parallel resonant crystal

should be used. This crystal must have less than 300 ppm

of error across temperature in order for the IDT5V41065 to

meet PCI Express specifications.

R_R475



General PCB Layout Recommendations

Crystal Capacitors

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Crystal capacitors are connected from pins X1 to ground

and X2 to ground to optimize the accuracy of the output

frequency.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

C = Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (C - 8) * 2

2. No vias should be used between decoupling capacitor

and VDD pin.

For example, for a crystal with a 16 pF load cap, each

external crystal cap would be 16 pF. (16-8)*2=16.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

Current Source (Iref) Reference Resistor - R

If board target trace impedance (Z) is 50, then R = 475

(1%), providing IREF of 2.32 mA. The output current (I ) is

equal to 6*IREF.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the IDT5V41065.This includes signal

traces just underneath the device, or on layers adjacent to

the ground plane layer used by the device.

Output Termination

The PCI-Express differential clock outputs of the

IDT5V41065 are open source drivers and require an

external series resistor and a resistor to ground. These

resistor values and their allowable locations are shown in

detail in the PCI-Express Layout Guidelines section.

The IDT5V41065 can also be configured for LVDS

compatible voltage levels. See the LVDS Compatible

Layout Guidelines section.

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Layout Guidelines

SRC Reference Clock

Common Recommendations for Differential Routing

L1 length, route as non-coupled 50ohm trace

L2 length, route as non-coupled 50ohm trace

L3 length, route as non-coupled 50ohm trace

Dimension or Value

0.5 max

0.2 max

Unit Figure

inch

ohm

49.9

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

2 min to 16 max

1.8 min to 14.4 max

inch

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

0.25 to 14 max

0.225 min to 12.6 max

inch

Figure 1: Down Device Routing

L4'

L2'

L1'

HCSL Output Buffer

PCI Express

Down Device

REF_CLK Input

L3' L3

Figure 2: PCI Express Connector Routing

L4'

L2'

L1'

HCSL Output Buffer

PCI Express

Add-in Board

REF_CLK Input

L3' L3

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Alternative Termination for LVDS and other Common Differential Signals (figure 3)

Vdiff

0.45v

0.58

0.80

0.60

Vp-p

0.22v

0.28

0.40

0.3

Vcm

1.08

0.6

1.2

Note

150

78.7

174

100

137

none

140

100

ICS874003i-02 input compatible

Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Figure 3

R1a

R1b

L4'

L2'

L1'

R2a

R2b

HCSL Output Buffer

Down Device

REF_CLK Input

L3'

Cable Connected AC Coupled Application (figure 4)

Component

Value

Note

R5a, R5b

R6a, R6b

8.2K 5%

1K 5%

0.1 µF

Vcm

0.350 volts

Figure 4

3.3 Volts

R5a

R5b

L4'

R6a

R6b

PCIe Device

REF_CLK Input

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Typical PCI-Express (HCSL) Waveform

700 mV

500 ps

t_OR

t_OF

0.525 V

0.175 V

0.525 V

0.175 V

Typical LVDS Waveform

1325 mV

1000 mV

500 ps

t_OR

t_OF

1250 mV

1150 mV

1250 mV

1150 mV

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Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the IDT5V41065. These ratings are stress ratings

only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of

the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product

reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Item

Supply Voltage, VDDXD, VDDODA

All Inputs and Outputs

Rating

4.6 V

-0.5 V to VDD+0.5 V

0 to +70C

Ambient Operating Temperature (commercial)

Ambient Operating Temperature (industrial)

Storage Temperature

-40 to +85C

-65 to +150C

125C

Junction Temperature

Soldering Temperature

260C

ESD Protection (Input)

2000 V min. (HBM)

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C

Parameter

Symbol

Conditions

Min.

3.135

2.2

Typ.

3.3

Max.

3.465

Units

Supply Voltage

Input High Voltage

S0, S1, OE, ICLK, SS0, SS1

0 < Vin < VDD

VDD +0.3

Input Low Voltage

VSS-0.3

-5

0.8

Input Leakage Current

A

k

Operating Supply Current

@100 MHz

R =33R =50, C =2 pF

OE =Low

DDOE

Input Capacitance

Output Capacitance

X1, X2 Capacitance

Pin Inductance

Input pin capacitance

Output pin capacitance

OUT

INX

Output Impedance

Pull-up Resistor

CLK outputs

3.0

S0, S1, OE, SS0, SS1

100

1. Single edge is monotonic when transitioning through region.

2. Inputs with pull-ups/-downs are not included.

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AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1

Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85C

Parameter

Input Frequency

Symbol

Conditions

Min.

Typ.

Max.

Units

MHz

Output Frequency

HCSL termination

200

100

850

LVDS termination

HCSL

1,2

Output High Voltage

1,2

Output Low Voltage

HCSL

-150

250

1,2

Crossing Point Voltage

Absolute

550

140

100

1,2,4

Variation over all edges

1,3

Jitter, Cycle-to-Cycle

Frequency Synthesis Error

Modulation Frequency

All outputs

ppm

kHz

Spread spectrum

32.9

700

125

1,2

Rise Time

From 0.175 V to 0.525 V

From 0.525 V to 0.175 V

175

1,2

Fall Time

1,2

Rise/Fall Time Variation

Output to Output Skew

1,3

Duty Cycle

Output Enable Time

All outputs

100

1.8

Output Disable Time

All outputs

Stabilization Time

From power-up VDD=3.3 V

STABLE

Spread Spectrum Transition

Time

Stabilization time after spread

spectrum changes

SPREAD

Note 1: Test setup is R =33R =50 with C =2 pF, Rr = 475 (1%).

Note 2: Measurement taken from a single-ended waveform.

Note 3: Measurement taken from a differential waveform.

Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.

Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.

Electrical Characteristics - Differential Phase Jitter

Parameter

Symbol

Conditions

Min Typ Max

Units

Notes

1,2,3

PCIe Gen1

0.8

2.3

ps (p-p)

jphasePLL

Jitter, Phase

PCIe Gen2, 10 kHz < f < 1.5 MHz

ps (RMS)

jphaseLO

PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)

3.1

jphaseHIGH

Note 1. Guaranteed by design and characterization, not 100% tested in production.

Note 2. See http://www.pcisig.com for complete specs.

Note 3: Applies to 100MHz, spread off and 0.5% down spread only.

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Thermal Characteristics (16TSSOP)

Parameter

Thermal Resistance Junction to

Ambient

Symbol

Conditions

Min.

Typ. Max. Units



Still air

1 m/s air flow

3 m/s air flow

C/W

Thermal Resistance Junction to Case

Thermal Characteristics(16VFQFPN)

Parameter

Symbol

Conditions

Typ. Max. Units

Thermal Resistance Junction to

Ambient



Still air

63.2

55.9

51.4

65.8

C/W

1 m/s air flow

3 m/s air flow

Thermal Resistance Junction to Case

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Marking Diagram (5V41065PGG)

Marking Diagram (5V41065PGGI)

IDT5V410

65PGGI

YYWW$

IDT5V410

65PGG

YYWW$

Notes:

1. Line 1 and 2: IDT part number.

2. Line 3: YYWW – Date code; $ – Assembly location.

3. “G” after the two-letter package code designates RoHS compliant package.

4. “I” at the end of part number indicates industrial temperature range.

5. Bottom marking: country of origin if not USA.

Marking Diagram (5V41065NLGI)

XXX

YWW$

065G

XXX

YWW$

065GI

Notes:

1. Line 1: Lot number.

2. Line 2: YWW – Date code; $ – Assembly location.

3. “G” designates RoHS compliant package.

4. “I” at the end of part number indicates industrial temperature range.

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Ordering Information

Part / Order Number

5V41065PGG

Marking

See Page 11

Shipping Packaging

Tubes

Package

16-pin TSSOP

16-pin QFN

Temperature

0 to +70 C

5V41065PGG8

5V41065PGGI

5V41065PGGI8

5V41065NLG

Tape and Reel

Tubes

0 to +70 C

-40 to +85 C

0 to +70 C

Tape and Reel

Trays

See Page 11

5V41065NLG8

5V41065NLGI

Tape and Reel

Trays

16-pin QFN

0 to +70 C

16-pin QFN

-40 to +85 C

5V41065NLGI8

Tape and Reel

16-pin QFN

“G” after the two-letter package code are the Pb-Free configuration, RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes

no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT

does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Revision History

Rev. Originator

Date

Description of Change

07/15/08 New datasheet; Preliminary initial release.

RDW

01/13/10 Added Gen2 to title; update Electrical tables per char; added Differential Phase Jitter table.

04/27/10 Updated electrical tables per char; VDD is now 3.3 5%; released to final.

07/19/10 1. Updated title and general description

2. Updated cycle-to-cycle jitter spec from 125 to 100 ps.

RDW

11/21/11 1. Changed title to “2 Output PCIe GEN1/2 Synthesizer”

2. Added note to Features section: “For PCIe Gen3 applications, see 5V41235”

3. Updated Differential Phase Jitter table.

J, Chao

08/26/13 1. Added 16VFQFPN notes in Features section

2. Added pinout and “Output/Spread Selection” table for 16VFQFPN.

3. Updated Pin Description table to include VFQFPN pin descriptions.

4. Added Thermal Characteristics table for 16VFQFPN.

5. Added marking diagrams for 16VFQFPN.

6. Added Package Dimensions/Drawing for 16VFQFPN.

7. Updated Ordering Information to include 16VFQFPN.

C.P.

04/17/17 1. Replaced package outline drawings with latest NLG16 and PGG16 drawings.

2. Updated legal disclaimer.

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