转到网站首页
转为中文步骤：
1、请用电脑端360浏览器打开本页地址，如您电脑未安装360浏览器，请点这里下载;
2、点击360浏览器右上角的翻译插件，如右图红圈中所示:
3、点击所弹出窗口里的右下角的按钮 “翻译当前网页”;
4、弹窗提示翻译完毕后关闭弹窗即可；
DATASHEET  
ISL97645A  
Boost + VON Slice + VCOM + Reset  
FN6353  
Rev 1.00  
October 21, 2010  
The ISL97645A represents an integrated DC/DC regulator  
for monitor and notebook applications with screen sizes up  
to 20”. The device integrates a boost converter for  
Features  
• 2.7V to 5.5V Input  
generating AVDD, a VON slice circuit, and a high performance  
• 2.6A Integrated Boost for Up to 20V AVDD  
• Integrated VON Slice  
VCOM amplifier.  
The boost converter features a 2.6A FET and has user  
programmable soft-start and compensation. With efficiencies  
up to 92%, the AVDD is user selectable from 7V to 20V.  
• RESET signal generated by Supply Monitor  
• 600kHz/1.2MHz fS  
• VCOM Amplifier  
- 30MHz BW  
The VON slice circuit can control gate voltages up to 30V.  
High and low levels are programmable, as well as discharge  
rate and timing.  
- 50V/µs SR  
- 400mA Peak Output Current  
The supply monitor can be used to monitor the input voltage  
to prevent low voltage operation.  
• UV and OT Protection  
• 24 Ld 4x4 QFN  
The integrated VCOM features high speed and drive  
capability. With 30MHz bandwidth and 50V/µs slew rate, the  
• Pb-Free (RoHS Compliant)  
VCOM amplifier is capable of driving 400mA peaks, and  
100mA continuous output current.  
Applications  
• LCD Monitors (15”+)  
• Notebook Display (up to 16”)  
Ordering Information  
PART  
TEMP.  
NUMBER  
(Notes 1, 2, 3)  
PART  
MARKING  
RANGE  
(°C)  
PACKAGE  
(Pb-Free)  
PKG.  
DWG. #  
Pinout  
ISL97645A  
(24 LD 4x4 QFN)  
TOP VIEW  
ISL97645AIRZ  
NOTES:  
976 45AIRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D  
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details  
on reel specifications.  
2. These Intersil Pb-free plastic packaged products employ special Pb-  
free material sets, molding compounds/die attach materials, and  
100% matte tin plate plus anneal (e3 termination finish, which is  
RoHS compliant and compatible with both SnPb and Pb-free  
soldering operations). Intersil Pb-free products are MSL classified at  
Pb-free peak reflow temperatures that meet or exceed the Pb-free  
requirements of IPC/JEDEC J STD-020.  
24 23 22 21 20 19  
GND  
VGH_M  
VFLK  
LX  
18  
17  
16  
15  
14  
13  
1
2
3
4
5
6
VIN2  
FREQ2  
COMP  
SS  
3. For Moisture Sensitivity Level (MSL), please see device  
information page for ISL97645A. For more information on  
MSL please see techbrief TB363.  
VDPM  
VDD1  
VDD2  
RESET  
7
8
9
10 11 12  
FN6353 Rev 1.00  
October 21, 2010  
Page 1 of 16  
ISL97645A  
Pin Descriptions  
PIN NUMBER  
NAME  
DESCRIPTION  
1
2
3
4
GND  
VGH_M  
VFLK  
Signal ground  
Gate Pulse Modulator Output  
Gate Pulse Modulator Control input  
VDPM  
Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is  
enabled. A 20µA current source charges CDPM. Power on delay time = 60.75k*CDPM.  
5
6
VDD1  
VDD2  
OUT  
Gate Pulse Modulator Low Voltage Input  
VCOM Amplifier Supply  
7
VCOM Amplifier Output  
8
NEG  
VCOM Amplifier Inverting input  
9
POS  
VCOM Amplifier Non-inverting input  
10  
11  
12  
13  
14  
15  
AGND  
CD2  
VCOM Amplifier Ground  
Voltage detector rising edge delay. Connect a capacitor between this pin and GND to set the rising edge delay.  
Voltage detector threshold. Connect to the center of a resistive divider between VIN and GND.  
Voltage detector reset output.  
VDIV  
RESET  
SS  
Boost Converter Soft-Start. Connect a capacitor between this pin and GND to set the soft-start time.  
COMP  
Boost Converter Compensation pin. Connect a series resistor and capacitor between this pin and GND to  
optimize transient response.  
16  
17  
18  
19  
20  
21  
22  
23  
24  
FREQ  
VIN2  
LX  
Boost Converter frequency select  
Boost Converter power supply  
Boost Converter Switching Node  
ENABLE  
FB  
Chip Enable pin. Connect to VIN1 for normal operation, GND for shutdown.  
Boost Converter Feedback  
PGND  
RE  
Boost Converter Power Ground  
Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate.  
Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time.  
Gate Pulse Modulator High Voltage Input  
CE  
VGH  
FN6353 Rev 1.00  
October 21, 2010  
Page 2 of 16  
ISL97645A  
Absolute Maximum Ratings  
Thermal Information  
Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V  
VDD2, OUT, NEG and POS  
Thermal Resistance  
JA (°C/W)  
39  
JC (°C/W)  
2.5  
4x4 QFN Package (Notes 4, 5) . . . . . .  
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +25V  
VDD1, VGH and VGH_M  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C  
Power Dissipation  
TA +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W  
TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W  
TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W  
TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W  
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +32V  
Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . ±6V  
Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . ±0.5V  
All Other Pins to GND, AGND and PGND . . . . . . . . . . -0.5 to +6.5V  
Input, Output, or I/O Voltage . . . . . . . . . . .GND -0.3V to VIN + 0.3V  
Pb-Free Reflow Profile  
see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
Recommended Operating Conditions  
Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V  
Boost Output Voltage Range, AVDD. . . . . . . . . . . . . . . . . . 8V to 20V  
Input Capacitance, CIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22µF  
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH  
Output Capacitance, COUT. . . . . . . . . . . . . . . . . . . . . . . .2µF x 22µF  
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C  
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and  
result in failures not covered by warranty.  
NOTES:  
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech  
Brief TB379.  
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.  
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C  
Unless Otherwise Noted. Boldface limits apply over the operating temperature range,  
-40°C to +85°C.  
MIN  
MAX  
SYMBOL  
GENERAL  
PARAMETER  
TEST CONDITION  
(Note 6)  
TYP  
(Note 6)  
UNIT  
VS  
VIN Input Voltage Range  
2.7  
3.3  
1
5.5  
3.5  
V
µA  
mA  
V
IS_DIS  
IS  
VIN Supply Currents when Disabled  
VIN Supply Currents  
ENABLE = 0V  
ENABLE = 5V, LX not switching  
VIN2 Rising  
1
UVLO  
Under Voltage Lockout Threshold  
2.3  
2.2  
2.45  
2.35  
140  
100  
2.6  
2.5  
V
IN2 Falling  
V
OTR  
OTF  
Thermal Shutdown Temperature  
Temperature Rising  
Temperature Falling  
°C  
°C  
LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM  
VIL  
VIH  
RIL  
Low Voltage Threshold  
High Voltage Threshold  
Pull-Down Resistor  
0.8  
400  
20  
V
V
2.2  
Enabled, Input at VIN  
150  
250  
k  
STEP-UP SWITCHING REGULATOR  
AVDD Output Voltage Range  
VBOOST/IOUT Load Regulation  
VIN*1.25  
V
50mA < ILOAD < 250mA  
0.2  
%
%
%
VBOOST/VIN  
Line Regulation  
I
LOAD = 150mA, 3.0 < VIN < 5.5V  
0.15  
0.25  
3
ACCAVDD  
Overall Accuracy (Line, Load,  
Temperature)  
10mA < ILOAD < 300mA,  
3.0 < VIN < 5.5V, 0°C < TA < +85°C  
-3  
VFB  
Feedback Voltage (VFB  
)
ILOAD = 100mA, TA = +25°C  
1.20  
1.21  
1.21  
1.22  
V
V
ILOAD = 100mA, TA = -40°C to +85°C  
1.19  
1.23  
FN6353 Rev 1.00  
October 21, 2010  
Page 3 of 16  
ISL97645A  
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C  
Unless Otherwise Noted. Boldface limits apply over the operating temperature range,  
-40°C to +85°C. (Continued)  
MIN  
MAX  
SYMBOL  
PARAMETER  
FB Input Bias Current  
TEST CONDITION  
(Note 6)  
TYP  
250  
150  
92  
(Note 6)  
UNIT  
nA  
IFB  
500  
300  
rDS(ON)  
EFF  
Switch ON-resistance  
Peak Efficiency  
m  
%
ILIM  
Switch Current Limit  
Max Duty Cycle  
2.9  
A
DMAX  
fOSC  
85  
550  
1.0  
90  
%
Oscillator Frequency  
FREQ = 0V  
650  
1.2  
800  
1.4  
kHz  
MHz  
µA  
FREQ = VIN2  
ISS  
Soft-Start Slew Current  
SS < 1V, TA = +25°C  
2.75  
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated  
VSAMP  
ISAMP  
VOS  
IB  
Supply Voltage  
4.5  
20  
V
mA  
mV  
nA  
Supply Current  
3
3
0
Offset Voltage  
20  
100  
Noninverting Input Bias Current  
Common Mode Input Voltage Range  
Common-Mode Rejection Ratio  
Power Supply Rejection Ratio  
Output Voltage Swing High  
Output Voltage Swing High  
Output Voltage Swing Low  
Output Voltage Swing Low  
Output Short Circuit Current  
Slew Rate  
CMIR  
CMRR  
PSRR  
VOH  
VOH  
VOL  
0
VDD2  
V
50  
70  
70  
dB  
85  
VDD2 - 50  
VDD2 - 450  
50  
dB  
IOUT(source) = 5mA  
IOUT(source) = 50mA  
IOUT(sink) = 5mA  
mV  
mV  
mV  
mV  
mA  
V/µs  
MHz  
VOL  
IOUT(sink) = 50mA  
450  
ISC  
250  
400  
SR  
50  
BW  
Gain Bandwidth  
-3dB gain point  
30  
GATE PULSE MODULATOR  
VGH  
VGH Voltage  
7
30  
V
V
VIH_VDPM  
IVGH  
VDPM Enable Threshold  
VGH Input Current  
1.18  
1.215  
260  
40  
1.25  
VFLK = 0  
µA  
µA  
V
RE = 33k, VFLK = VDD1  
VDD1  
VDD1 Voltage  
3
VGH - 2  
2
IVDD1  
VDD1 Input Current  
VGH to VGH_M On Resistance  
VGH_M Discharge Current  
VDPM Charge Current  
DELAY Time  
-2  
0.1  
70  
8
µA  
RONVGH  
IDIS_VGH  
IDPM  
tDEL  
RE = 33k  
mA  
µA  
µs  
20  
1.9  
CE = 470pF, RE = 33k  
FN6353 Rev 1.00  
October 21, 2010  
Page 4 of 16  
ISL97645A  
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C  
Unless Otherwise Noted. Boldface limits apply over the operating temperature range,  
-40°C to +85°C. (Continued)  
MIN  
MAX  
SYMBOL  
SUPPLY MONITOR  
VIH_VDIV  
PARAMETER  
TEST CONDITION  
(Note 6)  
TYP  
(Note 6)  
UNIT  
VDIV High Threshold  
VDIV rising  
VDIV falling  
1.18  
V
V
VIL_VDIV  
VDIV Low Threshold  
1.05  
ICD2  
CD2 Charge Current  
10  
750  
µA  
s
RIL_RESET  
tDELAY_RESET  
NOTE:  
RESET Pull-Down Resistance  
RESET Delay on the Rising Edge  
121.5k*CD  
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization  
and are not production tested.  
I
Typical Performance Curves  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
100  
f
= 650kHz  
OSC  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
f
= 1.2MHz  
OSC  
f
= 650kHz  
= 1.2MHz  
OSC  
f
OSC  
0
200  
400  
600  
(mA)  
800  
1000  
1200  
0
200  
400  
600  
(mA)  
800  
1000  
1200  
IA  
IA  
VDD  
VDD  
FIGURE 2. AVDD LOAD REGULATION vs IAVDD  
FIGURE 1. AVDD EFFICIENCY vs IAVDD  
10.5  
10.45  
10.4  
L = 10µH, C  
= 40µF, C  
= 2.2nF, R  
= 10k  
COMP  
OUT  
COMP  
A
150mA  
VDD  
IA  
VDD  
A
500mA  
VDD  
10.35  
10.3  
10.25  
10.2  
A
(AC COUPLED)  
VDD  
10.15  
3
3.5  
4.0  
4.5  
(V)  
5.0  
5.5  
6.0  
V
IN  
FIGURE 3. LINE REGULATION AVDD vs VIN  
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE  
FN6353 Rev 1.00  
October 21, 2010  
Page 5 of 16  
ISL97645A  
Typical Performance Curves (Continued)  
CE = 1pF, RE = 100k  
CE = 1000pF, RE = 100k  
VGH_M  
VFLK  
VGH_M  
VFLK  
FIGURE 6. GPM CIRCUIT WAVEFORM  
FIGURE 5. GPM CIRCUIT WAVEFORM  
CE = 10pF, RE = 100k  
CE = 10pF, RE = 150k  
VGH_M  
VGH_M  
VFLK  
VFLK  
FIGURE 7. GPM CIRCUIT WAVEFORM  
FIGURE 8. GPM CIRCUIT WAVEFORM  
INPUT SIGNAL  
OUTPUT SIGNAL  
FIGURE 10. VCOM RISING SLEW RATE  
FIGURE 9. VGHM FOLLOWS VGH WHEN THE SYSTEM  
POWERS OFF  
FN6353 Rev 1.00  
October 21, 2010  
Page 6 of 16  
ISL97645A  
Typical Performance Curves (Continued)  
INPUT  
SIGNAL  
OUTPUT  
SIGNAL  
(-3dB ATTENTUATION  
FROM INPUT SIGNAL)  
FIGURE 11. VCOM BANDWIDTH MEASUREMENT  
FN6353 Rev 1.00  
October 21, 2010  
Page 7 of 16  
ISL97645A  
Block Diagram  
FREQ  
LX  
OSCILLATION  
GENERATOR  
SLOPE  
COMPENSATION  
COMP  
SUMMING  
AMPLIFIER  
FB  
-
PWM  
LOGIC  
+
2.5µA  
-
+
PGND  
SS  
VIN  
REFERENCE  
GENERATOR  
START-UP AND  
FAULT CONTROL  
20µA  
VDPM  
ENABLE  
CD2  
10µA  
+
-
V
REF  
OUT  
RESET  
VDIV  
VDD2  
+
-
V
REF  
POS  
NEG  
GND  
+
-
750  
GPM  
CIRCUIT  
VDD1  
VFLK VGH VGH_M CE  
RE  
FIGURE 12. ISL97645A BLOCK DIAGRAM  
FN6353 Rev 1.00  
October 21, 2010  
Page 8 of 16  
ISL97645A  
Functional Block Diagram  
V
A
IN  
VDD  
VIN  
LX  
COMP  
SS  
BOOST  
FB  
PGND  
VSHDN  
FREQ-  
V
ON  
VGH  
VDPM  
VFLK  
VDD1  
GPM  
CIRCUIT  
CE  
RE  
V
VGH_M  
VDD2  
OUT  
GATE  
POS  
NEG-  
VIN  
RESET  
REF  
CD2  
AGND  
GND  
VIN  
VDIV  
FIGURE 13. FUNCTIONAL BLOCK DIAGRAM  
Applications Information  
Boost Converter  
The ISL97645A provides a complete power solution for TFT  
LCD applications. The system consists of one boost converter  
to generate AVDD voltage for column drivers, one integrated  
Frequency Selection  
The ISL97645A switching frequency can be user selected to  
operate at either constant 650kHz or 1.2MHz. Lower switching  
frequency can save power dissipation, while higher switching  
frequency can allow smaller external components like inductor  
and output capacitors, etc. Connecting the FREQ pin to GND  
sets the PWM switching frequency to 650kHz, or connecting  
FREQ pin to VIN for 1.2MHz.  
VCOM buffer which can provide up to 400mA peak current, and  
one supply monitor to generate the reset signal when the input  
voltage is low. This part also integrates Gate Pulse Modulator  
circuit that can help to optimize the picture quality.  
Enable Control  
Soft-Start  
When enable pin is pulling down, the ISL97645A is shut down  
reducing the supply current to <10µA. When the voltage at  
enable pin reaches 2.2V, the ISL97645A is on.  
The soft-start is provided by an internal 2.5µA current source to  
charge the external soft-start capacitor. The ISL97645A ramps  
up current limit from 0A up to full value, as the voltage at SS  
pin ramps from 0 to 1.2V. Hence the soft-start time is 4.8ms  
when the soft-start capacitor is 10nF, 22.6ms for 47nF and  
48ms for 100nF.  
FN6353 Rev 1.00  
October 21, 2010  
Page 9 of 16  
ISL97645A  
The current through the MOSFET is limited to 2.6APEAK  
.
Operation  
The boost converter is a current mode PWM converter  
operating at either a 650kHz or 1.2MHz. It can operate in both  
discontinuous conduction mode (DCM) at light load and  
continuous mode (CCM). In continuous current mode, current  
flows continuously in the inductor during the entire switching  
cycle in steady state operation. The voltage conversion ratio in  
continuous current mode is given by Equation 1:  
This restricts the maximum output current (average) based on  
Equation 3:  
I  
V
IN  
V
O
L
(EQ. 3)  
--------  
---------  
I
=
I
–
LMT  
OMAX  
2
Where IL is peak to peak inductor ripple current, and is set by  
Equation 4:  
V
1
Boost  
(EQ. 1)  
------------------  
-------------  
=
V
1 – D  
V
D
f
s
IN  
IN  
(EQ. 4)  
--------- ---  
I  
=
L
L
Where D is the duty cycle of the switching MOSFET.  
where fS is the switching frequency (650kHz or 1.2MHz).  
Figure 12 shows the block diagram of the boost regulator. It  
uses a summing amplifier architecture consisting of gm stages  
for voltage feedback, current feedback and slope  
compensation. A comparator looks at the peak inductor current  
cycle by cycle and terminates the PWM cycle if the current limit  
is reached.  
Table 2 gives typical values (margins are considered 10%, 3%,  
20%, 10% and 15% on VIN, VO, L, fS and IOMAX).  
Capacitor  
An input capacitor is used to suppress the voltage ripple  
injected into the boost converter. The ceramic capacitor with  
capacitance larger than 10µF is recommended. The voltage  
rating of input capacitor should be larger than the maximum  
input voltage. Some capacitors are recommended in Table 1  
for input capacitor.  
An external resistor divider is required to divide the output  
voltage down to the nominal reference voltage. Current drawn  
by the resistor network should be limited to maintain the overall  
converter efficiency. The maximum value of the resistor  
network is limited by the feedback input bias current and the  
potential for noise being coupled into the feedback pin. A  
resistor network in the order of 60kis recommended. The  
boost converter output voltage is determined by Equation 2:  
TABLE 1. BOOST CONVERTER INPUT CAPACITOR  
RECOMMENDATION  
CAPACITOR  
10µF/16V  
SIZE  
1206  
0805  
1210  
MFG  
TDK  
PART NUMBER  
C3216X7R1C106M  
R
+ R  
2
R
2
1
(EQ. 2)  
--------------------  
V
=
V  
Boost  
FB  
10µF/10V  
22µF/10V  
Murata GRM21BR61A106K  
Murata GRB32ER61A226K  
TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION  
V
IN (V)  
VO (V)  
9
L (µH)  
10  
FS (MHz)  
0.65  
0.65  
0.65  
0.65  
0.65  
0.65  
0.65  
1.2  
IOMAX (mA)  
636  
3
3
3
5
5
5
5
3
3
3
5
5
5
5
12  
15  
9
10  
419  
10  
289  
10  
1060  
699  
12  
15  
18  
9
10  
10  
482  
10  
338  
10  
742  
12  
15  
9
10  
1.2  
525  
10  
1.2  
395  
10  
1.2  
1236  
875  
12  
15  
18  
10  
1.2  
10  
1.2  
658  
10  
1.2  
514  
FN6353 Rev 1.00  
October 21, 2010  
Page 10 of 16  
ISL97645A  
Note: Capacitors have a voltage coefficient that makes their  
effective capacitance drop as the voltage across then  
increases. COUT in the equation above assumes the effective  
value of the capacitor at a particular voltage and not the  
manufacturer’s stated value, measured at 0V.  
Inductor  
The boost inductor is a critical part which influences the output  
voltage ripple, transient response, and efficiency. Values of  
3.3µH to 10µH are used to match the internal slope  
compensation. The inductor must be able to handle the  
following average and peak current are in Equation 5:  
Table 5 shows some selections of output capacitors.  
I
O
-------------  
I
I
=
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION  
LAVG  
1 – D  
(EQ. 5)  
I  
CAPACITOR SIZE  
MFG  
TDK  
Murata  
PART NUMBER  
C3225X7R1E106M  
GRM32DR61E106K  
L
--------  
+
= I  
LPK  
LAVG  
2
10µF/25V  
10µF/25V  
1210  
1210  
Some inductors are recommended in Table 3.  
TABLE 3. BOOST INDUCTOR RECOMMENDATION  
Compensation  
DIMENSIONS  
The boost converter of ISL97645A can be compensated by a  
RC network connected from CM1 pin to ground. 4.7nF and 10k  
RC network is used in the demo board. The larger value  
resistor and lower value capacitor can lower the transient  
overshoot, however, at the expense of stability of the loop.  
INDUCTOR  
6.8µH/3APEAK  
10µH/4APEAK  
(mm)  
MFG  
PART NUMBER  
7.3x6.8x3.2 TDK  
RLF7030T-6R8N3R0  
CDR8D43-100NC  
CD1-5R2  
8.3x8.3x4.5 Sumida  
5.2µH/4.55APEAK 10x10.1x3.8 Cooper  
Bussmann  
Cascaded MOSFET Application  
An 20V N-Channel MOSFET is integrated in the boost  
regulator. For the applications where the output voltage is  
greater than 20V, an external cascaded MOSFET is needed as  
shown in Figure 14. The voltage rating of the external  
Rectifier Diode  
A high-speed diode is necessary due to the high switching  
frequency. Schottky diodes are recommended because of their  
fast recovery time and low forward voltage. The reverse  
voltage rating of this diode should be higher than the maximum  
output voltage. The rectifier diode must meet the output current  
and peak inductor current requirements. The following table is  
some recommendations for boost converter diode.  
MOSFET should be greater than AVDD  
.
A
V
VDD  
IN  
TABLE 4. BOOST CONVERTER RECTIFIER DIODE  
RECOMMENDATION  
LX  
DIODE  
SS23  
VR/IAVG RATING PACKAGE  
MFG  
FB  
INTERSIL  
ISL97645A  
30V/2A  
40V/3A  
30V/2A  
SMB  
SMC  
SMB  
Fairchild  
Semiconductor  
MBRS340  
SL23  
International  
Rectifier  
Vishay  
Semiconductor  
Output Capacitor  
FIGURE 14. CASCADED MOSFET TOPOLOGY FOR HIGH  
OUTPUT VOLTAGE APPLICATIONS  
The output capacitor supplies the load directly and reduces the  
ripple voltage at the output. Output ripple voltage consists of  
two components:  
1. the voltage drop due to the inductor ripple current flowing  
through the ESR of output capacitor.  
2. charging and discharging of the output capacitor.  
V
– V  
I
O
1
f
s
O
IN  
----------------------- --------------- ---  
V
= I  
ESR +  
LPK  
(EQ. 6)  
RIPPLE  
V
C
O
OUT  
For low ESR ceramic capacitors, the output ripple is dominated  
by the charging and discharging of the output capacitor. The  
voltage rating of the output capacitor should be greater than  
the maximum output voltage.  
FN6353 Rev 1.00  
October 21, 2010  
Page 11 of 16  
ISL97645A  
Supply Monitor Circuit  
Gate Pulse Modulator Circuit  
The Supply Monitor circuit monitors the voltage on VDIV, and  
sets open-drain output RESET low when VDIV is below 1.15V  
(rising) or 1.1V (falling).  
The gate pulse modulator circuit functions as a three way  
multiplexer, switching VGHM between ground, VDD1 and  
VGH. Voltage selection is provided by digital inputs VDPM  
(enable) and VFLK (control). High to low delay and slew  
control is provided by external components on pins CE and  
RE, respectively. A block diagram of the gate pulse modulator  
circuit is shown in Figure 16.  
There is a delay on the rising edge, controlled by a capacitor  
on CD2. When VDIV exceeds 1.15V (rising), CD2 is charged  
up from 0V to 1.215V by a 10µA current source. Once CD2  
exceeds 1.215V, RESET will go tri-state. When VDIV falls  
below 1.1V, RESET will become low with a 750 pull-down  
resistance. The delay time is controlled by Equation 7:  
When VDPM is LOW, the block is disabled and VGHM is  
grounded. When the input voltage exceeds UVLO threshold,  
VDPM starts to drive an external capacitor with 20A. Once  
VDPM exceeds 1.215V, the GPM circuit is enabled, and the  
output VGH_M is determined by VFLK, RESET signal and  
VGH voltage. If RESET signal is high, and when VFLK goes  
high, VGHM is pulled to VGH by a 70switch. When VFLK  
goes low, there is a delay controlled by capacitor CE, following  
which VGHM is driven to VDD1, with a slew rate controlled by  
resistor RE. Note that VDD1 is used only as a reference  
voltage for an amplifier, thus does not have to source or sink a  
significant DC current.  
(EQ. 7)  
t
= 121.5k CD2  
delay  
For example, the delay time is 12.15ms if the CD2 = 100nF.  
Figure 15 is the Supply Monitor Circuit timing diagram.  
1.15V  
VDIV  
1.1V  
Low to high transition is determined primarily by the switch  
resistance and the external capacitive load. High to low  
transition is more complex. Take the case where the block is  
already enabled (VDPM is H). When VFLK is H, pin CE is  
grounded. On the falling edge of VFLK, a current is passed into  
pin CE, to charge an external capacitor to 1.2V. This creates a  
delay, equal to CE*4200. At this point, the output begins to pull  
down from VGH to VDD1. The slew current is equal to 300/(RE  
1.215V  
CD2  
RESET DELAY TIME IS  
CONTROLLED BY CD2  
CAPACITOR  
RESET  
+ 5000), and the dv/dt slew rate is Isl/CLOAD  
.
FIGURE 15. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM  
where CLOAD is the load capacitance applied to VGHM.  
When RESET signal changes to low, and VGH voltage is  
above 2.5V, the VGH_M will be tied to VGH voltage until the  
VGH voltage falls down to 2.5V. If the VGH voltage is lower  
than 2.5V, GPM block will not work properly, and there is no  
active control for VGH_M output. The following table shows the  
VGH_M status based on VIN, VGH and RESET:  
FN6353 Rev 1.00  
October 21, 2010  
Page 12 of 16  
ISL97645A  
.
VGH  
VGH_M  
EnGPM1  
VDD1  
x240  
VREF  
RE  
200µA  
CE  
CONTROL  
AND  
VFLK  
TIMING  
FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM  
Vin  
UVLO  
Threshold  
0
VGH  
RESET  
VDPM  
1.215V  
VFLK  
VGH  
VGH_M is forced to  
VGH when RESET  
goes to low AND  
VGH>2.5V  
VGH_M  
VGL  
Slope is controlled  
by RE  
Delay time is  
controlled by CE  
Power on delay time is  
controlled by CDPM  
FIGURE 17. GATE PULSE MODULATOR TIMING DIAGRAM  
FN6353 Rev 1.00  
October 21, 2010  
Page 13 of 16  
ISL97645A  
TABLE 6. VGH_M STATUS TABLE  
VIN  
VDPM  
RESET  
VGH  
VGH_M  
COMMENT  
x
x
x
<2.5V  
GROUND  
Will be grounded if VIN is above  
a logic threshold. Could occur at  
power-up or power-down  
>VLOR  
x
<1.215V  
<1.215V  
x
>2.5V  
>2.5V  
GROUND  
GROUND  
Start-up only condition: If either  
VIN> VLOR or reset is H, but  
High  
VDPM < 1.215V, GND VGHM  
>VLOR  
>1.215V  
High  
>2.5V  
Switching  
controlled by  
VFLK  
x
x
Low  
>2.5V  
VGH  
Power-down state. Could occur  
at power-up if part starts with  
VGH > 2.5V  
amplifier will top the reservoir capacitor back up once the pulse  
has stopped. This will happen on the µs time scale in practical  
systems and for pulses 2 or 3 times the current limit, the VCOM  
voltage will have settled again before the next line is  
processed.  
Start-Up Sequence  
When VIN exceeds VLOR and ENABLE reaches the VIH  
threshold value, Boost converter starts up, and gate pulse  
modulator circuit output holds until VDPM is charged to  
1.215V. Note that there is a DC path in the boost converter  
from the input to the output through the inductor and diode,  
hence the input voltage will be seen at output with a forward  
voltage drop of diode before the part is enabled. If this voltage  
is not desired, the following circuit can be inserted between  
input and inductor to disconnect the DC path when the part is  
disabled.  
Fault Protection  
ISL97645A provides the overall fault protections including over  
current protection and over-temperature protection.  
An internal temperature sensor continuously monitors the die  
temperature. In the event that die temperature exceeds the  
thermal trip point, the device will shut down and disable itself.  
The upper and lower trip points are typically set to +140°C and  
+100°C respectively.  
.
INPUT  
TO INDUCTOR  
ENABLE  
FIGURE 18. CIRCUIT TO DISCONNECT THE DC PATH OF  
BOOST CONVERTER  
V
Amplifier  
COM  
The VCOM amplifier is designed to control the voltage on the  
back plate of an LCD display. This plate is capacitively coupled  
to the pixel drive voltage which alternately cycles positive and  
negative at the line rate for the display. Thus the amplifier must  
be capable of sourcing and sinking capacitive pulses of  
current, which can occasionally be quite large (a few 100mA  
for typical applications).  
The ISL97645A VCOM amplifier's output current is limited to  
400mA. This limit level, which is roughly the same for sourcing  
and sinking, is included to maintain reliable operation of the  
part. It does not necessarily prevent a large temperature rise if  
the current is maintained. (In this case the whole chip may be  
shut down by the thermal trip to protect functionality.) If the  
display occasionally demands current pulses higher than this  
limit, the reservoir capacitor will provide the excess and the  
FN6353 Rev 1.00  
October 21, 2010  
Page 14 of 16  
ISL97645A  
Layout Recommendation  
The device’s performance including efficiency, output noise,  
transient response and control loop stability is dramatically  
affected by the PCB layout. PCB layout is critical, especially  
at high switching frequency.  
There are some general guidelines for layout:  
1. Place the external power components (the input  
capacitors, output capacitors, boost inductor and output  
diodes, etc.) in close proximity to the device. Traces to  
these components should be kept as short and wide as  
possible to minimize parasitic inductance and resistance.  
2. Place VIN and VDD bypass capacitors close to the pins.  
3. Reduce the loop area with large AC amplitudes and fast  
slew rate.  
4. The feedback network should sense the output voltage  
directly from the point of load, and be as far away from LX  
node as possible.  
5. The power ground (PGND) and signal ground (SGND)  
pins should be connected at only one point.  
6. The exposed die plate, on the underneath of the  
package, should be soldered to an equivalent area of  
metal on the PCB. This contact area should have multiple  
via connections to the back of the PCB as well as  
connections to intermediate PCB layers, if available, to  
maximize thermal dissipation away from the IC.  
7. To minimize the thermal resistance of the package when  
soldered to a multi-layer PCB, the amount of copper track  
and ground plane area connected to the exposed die  
plate should be maximized and spread out as far as  
possible from the IC. The bottom and top PCB areas  
especially should be maximized to allow thermal  
dissipation to the surrounding air.  
8. A signal ground plane, separate from the power ground  
plane and connected to the power ground pins only at the  
exposed die plate, should be used for ground return  
connections for control circuit.  
9. Minimize feedback input track lengths to avoid switching  
noise pick-up.  
A demo board is available to illustrate the proper layout  
implementation.  
© Copyright Intersil Americas LLC 2007-2010. All Rights Reserved.  
All trademarks and registered trademarks are the property of their respective owners.  
For additional products, see www.intersil.com/en/products.html  
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted  
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html  
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such  
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are  
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its  
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6353 Rev 1.00  
October 21, 2010  
Page 15 of 16  
ISL97645A  
Package Outline Drawing  
L24.4x4D  
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
Rev 2, 10/06  
4X  
2.5  
4.00  
A
20X  
0.50  
PIN #1 CORNER  
(C 0 . 25)  
B
19  
24  
PIN 1  
INDEX AREA  
1
18  
2 . 50 ± 0 . 15  
13  
0.15  
(4X)  
12  
24X 0 . 4 ± 0 . 1  
7
0.10 M C  
A B  
TOP VIEW  
+ 0 . 07  
24X 0 . 23  
4
- 0 . 05  
BOTTOM VIEW  
SEE DETAIL "X"  
C
0.10  
0 . 90 ± 0 . 1  
C
BASE PLANE  
( 3 . 8 TYP )  
SEATING PLANE  
0.08  
SIDE VIEW  
C
(
2 . 50 )  
( 20X 0 . 5 )  
5
C
0 . 2 REF  
( 24X 0 . 25 )  
0 . 00 MIN.  
0 . 05 MAX.  
( 24X 0 . 6 )  
DETAIL "X"  
TYPICAL RECOMMENDED LAND PATTERN  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
FN6353 Rev 1.00  
October 21, 2010  
Page 16 of 16