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Document Number: MPC17511A  
Rev 2.0, 4/2007  
Freescale Semiconductor  
Technical Data  
1.0 A 6.8 V H-Bridge Motor  
Driver IC  
17511A  
The 17511A is a monolithic H-Bridge designed to be used in  
portable electronic applications to control small DC motors or bipolar  
step motors. End applications include head positioners (CDROM or  
disk drive), camera focus motors, and camera shutter solenoids.  
H-BRIDGE MOTOR DRIVER IC  
The 17511A can operate efficiently with supply voltages as low as  
2.0 V to as high as 6.8 V. Its low RDS(ON) H-Bridge output MOSFETs  
(0.46 Ω typical) can provide continuos motor drive currents of 1.0 A  
and handle peak currents up to 3.0 A. It is easily interfaced to low-  
cost MCUs via parallel 3.0 V- or 5.0 V- compatible logic. The device  
can be pulse width modulated (PWM-ed) at up to 200 kHz.  
This device contains an integrated charge pump and level shifter  
(for gate drive voltages), integrated shoot-through current protection  
(cross-conduction suppression logic and timing), and undervoltage  
detection and shutdown circuitry.  
EP SUFFIX (PB-FREE)  
98ARL10577D  
EV SUFFIX (PB-FREE)  
98ASH70109A  
24-PIN QFN  
16-PIN VMFP  
The 17511A has four operating modes: Forward, Reverse, Brake,  
and Tri-Stated (High Impedance).  
ORDERING INFORMATION  
Temperature  
Features  
Device  
Package  
Range (T )  
A
• 2.0 V to 6.8 V Continuous Operation  
• Output Current 1.0 A (DC), 3.0 A (Peak)  
• MOSFETs < 600 mΩ RDS(ON) @ 25°C Guaranteed  
• 3.0 V/5.0 V TTL-/CMOS-Compatible Inputs  
• PWM Frequencies up to 200 kHz  
• Undervoltage Shutdown  
MPC17511AEV/EL  
MPC17511AEP/R2  
16 VMFP  
24 QFN  
-20°C to 65°C  
• Cross-Conduction Suppression  
• Low Power Consumption  
• Pb-Free Packaging Designated by Suffix Codes EV and EP  
5.0 V  
17511A  
VDD  
C1L  
C1H  
C2L  
C2H  
CRES  
15 V  
VM  
GOUT  
OUT1  
MOTOR  
EN  
GIN  
IN1  
IN2  
OUT2  
MCU  
GND  
Figure 1. 17511A Simplified Application Diagram  
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,  
as may be required, to permit improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
Charge Pump  
C2H  
C1L  
C2L  
C1H  
CRES  
GOUT  
Low-  
VDD  
Voltage  
Shutdown  
VM  
IN1  
IN2  
GIN  
EN  
OUT1  
OUT2  
Level  
Shifter  
Predriver  
VDD  
Control  
Logic  
VDD  
PGND  
LGND  
Figure 2. 17511A Simplified Internal Block Diagram  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
C2H  
C2L  
C1H  
1
2
3
4
16  
15  
CRES  
GOUT  
C1L  
VM  
14  
13  
12  
11  
10  
9
OUT2  
PGND  
V
DD  
IN1  
IN2  
EN  
5
6
7
OUT1  
GIN  
8
LGND  
Figure 3. VMFP Pin Connections  
Table 1. VMFP Pin Function Description  
Pin  
Pin Name  
Formal Name  
Definition  
Number  
Charge pump bucket capacitor 2 (negative pole).  
Charge pump bucket capacitor 1 (positive pole).  
Charge pump bucket capacitor 1 (negative pole).  
Driver power supply voltage input pin.  
Control circuit power supply pin.  
1
2
C2L  
C1H  
C1L  
Charge Pump 2L  
Charge Pump 1H  
Charge Pump 1L  
Motor Drive Power Supply  
Logic Supply  
3
4
VM  
5
VDD  
IN1  
Control signal input 1  
6
Input Control 1  
Control signal input 2.  
7
IN2  
Input Control 2  
Enable control signal input pin.  
8
EN  
Enable Control  
Logic ground pin.  
9
LGND  
GIN  
Logic Ground  
LOW = True control signal for GOUT pin.  
Driver output 1 (right half of H-Bridge).  
Driver ground pin.  
10  
11  
12  
13  
14  
15  
Gate Driver Input  
H-Bridge Output 1  
Power Ground  
OUT1  
PGND  
OUT2  
GOUT  
CRES  
Driver output 2 (left half of H-Bridge).  
Output gate driver signal to external MOSFET switch.  
Charge pump reservoir capacitor pin.  
H-Bridge Output 2  
Gate Driver Output  
Charge Pump Output Capacitor  
Connection  
Charge pump bucket capacitor 2 (positive pole).  
16  
C2H  
Charge Pump 2H  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
24 23 22 21 20 19  
18  
17  
16  
15  
14  
13  
1
2
3
4
5
6
NC  
VM  
VM  
VM  
OUT2  
PGND  
PGND  
OUT1  
NC  
VM  
NC  
NC  
7
8
9
10 11 12  
Figure 4. QFN Pin Connections  
Table 2. QFN Pin Function Description  
Pin  
Pin Name  
Formal Name  
Definition  
Number  
Driver power supply voltage input pin.  
This pin is not used.  
1, 2, 3, 4  
VM  
NC  
Motor Drive Power Supply  
No Connect  
5, 6, 13, 18  
Control circuit power supply pin.  
Control signal input 1.  
7
8
VDD  
IN1  
Logic Supply  
Logic Input Control 1  
Logic Input Control 2  
Enable Control  
Control signal input 2.  
9
IN2  
Enable control signal input pin.  
10  
11  
12  
14  
15, 16  
17  
19  
20  
21  
22  
23  
24  
EN  
Logic ground pin.  
LGND  
GIN  
Logic Ground  
LOW = True control signal for GOUT pin.  
Driver output 1 (right half of H-Bridge).  
Driver ground pin.  
Gate Driver Input  
Output 1  
OUT1  
PGND  
OUT2  
GOUT  
CRES  
C2H  
C2L  
Power Ground  
Driver output 2 (left half of H-Bridge).  
Output gate driver signal to external MOSFET switch.  
Pre-driver circuit power supply pin.  
Charge pump bucket capacitor 2 (positive pole).  
Charge pump bucket capacitor 2 (negative pole).  
Charge pump bucket capacitor 1 (positive pole).  
Charge pump bucket capacitor 1 (negative pole).  
Output 2  
Gate Driver Output  
Pre-Driver Power Supply  
Charge Pump 2H  
Charge Pump 2L  
Charge Pump 1H  
Charge Pump 1L  
C1H  
C1L  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 3. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent  
damage to the device.  
Rating  
Symbol  
Value  
Unit  
Motor Supply Voltage  
VM  
VCRES  
VDD  
-0.5 to 8.0  
-0.5 to 14.0  
-0.5 to 7.0  
V
V
V
V
A
Charge Pump Output Voltage  
Logic Supply Voltage  
Signal Input Voltage (EN, IN1, IN2, GIN)  
VIN  
-0.5 to V +0.5  
DD  
Driver Output Current  
Continuous  
IO  
1.0  
3.0  
Peak (1)  
IOPK  
ESD Voltage (2)  
Human Body Model  
Machine Model  
V
VESD1  
VESD2  
±1800  
±100  
Storage Temperature Range  
Operating Ambient Temperature  
Operating Junction Temperature  
Thermal Resistance (3)  
TSTG  
TA  
-65 to 150  
-20 to 65  
-20 to 150  
150  
°C  
°C  
TJ  
°C  
RθJA  
PD  
°C/W  
mW  
Power Dissipation (4)  
830  
Soldering Temperature (5)  
Peak Package Reflow Temperature During Reflow (6)  
Notes  
TSOLDER  
TPPRT  
260  
°C  
(7)  
°C  
,
Note 7  
1.  
T = 25°C, 10 ms pulse width at 200 ms intervals.  
A
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in  
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).  
3. 37 x 50 x 1.6 [mm] glass EPOXY board mount.  
4. Maximum at T = 25°C.  
A
5. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 4. Static Electrical Characteristics  
Characteristics noted under conditions TA = 25°C, VM = V = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted  
DD  
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
POWER  
Driver Circuit Power Supply Voltage  
Logic Supply Voltage  
V
2.0  
2.7  
5.0  
5.0  
0.1  
6.8  
5.7  
1.0  
V
V
M
V
DD  
Capacitor for Charge Pump  
C1, C2, C3  
0.01  
µF  
Standby Power Supply Current  
Motor Supply Standby Current  
I
V
MSTBY  
–
–
–
–
1.0  
1.0  
µA  
I
Logic Supply Standby Current (8)  
V
DDSTBY  
mA  
Operating Power Supply Current  
I
V
Logic Supply Current (9)  
DD  
–
–
–
–
3.0  
0.7  
mA  
mA  
I
C
RES  
Charge Pump Circuit Supply Current  
Low V  
Detection Voltage (10)  
V
DET  
1.5  
–
2.0  
2.5  
V
DD  
DD  
Driver Output ON Resistance (11)  
R
0.46  
0.60  
Ω
DS(ON)  
GATE DRIVE  
V
Gate Drive Voltage (12)  
No Current Load  
C
V
V
RES  
12  
10  
13  
13.5  
–
V
Gate Drive Ability (Internally Supplied)  
I
C
RESLOAD  
11.2  
C
= -1.0 mA  
RES  
Gate Drive Output  
V
V
V
V
C
-0.5  
C
-0.1  
C
RES  
I
l
= -50 µA  
RES  
RES  
V
OUT  
GOUTHIGH  
LGND  
LGND+0.1 LGND+0.5  
= 50 µA  
V
IN  
GOUTLOW  
CONTROL LOGIC  
Logic Input Voltage  
V
V
0
–
V
V
IN  
IH  
DD  
–
Logic Input Function (2.7 V < V  
High-Level Input Voltage  
Low-Level Input Voltage  
High-Level Input Current  
Low-Level Input Current  
< 5.7 V)  
DD  
V
x 0.7  
–
–
–
–
V
V
DD  
V
–
V
x 0.3  
DD  
IL  
I
–
1.0  
µA  
µA  
IH  
I
-1.0  
–
IL  
Pull-Up Resistance (EN, GIN)  
R
50  
100  
200  
kΩ  
PU  
Notes  
I
8.  
V
includes current to the predriver circuit.  
DDSTBY  
I
9.  
V
includes current to the predriver circuit.  
DD  
10. Detection voltage is defined as when the output becomes high-impedance after V  
drops below the detection threshold. When the  
DD  
V
V
gate voltage  
C
is applied from an external source,  
C
= 7.5 V.  
RES  
RES  
11. IO = 1.0 A source + sink.  
12. Input logic signal not present.  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 5. Dynamic Electrical Characteristics  
Characteristics noted under conditions TA = 25°C, VM = V = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted  
DD  
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
INPUT (EN, IN1, IN2, GIN)  
Pulse Input Frequency  
Input Pulse Rise Time (13)  
Input Pulse Fall Time (15)  
OUTPUT  
f
–
–
–
–
–
–
200  
kHz  
µs  
IN  
t
1.0 (14)  
1.0 (14)  
R
t
µs  
F
Propagation Delay Time  
Turn-ON Time  
µs  
µs  
tPLH  
tPHL  
–
–
0.55  
0.55  
1.0  
1.0  
Turn-OFF Time  
GOUT Propagation Delay Time  
Turn-ON Time  
tSON  
–
–
0.15  
0.15  
0.5  
0.5  
Turn-OFF Time  
tSOFF  
Charge Pump Circuit (16)  
Rise Time (17)  
tVCRESON  
ms  
ms  
–
–
0.1  
–
3.0  
10  
t
Low-Voltage Detection Time  
VDDDET  
Notes  
13. Time is defined between 10% and 90%.  
14. That is, the input waveform slope must be steeper than this.  
15. Time is defined between 90% and 10%.  
16. When C1 = C2 = C3 = 0.1 µF.  
17. Time to charge CRES to 11 V after application of VDD  
.
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
TIMING DIAGRAMS  
V
V
DDDETON  
DDDETOFF  
EN, IN1, IN2  
2.5 V/3.5 V  
50%  
50%  
(GIN)  
V
DD  
0.8 V/  
1.5 V  
t
PLH  
t
PHL  
SOFF  
t
t
(t  
)
(t  
)
SON  
V
DDDET  
V
DDDET  
90%  
10%  
90%  
OUT1, OUT2  
(GOUT)  
0%  
(<1.0 µA)  
IM  
Figure 6. Low-Voltage Detection  
OUTPUT  
Figure 5. tPLH, tPHL, and tPZH Timing  
Table 6. Truth Table  
INPUT  
EN  
H
H
H
H
L
IN1  
H
H
L
IN2  
H
L
GIN  
X
OUT1  
OUT2  
GOUT  
L
H
L
L
L
X
X
X
X
L
X
H
L
X
H
Z
L
L
X
Z
L
X
X
X
H
H
X
X
H
X
X
X
X
L
X
X
L
H
H = High.  
L = Low.  
Z = High impedance.  
X = Don’t care.  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
8
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 17511A is a monolithic H-Bridge power IC applicable  
to small DC motors used in portable electronics. The 17511A  
can operate efficiently with supply voltages as low as 2.0 V to  
as high as 6.8 V, and it can provide continuos motor drive  
currents of 1.0 A while handling peak currents up to 3.0 A. It  
is easily interfaced to low-cost MCUs via parallel 3.0 V- or  
5.0 V-compatible logic. The device can be pulse width  
modulated (PWM-ed) at up to 200 kHz. The 17511A has four  
operating modes: Forward, Reverse, Brake, and Tri-State  
(High Impedance).  
primary windings with a switched square wave to produce  
secondary winding AC currents.  
As shown in Figure 2, 17511A Simplified Internal Block  
Diagram, page 2, the 17511A is a monolithic H-Bridge with  
built-in charge pump circuitry. For a DC motor to run, the  
input conditions need to be set as follows: ENable input logic  
HIGH, one INput logic LOW, and the other INput logic HIGH  
(to define output polarity). The 17511A can execute dynamic  
braking by setting both IN1 and IN2 logic HIGH, causing both  
low-side MOSFETs in the output H-Bridge to turn ON.  
Dynamic braking can also implemented by taking the ENable  
logic LOW. The output of the H-Bridge can be set to an open-  
circuit high-impedance (Z) condition by taking both IN1 and  
IN2 logic LOW. (refer to Table 6, Truth Table, page 8).  
Basic protection and operational features (direction,  
dynamic braking, PWM control of speed and torque, main  
power supply undervoltage detection and shutdown, logic  
power supply undervoltage detection and shutdown), in  
addition to the 1.0 A rms output current capability, make the  
17511A a very attractive, cost-effective solution for  
controlling a broad range of small DC motors. In addition, a  
pair of 17511A devices can be used to control bipolar step  
motors. The 17511A can also be used to excite transformer  
The 17511A outputs are capable of providing a continuous  
DC load current of up to 1.2 A. An internal charge pump  
supports PWM frequencies to 200 kHz. The EN pin also  
controls the charge pump, turning it off when EN = LOW, thus  
allowing the 17511A to be placed in a power-conserving  
sleep mode.  
FUNCTIONAL PIN DESCRIPTION  
to the load attached between OUT1 and OUT2. All VM pins  
must be connected together on the printed circuit board with  
as short as possible traces offering as low impedance as  
possible between pins.  
OUT1 AND OUT2  
The OUT1 and OUT2 pins provide the connection to the  
internal power MOSFET H-Bridge of the IC. A typical load  
connected between these pins would be a small DC motor.  
These outputs will connect to either VM or PGND, depending  
on the states of the control inputs (refer to Table 6, Truth  
Table, page 8).  
VM has an undervoltage threshold. If the supply voltage  
drops below the undervoltage threshold, the output power  
stage switches to a tri-state condition. When the supply  
voltage returns to a level that is above the threshold, the  
power stage automatically resumes normal operation  
according to the established condition of the input pins.  
PGND AND LGND  
The power and logic ground pins (PGND and LGND)  
should be connected together with a very low-impedance  
connection.  
IN1, IN2, AND EN  
The IN1, IN2, and EN pins are input control pins used to  
control the outputs. These pins are 5.0 V CMOS-compatible  
inputs with hysteresis. The IN1, IN2, and EN work together to  
control OUT1 and OUT2 (refer to Table 6, Truth Table).  
CRES  
The CRES pin provides the connection for the external  
reservoir capacitor (output of the charge pump). Alternatively  
this pin can also be used as an input to supply gate-drive  
voltage from an external source via a series current-limiting  
resistor. The voltage at the CRES pin will be approximately  
three times the VDD voltage, as the internal charge pump  
utilizes a voltage tripler circuit. The VCRES voltage is used by  
the IC to supply gate drive for the internal power MOSFET  
H-Bridge.  
GIN  
The GIN input controls the GOUT pin. When GIN is set  
logic LOW, GOUT supplies a level-shifted high-side gate  
drive signal to an external MOSFET. When GIN is set logic  
HIGH, GOUT is set to GND potential.  
C1L AND C1H, C2L AND C2H  
VM  
These two pairs of pins, the C1L and C1H and the C2L and  
C2H, connect to the external bucket capacitors required by  
the internal charge pump. The typical value for the bucket  
capacitors is 0.1 µF.  
The VM pins carry the main supply voltage and current into  
the power sections of the IC. This supply then becomes  
controlled and/or modulated by the IC as it delivers the power  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
threshold. If the supply voltage drops below the undervoltage  
threshold, the output power stage switches to a tri-state  
condition. When the supply voltage returns to a level that is  
above the threshold, the power stage automatically resumes  
normal operation according to the established condition of  
the input pins.  
GOUT  
The GOUT output pin provides a level-shifted, high-side  
gate drive signal to an external MOSFET with C  
500 pF.  
up to  
ISS  
VDD  
The VDD pin carries the 5.0 V supply voltage and current  
into the logic sections of the IC. VDD has an undervoltage  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  
TYPICAL APPLICATIONS  
FUNCTIONAL PIN DESCRIPTION  
TYPICAL APPLICATIONS  
Figure 7 shows a typical application for the 17511A. When  
applying the gate voltage to the CRES pin from an external  
source, be sure to connect it via a resistor equal to, or greater  
V
than, RG  
=
C
/0.02 Ω.  
RES  
5.0 V  
17511A  
VDD VM  
GOUT  
V
NC C1L  
CRES < 14 V  
NC C1H  
NC C2L  
NC C2H  
V
RG  
> CRES/0.02 Ω  
CRES  
OUT1  
0.01 µF  
RG  
Motor  
EN  
Solenoid  
GIN  
IN1  
IN2  
OUT2  
GND  
MCU  
NC = No Connect  
Figure 7. 17511A Typical Application Diagram  
CEMF SNUBBING TECHNIQUES  
5.0 V  
5.0 V  
5.0 V  
5.0 V  
Care must be taken to protect the IC from potentially  
damaging CEMF spikes induced when commutating currents  
in inductive loads. Typical practice is to provide snubbing of  
voltage transients via placing a capacitor or zener at the  
supply pin (VM) (see Figure 8).  
17511A  
17511A  
VM  
V
DD  
VM  
V
DD  
C1L  
C1H  
C2L  
C2H  
C1L  
C1H  
C2L  
C2H  
OUT1  
OUT1  
CRES  
CRES  
OUT2  
OUT2  
GND  
GND  
Figure 8. CEMF Snubbing Techniques  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
PACKAGING  
PACKAGE DIMENSIONS  
PACKAGING  
PACKAGE DIMENSIONS  
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.  
EV (PB-FREE) SUFFIX  
16-PIN VMFP  
PLASTIC PACKAGE  
98ASH70109A  
ISSUE A  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
12  
PACKAGING  
PACKAGE DIMENSIONS  
PACKAGE DIMENSIONS (CONTINUED)  
EP (PB-FREE) SUFFIX  
24-LEAD QFN  
NON-LEADED PACKAGE  
98ARL10577D  
ISSUE A  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
PACKAGING  
PACKAGE DIMENSIONS  
PACKAGE DIMENSIONS (CONTINUED)  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
•
•
•
Implemented Revision History page  
Converted to Freescale format  
Added Peak Package Reflow Temperature During Reflow (solder reflow) parameter and Note with  
instructions from www.freescale.com to Maximum Ratings Table 3  
4/2007  
2.0  
17511A  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
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MPC17511A  
Rev 2.0  
4/2007