18730_06--Datasheet/数据表在线中文翻译

Document Number: MPC18730

Rev. 4.0, 8/2006

Freescale Semiconductor

Advance Information

Power Management IC with Five

Regulated Outputs

18730

Programmed Through 3-Wire

Serial Interface

POWER MANAGEMENT IC

The MPC18730 Power Management IC (PMIC) regulates five

independent output voltages from either a single cell Li-Ion (2.7 V to

4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to

2.2 V input range).

The PMIC includes 2 DC-DC converters and 3 low drop out (LDO)

linear regulators. The output voltage for each of the 5 output voltages

is set independently through a 3-wire serial interface. The serial

interface also configures the PMIC's versatile start-up control system,

which includes multiple wakeup, sleep, standby, and reset modes to

minimize power consumption for portable equipment.

EP SUFFIX (PB-FREE)

98ARL10571D

64-PIN QFN

In single cell Li-Ion applications two DC-DC converters are

configured as buck (step-down) regulators. In single cell Ni-MH or dry

cell applications, one DC-DC converter is configured as a boost

(step-up) regulator, and the other as buck-boost regulator. The DC-

DC converters' output voltages have set ranges 1.613 V to 3.2 V at

up to 120 mA, and 0.805 V to 1.5 V up to 100 mA.

ORDERING INFORMATION

Temperature

Package

Device

Range (T )

A

MPC18730EP/R2

-10°C to 65°C

64 QFN

Features

• Operates from single cell Li-Ion, Ni-MH, or Alkaline

• 2 DC-DC Converters

• 3 Low Drop Regulators

• Serial Interface Sets Output Voltages

• 4 Wake Inputs

• Low Current Standby Mode

• Pb-Free Packaging Designated by Suffix Code EP

MPC18730

VB

Programmable

1.613 V to 3.2 V

VBATT

VREF

VOUT1

VO1_SENSE

VO

SW1

Programmable

0.805 V to 1.5 V

VOUT2

PGOOD1

VGATE_EXT

VO2_SENSE

SW2

VO

SREGI1

Programmable

0.865 V to 2.8 V

SREGO1

PGOOD2

SREGI2

SREGO2

Programmable

0.011 V to 2.8 V

CONTROL

LOGIC

SREGI3

MCU

Programmable

2.08 V to 2.8 V

{

SREGO3

INPUTS

GND

VGATE

VB

GNDGATE

SWGATE

Figure 1. MPC18730 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

VMODE

VBATT

HVB

LVB

VBATT

LVB

Driver

VMODE

VO1_SENSE

PGOOD1(Int)

VREF

VO1_SENSE

PGOOD1(Int)

CLEAR

BANDGAP

REFERENCE

V_STDBY

VOUT1

VREF

VGATE

LSWO

PGOOD1(Int)

VO1_SENSE

POWER

SWITCH1

VO1_SENSE

VIN1

PGOOD1

VGATE

RESET

Block 1

REF1

Step-UpDown

DC/DC

PGOOD1_DELAY

Converter

CH1

SW1

RESET1_TH

EAIN1

PGND1

VOUT2

EAOUT1

VGATE

DMAX1

POWER

SWITCH2

PGOOD2(Int)

VGATE

VO1_SENSE

VO2_SENSE_IN

VO2_SENSE

PGOOD2(Int)

PGOOD2

RESET

Block 2

HG

REF2

LG

Step-UpDown

PGOOD2_DELAY

EAOUT2

DC/DC

Converter

CH2

VIN2

EAIN2

SW2

DMAX2

PGND2

SREGI1

VGATE

REF3

Series Pass

Regulator1

SREGC1

SREGO1

SREGI2

VGATE

SREGC2

SREGC3

Series Pass

Regulator2

REF4

V_STDBY

SREGO2

SREG2G

SREGI3

VGATE

VO1_SENSE

VBATT

WAKE1B

WAKE2B

Series Pass

Regulator3

REF5

WAKE3B

WAKE4B

SREGO3

VBATT

EXT_CLOCK

PGOOD1(Int)

PGOOD2

SEQ_SELECT

DATA

CH_PUMP

CPoff

STRB

VBATT

VGATE

CONTRO(LInt)

Control

Logic

SEQ_SELECT

SCKIN

VO1_SENSE

VGATE

CLEAR

SLEEP

Step-Up

DC/DC

Convertor

VG_SELECT

SWGATE

EXT_CLOCK

VGATE_DUTY

REF4

GNDGATE

GND

REF2

REF1

VGATE

REF3

REF5

VGATESEL1

VGATESEL2

EXT gate

On

VREF

VGATE_EXT

On

Buffer

REF DAC

WATCHDOG

Figure 2. MPC18730 Simplified Internal Block Diagram

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

SREGC2

49

1

CLEAR

50

48

64 63 62 61 60 59 58 57 56 55 54 53 52 51

WAKE4B

WAKE3B

WAKE2B

WAKE1B

LSWO

SREGI3

2

3

SREGO3

47

46

45

44

43

42

41

40

39

38

37

36

35

34

4

SREGC3

VGATE_EXT

LG

5

6

LVB

HG

7

HVB

8

VO2_SENSE

VO2_SENSE_IN

V_STDBY

VO1_SENSE

9

VOUT2

VIN2

10

11

12

13

14

15

16

TOP VIEW

VOUT1

VIN1

SW2

SW1

SW2

SW1

PGND2

PGND1

PGOOD2

19 20 21 22 23 24 25 26 27 28 29 30 31 32

18

17

PGOOD2_DELAY

33

Figure 3. MPC18730 Pin Connections

Table 1. MPC18730 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Function

Pin Number

Pin Name

Formal Name

Definition

Start-up Signal Input Latch/Clear

1

2

3

4

5

6

CLEAR

WAKE4B

WAKE3B

WAKE2B

WAKE1B

LSWO

Input

Output

Clear

Start-up Signal Input 4

Start-up Signal Input 3

Start-up Signal Input 2

Start-up Signal Input 1

Low-Side Switch Output Pin

Wake Signal 4

Wake Signal 3

Wake Signal 2

Wake Signal 1

Low-Side Switch

Output

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Table 1. MPC18730 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Function

Pin Number

Pin Name

Formal Name

Definition

VB Power Supply Connection for Ni_mh

VB Power Supply Connection for Li_ion

V_STDBY Voltage Output

7

8

LVB

HVB

Input

Low Voltage Battery

High Voltage Battery

Standby Voltage

9

V_STDBY

VO1_SENSE

Output

Input

Switching Power Supply Circuit 1, VO1_SENSE Voltage Input,

VO1_SENSE Power Supply

10

Voltage Input 1

Power Switch 1 Output

11

12

13

14

15

16

17

VOUT1

VIN1

Output

Power

Ground

Output

Voltage Output 1

Switching 1

Switching Power Supply Circuit 1 Output

Switching Power Supply Circuit 1 Coil Connection

Switching Power Supply Circuit 1 Power GND

Reset Circuit 1 Reset Signal Output

SW1

Switching 1

PGND1

PGOOD1

Power Ground 1

Inverted Reset

Output 1

Reset Circuit 1 Reset Signal Delaying Capacitor Connection

18

PGOOD1_DELAY

Input

Reset Delay

Capacitor 1

Switching Power Supply Circuit 1 Reset Voltage Reference Output

Switching Power Supply Circuit 1 Maximum Duty Setting

Switching Power Supply Circuit 1 Error Amp Output

19

20

21

RESET1_TH

DMAX1

Output

Power

Output

Reset1 Adjustment

Duty Control

EAOUT1

Reference Feedback

1

Switching Power Supply Circuit 1 Error Amp Inverse Input

22

23

EAIN1

Input

Input Minus 1

VGATE Power Supply Circuit Charge Pump Capacitor Connection

CH_PUMP

Power

Charge Pump

Capacitor

VGATE Power Supply Circuit Voltage Output, Pre-Diver Circuit Power

Supply

24

VGATE

Output

Gate Voltage

VGATE Power Supply Circuit Coil Connection

VGATE Power Supply Circuit Power GND

25

26

27

28

29

30

31

SWGATE

GNDGATE

VBATT

Power

Ground

Power

Output

Input

Switching

Power Ground 3

Battery Voltage

VGATE Select 2

VGATE Select 1

Input Minus

VB Power Supply Connection

VG Power Supply Circuit Output Voltage Setting 2

VGATE Power Supply Circuit Output Voltage Setting 1

Switching Power Supply Circuit 2 Error Amp Inverting Input

Switching Power Supply Circuit 2 Error Amp Output

VGATESEL2

VGATESEL1

EAIN2

EAOUT2

Output

Reference Feedback

2

Switching Power Supply Circuit 2 Maximum Duty Setting

Reset Circuit 2 Reset Signal Delay Capacitor Connection

32

33

DMAX2

Power

Input

Duty Control

PGOOD2_DELAY

Reset Delay

Capacitor 1

Reset Circuit 2 Reset Signal Output

34

PGOOD2

Output

Inverted Reset

Output 2

Switching Power Supply Circuit 2 Power GND

35

36

PGND2

Ground

Power Ground 2

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

PIN CONNECTIONS

Table 1. MPC18730 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Function

Pin Number

Pin Name

Formal Name

Definition

Switching Power Supply Circuit 2 Coil Connection

Switching Power Supply Circuit 2 Output

Power Switch 2 Output

37

38

39

40

41

42

43

SW2

Power

Output

Input

Switching

VIN2

Voltage Output

Voltage Input

VOUT2

Power Switch 2 Voltage Input

VO2_SENSE_IN

VO2_SENSE

HG

Switching Power Supply Circuit 2 VO2_SENSE Voltage Input

Input

Voltage Input

Switching Power Supply Circuit 2 Step down Top side FET Gate

Output for Ni_mh

Output

Step Down Top FET 2

Switching Power Supply Circuit 2 Step down Bottom side FRT Gate

Output for Ni_mh

44

LG

Output

Step Down Bottom

FET 2

External Transistor Gate Signal Output

45

46

47

48

49

50

VGATE_EXT

SREGC3

SREGO3

SREGI3

Output

Power

Output

Power

Output

Gate Switch

Series Pass Power Supply Circuit 3 External Feedback Connection

Series Pass Power Supply Circuit 3 Output

Regulator Capacitor 3

Regulator Output 3

Regulator Input 3

Series Pass Power Supply Circuit 3 Power Supply

Series Pass Power Supply Circuit 2 External Feedback Connection

SREGC2

SREG2G

Regulator Capacitor 2

Series Pass Power Supply Circuit 2 External Transistor Gate Signal

Output

Regulator Gate

Output 2

Series Pass Power Supply Circuit 2 Output

Series Pass Power Supply Circuit 2 Power Supply

Series Pass Power Supply Circuit 1 External Feedback Connection

Series Pass Power Supply Circuit 1 Output

Series Pass Power Supply Circuit 1 Power Supply

GND

51

52

53

54

55

56

57

58

59

60

61

62

63

64

SREGO2

SREGI2

SREGC1

SREGO1

SREGI1

GND

Output

Power

Output

Power

Ground

Output

Input

Regulator Output 2

Regulator Input 2

Regulator Capacitor 1

Regulator Output 1

Regulator Input 1

Ground

Reference Voltage Output

VREF

Reference Voltage

Data Signal

Serial Interface Data Signal Input

DATA

Serial Interface Strobe Signal Input

Serial Interface Clock Signal Input

Watchdog Timer Capacitor Connection

Start-Up Sequence Setting Input

STRB

Input

Strobe

SCKIN

Input

Serial Clock

WATCHDOG

SEQ_SELECT

EXT_CLOCK

SLEEP

Input

Watch Dog Timer

Sequence Input

Clock Input

Input

External Synchronous Clock Signal Input

Sleep Signal Input

Input

Sleep Signal

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

Analog Signal Input ⁽¹⁾

V_BATT

V_INAN

-0.5 to 5.0

V

-0.5 to VO1+0.5

Logic Signal Input

WAKE1~4B

V_ILRSTB

V_ILGC

-0.5 to V_STDBY+0.5

-0.5 to VO1_SENSE+0.5

-0.5 to VBATT+0.5

CLEAR, SLEEP, EXT_CLOCK, SCKIN, DATA, STRB

VGATESEL1,2

V_ILGSEL

Output Power Current

mA

VOUT1 Power Supply Circuit ⁽²⁾

VOUT2 Power Supply Circuit

SREG1 Power Supply Circuit

SREG2 Power Supply Circuit

SREG3 Power Supply Circuit

VGATE Power Supply Circuit

PGOOD1 Power Supply Circuit

I_OVO1

I_OVO2

120

100

80

I_OREG1

I_OREG2

I_OREG3

I_OVG

100

80

8

I_OPGOOD1

-20

Open-Drain Output Apply Voltage

V

PGOOD1

LSWO

V_IODR

V_IODV

-0.5 to 3.3

ESD Voltage ⁽³⁾

Human Body Model (HBM)

Machine Model (MM)

Charge Device Model (CDM)

V

±1500

± 200

± 750

ESD1

ESD2

V_CDM

THERMAL RATINGS

Operating Temperature

Ambient

°C

T

-10 to 65

150

A

Junction

T

J

Storage Temperature

T_STG

-50 to 150

69

°C

Thermal Resistance ⁽⁴⁾

Junction to Ambient

R

°C/W

θJA

Lead Soldering Temperature⁽⁵⁾

T

260

°C

SOLDER

Notes

1. VREF, DMAX1, DMAX2, SREGC1, SREGC2, SREGC3 and RESET1_TH.

2. Includes the series pass power supply circuit output current

3. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω), the Machine Model (MM)

(C_ZAP= 200 pF, R_ZAP= 0 Ω), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0pF).

4. Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7.

5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

STATIC

Table 3. Static Electrical Characteristics

Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, f_CLK= 176.4 kHz unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 27°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

GENERAL

VB Power Supply Voltage

Power Supply Voltage 1

Power Supply Voltage 2

V

V_LVB

V_HVB

0.9

2.7

1.2

3.5

2.2

4.2

Series Regulator Input Voltage ^{(6), (7)}

V_SREGI

V_BST

V_SREG+0.2⁽⁸⁾

V_SREG+0.3

V_SREG+0.4

-

V

Start-Up Voltage

0.9

0

-

Analog Signal Input ⁽⁹⁾

V_IANA

VO1_SENSE

Logic Signal Input

WAKE1~4B

V_ILRSTB

V_ILGC

0

-

V_STDBY

VO1_SENSE

VBATT

CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN

VGATESEL1, 2

V_ILGSEL

Output Power Current

mA

VOUT1 Power Supply Circuit ⁽¹⁰⁾

I_OVOUT1

I_OVOUT2

I_OSREG1

I_OSREG2

I_OSREG3

I_OVG

0

-

100

80

60

80

60

6.0

0

VOUT2 Power Supply Circuit ⁽¹⁰⁾

SREG1 Power Supply Circuit

SREG2 Power Supply Circuit

SREG3 Power Supply Circuit

VGATE Power Supply Circuit

PGOOD

5.0

6.0

5.0

-5.0

-

I_OPGOOD

Supply Current in Stand-by mode

VB Supply Current (VB = 1.2 V for Ni_MH)

(HVB = 3.5 V for Li-Ion)

µA

I_BSNi

I_BSLi

-

5.0

8.0

10

12

Supply Current in Operating mode

VB Supply Current (VB = 1.2 V for Ni_MH)

(HVB = 3.5 V for Li-Ion)

mA

I_BNi

I_BLi

-

9.0

7.0

18

14

Reference Power Supply Circuit

Output Voltage

V_REF

1.255

-0.3

1.275

-

1.295

0.3

V

Output Current

I_OREF

mA

Switching Power Supply 1

V_OUT1

2.3

2.4

2.5

V

VOUT1 Output Voltage (I_o= 0~100 mA)

Notes

6. When applying voltage from an external source.

7. 0.3 V when VGATE is 4.5 V.

8. Provide 2 V or higher for the voltage difference (VGATE - VO1_SENSE).

9. VREF, DMAX1, DMAX2, SREGC1, SREGC2, SREGC3 and RESET1_TH.

10. Includes the series pass power supply circuit output current.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, f_CLK= 176.4 kHz unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 27°C under nominal conditions unless

otherwise noted.

Characteristic

Switching Power Supply 2

Symbol

Min

Typ

Max

Unit

V

VOUT2 Output Voltage (I_o= 0~80 mA)

V_OUT2

V_DW2TH

V_DW2TL

V_DW2BH

V_DW2BL

1.05

5.2

0

1.15

1.25

VGATE

0.3

HG Output Voltage ⁽¹¹⁾(I_source= 400 µA)

(I_sink= 400 µA)

-

5.2

0

VGATE

0.3

LG Output Voltage ⁽¹¹⁾(I_source= 400 µA)

(I_sink= 400 µA)

Series Pass Power Supply Circuit

SREG1 Control Voltage (I_o= 5~60 mA) ⁽¹²⁾

V_SREG1

SR1OFST

V_SREG2

2.7

-13.5

2.7

-17

2.7

-11

5.0

0

2.8

2.9

24.5

2.9

V

mV

V

-

SREG1-Error AMP Input offset voltage ⁽¹³⁾

SREG2 Control Voltage (I_o= 6~80 mA) ⁽¹²⁾

2.8

SR2OFST

V_SREG3

-

17

mV

V

SREG2-Error AMP Input offset voltage ⁽¹⁴⁾

SREG3 Control Voltage (I_o= 5~60 mA) ⁽¹²⁾

2.8

2.9

SR3OFST

SREG2GH

SREG2GL

-

23

mV

V

SREG3-Error AMP Input offset voltage ⁽¹⁵⁾

SREG2G Output Voltage ⁽¹⁶⁾(I_source= 2.5 µA)

(I_sink= 2.5 µA)

VGATE

0.5

V

Power Switch On Resistance

VOUT1 Circuit

W

V

R_VOUT1

R_VOUT2

-

0.4

0.6

VOUT2 Circuit

VGATE Power Supply Circuit

(I_o= 0~6 mA) ⁽¹⁷⁾

V_{GATE_00}

V_{GATE_10}

5.5

6.0

6.5

5.4

4.6

5.0

(I_o= 0~6 mA) ⁽¹⁸⁾

V_{O1_SENSE1LH}

V_{O1_SENSE_1LL}

V_GH

VB x 0.85

-

VB

CH_PUMP Output Voltage (I_source= 2.5 mA)

(I_sink= 2.5 mA)

0

-

0.4

10.5

VGH Voltage (Certified value)

V_STDBY Output Voltage for Li_ion (I_o= 300 µA) ⁽¹⁹⁾

V_LVB

1.75

-

2.45

V

Notes

11. Connect a transistor with gate capacity of 200 pF or smaller to HG and LG

12. If a capacitor with capacitance of 22 µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC

when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is

connected as follows:

SREGI1 = 3.0 V to 3.3 V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.

SREGI2 = 3.0 V to 3.3 V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.

SREGI3 = 3.0 V to 3.3 V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.

13. Calculated by the right formula for input offset: SR1OFST = (Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k))

14. Calculated by the right formula for input offset: SR2OFST = (Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k))

15. Calculated by the right formula for input offset: SR3OFST = (Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k))

16. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.

17. When VGATESEL1 is Low and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.

18. When VGATESEL1 is High and VGATESEL2 is Low, I/O = 3 mA or higher is certified by specification.

19. When HVB is 4.2 V and the load from V_STDBY is 0.5 µA or higher.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

STATIC

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE= 6.0 V, f_CLK= 176.4 kHz unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 27°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Reset Circuit

Reset Voltage 1

V_RST1

V_RST2

0.85 x

0.88 x

0.91 x

V

VO1_SENSE VO1_SENSE VO1_SENSE

0.80 x 0.85 x 0.90 x

VO1_SENSE VO1_SENSE VO1_SENSE

Reset Voltage 2

Hysteresis Voltage 1 (@RST1)

Hysteresis Voltage 2 (@RST2)

PGOOD (V_PGOOD= 2.4 V)

V_HYRS1

V_HYRS2

40

50

0

78

75

-

115

100

10

mV

µA

V

I_PGOOD1,2

V_PGOOD1,2

V_OLCR1,2

V_IHCR1,2

V_ILCR1,2

(I_sink= 2 mA)

0

-

0.5

PGOOD_DELAY (I_sink= 100 µA)

0

-

0.7

V

High Level Threshold Voltage

Low Level Threshold Voltage

PGOOD_DELAY Pull-Up Resistance

1.25

0.75

50

1.42

1.00

100

1.65

1.15

150

V

R_PUPRC1,2

KΩ

V_STDBY Output Resistance

Output Resistance (VO1_SENSE)

Output Resistance (VBATT)

W

R_{VO1_SENSE}

R_VB

-

30

45

200

400

LSWO Output Resistance

Output Resistance

R_LSWO

-

42

50

W

V

VGATE_EXT

VGATE_EXT Output Voltage (I_source= 100 µA)

(I_sink= 100 µA)

V_OHEXTG

V_OLEXTG

VGATE x 0.9

0

-

VGATE

VGATE x 0.1

Logic Input

"H" Level Input Voltage ⁽²⁰⁾

"L" Level Input Voltage ⁽²⁰⁾

"H" Level Input Voltage ⁽²¹⁾

"L" Level Input Voltage ⁽²¹⁾

"H" Level Input Voltage ⁽²²⁾

"L" Level Input Voltage ⁽²²⁾

"H" Level Input Current ^{(20), (22)}

"L" Level Input Current ^{(22), (23)}

Pull Up Resistance ⁽²⁴⁾

V_IHVS

V_ILVS

V_IH

V_STDBY - 0.2

-

V

-

1.5

-

0.2

-

V

V_IL

-

0.4

-

V

V_IHVB

V_ILVB

I_IH

VB - 0.2

-

V

-

0.2

1.0

770

625

V

-1.0

410

330

µA

KΩ

I_IL

-

R_PUP

R_PDW

590

480

Pull Down Resistance ⁽²⁵⁾

Notes

20. Applied to WAKEB1 ~ 4 and SEQ_SELECT.

21. Applied to CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN.

22. Applied to VGATESEL1 and 2.

23. Applied to WAKEB1 ~ 3, CLEAR, SLEEP, EXT_CLOCK, DATA, STRB, SCKIN and SEQ_SELECT.

24. Applied to WAKEB4.

25. Applied to CLEAR, SLEEP, EXT_CLOCK, DATA, STRB and SCKIN.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

DYNAMIC

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions VBATT = 1.2 V, VO1_SENSE = 2.4 V, VGATE = 6.0 V, f_CLK= 176.4 kHz unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 27°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OSCILLATOR

Internal Oscillation Frequency

f_ICK

150

-

200

250

-

kHz

MICRO CONTROLLER INTERFACE

Clock Signal Input ⁽²⁶⁾

f_CLK

176.4

Serial Interface (Refer to Figure 5, Serial Interface Timing Diagrams)

DATA Set Up Time

t_s

20

-

nsec

MHz

nsec

DATA Hold Time

t_h

-

SCKIN Clock Frequency

SCKIN 'H' Pulse Width

f_sck

t_wckh

t_wckl

t_hck

t_ssb

t_wsb

6.0

50

-

SCKIN 'L' Pulse Width

SCKIN Hold Time

STRB Set Up Time

STRB Pulse Width

Notes

26. Duty 50%.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

WAKE1~4(int)

EXT_CLOCK

V_STDBY

VBATT

INT

EXT(Serial setting)

VO1_SENSE

VBATT

VGATE

VBATT

VO1_SENSE

PGOOD1(Int)

PGOOD_DELAY set value

VO1_SENSE

PGOOD1

VBATT

VO1_SENSE

VOUT1

VO1_SENSE

VO2_SENSE

VOUT2

VO1_SENSE

PGOOD2(Int)

PGOOD_DELAY set value

VO1_SENSE

PGOOD1

SREG1~3

SEQ_SELECT setting

DATA

STRB

SEQ_SELECT setting

CLEAR

SLEEP

Standby Mode

Start-Up

Operation Mode

Standby Mode

*1: When using Ni_mh. High-Z when using Li_ion.

Figure 4. Power Supply Start-Up Timing Diagram

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

t

WCKL

t

SSB

WCKH

HCK

SCKIN

t

H

S

A2

DATA

STRB

D0

A3

t

WSB

Figure 5. Serial Interface Timing Diagrams

DATA1

Table 5. Serial Interface Functions

Register Name Address

DATA2

0 CLEAR, SLEEP 1000

CLEAR

PSW1

SLEEP

PSW2

Reserved

PGOOD1

Reserved

VOUT2

Reserved

SREG1

Reserved

SREG2

Reserved

SREG3

Reserved

PGOOD2

1

2

3

4

5

6

7

Power Mode

Clock Select

VO1_SENSE

VO2_SENSE

SREG1

0001

0010

0011

0100

0101

0110

0111

Ext / Int Half Freq RSTB sleep S_Off_VGATE VG_Duty[3] VG_Duty[2] VG_Duty[1]

VG_Duty[0]

S_Off_VO1_SENSE

S_Off_VO2_SENSE

Reserved

MSB

VO1_SENSE Output Voltage

VO2_SENSE Output Voltage

SREG1 Output Voltage

LSB

SREG2

SREG2 Output Voltage

LSB

SREG3

SREG3 Output Voltage

LSB

CP Off

EXTG On

Twelve bits immediately before start-up of STRB are

always effective. Upon power on, the internal power on reset

works to initialize the registers. Serial data is fetched in the

order of Add_[3], Add_[2], ..., Add_[0], DATA1_[3],

DATA1_[2], ...., DATA2_[0].

Table 6. Block Operation

INPUT

OUTPUT

WAKE

(Int)

PGOOD1

(Int)

REG

1,2,3

PGOOD1

PGOOD2(Int)

SEQ_SELECT

VGATE

VO1_SENSE

VO2_SENSE

VOUT1,2

L

X

L

X

L

X

L

X

L

-

H

O

H

L

-

O

-

L

H

L

-

H

O

H

O : Operation, - : Stop, X : Don’t care

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Table 7. Start-Up Sequence Settings

SEQ_SELE

CT

CLEAR/

SLEEP

Series Regulators

V_STDBY

GND

PGOOD2(Ext)

PGOOD1(Ext)

PGOOD2(Int)

PGOOD1(Int)

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 18730 power management integrated circuit provides

five independent output voltages for the micro controller from

either a single cell Li-Ion or from a single cell Ni-MH or dry

cell. The PMIC includes two DC to DC converters and three

low drop out linear regulators. The output voltage for each of

the five output voltages is set independently through a 3-wire

serial interface. The PMIC has multiple wakeup, sleep, and

reset modes to minimize power consumption for portable

equipment. In single cell Li-Ion applications two DC-DC

converters are configured as buck regulators. In single cell

Ni-MH or dry cell applications, one DC-DC converter is

configured as a boost regulator, and the other as buck-boost

regulator.

FUNCTIONAL PIN DESCRIPTION

Channel-1 or Channel-2 DC/DC converter as

‘VO1_SENSEor VO2_SENSE.

CLEAR PIN (CLEAR)

This Clear input signal makes clear internal latches for

WAKE signal holding. The WAKE control circuit can not

receive another WAKE input until the latch is cleared by this

Clear input.

VOLTAGE OUTPUT PINS (VOUT1, VOUT2)

Output ‘VO1_SENSE or ‘VO2_SENSE’ voltage controlled

internal power switch.

WAKE SIGNAL PINS (WAKE1B, WAKE2B,

WAKE3B, WAKE4B) ... ACTIVE LOW

POWER INPUT PINS (VIN1, VIN2)

Any one WAKE input signal of these four WAKE inputs

awakes this device from sleep mode. The WAKE signals can

be made with external low side mechanical switch and

resistance that is pulled up to VSTB rail.

The power input pins (VIN1, VIN2) are drain pins on the

top side FET of the DC/DC converter switcher. They are the

power input for the buck converter and output for the boost

converter.

LOW-SIDE SWITCH OUTPUT PIN (LSWO)

SWITCHING PINS (SW1, SW2)

Low-Side switch output that is turned on with ‘CLEAR’

signal. It can be used for external key input latches clear.

Switching Pins (SW1, SW2) are the output of the half

bridge and connect to the external inductance.

LOW VOLTAGE BATTERY PIN (LVB)

POWER GROUND PINS (PGND1, PGND2,

GNDGATE)

This input pin is used for temporarily power supply while

wake up for 1cell Ni-MH battery or 1 cell dry cell battery (=

Low Voltage Battery) use. It has to be connected to VB rail.

When Li-Ion battery is used, the pin has to be open.

Ground level node for DC/DC converter and Charge Pump

portion.

INVERTED RESET OUTPUT PINS (PGOOD1,

PGOOD2)

HIGH VOLTAGE BATTERY PIN (HVB)

This input pin is used for temporarily power supply while

wake up for Li-Ion battery (= High Voltage Battery) use. It has

to be connected to the VB rail. When a Ni-MH battery is used,

the pin has to be connected to ground level.

Reset signal output for external MPU or the something

controller. PGOOD1 keeps ‘Low’ level while the

VO1_SENSE voltage is less than internal reference voltage.

PGOOD2 follows to VO2_SENSE voltage.

STANDBY VOLTAGE PIN (V_STDBY)

RESET DELAY CAPACITOR PINS

Standby Voltage is made from LVB or HVB that depends

on which battery is used. This voltage is used for internal

logic and analog circuit at standby (sleep) mode temporarily

before ‘VO1_SENSE’ voltage is established.

(PGOOD1_DELAY, PGOOD2_DELAY)

The capacitor connected to this pin decides delay time to

negate the Reset signal from exceeding the reference

voltage level.

VOLTAGE INPUT PINS (VO1_SENSE, VO2_SENSE)

RESET 1 ADJUSTMENT PIN (RESET1_TH)

This power supply input pin named ‘VO1_SENS or

VO2_SENSE’ is for internal logic and analog circuits and for

input of ‘VOUT1’ output via power switch. Input for ‘VOUT2’

is ‘VO2_SENSE_IN’ pin. It is supplied from the output of

Used to adjust the reset level with external resistance

which is connected to VO1_SENSE for PGOOD1.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

DUTY CONTROL PINS (DMAX1, DMAX2)

REGULATOR CONTROL PINS (SREGC1, SREGC2,

SREGC3)

Connected external voltage to this pin via capacitance can

control the duty of DC/DC converter switching. Use of the pin

for this is not recommended.

Feed back pin for each series regulators. This pin voltage

is compared with internal reference voltage. Input the feed

back voltage that divided SREGO voltage by resistances.

REFERENCE FEEDBACK PINS (EAOUT1, EAOUT2)

REGULATOR OUTPUT PINS (SREGO1, SREGO2,

SREGO3)

Output node of internal error amp. for DC/DC converter 1

and 2. Used for phase compensation.

Series regulator output pins. All output voltages can be

variable with internal DAC via serial I/F.

INPUT MINUS PINS (EAIN1, EAIN2)

Minus input of internal error amp. for DC/DC converter 1

and 2. Used for phase compensation.

REGULATOR INPUT PINS (SREGI1, SREGI2,

SREGI3)

CHARGE PUMP CAPACITOR PIN (CH_PUMP)

Series regulator power input pins. To be connected to

battery voltage in general.

In case of use higher voltage than VGATE externally,

connect capacitance and diodes between VGATE. The

charge pump structure can output VGATE + VB - 2 x VF

voltage. There is no meaning for Ni-MH or dry cell battery,

because the VB voltage is almost same as 2 x VF voltage.

Recommend to use for Li-Ion battery use.

GROUND PIN (GND)

Ground pin for logic and analog circuit portion (not power

portion). Recommend to connect to clean ground which

separated with power ground line.

GATE VOLTAGE PIN (VGATE)

REFERENCE VOLTAGE PIN (VREF)

Output pin of boost converter for gate drive voltage. The

output voltage is decided by VGSEL input.

Output of internal reference voltage. It can be used

externally. Output current capacity is less than 300 µA.

SWITCHING FOR GATE VOLTAGE PIN (SWGATE)

DATA INPUT PIN (DATA)

Switching pin for VGATE boost converter. Connect to

external inductance.

Serial data input pin for the serial interface. The last 12 bits

received before the strobe signal’s low to high transition are

latched.

BATTERY VOLTAGE PIN (VBATT)

Power supply input that connects to Ni-MH or Dry cell or

Li-Ion battery.

STROBE PIN (STRB)

Strobe signal input pin for serial interface. It latches the 12

bits of data input to the internal control registers.

VGATE SELECT PINS (VGATESEL1, VGATESEL2)

VGATE output voltage is decided with these two bits input.

SERIAL CLOCK PIN (SCKIN)

Clock input pin for serial interface. Input data are taken in

to I/F with this clock.

VOLTAGE INPUT FOR POWER SWITCH 2 PIN

(VO2_SENSE_IN)

WATCH DOG TIMER PIN (WATCHDOG)

Input of VOUT2 output via power switch. Connect to

VO2_SENSE pin externally.

Watch dog timer prevent unstable wake up (flips between

wake-up and failure). If there is no ‘CLEAR’ input after any

WAKEnB input before this WATCHDOG is expired, this

device moves to ‘SLEEP’ mode to prevent wake failure

hanging-up situation.

STEP DOWN FET GATE DRIVE PINS (HG, LG)

Gate drive output pins for external FETs to use DC/DC

converter 2 as Buck / Boost converter.

SEQUENCE SELECT PIN (SEQ_SELECT)

GATE SWITCH PIN (VGATE_EXT)

Select judgement Reset channel for wake-up complete

with this input. If this input level is V_STDBY voltage, this

device judges the wake-up completion with Reset2 (DC/

DC2). If it is Ground, judge with Reset1 (DC/DC1). See

Table 7, on page 13.

Gate drive output pin for external low side switch. It can be

used for power switch turning On/OFF for remote controller

part.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

CLOCK INPUT PIN (EXT_CLOCK)

SLEEP MODE PIN (SLEEP)

Clock input pin for internal switching part. This device has

a oscillator internally, but can use this input clock for internal

switching frequency. It is selected by Clock select bit. See

Table 19, on page 25.

The sleep input signal puts the device in sleep mode. All

output voltages are down, and internal current consumption

will be minimum.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

If SLEEP goes High to place the chip into the standby

mode while any of the WAKEB pins is Low, the chip can be

awakened again. This may happen if, when an WAKEB pin

and LSWO are connected, SLEEP goes High earlier than the

period of time (*1) specified by the external component of the

WAKEB pin.

START-UP CONTROL INPUT (SYSTEM CONTROL)

The latch is set at the rising edge of any WAKE1B-4B input

pin, and WAKE(int) goes High. WAKE1~4B inputs consist of

OR logic. At this time, the input pin which went Low keeps

latched until CLEAR goes High. After the latch is reset by

CLEAR, WAKE(int) goes Low when SLEEP goes High. The

latch is also cleared and WAKE(int) goes Low when SLEEP

goes High before the latch is cleared by CLEAR. In this case,

CLEAR keeps negated while PGOOD1, 2(Ext) is Low.

SLEEP keeps negated while PGOOD1, 2(Ext) is Low or

CLEAR is High. The period of time for which CLEAR and

SLEEP are negated can be set by the SEQ_SELECT pin.

Refer to Truth Table 5, on page 12 for the correspondence

between the SEQ_SELECT pin settings and negation period.

Also, if the period of time after WAKE(int) goes High until

CLEAR goes High from Low is longer than the time specified

by WATCHDOG, internal sleep will start up to place the chip

into the standby mode.

(*1: It is 30 µsec when a capacitor is not connected as the

external component.)

WAKEB

CLEAR

Time specified by WATCHDOG

WATCHDOG

WAKE(Int)

Figure 6. Start-Up Timing Diagram

STANDBY POWER SUPPLY CIRCUIT

LSWO

Short-circuit VBATT and LVB, and connect a

Schottky diode between VBATT and V_STDBY

only when using Ni_mh.

CLEAR

VBATT

VO1_SENSE

VBATT

LVB

HVB

Standby

Power

Supply

Control

PGOOD1

PGOOD1(Int)

V_STDBY

When using Li_ion, leave LVB open, and short-

circuit HVB and VBATT.

V_STDBY

Figure 7. Standby Power Supply Circuit Diagram

When PGOOD1(int) is Low, output LVB voltage to

V_STDBY pin. When PGOOD1(int) is High, output

VO1_SENSE voltage to V_STDBY pin. When CLEAR is Low,

LSWO is open. When PGOOD1(int) is High and CLEAR is

High, LSWO output voltage turns GND. When PGOOD1(int)

is Low and PGOOD1 is High, discharge the external

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

capacitor which is connected to V_STDBY. When using

Ni_mh, short-circuit VBATT and LVB to external components

and HVB to GND. When using Li_ion, short-circuit HVB to

VBATT, and leave LVB open. When using Ni_MH, the VB

voltage is output from V_STDBY in Standby mode. When

using Li-Ion, 50% of the VBATT voltage is output to

V_STDBY pin in Standby Mode.

Table 8. HVB and LVB Connection

MODE

HVB

LVB

Li_ion

Ni_mh

VBATT⁽²⁷⁾

GND

open

VBATT⁽²⁷⁾

Notes

27. Externally connect to VBATT.

Table 9. V_STDBY and LSWO Operation

INPUT

OUTPUT

V_STDBY

WAKE(Int)

PGOOD2(Int)

CLEAR

LSWO

L

H

X

L

X

L

VBATT

Z

L

H

VO1_SENSE

H

Z : High Impedance, X : Don’t care

RESET CIRCUIT

PGOOD1_DELAY,

PGOOD2_DELAY

VO1_SENSE

VO1_SENSE,

VO2_SENSE

VGATE

PGOOD1, 2

RESET1_TH

VO1_SENSE

Reset

Control

PGOOD1_DELAY,

PGOOD2_DELAY

(PGOOD1 side only)

BANDGAP

REFERENCE

PGOOD1, 2B(Int)

Figure 8. Reset Circuit Block Diagram

When the VO1_SENSE or VO2_SENSE voltage is higher

than the reference value, PGOOD1 or 2B goes High. When

PGOOD1(int) is Low and PGOOD1 is High, SLEEP(int) is

forced to place the chip into the standby mode.

Connect the capacitor between RESET1_TH and PGOOD

as directed below.

When SEQ_SELECT is Low:Between RESET1_TH and

PGOOD1_DELAY

Connect a capacitor between RESET1_TH and

PGOOD_DELAY. The capacitor is not necessary if a resistor

of 330KΩ or less is inserted between RESET1_TH and

VO1_SENSE for reset adjustment

When SEQ_SELECT is High:Between RESET1_TH and

PGOOD2_DELAY

Use a capacitor with approximately half of the capacitance

between PGOOD_DELAY and GND

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

PGOOD1(Int)

PGOOD1

SLEEP(Int)

Figure 9. Reset Timing Diagram

The VBATT voltage rises or falls and is output to VIN2.

When PGOOD2(int) is High, the power switch turns ON to

output the VO2_SENSE_IN voltage to VOUT2. If you turn

DDC2 OFF using the register, the power switch 2 also turns

OFF. Capacitance value which is connected to

VO2_SENSE_IN should be higher than the capacitor

connected to VOUT2.

POWER SUPPLY VO1_SENSE, VO2_SENSE:

NI_MH

The VBATT voltage rises and is output to VIN1. When

PGOOD2(int) is High, the power switch turns ON to output

the VO1_SENSE voltage to VOUT1. Capacitance value

which is connected to VO1_SENSE should be higher than

the capacitor connected to VOUT1.

Table 10. Output Voltage of VO1_SENSE

(28)

Address: 0011

B7

B6

B5

B4

B3

B2

B1

S_Off_VO1_SENSE

VO1_SENSE [V]⁽²⁹⁾

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

X

1.613

1.625

1.638

1.663

1.713

1.813

2.013

2.413

2.425

2.438

2.463

2.513

2.613

2.813

3.200

L

H

Notes

28. All combinations of input are not included.

29. Operation is not guaranteed when VO1_SENSE input voltage is 1.8 V or lower. By connecting a diode between VIN1

and VO1_SENSE, VIN1 can output voltage higher (with the voltage difference Vf) than VO1_SENSE.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 11. Output Voltage of VO2_SENSE

Address: 0100⁽³³⁾

B7

B6

B5

B4

B3

B2

B1

S_Off_VO2_SENSE

VO2_SENSE [V]

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

X

0.805

0.811

0.816

0.827

0.849

0.893

0.980

1.155

1.161

1.166

1.177

1.199

1.243

1.330

1.500

L

H

Notes

30. All combinations of input are not included

ON to output the VO2_SENSE_IN voltage to VOUT2. If you

turn DDC2 OFF using the register, the power switch 2 also

turns OFF. Capacitance value which is connected to

VO2_SENSE_IN should be higher than the capacitor

connected to VOUT2.

POWER SUPPLY VO1_SENSE, VO2_SENSE:

LI-ION

The VBATT voltage falls and is output to VO1_SENSE.

When using Li_ion, duty limit due to DMAX1 is not applied to

the switch. When PGOOD2(int) is High, the power switch

turns ON to output the VO1_SENSE voltage to VOUT1.

Capacitance value which is connected to VO1_SENSE

should be higher than the capacitor connected to VOUT1.

SERIES PASS POWER SUPPLY

The series pass outputs the SREGI1 voltage to SREGO1,

the SREGI2 voltage to SREGO2, and the SREGI3 voltage to

SREGO3. If you use MOSFET as the external component in

this case, connect the gate to SREG2G.

The VBATT voltage falls using only the internal transistor

and is output to VO2_SENSE. When using Li_ion, duty limit

due to DMAX2 is not applied to the switch, and HG and LG

are Low. When PGOOD2(int) is High, the power switch turns

Table 12. Output Voltage of SREG1

Address: 0101⁽³¹⁾

B7

B6

B5

B4

B3

B2

B1

Reserved

SREG1 [V]⁽³³⁾

L

H

L

H

L

H

L

H

L

H

L

H

0.865

0.880

0.895

0.926

0.986

1.107

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 12. Output Voltage of SREG1

Address: 0101⁽³¹⁾

B7

B6

B5

B4

B3

B2

B1

Reserved

SREG1 [V]⁽³³⁾

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

1.349

1.833

1.848

1.863

1.893

1.954

2.075

2.317

2.800

H

Notes

31. All combinations of input are not included.

32. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to

SREGC1 and 3 (65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND,

73.84KΩ between SREGO3 and SREGC3, and 26.16KΩ between SREGC3 and GND).

Table 13. Output Voltage of SREG2

Address: 0110⁽³³⁾

B7

B6

B5

B4

B3

B2

B1

B0

SREG2 [V]

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

0.011

0.022

0.033

0.055

0.098

0.186

0.361

0.711

1.411

1.422

1.433

1.455

1.498

1.586

1.761

2.111

2.800

L

H

Notes

33. All combinations of input are not included.

Table 14. Output Voltage of SREG3

Address: 0111⁽³⁴⁾

B7

B6

B5

B4

B3

B2

CP Off

EXTG On

SREG3 [V]⁽³⁵⁾

L

X

2.080

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 14. Output Voltage of SREG3

Address: 0111⁽³⁴⁾

B7

B6

B5

B4

B3

B2

CP Off

EXTG On

SREG3 [V]⁽³⁵⁾

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

X

2.091

2.102

2.125

2.170

2.260

2.440

2.451

2.462

2.485

2.530

2.620

2.800

L

H

Notes

34. All combinations of input are not included.

35. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to

SREGC1 and 3 (65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND, 73.84KΩ

between SREGO3 and SREGC3, and 26.16KΩ between SREGC3 and GND).

VG GENERATOR

VBATT

Start Up

VGATE

VBATT

SWGATE

Step-Up

Pre Driver

GNDGATE

VG_select

VG_duty

Figure 10. Circuit when using a Step-Up Converter

When WAKE (int) goes High from Low, the start-up circuit

raises the VB voltage and outputs it to VGATE, then outputs

the VGATE voltage when PGOOD1 (int) goes High. The

charge pump circuit can be used for both Ni_mh and Li_ion

by setting the necessary registers. The charge pump circuit is

disabled by default.

The VGATE voltage can be set in the range of 6 V to 4.5 V

according to the combination of VGATESEL1 and 2 pin

connections. Refer to Table 16, VGATE Voltage Settings and

VGATESEL1 and 2 Pin Connection on page 23 for the VG

voltage settings.

When using a charge pump, please refer to Figure 11.

18730

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22

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

VBATT

CH_PUMP

VGH

VBATT

CPoff

VGATE

Start Up

VGATE

VBATT

SWGATE

Step-Up

VGATE

Pre Driver

GNDGATE

VGATE_SELECT

VG_duty

Figure 11. Circuit When Using a Charge Pump

Table 15. VGATE Duty Settings

Address : 0010

Ext/Int

Half Freq

RSTB sleep

S_Off_VG

VG_Duty[3]

VG_Duty[2]

VG_Duty[1]

VG_Duty[0]

Duty

X

L

H

L

90 %

86 %

82 %

74 %

58 %

54 %

50 %

42 %

30 %

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Table 16. VGATE Voltage Settings and VGATESEL1 and 2 Pin Connection

VGATESEL1

VGATESEL2

VGATE [V]

GND

VBATT

GND

6.0

5.5

5.0

4.5

VBATT

18730

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23

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

REGISTER MAPPINGS

Table 17. CLEAR and SLEEP Control Register

1000

Bit

Data1

Data2

3

CLEAR

0

2

SLEEP

0

1

0

Reserved

0

3

Reserved

0

2

1

Reserved

0

Reserved

0

Name

Default

Reserved

0

Reserved

0

CLEAR: CLEAR Control

1 = CLEAR is high

Reserved : Freescale defined register *1

1 = Forbidden

0 = CLEAR is low

0 = Required

SLEEP: SLEEP Control

1 = SLEEP is high

Reserved : Freescale defined register *1

1 = Forbidden

0 = SLEEP is low

0 = Required

Reserved: Freescale defined register *1

1 = Forbidden

Reserved: Freescale defined register *1

1 = Forbidden

0 = Required

Reserved: Freescale defined register *1

1 = Forbidden

Note: Do NOT change Reserved Register from default

value.

0 = Required

*1: Data write to this address (1000) is allowed for the

most significant two bits only. The least significant 6 bits are

only used for the factory test. When writing data, always write

0 to these six bits.

Reserved: Freescale defined register *1

1 = Forbidden

0 = Required

Table 18. Power Mode Register

0001

Bit

Data1

Data2

3

PSW1

1

2

PSW2

1

PGOOD1

0

VOUT2

1

3

SREG1

1

2

SREG2

1

SREG3

1

0

PGOOD2

0

Name

Default

PSW1: VOUT1 Power Switch control

1 = Power Switch on

SREG2: Series Pass Regulator Channel2 output

Control *3

0 = Power Switch off

1 = Regulator off

0 = Regulator on

PSW2: VOUT2 Power Switch control

1 = Power Switch on

0 = Power Switch off

SREG3: Series Pass Regulator Channel3 output Control

1 = Regulator on

0 = Regulator off

PGOOD1: PGOOD1 Mask *1

1 = PGOOD1 mask on

0 = PGOOD1 mask off

PGOOD2: PGOOD2 Mask

1 = PGOOD2 mask on

0 = PGOOD2 mask off

*1

VO2_SENSE: DC/DC Converter Channel 2 output Control

*2

*1: When switching the output voltage of VO1_SENSE (2),

write 1 to the PGOOD1 (2) Mask bit in advance to fix the rest

output to High for preventing erroneous operation.

1 = DDC2 on

0 = DDC2 off

SREG1: Series Pass Regulator Channel1 output Control

1 = Regulator on

0 = Regulator off

*2: When turning DDC2 OFF, set the PGOOD2 bit to High

to Mask PGOOD2. If you turn DDC2 OFF, the power switch

2 also turns OFF.

18730

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24

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 19. Clock Select Register

0010

Data1

Data2

Bit

3

Ext/Int

0

2

Half Freq

0

1

0

S_Off_VG

0

3

2

1

0

Name

Default

RSTB sleep

1

VG_Duty [3] VG_Duty[2] VG_Duty[1] VG_Duty[0]

0

Ext / Int: Clock Select control 1

1 = External Clock

VG_Duty[2]: VG Duty Control Bit 2

1 = VG Duty[2] is high

0 = Internal Clock

0 = VG Duty[2] is low

2FS: Clock Select control 2

1 = 2FS on

VG_Duty[1]: VG Duty Control Bit1

1 = VG Duty[1] is high

0 = 2FS off

0 = VG Duty[1] is low

RSTB Sleep: RSTB Sleep Monitor

1 = RSTB SLEEP Monitor off

0 = RSTB SLEEP Monitor on

*1

VG_Duty[0]: VG Duty Control LSB

1 = VG Duty[0] is high

0 = VG Duty[0] is low

S_Off_VG: VG Top side transistor off

1 = Synchronous Rectification Off

0 = Synchronous Rectification On

VG is controlled by PFM method. This register can change

the duty by 16 steps.

Refer to Table 15, VGATE Duty Settings on page 23 for

the correspondence between the VG Duty maximum values

and register settings.

VG_Duty[3]: VG Duty Control MSB

1 = VG Duty[3] is high

0 = VG Duty[3] is low

Table 20. VO1_SENSE Output Voltage Register

0011

Bit

Data1

Data2

3

2

1

0

3

2

1

0

VO1_SENSE

[6]

VO1_SENSE

[5]

VO1_SENSE

[4]

VO1_SENSE

[3]

VO1_SENSE

[2]

VO1_SENSE

[1]

VO1_SENSE

[0]

S_Off_VO1_SENSE

Name

Default

1

0

VO1_SENSE[6]: Reference DAC MSB

1 = VO1_SENSE[6] on

0 = VO1_SENSE[6] off

VO1_SENSE[1]: Reference DAC Bit1

1 = VO1_SENSE[1] on

0 = VO1_SENSE[1] off

VO1_SENSE[5]: Reference DAC Bit5

1 = VO1_SENSE5] on

VO1_SENSE[0] on

0 = VO1_SENSE[0] off

0 = VO1_SENSE[5] off

S_Off_VO1_SENSE: DDC1 Top side (Ni_mh) / Bottom

side (Li_ion) transistor off

1 = Synchronous Rectification Off

VO1_SENSE[4]: Reference DAC Bit4

1 = VO1_SENSE[4] on

0 = VO1_SENSE[4] off

0 = Synchronous Rectification On

VO1_SENSE[3]: Reference DAC Bit3

1 = VO1_SENSE[3] on

0 = VO1_SENSE[3] off

Refer to Table 10, Output Voltage of VO1_SENSE on

page 19 for the correspondence between the output voltage

and register settings.

VO1_SENSE[2]: Reference DAC Bit2

1 = VO1_SENSE[2] on

0 = VO1_SENSE[2] off

18730

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25

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 21. VO2_SENSE Output Voltage Register

0100

Bit

Data1

Data2

3

2

1

0

3

2

1

0

VO2_SENSE

[6]

VO2_SENSE

[5]

VO2_SENSE

[4]

VO2_SENSE

[3]

VO2_SENSE

[2]

VO2_SENSE

[1]

VO2_SENSE

[0]

S_Off_VO2_SENSE

Name

Default

1

0

VO2_SENSE[6]: Reference DAC MSB

1 = VO2_SENSE[6] on

0 = VO2_SENSE[6] off

VO2_SENSE[1]: Reference DAC Bit1

1 = VO2_SENSE[1] on

0 = VO2_SENSE[1] off

VO2_SENSE[5]: Reference DAC Bit5

1 = VO2_SENSE[5] on

VO2_SENSE [0]: Reference DAC LSB

1 = VO2_SENSE [0] on

0 = VO2_SENSE[5] off

0 = VO2_SENSE [0] off

VO2_SENSE[4]: Reference DAC Bit4

1 = VO2_SENSE[4] on

S_Off_VO2_SENSE: DDC2 Top side & LG (Ni_mh) /

Bottom side (Li_ion) transistor off

0 = VO2_SENSE[4] off

1 = Synchronous Rectification Off

0 = Synchronous Rectification On

VO2_SENSE[3]: Reference DAC Bit3

1 = VO2_SENSE[3] on

0 = VO2_SENSE[3] off

Refer to Table 11, Output Voltage of VO2_SENSE on

page 20 for the correspondence between the output voltage

and register settings.

VO2_SENSE[2]: Reference DAC Bit2

1 = VO2_SENSE[2] on

0 = VO2_SENSE[2] off

Table 22. Regulator1 Output Voltage Register

0101

Bit

Data1

Data2

3

2

1

0

3

2

1

0

Reserved

1

Name

Default

SREG1_V[6]

1

SREG1_V[5]

1

SREG1_V[4]

1

SREG1_V[3]

1

SREG1_V[2]

1

SREG1_V[1]

1

SREG1_V[0]

1

SREG1_V[6]: Reference DAC MSB

1 = SREG1_V[6] on

SREG1 [1]: Reference DAC Bit1

1 = SREG1_V[1] on

0 = SREG1_V[6] off

0 = SREG1_V[1] off

SREG1_V[5]: Reference DAC Bit5

1 = SREG1_V[5] on

SREG1_V[0]: Reference DAC LSB

1 = SREG1_V[0] on

0 = SREG1_V[5] off

0 = SREG1_V[0] off

SREG1_V[4]: Reference DAC Bit4

1 = SREG1_V[4] on

Reserved : Blank register bit (Freescale Pre-Defined

Register)

0 = SREG1_V[4] off

1 = Preferred

0 = Forbidden

SREG1_V[3]: Reference DAC Bit3

1 = SREG1_V[3] on

0 = SREG1_V[3] off

Note: Do NOT change Reserved Register from default

value.

SREG1_V[2] : Reference DAC Bit2

1 = SREG1_V[2] on

0 = SREG1_V[2] off

Refer to Table 12, Output Voltage of SREG1 on page 20

for the correspondence between the output voltage and

register settings.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 23. Regulator2 Output Voltage Register

0110

Bit

Data1

Data2

3

2

1

0

3

2

1

0

Name

Default

SREG2_V[7]

1

SREG2_V[6]

1

SREG2_V[5]

1

SREG2_V[4]

1

SREG2_V[3]

1

SREG2_V[2]

1

SREG2_V[1]

1

SREG2_V[0]

1

SREG2_V[7]: Reference DAC MSB

1 = SREG2_V[7] on

0 = SREG2_V[7] off

SREG2_V[2]: Reference DAC Bit2

1 = SREG2_V[2] on

0 = SREG2_V[2] off

SREG2_V[6]: Reference DAC Bit6

1 = SREG2_V[6] on

SREG2_V[1]: Reference DAC Bit1

1 = SREG2_V[1] on

0 = SREG2_V[6] off

0 = SREG2_V[1] off

SREG2_V[5]: Reference DAC Bit5

1 = SREG2_V[5] on

SREG2_V[0]: Reference DAC LSB

1 = SREG2_V[0] on

0 = SREG2_V[5] off

0 = SREG2_V[0] off

SREG2_V[4]: Reference DAC Bit4

1 = SREG2_V[4] on

0 = SREG2_V[4] off

Refer to Table 13, Output Voltage of SREG2 on page 21

for the correspondence between the output voltage and

register settings.

SREG2_V[3]: Reference DAC Bit3

1 = SREG2_V[3] on

0 = SREG2_V[3] off

Table 24. Regulator3 Output Voltage Register

0111

Bit

Data1

Data2

3

2

1

0

3

2

1

CP Off

1

0

EXTG On

1

Name

Default

SREG3_V[5]

1

SREG3_V[4]

1

SREG3_V[3]

1

SREG3_V[2]

1

SREG3_V[1]

1

SREG3_V[0]

1

SREG3_V[5]: Reference DAC MSB

1 = SREG3_V[5] on

SREG3_V[0]: Reference DAC LSB

1 = SREG3_V[0] on

0 = SREG3_V[5] off

0 = SREG3_V[0] off

SREG3_V[4]: Reference DAC Bit4

1 = SREG3_V[4] on

CP Off: Charge Pump Control

1 = Charge Pump off

0 = SREG3_V[4] off

0 = Charge Pump on

SREG3_V[3]: Reference DAC Bit3

1 = SREG3_V[3] on

0 = SREG3_V[3] off

EXTG On: VGATE_EXT Control *

1 = VGATE_EXT is low (GND level)

0 = VGATE_EXT is high (VG level)

SREG3_V[2] : Reference DAC Bit2

1 = SREG3_V[2] on

EXTG On Register is assumed to use Pch FET as external

MOSFET.

0 = SREG3_V[2] off

If Nch FET will be used, Control logic should be inverted.

SREG3_V[1] : Reference DAC Bit1

1 = SREG3_V[1] on

0 = SREG3_V[1] off

Refer to Table 14, Output Voltage of SREG3 on page 21

for the correspondence between the output voltage and

register settings.

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

TYPICAL APPLICATIONS

HVB

VBATT

VMODE

VBATT

LVB

Driver

VMODE

VO1_SENSE

PGOOD1(Int)

VO1_SENSE

V_STDBY

VOUT1

VREF

PGOOD1(Int)

CLEAR

VREF

BANDGAP

REFERENCE

VGATE

LSWO

VO1_SENSE

PGOOD1(Int)

VO1_SENSE

POWER

SWITCH1

VO1_SENSE

VGATE

VO1_SENSE

VIN1

PGOOD1

PGOOD1_DELAY

PGOOD1(Int)

REF1

RESET

Block 1

Step-UpDown

DC/DC

VBATT

VO1_SENSE

SW1

Converter

CH1

RESET1_TH

EAIN1

PGND1

EAOUT1

VREF

VGATE

PGOOD1_DELAY

or

PGOOD2_DELAY

VOUT2

DMAX1

POWER

PGOOD2(Int)

VGATE

VO2_SENSE_IN

VO2_SENSE

VO1_SENSE

PGOOD2

SWITCH2

VO1_SENSE

PGOOD2(Int)

VBATT

HG

LG

RESET

Block 2

REF2

PGOOD2_DELAY

EAOUT2

Step-UpDown

DC/DC

Converter

VIN2

CH2

SW2

EAIN2

VREF

DMAX2

PGND2

SREGI1

VGATE

SREGO1

REF3

Series Pass

Regulator1

SREGC1

SREGO1

SREG12

SREGO2

VGATE

SREGC2

SREGC3

Series Pass

Regulator2

SREGO3

REF4

SREGO2

V_STDBY

SREG2G

SREGI3

VGATE

VO1_SENSE

VBATT

WAKE1B

WAKE2B

Series Pass

Regulator3

REF5

WAKE3B

SREGO3

VBATT

WAKE4B

SEQ_SELECT

DATA

EXT_CLOCK

CPoff

PGOOD1(Int)

PGOOD2

CH_PUMP

VGATE

STRB

VO1_SENSE

VBATT

^CONTROL(Int)

VGATE

SEQ_SELECT

SCKIN

CLEAR

SLEEP

Control

Logic

VBATT

Step-Up

DC/DC

Convertor

VG_select

VG_duty

SWGATE

EXT_CLOCK

GNDGATE

GND

VGATE

REF2

REF1

REF4

VGATESEL1

VGATESEL2

REF3

REF5

EXT gate

On

Buffer

VGATE_EXT

On

WATCHDOG

REF DAC

VREF

Figure 12. MPC18730 Typical Application Diagram (Ni-MH Battery)

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

TYPICAL APPLICATIONS

VBATT

HVB

VMODE

VBATT

LVB

Driver

LVB

VMODE

PGOOD1(Int)

VO1_SENSE

VREF

PGOOD1(Int)

CLEAR

V_STDBY

VREF

BANDGAP

REFERENCE

VGATE

VOUT1

LSWO

VO1_SENSE

PGOOD1(Int)

VO1_SENSE

POWER

VO1_SENSE

SWITCH1

PGOOD1(Int)

VO1_SENSE

VGATE

VBATT

VIN1

PGOOD1

RESET

Block 1

PGOOD1_DELAY

REF1

Step-UpDown

DC/DC

VO1_SENSE

SW1

Converter

RESET1_TH

EAIN1

CH1

PGND1

EAOUT1

VGATE

PGOOD1_DELAY

or

PGOOD2_DELAY

VOUT2

POWER

SWITCH2

DMAX1

VO1_SENSE

PGOOD2(Int)

VGATE

VO2_SENSE_IN

VO2_SENSE

VO1_SENSE

PGOOD2(Int)

PGOOD2

HG

RESET

Block 2

LG

REF2

PGOOD2_DELAY

EAOUT2

Step-UpDown

DC/DC

Converter

VBATT

VIN2

EAIN2

CH2

SW2

PGND2

SREGI1

DMAX2

VGATE

SREGO1

REF3

Series Pass

Regulator1

SREGC1

SREGO1

SREG12

SREGO2

VGATE

Series

Pass

Regulator2

SREGC2

SREGC3

SREGO3

REF4

SREGO2

V_STDBY

SREG2G

SREGI3

VGATE

VO1_SENSE

VBATT

WAKE1B

WAKE2B

Series Pass

Regulator3

REF5

WAKE3B

SREGO3

WAKE4B

SEQ_SELECT

DATA

VBATT

EXT_CLOCK

PGOOD1(Int)

PGOOD2

CH_PUMP

VGH

CPoff

STRB

VGATE

VBATT

SEQ_SELECT

^CONTROL(Int)

SCKIN

VGATE

VO1_SENSE

VBATT

CLEAR

SLEEP

Control

Logic

Step-Up

DC/DC

Convertor

VG_select

VG_duty

SWGATE

EXT_CLOCK

GND

GNDGATE

VGATE

REF2

REF4

VGATESEL1

VGATESEL2

REF3

REF5

REF1

EXT gate

VGATE_EXT

On

Buffer

WATCHDOG

REF DAC

VREF

Figure 13. MPC18730 Typical Application Diagram (Li-Ion Battery)

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EP (Pb-FREE) SUFFIX

64-PIN 0.5 mm pitch

PLASTIC PACKAGE

98ARL10571D

ISSUE B

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

PACKAGING

PACKAGE DIMENSIONS

EP (Pb-FREE) SUFFIX

64-PIN 0.5 mm pitch

PLASTIC PACKAGE

98ARL10571D

ISSUE B

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

PACKAGING

PACKAGE DIMENSIONS

EP (Pb-FREE) SUFFIX

64-PIN 0.5 mm pitch

PLASTIC PACKAGE

98ARL10571D

ISSUE B

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

PACKAGING

PACKAGE DIMENSIONS

EP (Pb-FREE) SUFFIX

64-PIN 0.5 mm pitch

PLASTIC PACKAGE

98ARL10571D

ISSUE B

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

REVISION HISTORY

REVISION

3.0

DATE

DESCRIPTION OF CHANGES

04/2006

8/2006

• Changed 34 of 64 Pin names to align with Application Note, AN3247 Rev 1.0.

• Minor changes to correct errors and inconsistencies.

• Updated form and style.

4.0

18730

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

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MPC18730

Rev. 4.0

8/2006