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Document number: MC34712  
Rev. 4.0, 5/2007  
Freescale Semiconductor  
Advance Information  
3.0 A 1.0 MHz Fully Integrated  
DDR Switch-Mode Power  
Supply  
34712  
The 34712 is a highly integrated, space efficient, low cost, single  
synchronous buck switching regulator with integrated N-channel  
power MOSFETs. It is a high performance point-of-load (PoL) power  
supply with the ability to track an external reference voltage.  
SWITCH-MODE POWER SUPPLY  
Its high efficient 3.0 A sink and source capability combined with its  
voltage tracking/sequencing ability and tight output regulation, makes  
it ideal to provide the termination voltage (VTT) for modern data buses  
such as Double-Data-Rate (DDR) memory buses. It also provides a  
buffered output reference voltage (VREF) to the memory chipset  
The 34712 offers the designer the flexibility of many control,  
supervisory, and protection functions to allow for easy implementation  
of complex designs. It is housed in a Pb-Free, thermally enhanced,  
and space efficient 24-Pin Exposed Pad QFN.  
Features  
EP SUFFIX  
98ARL10577D  
24-PIN QFN  
• 45 mIntegrated N-Channel Power MOSFETs  
• Input Voltage Operating Range from 3.0 V to 6.0 V  
±1 % Accurate Output Voltage, Ranging from 0.7 V to 1.35 V  
±1 % Accurate Buffered Reference Output Voltage  
• Programmable Switching Frequency Range from 200 kHz to  
1.0 MHz with a default of 1.0 MHz  
• Over Current Limit and Short Circuit Protection  
• Thermal Shutdown  
• Output Overvoltage and Undervoltage Detection  
• Active Low Power Good Output Signal  
ORDERING INFORMATION  
Temperature  
Package  
Device  
Range (T )  
A
MC34712EP/R2  
-40 to 85°C  
24 QFN  
• Active Low Standby and Shutdown Inputs  
• Pb-Free Packaging Designated by Suffix Code EP.  
VIN  
(3.0V TO 6.0V)  
34712  
PVIN  
BOOT  
TERMINATING  
RESISTORS  
VDDQ  
VREFIN  
VTT  
SW  
VOUT  
VIN  
MEMORY  
BUS  
VDDQ  
VDDI  
FREQ  
GND  
SD  
INV  
DDR MEMORY  
COMP  
CHIPSET  
VDDQ  
VREFOUT  
VREF  
VIN  
DDR MEMORY  
CONTROLER  
PGND  
PG  
MCU  
STBY  
Figure 1. 34712 Simplified Application Diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
STBY  
SD  
Thermal  
Monitoring  
Internal  
Vo l tag e  
VIN  
Regulator  
PG  
System  
Reset  
System  
Cont rol  
M2  
M1  
Isense  
V
BOOT  
PVIN  
SW  
DDI  
Ilimit  
Current  
Monitoring  
Discharge  
V
IN  
V
BOOT  
Oscillator  
Buck  
F
M3  
M4  
SW  
Cntl.  
Prog. Frequency  
Gate  
Driver  
FREQ  
Isense  
Logic  
V
DDI  
PGND  
COMP  
PWM  
Comparator  
VDDI  
Ramp  
Generator  
V
BG  
Bandgap  
Regulator  
Error  
Amplifier  
VREFIN  
INV  
R
REF1  
Buffer  
VOUT  
M5  
Discharge  
R
RE F2  
M6  
Discharge  
VREFOUT  
GND  
Figure 2. 34712 Simplified Internal Block Diagram  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
20  
24  
21  
22  
19  
23  
GND  
FREQ  
NC  
PVIN  
1
18  
2
3
17 SW  
SW  
SW  
16  
15  
14  
13  
Transparent  
Top View  
4
PG  
STBY  
PGND  
PGND  
5
6
SD  
8
9
7
10  
12  
11  
Figure 3. 34712 Pin Connections  
Table 1. 34712 Pin Definitions  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
Analog signal ground of IC  
1
2
3
4
5
6
GND  
FREQ  
NC  
Ground  
Passive  
None  
Signal Ground  
Frequency Adjustment  
No Connect  
Buck converter switching frequency adjustment pin  
No internal connections to this pin  
Active-low (open drain) power-good status reporting pin  
Standby mode input control pin  
PG  
Output  
Input  
Power Good  
Standby  
STBY  
SD  
Shutdown mode input control pin  
Input  
Shutdown  
Voltage-Tracking-  
Reference Input  
Voltage-Tracking-Reference voltage input  
7
VREFIN  
Input  
Reference Voltage  
Output  
Buffered output equal to 1/2 of voltage-tracking reference  
8
9
VREFOUT  
COMP  
Output  
Passive  
Input  
Buck converter external compensation network pin  
Buck converter error amplifier inverting input pin  
Compensation  
Error Amplifier  
Inverting Input  
10  
INV  
Discharge FET drain connection (connect to buck converter output  
capacitors)  
Output Voltage  
Discharge FET  
11  
VOUT  
Output  
Ground return for buck converter and discharge FET  
Buck converter power switching node  
12,13,14  
15,16,17  
PGND  
SW  
Ground  
Power  
Power Ground  
Switching Node  
Power-Circuit Supply Buck converter main supply voltage input  
Input  
18,19,20  
21  
PVIN  
Supply  
Bootstrap switching node (connect to bootstrap capacitor)  
BOOT  
Passive  
Bootstrap  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
Table 1. 34712 Pin Definitions (continued)  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
Logic circuits supply voltage input  
Logic-Circuit Supply  
Input  
22,23  
24  
VIN  
Supply  
Internal Voltage  
Regulator  
Internal Vdd Regulator (connect filter capacitor to this pin)  
VDDI  
Passive  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Ratings  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Input Supply Voltage (VIN) Pin  
VIN  
-0.3 to 7.0  
-0.3 to 7.0  
-0.3 to 7.5  
-0.3 to 7.5  
-0.3 to 7.0  
-0.3 to 3.0  
±3.0  
V
V
V
V
V
V
A
High-Side MOSFET Drain Voltage (PVIN) Pin  
Switching Node (SW) Pin  
PVIN  
VSW  
BOOT Pin (Referenced to SW Pin)  
PG, VOUT, SD, and STBY Pins  
VBOOT - VSW  
-
-
VDDI, FREQ, INV, COMP, VREFIN, and VREFOUT Pins  
Continuous Output Current (1)  
IOUT  
ESD Voltage (2)  
VESD1  
VESD3  
Human Body Model  
Device Charge Model (CDM)  
±2000  
±750  
V
THERMAL RATINGS  
Operating Ambient Temperature (3)  
Storage Temperature  
TA  
TSTG  
TPPRT  
TJ(MAX)  
PD  
-40 to 85  
-65 to +150  
Note 5  
°C  
°C  
°C  
Peak Package Reflow Temperature During Reflow (4), (5)  
Maximum Junction Temperature  
Power Dissipation (TA = 85 °C) (6)  
Notes  
+150  
2.9  
°C  
W
1. Continuous output current capability so long as T is TJ(MAX)  
.
J
2. ESD1 testing is performed in accordance with the Human Body Model (C  
accordance with the Charge Device Model (CDM).  
=100 pF, R  
=1500 ), ESD3 testing is performed in  
ZAP  
ZAP  
3. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.  
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
6. Maximum power dissipation at indicated ambient temperature.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings (continued)  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Ratings  
Symbol  
Value  
Unit  
THERMAL RESISTANCE (7)  
Thermal Resistance, Junction to Ambient, Single-Layer Board (1s) (8)  
Thermal Resistance, Junction to Ambient, Four-Layer Board (2s2p) (9)  
Thermal Resistance, Junction to Board (10)  
RθJA  
RθJMA  
RθJB  
139  
43  
°C/W  
°C/W  
°C/W  
22  
Notes  
7. The PVIN, SW, and GND pins comprise the main heat conduction paths.  
8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.  
9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the  
board.  
10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top  
surface of the board near the package.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
IC INPUT SUPPLY VOLTAGE (VIN)  
Symbol  
Min  
Typ  
Max  
Unit  
Input Supply Voltage Operating Range  
VIN  
IIN  
3.0  
-
-
-
6.0  
25  
V
Input DC Supply Current (11)  
mA  
Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs  
Input DC Supply Current (11)  
IINQ  
-
-
-
-
15  
mA  
µA  
Standby Mode, SD = 1 & STBY = 0  
Input DC Supply Current (11)  
IINOFF  
100  
Shutdown Mode, SD = 0 & STBY = X  
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)  
Internal Supply Voltage Range  
VDDI  
2.35  
2.5  
2.65  
V
BUCK CONVERTER (PVIN, SW, GND, BOOT, INV, COMP)  
High-side MOSFET Drain Voltage Range  
Output Voltage Adjustment Range (12)  
PVIN  
VOUT  
-
2.5  
0.7  
-
-
-
6.0  
1.35  
1.0  
V
V
Output Voltage Accuracy (12), (13), (14)  
-1.0  
%
Line Regulation (12)  
REGLN  
REGLD  
-1.0  
-1.0  
-
-
1.0  
1.0  
%
%
Normal Operation, VIN = 3.0 V to 6.0 V, IOUT = ±3.0 A  
Load Regulation (12)  
Normal Operation, IOUT = -3.0 A to 3.0 A  
Error Amplifier Common Mode Voltage Range (12), (15)  
V
0.0  
-1.5  
1.5  
-3.0  
-
-
1.35  
-8.0  
8.0  
3.0  
-
V
%
%
A
REF  
Output Undervoltage Threshold  
VUVR  
VOVR  
IOUT  
ILIM  
-
-
Output Overvoltage Threshold  
Continuous Output Current  
-
Over Current Limit, Sinking and Sourcing  
4.0  
A
Short Circuit Current Limit  
(Sourcing and Sinking)  
ISHORT  
-
6.5  
-
A
(12)  
High-Side N-CH Power MOSFET (M3) RDS(ON)  
RDS(ON)HS  
10  
10  
-
-
45  
45  
mΩ  
mΩ  
IOUT = 1.0 A, VBOOT - VSW = 3.3 V  
(12)  
Low-Side N-CH Power MOSFET (M4) RDS(ON)  
RDS(ON)LS  
IOUT = 1.0 A, VIN = 3.3 V  
Notes  
11. See section “MODES OF OPERATION”, page 14 has a detailed description of the different operating modes of the 34712  
12. Design information only, this parameter is not production tested.  
13. ±1% is assured at room temperature.  
14. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended.  
15. The 1% output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7V at room  
temperature.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
M2 RDS(ON)  
RDS(ON)M2  
1.5  
-
4.0  
(VIN = 3.3 V, M2 is on)  
PVIN Pin Leakage Current  
IPVIN  
-10  
-
10  
µA  
(Standby and Shutdown Modes)  
INV Pin Leakage Current  
IINV  
-1.0  
-
1.0  
µA  
°C  
°C  
Thermal Shutdown Threshold (16)  
TSDFET  
TSDHYFET  
-
-
170  
25  
-
-
Thermal Shutdown Hysteresis (16)  
OSCILLATOR (FREQ)  
Oscillator Frequency Adjusting Reference Voltage Range  
TRACKING (VREFIN, VREFOUT, VOUT)  
VREFIN External Reference Voltage Range (16)  
VREFOUT Buffered Reference Voltage Range  
VREFOUT Buffered Reference Voltage Accuracy (17)  
VREFOUT Buffered Reference Voltage Current Capability  
VREFOUT Buffered Reference Voltage Over Current Limit  
VREFOUT Total Discharge Resistance(16)  
VOUT Total Discharge Resistance (16)  
VFREQ  
0.0  
-
VDDI  
V
VREFIN  
VREFOUT  
-
0.0  
0.0  
-1.0  
0.0  
-
-
-
2.7  
1.35  
1.0  
8.0  
-
V
V
-
%
IREFOUT  
IREFOUTLIM  
RTDR(M6)  
RTDR(M5)  
-
mA  
mA  
11  
50  
50  
-
-
-
-
VOUT Pin Leakage Current  
IVOUTLKG  
-1.0  
-
1.0  
µA  
(Standby Mode, VOUT = 3.6 V)  
CONTROL AND SUPERVISORY (STBY, SD, PG)  
STBY High Level Input Voltage  
STBY Low Level Input Voltage  
STBY Pin Internal Pull Up Resistor  
SD High Level Input Voltage  
VSTBYHI  
VSTBYLO  
RSTBYUP  
VSDHI  
2.0  
-
-
-
-
-
-
-
-
V
V
0.4  
2.0  
-
1.0  
2.0  
-
MΩ  
V
SD Low Level Input Voltage  
VSDLO  
0.4  
2.0  
V
SD Pin Internal Pull Up Resistor  
RSDUP  
1.0  
MΩ  
PG Low Level Output Voltage  
(IPG = 3.0 mA)  
VPGLO  
-
-
-
0.4  
1.0  
V
PG Pin Leakage Current  
IPGLKG  
-1.0  
µA  
(M1 is off, Pulled up to VIN)  
Notes  
16. Design information only, this parameter is not production tested.  
17. The 1 % accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
8
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
BUCK CONVERTER (PVIN, SW, GND, BOOT)  
Switching Node (SW) Rise Time (19)  
(PVIN = 3.3 V, IOUT = ±3.0 A)  
tRISE  
tFALL  
tSS  
-
-
14  
20  
-
-
-
ns  
ns  
Switching Node (SW) Fall Time (19)  
(PVIN = 3.3 V, IOUT = ±3.0 A)  
Soft Start Duration  
(Normal Mode)  
1.3  
2.6  
ms  
Over Current Limit Timer  
tLIM  
-
10  
-
-
ms  
ms  
µs  
Over Current Limit Retry Time-out Period  
Output Undervoltage/Overvoltage Filter Delay Timer  
OSCILLATOR (FREQ)  
tTIMEOUT  
tFILTER  
80  
5.0  
120  
25  
-
Oscillator Default Switching Frequency (18)  
(FREQ = GND)  
FSW  
FSW  
-
1.0  
-
-
MHz  
kHz  
Oscillator Switching Frequency Range  
CONTROL AND SUPERVISORY (STBY, SD, PG)  
PG Reset Delay  
200  
1000  
tPGRESET  
tTIMEOUT  
8.0  
80  
-
-
12  
ms  
ms  
Thermal Shutdown Retry Time-out Period (19)  
120  
Notes  
18. Oscillator Frequency tolerance is ±10%.  
19. Design information only, this parameter is not production tested.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
In modern microprocessor/memory applications, address  
commands and control lines require system level termination  
to a voltage (VTT) equal to 1/2 the memory supply voltage  
(VDDQ). Having the termination voltage at midpoint, the power  
supply insures symmetry for switching times. Also, a  
continuous current. It provides protection against output over  
current, overvoltage, undervoltage, and overtemperature  
conditions. It also protects the system from short circuit  
events. It incorporates a power-good output signal to alert the  
host when a fault occurs.  
reference voltage (VREF) that is free of any noise or voltage  
variations is needed for the DDR SDRAM input receiver,  
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will  
effect the setup and hold time of the memory. To comply with  
DDR requirements and to obtain best performance, VTT and  
VREF need to be tightly regulated to track 1/2 VDDQ across  
voltage, temperature, and noise margins. VTT should track  
any variations in the DC VREF value (VTT = VREF +/- 40 mV),  
(See Figure 4) for a DDR system level diagram.  
For boards that support the Suspend-To-RAM (S3) and  
the Suspend-To-Disk (S5) states, the 34712 offers the STBY  
and the SD pins respectively. Pulling any of these pins low,  
puts the IC in the corresponding state.  
By integrating the control/supervisory circuitry along with  
the Power MOSFET switches for the buck converter into a  
space-efficient package, the 34712 offers a complete, small-  
size, cost-effective, and simple solution to satisfy the needs  
of DDR memory applications.  
The 34712 supplies the VTT and a buffered VREF output.  
To ensure compliance with DDR specifications, the VDDQ line  
is applied to the VREFIN pin and divided by 2 internally  
through a precision resistor divider. This internal voltage is  
then used as the reference voltage for the VTT output. The  
same internal voltage is also buffered to give the VREF  
voltage at the VREFOUT pin for the application to use without  
the need for an external resistor divider. The 34712 provides  
the tight voltage regulation and power sequencing/tracking  
required along with handling the DDR peak transient current  
requirements. Buffering the VREF output helps its immunity  
against noise and load changes.  
Besides DDR memory termination, the 34712 can be used  
to supply termination for other active buses and graphics card  
memory. It can be used in Netcom/Telecom applications like  
servers. It can also be used in desktop motherboards, game  
consoles, set top boxes, and high end high definition TVs.  
V
V
V
DDQ  
DDQ  
TT  
R
T
R
S
The 34712 utilizes a voltage mode synchronous buck  
switching converter topology with integrated low RDS(ON)  
(45 m) N-channel power MOSFETs to provide a VTT voltage  
with an accuracy of less than ±2.0 %. It has a programmable  
switching frequency that allows for flexibility and optimization  
over the operating conditions and can operate at up to  
1.0 MHz to significantly reduce the external components size  
and cost. The 34712 can sink and source up to 3.0 A of  
V
REF  
BUS  
DDR Memory Input Receiver  
DDR Memory Controller  
Figure 4. DDR System Level Diagram  
FUNCTIONAL PIN DESCRIPTION  
REFERENCE VOLTAGE INPUT (VREFIN)  
FREQUENCY ADJUSTMENT INPUT (FREQ)  
The 34712 will track 1/2 the voltage applied at this pin.  
The buck converter switching frequency can be adjusted  
by connecting this pin to an external resistor divider between  
VDDI and GND pins. The default switching frequency (FREQ  
pin connected to ground, GND) is set at 1.0 MHz.  
REFERENCE VOLTAGE OUTPUT (VREFOUT)  
This is a buffered reference voltage output that is equal to  
1/2 VREFIN. It has a 10.0 mA current drive capability. This  
output is used as the VREF voltage rail and should be filtered  
against any noise. Connect a 0.1 µF, 6 V low ESR ceramic  
filter capacitor between this pin and the GND pin and  
between this pin and VDDQ rail. VREFOUT is also used as the  
reference voltage for the buck converter error amplifier.  
SIGNAL GROUND (GND)  
Analog ground of the IC. Internal analog signals are  
referenced to this pin voltage.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)  
POWER INPUT VOLTAGE (PVIN)  
This is the output of the internal bias voltage regulator.  
Connect a 1.0 µF, 6 V low ESR ceramic filter capacitor  
between this pin and the GND pin. Filtering any spikes on this  
output is essential to the internal circuitry stable operation.  
Buck converter power input voltage. This is the drain of the  
buck converter high-side power MOSFET.  
BOOTSTRAP INPUT (BOOT)  
Bootstrap capacitor input pin. Connect a capacitor (as  
discussed on page 19) between this pin and the SW pin to  
enhance the gate of the high-side Power MOSFET during  
switching.  
OUTPUT VOLTAGE DISCHARGE PATH (VOUT)  
Output voltage of the Buck Converter is connected to this  
pin. it only serves as the output discharge path once the SD  
signal is asserted.  
SHUTDOWN INPUT (SD)  
ERROR AMPLIFIER INVERTING INPUT (INV)  
If this pin is tied to the GND pin, the device will be in  
Shutdown Mode. If left unconnected or tied to the VIN pin, the  
device will be in Normal Mode. The pin has an internal pull up  
of 1.5 M. This input accepts the S5 (Suspend-To-Disk)  
control signal.  
Buck converter error amplifier inverting input. Connect the  
VTT voltage directly to this pin.  
COMPENSATION INPUT (COMP)  
Buck converter external compensation network connects  
to this pin. Use a type III compensation network.  
STANDBY INPUT (STBY)  
If this pin is tied to the GND pin, the device will be in  
Standby Mode. If left unconnected or tied to the VIN pin, the  
device will be in Normal Mode. The pin has an internal pull up  
of 1.5 M. This input accepts the S3 (Suspend-To-RAM)  
control signal.  
INPUT SUPPLY VOLTAGE (VIN)  
IC power supply input voltage. Input filtering is required for  
the device to operate properly.  
POWER GROUND (PGND)  
POWER GOOD OUTPUT SIGNAL (PG)  
Buck converter and discharge MOSFETs power ground. It  
is the source of the buck converter low-side power MOSFET.  
This is an active low open drain output that is used to  
report the status of the device to a host. This output activates  
after a successful power up sequence and stays active as  
long as the device is in normal operation and is not  
experiencing any faults. This output activates after a 10 ms  
delay and must be pulled up by an external resistor to a  
supply voltage (e.g.,VIN.).  
SWITCHING NODE (SW)  
Buck converter switching node. This pin is connected to  
the output inductor.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
System Control  
& Logic  
Internal Bias  
Circuits  
Oscillator  
Control &  
Supervisory  
Functions  
Tracking &  
Sequencing  
Protection  
Functions  
Buck Converter  
Figure 5. 34712 Internal Block Diagram  
resistor divider to the FREQ pin, between VDDI and GND  
INTERNAL BIAS CIRCUITS  
pins (See Figure 1).  
This block contains all circuits that provide the necessary  
supply voltages and bias currents for the internal circuitry. It  
consists of:  
PROTECTION FUNCTIONS  
This block contains the following circuits:  
• Internal Voltage Supply Regulator: This regulator  
supplies the VDDI voltage that is used to drive the digital/  
analog internal circuits. It is equipped with a Power-On-  
Reset (POR) circuit that watches for the right regulation  
levels. External filtering is needed on the VDDI pin. This  
block will turn off during the shutdown mode.  
• Internal Bandgap Reference Voltage: This supplies the  
reference voltage to some of the internal circuitry.  
• Bias Circuit: This block generates the bias currents  
necessary to run all of the blocks in the IC.  
• Over Current Limit and Short Circuit Detection: This  
block monitors the output of the buck converter for over  
current conditions and short circuit events and alerts the  
system control for further command.  
• Thermal Limit Detection: This block monitors the  
temperature of the device for overheating events. If the  
temperature rises above the thermal shutdown  
threshold, this block will alert the system control for  
further commands.  
• Output Overvoltage and Undervoltage Monitoring: This  
block monitors the buck converter output voltage to  
ensure it is within regulation boundaries. If not, this  
block alerts the system control for further commands.  
SYSTEM CONTROL AND LOGIC  
This block is the brain of the IC where the device  
processes data and reacts to it. Based on the status of the  
STBY and SD pins, the system control reacts accordingly and  
orders the device into the right status. It also takes inputs  
from all of the monitoring/protection circuits and initiates  
power up or power down commands. It communicates with  
the buck converter to manage the switching operation and  
protects it against any faults.  
CONTROL AND SUPERVISORY FUNCTIONS  
This block is used to interface with an outside host. It  
contains the following circuits:  
• Standby Control Input: An outside host can put the  
34712 device into standby mode (S3 or Suspend-To-  
RAM mode) by sending a logic “0” to the STBY pin.  
• Shutdown Control Input: An outside host can put the  
34712 device into shutdown mode (S5 or Suspend-To-  
Disk mode) by sending a logic “0” to the SD pin.  
• Power Good Output Signal PG: The 34712 can  
communicate to an external host that a fault has  
OSCILLATOR  
This block generates the clock cycles necessary to run the  
IC digital blocks. It also generates the buck converter  
switching frequency. The switching frequency has a default  
value of 1.0 MHz and can be programmed by connecting a  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
12  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
occurred by releasing the drive on the PG pin high,  
allowing the signal/pin to be pulled high by the external  
pull-up resistor.  
regulated output voltage used by the loads for reliable  
operation. The buck converter is a high performance, fixed  
frequency (externally adjustable), synchronous buck PWM  
voltage-mode control. It drives integrated 45 mN-channel  
power MOSFETs saving board space and enhancing  
efficiency. The switching regulator output voltage is  
adjustable with an accuracy of less than ±2.0 % to meet DDR  
requirements. Its output has the ability to track 1/2 the voltage  
applied at the VREFIN pin. The regulator's voltage control  
loop is compensated using a type III compensation network,  
with external components to allow for optimizing the loop  
compensation, for a wide range of operating conditions. A  
typical Bootstrap circuit with an internal PMOS switch is used  
to provide the voltage necessary to properly enhance the  
high-side MOSFET gate.  
TRACKING AND SEQUENCING  
This block allows the output of the 34712 to track 1/2 the  
voltage applied at the VREFIN pin. This allows the VREF and  
TT voltages to track 1/2 VDDQ and assures that none of them  
will be higher than VDDQ at any point during normal operating  
conditions. For power down during a shutdown (S5) mode,  
the 34712 uses internal discharge MOSFETs (M5 and M6 on  
Figure 2) to discharge VTT and VREF respectively. These  
discharge MOSFETs are only active during shutdown mode.  
Using this block along with controlling the SD and STBY pins  
can offer the user power sequencing capabilities by  
V
The 34712 is designed to address DDR memory power  
supplies. The integrated converter has the ability to both sink  
and source up to 3.0 A of continuous current, making it  
suitable for bus termination power supplies.  
controlling when to turn the 34712 outputs on or off.  
BUCK CONVERTER  
This block provides the main function of the 34712: DC to  
DC conversion from an un-regulated input voltage to a  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
VIN < 3.0V  
SD = 1 &  
STBY = 0  
SD = 0 &  
STBY = x  
Power Off  
TT = OFF  
V
V
REF = OFF  
Standby  
VTT = OFF  
Shutdown  
PG = 1  
VTT = Discharge  
V
REF = ON  
V
REF = Discharge  
3.0V < = VIN < = 6.0V  
PG = 1  
PG = 1  
SD = 1 &  
STBY = 1  
SD = 1 &  
STBY = 1  
Short Circuit  
TT = OFF  
Overvoltage  
Normal  
VTT  
< VOV  
tTIMEOUT Expired  
V
VTT = ON  
VTT  
> VOV  
IOUT > = ISHORT  
V
TT = ON  
V
REF = OFF  
VREF = ON  
V
REF = ON  
PG = 1  
PG = 1  
PG = 0  
tTIMEOUT Expired  
VTT > VUV  
Over Current  
Undervoltage  
TT = ON  
TJ < = 145°C &  
TIMEOUT Expired  
V
V
TT = OFF  
REF = ON  
IOUT > = ILIM  
For > = 10ms  
V
t
VTT < VUV  
V
REF = ON  
Thermal  
Shutdown  
TT = OFF  
PG = 1  
PG = 1  
V
V
REF = OFF  
PG = 1  
TJ > = 170°C  
Figure 6. Operation Modes Diagram  
Shutdown Mode  
MODES OF OPERATION  
The 34712 has three primary modes of operation:  
In this mode, activated by pulling the SD pin low, the chip  
is in a shutdown state and the outputs are all disabled and  
discharged. This is the S4/S5 power state or Suspend-To-  
Disk state, where the DRAM will loose all of its data content  
(no power supplied to the DRAM). The reason to discharge  
the VTT and VREF lines is to ensure upon exiting, the  
Normal Mode  
In normal mode, all functions and outputs are fully  
operational. To be in this mode, the VIN needs to be within its  
operating range, both Shutdown and Standby inputs are  
high, and no faults are present. This mode consumes the  
most amount of power.  
Shutdown Mode that VTT and VREF are lower than VDDQ  
,
otherwise VTT can remain floating high, and be higher than  
VDDQ upon powering up. In this mode, the 34712 consumes  
the least amount of power since almost all of the internal  
blocks are disabled.  
Standby Mode  
This mode is predominantly used in Desktop memory  
solutions where the DDR supply is desired to be ACPI  
compliant (Advanced Configuration and Power Interface).  
When this mode is activated by pulling the STBY pin low, VTT  
is put in High Z state, IOUT = 0 A, and VREF stays active. This  
is the S3 state Suspend-To-Ram or Self Refresh mode and it  
is the lowest DRAM power state. In this mode, the DRAM will  
preserve the data. While in this mode, the 34712 consumes  
less power than in the normal mode, because the buck  
converter and most of the internal blocks are disabled.  
START-UP SEQUENCE  
When power is first applied, the 34712 checks the status  
of the SD and STBY pins. If the device is in a shutdown mode,  
no block will power up and the output will not attempt to ramp.  
If the device is in a standby mode, only the VDDI internal  
supply voltage and the bias currents are established and no  
further activities will occur. Once the SD and STBY pins are  
released to enable the device, the internal VDDI POR signal is  
also released. The rest of the internal blocks will be enabled  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
FUNCTIONAL DEVICE OPERATION  
PROTECTION AND DIAGNOSTIC FEATURES  
and the buck converter switching frequency value is  
the IC goes out of standby or shutdown mode, power is  
recycled, or after a fault retry.  
determined by reading the FREQ pin. A soft start cycle is then  
initiated to ramp up the output of the buck converter (VTT).  
The buck converter error amplifier uses the voltage on the  
VREFOUT pin (VREF) as its reference voltage. VREF is equal  
to 1/2 VDDQ, where VDDQ is applied to the VREFIN pin. This  
way, the 34712 assures that VREF and VTT voltages track 1/2  
To fully take advantage of soft starting, it is recommended  
not to enable the 34712 output before introducing VDDQ on  
the VREFIN pin. If this happens after a soft start cycle expires  
and the VREFIN voltage has a high dv/dt, the output will  
naturally track it immediately and ramp up with a fast dv/dt  
itself and that will defeat the purpose of soft starting. For  
reliable operation, it is best to have the VDDQ voltage  
available before enabling the output of the 34712.  
VDDQ to meet DDR requirements.  
Soft start is used to prevent the output voltage from  
overshooting during startup. At initial startup, the output  
capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage  
across the inductor will be PVIN during the capacitor charge  
phase which will create a very sharp di/dt ramp. Allowing the  
inductor current to rise too high can result in a large  
difference between the charging current and the actual load  
current that can result in an undesired voltage spike once the  
capacitor is fully charged. The soft start is active each time  
After a successful start-up cycle where the device is  
enabled, no faults have occurred, and the output voltage has  
reached its regulation point, the 34712 pulls the power good  
output signal low after a 10 ms reset delay, to indicate to the  
host that the device is in normal operation.  
PROTECTION AND DIAGNOSTIC FEATURES  
The 34712 monitors the application for several fault  
conditions to protect the load from overstress. The reaction of  
the IC to these faults ranges from turning off the outputs to  
just alerting the host that something is wrong. In the following  
paragraphs, each fault condition is explained:  
current limit (ILIM), the converter will start a cycle-by-cycle  
operation to limit the current, and a 10 ms over current limit  
timer (tLIM) starts. The converter will stay in this mode of  
operation until one of the following occurs:  
• The current is reduced back to the normal level before  
tLIM expires, and in this case normal operation is  
regained.  
Output Overvoltage  
• tLIM expires without regaining normal operation, at  
which point the device turns off the output and the  
power good output signal is pulled high. At the end of a  
time-out period of 100 ms (tTIMEOUT), the device will  
attempt another soft start cycle.  
An overvoltage condition occurs once the output voltage  
goes higher than the rising overvoltage threshold (VOVR). In  
this case, the power good output signal is pulled high, alerting  
the host that a fault is present, but the VTT and VREF outputs  
will stay active. To avoid erroneous overvoltage conditions, a  
20 µs filter is implemented. The buck converter will use its  
feedback loop to attempt to correct the fault. Once the output  
voltage falls below the falling overvoltage threshold (VOVF),  
the fault is cleared and the power good output signal is pulled  
low, the device is back in normal operation.  
• The device reaches the thermal shutdown limit (TSDFET  
)
and turns off the output. The power good output signal  
is pulled high.  
Short Circuit Current Limit  
This block uses the same current detection mechanism as  
the over current limit detection block. If the load current  
reaches the ISHORT value, the device reacts by shutting down  
the output immediately. This is necessary to prevent damage  
in case of a permanent short circuit. Then, at the end of a  
time-out period of 100 ms (tTIMEOUT), the device will attempt  
another soft start cycle.  
Output Undervoltage  
An undervoltage condition occurs once the output voltage  
falls below the falling undervoltage threshold (VUVF). In this  
case, the power good output signal is pulled high, alerting the  
host that a fault is present, but the VTT and VREF outputs will  
stay active. To avoid erroneous undervoltage conditions, a  
20 µs filter is implemented. The buck converter will use its  
feedback loop to attempt to correct the fault. Once the output  
voltage rises above the rising undervoltage threshold (VUVR),  
the fault is cleared and the power good output signal is pulled  
low, the device is back in normal operation.  
Thermal Shutdown  
Thermal limit detection block monitors the temperature of  
the device and protects against excessive heating. If the  
temperature reaches the thermal shutdown threshold  
(TSDFET), the converter output switches off and the power  
good output signal indicates a fault by pulling high. The  
device will stay in this state until the temperature has  
decreased by the hysteresis value and then After a time-out  
period (TTIMEOUT) of 100 ms, the device will retry  
Output Over Current  
This block detects over current in the Power MOSFETs of  
the buck converter. It is comprised of a sense MOSFET and  
a comparator. The sense MOSFET acts as a current  
detecting device by sampling a ratio of the load current. That  
sample is compared via the comparator with an internal  
reference to determine if the output is in over current or not.  
If the peak current in the output inductor reaches the over  
automatically and the output will go through a soft start cycle.  
If successful normal operation is regained, the power good  
output signal is asserted low to indicate that.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
TYPICAL APPLICATIONS  
PROTECTION AND DIAGNOSTIC FEATURES  
TYPICAL APPLICATIONS  
VIN  
BOOT  
VIN  
BOOT  
I/O SIGNALS  
4.7_nopop  
VDDI  
C15  
SW  
VDDI  
J2  
0.1uF  
PVIN  
PVIN  
R16  
PVIN  
3
2
1
VIN  
C14  
U1  
GND  
0.1uF  
R12  
10k_nopop FREQ  
J3  
GND  
VMASTER  
VOUT  
3
2
1
1
18  
17  
16  
15  
14  
13  
SGND  
FREQ  
N/C  
PVIN  
SW  
SW  
R11  
10k  
FREQ  
2
3
4
5
6
SW  
SW  
MC34712  
PG  
PG  
PG  
SW  
STBY  
VMASTER PGOOD LED  
STBY  
SD  
STBY  
SD  
GND  
GND  
SD  
GND  
VMASTER  
VIN  
R7  
1k  
R8  
10k_nopop  
VREFIN  
VREFIN  
VREFIN  
D1  
LED  
R9  
C11  
C13  
0.1uF  
10k_nopop  
0.1uF  
VOUT  
LED  
VOUT  
VREFOUT  
VREFOUT  
INV  
INV  
C12  
0.1uF  
COMP  
COMP  
JUMPERS  
BUCK CONVERTER  
VOUT1 VOUT2  
L1  
J1  
SW  
VOUT  
PVIN  
VMASTER  
VREFIN  
1
2
1
3
5
7
9
2
4
6
8
10  
STBY  
1.5uH  
LED  
PG  
R3  
STBY  
1
1
2
2
D2  
PMEG2010EA_nopop  
C6  
100uF  
C7  
100uF  
C8  
100uF  
SD  
4.7_nopop  
C9  
CON10A  
1nF_nopop  
SD  
OPTIONAL nopop  
COMPENSATION NETWORK  
PVIN CAPACITORS  
VOUT  
VDDI  
PVIN  
FREQ  
R6  
C20  
1nF  
C1  
0.1uF  
C2  
1uF  
C3  
100uF  
C4  
100uF  
C5  
100uF  
POT_50K_nopop  
R1  
INV  
20k  
C18  
COMP  
R14  
300  
VIN CAPACITORS  
0.02nF  
VIN  
R15  
15k  
C19  
R2  
12.7k_nopop  
C17  
C16  
1.9nF  
10uF  
0.1uF  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
16  
TYPICAL APPLICATIONS  
PROTECTION AND DIAGNOSTIC FEATURES  
Inductor calculation is straight forward, being  
COMPONENT SELECTION  
SWITCHING FREQUENCY SELECTION  
The switching frequency defaults to a value of 1.0 MHz  
when the FREQ pin is grounded, and 200 KHz when the  
FREQ pin is connected to VDDI. Intermediate switching  
frequencies can be obtained by connecting an external  
resistor divider to the FREQ pin. The table below shows the  
resulting switching frequency versus FREQ pin voltage.  
where,  
Table 5. Switching Frequency Adjustment  
Maximum OFF time percentage  
Switching period.  
FREQUENCY  
200  
VOLTAGE APPLIED TO PIN FREQ  
2.341 – 2.500  
2.185 - 2.340  
253  
307  
2.029 - 2.184  
360  
1.873 - 2.028  
Drain – to – source resistance of FET  
Winding resistance of Inductor  
413  
1.717 – 1.872  
1.561 – 1.716  
1.405 - 1.560  
466  
520  
573  
1.249 - 1.404  
627  
1.093 - 1.248  
Output current ripple.  
680  
0.936 - 1.092  
OUTPUT FILTER CAPACITOR  
733  
0.781 - 0.936  
For the output capacitor, the following considerations are  
more important than the actual capacitance value, the  
physical size, the ESR and the voltage rating:  
787  
0.625 - 0.780  
840  
0.469 - 0.624  
Transient Response percentage, TR_%  
Maximum Transient Voltage, TR_v_dip = Vo*TR_%  
Maximum current step,  
893  
0.313 - 0.468  
947  
0.157 - 0.312  
1000  
0.000 - 0.156  
Inductor Current rise time,  
where,  
D_max = Maximum ON time percentage.  
IO = Rated output current.  
Figure 7. Resistor Divider for Frequency Adjustment  
SELECTION OF THE INDUCTOR  
Vin_min = Minimum input voltage at PVIN  
As a result, it is possible to calculate  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
TYPICAL APPLICATIONS  
PROTECTION AND DIAGNOSTIC FEATURES  
Gate  
F
Driver  
SW  
In order to find the maximum allowed ESR,  
SW  
PWM  
Comparitor  
L
VOUT  
Ramp  
Generator  
C
O
R
R
O
S
Error  
Amplifier  
C
S
INV  
V
REFOUT  
R
C
F
The effects of the ESR is often neglected by the designers  
and may present a hidden danger to the ultimate supply  
stability. Poor quality capacitors have widely disparate ESR  
value, which can make the closed loop response  
inconsistent.  
C
X
F
COMP  
34712  
Figure 9. Type III Compensation Network  
Consider the crossover frequency, FCROSS, of the open loop  
gain at one-sixth of the switching frequency, FSW.  
Then,  
Io  
Io_step  
Current  
response  
Worst case  
dt_I_rise  
assumption  
where RO is a user selected resistor. Knowing the LC  
frequency, it can be obtained the values of RF and CS:  
Figure 8. Transient Parameters  
TYPE III COMPENSATION NETWORK  
Power supplies are desired to offer accurate and tight  
regulation output voltages. To accomplish this requires a high  
DC gain. But with high gain comes the possibility of instability.  
The purpose of adding compensation to the internal error  
amplifier is to counteract some of the gains and phases  
contained in the control-to-output transfer function that could  
jeopardized the stability of the power supply. The Type III  
compensation network used for 34712 comprises two poles  
(one integrator and one high frequency pole to cancel the  
zero generated from the ESR of the output capacitor) and two  
zeros to cancel the two poles generated from the LC filter as  
shown in Figure 9.  
This gives as a result,  
&
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
18  
TYPICAL APPLICATIONS  
PROTECTION AND DIAGNOSTIC FEATURES  
Calculate Rs by placing the Pole 1 at the ESR zero  
frequency:  
BOOTSTRAP CAPACITOR  
The bootstrap capacitor is needed to supply the gate  
voltage for the high side MOSFET. This N-Channel MOSFET  
needs a voltage difference between its gate and source to be  
able to turn on. The high side MOSFET source is the SW  
node, so it is not ground and it is floating and moving in  
voltage, so we cannot just apply a voltage directly to the gate  
of the high side that is referenced to ground, we need a  
voltage referenced to the SW node. That is why the bootstrap  
capacitor is needed for. This capacitor charges during the  
high side off time, since the low side will be on during that  
time, so the SW node and the bottom of the bootstrap  
capacitor will be connected to ground and the top of the  
capacitor will be connected to a voltage source, so the  
capacitor will charge up to that voltage source (say 5V). Now  
when the low side MOSFET switches off and the high side  
MOSFET switches on, the SW nodes rises up to Vin, and the  
voltage on the boot pin will be Vcap + Vin. So the gate of the  
high side will have Vcap across it and it will be able to stay  
enhanced. A 0.1µF capacitor is a good value for this  
bootstrap element.  
Equating the Pole 2 at Crossover Frequency to achieve a  
faster response and a proper phase margin,  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
PACKAGING  
PACKAGING DIMENSIONS  
PACKAGING  
PACKAGING DIMENSIONS  
EP SUFFIX  
24 -PIN  
PLASTIC PACKAGE  
98ARL10577D  
ISSUE B  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
20  
PACKAGING  
PACKAGING DIMENSIONS  
EP SUFFIX  
24 -PIN  
PLASTIC PACKAGE  
98ARL10577D  
ISSUE B  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
21  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
Pre-release version  
Implemented Revision History page  
2/2006  
1.0  
Initial release  
11/2006  
2/2007  
5/2007  
2.0  
3.0  
4.0  
Converted format from Market Assessment to Product Preview  
Major updates to the data, form, and style  
Replaced all electrolytic capacitors with ceramic ones in Figure 1  
Deleted Deadtime in Dynamic Electrical Characteristics  
Moved Figures 8 ahead of TYPE III COMPENSATION NETWORK  
Changed Features fom 2% to 1%  
Changed 34712 Simplified Application Diagram  
Removed Machine Model in Maximum Ratings  
Added minimum limits to Input DC Supply Current (11) Normal mode, Input DC Supply Current (11)  
Standby mode, and Input DC Supply Current (11) Shutdown mode  
Added High-side MOSFET Drain Voltage Range  
(13) (14)  
Changed Output Voltage Accuracy (12)  
Changed Short Circuit Current Limit  
,
,
Changed High-Side N-CH Power MOSFET (M3) RDS(ON) (12) and Low-Side N-CH Power  
MOSFET (M4) RDS(ON) (12)  
Changed M2 RDS(ON)  
Changed PVIN Pin Leakage Current  
Changed VREFOUT Buffered Reference Voltage Accuracy (17), VREFOUT Buffered Reference  
Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over Current Limit  
Changed STBY Pin Internal Pull Up Resistor and SD Pin Internal Pull Up Resistor  
Changed Soft Start Duration, Over Current Limit Retry Time-out Period, and Output Undervoltage/  
Overvoltage Filter Delay Timer  
Changed Oscillator Default Switching Frequency (18)  
Changed PG Reset Delay and Thermal Shutdown Retry Time-out Period (19)  
Changed drawings in Typical Applications  
Changed drawing in Type III Compensation Network  
Removed PC34712EP/R2 from the ordering information and added MC34712EP/R2  
Changed the data sheet status to Advance Information  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
22  
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