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Document Number: MC34716  
Rev. 3.0, 5/2007  
Freescale Semiconductor  
Advance Information  
1.0 MHz Dual Switch-Mode DDR  
Power Supply  
34716  
The 34716 is a highly integrated, space-efficient, low cost, dual  
synchronous buck switching regulator with integrated N-channel  
power MOSFETs. It is a high performance point-of-load (PoL) power  
supply with its second output having the ability to track an external  
reference voltage. it provides a full power supply solution for Double-  
Data-Rate (DDR) Memories.  
DUAL SWITCH-MODE DDR POWER  
SUPPLY  
Channel one provides a source only 5.0 A drive capability, while  
channel two can sink and source up to 3.0 A. Both channels are highly  
efficient with tight output regulation. With its high current drive  
capability, channel one can be used to supply the VDDQ to the  
memory chipset. The second channel’s ability to track a reference  
voltage makes it ideal to provide the termination voltage (VTT) for  
modern data buses. The 34716 also provides a buffered output  
reference voltage (VREFOUT) to the memory chipset  
The 34716 offers the designer the flexibility of many control,  
supervisory, and protection functions to allow for easy implementation  
of complex designs. It is housed in a Pb-Free, thermally enhanced,  
and space efficient 26-Pin Exposed Pad QFN.  
EP SUFFIX  
98ASA10728D  
26-PIN QFN  
Features  
• 50 mIntegrated N-Channel Power MOSFETs  
• Input Voltage Operating Range from 3.0 V to 6.0 V  
ORDERING INFORMATION  
Temperature  
±1 % Accurate Output Voltages, Ranging from 0.7 V to 3.6 V  
• The second output Tracks 1/2 an External Reference Voltage  
±1 % Accurate Buffered Reference Output Voltage  
Package  
Device  
Range (T )  
A
MC34716EP/R2  
-40 to 85°C  
26 QFN  
• Programmable Switching Frequency Range from 200 kHz to  
1.0 MHz  
• Programmable Soft Start Timing for Channel One  
• Over Current Limit and Short Circuit Protection on Both Channels  
• Thermal Shutdown  
• Output Overvoltage and Undervoltage Detection  
• Active Low Power Good Output Signal  
• Active Low Standby and Shutdown Inputs  
• Pb-Free Packaging Designated by Suffix Code EP.  
34716  
3.0V to 6.0V VIN  
PVIN2  
VIN  
VDDQ  
VREFIN  
BOOT2  
PVIN1  
BOOT1  
VDDQ  
VTT  
SW2  
SW1  
VOUT1  
VOUT2  
Termination  
Resistors  
VDDQ  
INV2  
INV1  
DDR Memory  
Chipset  
DDR Memory  
Controller  
Memory Bus  
COMP1  
PGND1  
COMP2  
VREFOUT  
PGND2  
VREF  
VIN  
VDDI  
FREQ  
PG  
MCU  
STBY  
SD  
ILIM1  
GND  
Figure 1. 34716 Simplified Application Diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
STBY  
SD  
PG  
System  
Reset  
Thermal  
M1  
Monitoring  
System  
Control  
Oscillator  
Discharge  
VBG  
FREQ  
Buck  
Control  
Logic  
Bandgap  
Regulator  
ILIM2  
ILIM1  
VDDI  
ISENSE2  
ISENSE1  
Internal  
Voltage  
Regulator  
Current  
Monitoring  
ILIM1  
VIN  
BOOT1  
PVIN1  
BOOT2  
PVIN2  
M2  
VIN  
M3  
VIN  
M4  
M6  
M7  
Gate  
Driver  
Gate  
Driver  
SW1  
FSW  
FSW  
SW2  
ISENSE  
ISENSE  
M5  
PWM  
PWM  
PGND1  
COMP1  
Comparator  
Comparator  
PGND2  
COMP2  
Ramp  
Generator  
Ramp  
Generator  
Error  
Amplifier  
Error  
Amplifier  
VBG  
INV1  
INV2  
M8  
M9  
VOUT1  
VOUT2  
Discharge  
Discharge  
CHANNEL 2  
CHANNEL 1  
+
VREFIN  
M10  
Discharge  
GND  
VREFOUT  
Figure 2. 34716 Simplified Internal Block Diagram  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
19  
21 20  
24 23  
22  
26 25  
BOOT1  
PVIN1  
BOOT2  
PVIN2  
1
18  
17  
2
PVIN1  
SW1  
PVIN2  
SW2  
Transparent  
Top View  
3
4
16  
15  
SW1  
SW2  
PGND2  
PGND1  
PGND1  
VOUT1  
PGND2  
5
14 VOUT2  
6
7
9
12  
13  
8
10 11  
Figure 3. 34716 Pin Connections  
Table 1. 34716 Pin Definitions  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
Channel 1 Bootstrap capacitor input pin  
1
2
3
4
5
BOOT1  
PVIN1  
SW1  
Passive  
Supply  
Bootstrap  
Power Input Voltage  
Switching Node  
Power Ground  
Channel 1 Buck converter power input  
Channel 1 Buck converter switching node  
Input/Output  
Ground  
Channel 1 Buck converter and discharge MOSFETs power ground  
Channel 1 Buck converter output voltage discharge pin  
PGND1  
VOUT1  
Input  
Output Voltage  
Discharge Path  
Channel 1 Buck converter error amplifier inverting input  
Channel 1 Buck converter external compensation network input  
Voltage tracking reference voltage input  
6
7
INV1  
COMP1  
VREFIN  
VREFOUT  
PG  
Input  
Input  
Error Amplifier  
Inverting Input  
Buck Convertor  
Compensation Input  
8
Input  
Reference Voltage  
Input  
This is a buffered reference voltage output  
9
Output  
Output  
Reference Voltage  
Output  
It is an active low open drain power good status reporting output  
10  
Power Good Output  
Signal  
Shutdown mode input control pin  
11  
12  
SD  
Input  
Input  
Shutdown Input  
Channel 2 Buck converter external compensation network input  
COMP2  
Buck Convertor  
Compensation Input  
Channel 2 Buck converter error amplifier inverting input  
13  
INV2  
Input  
Error Amplifier  
Inverting Input  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
Table 1. 34716 Pin Definitions (continued)  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
Channel 2 Buck converter output voltage discharge pin  
14  
VOUT2  
Output  
Output Voltage  
Discharge Path  
Channel 2 Buck converter and discharge MOSFETs power ground  
Channel 2 Buck converter switching node  
Channel 2 Buck converter power input  
15  
16  
17  
18  
19  
PGND2  
SW2  
Ground  
Input/Output  
Power  
Power Ground  
Switching Node  
Power Input Voltage  
Bootstrap Input  
PVIN2  
BOOT2  
ILIM1  
Channel 2 Bootstrap capacitor input pin  
Channel 1 soft start adjustment  
Input  
Input  
Soft Start Adjustment  
Input  
No internal connections to this pin  
20  
21  
NC  
None  
Input  
No Connect  
The buck converters switching frequency adjustment input  
FREQ  
FrequencyAdjustment  
Input  
Power supply voltage of the IC  
Analog ground of the IC  
22,23  
24  
VIN  
GND  
VDDI  
Power  
Ground  
Output  
Input Supply Voltage  
Signal Ground  
Internal Supply Voltage Output  
25  
Internal Supply  
Voltage  
Standby mode input control pin  
26  
STBY  
Input  
Standby Input  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Ratings  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Input Supply Voltage (VIN) Pin  
VIN  
PVIN  
-0.3 to 7.0  
-0.3 to 7.0  
-0.3 to 7.5  
-0.3 to 7.5  
-0.3 to 7.0  
-0.3 to 3.0  
V
V
V
V
V
V
High-Side MOSFET Drain Voltage (PVIN1, PVIN2) Pins  
Switching Node (SW1, SW2) Pins  
VSW  
BOOT1, BOOT2 Pins (Referenced to SW1, SW2 Pins Respectively)  
PG, VOUT1, VOUT2, SD, and STBY Pins  
VBOOT - VSW  
-
-
VDDI, FREQ, ILIM1, INV1, INV2, COMP1, COMP2, VREFIN, and VREFOUT  
Pins  
Channel 1 Continuous Output Current (1)  
Channel 2 Continuous Output Current (1)  
ESD Voltage (2)  
IOUT1  
IOUT2  
+5.0  
±3.0  
A
A
V
Human Body Model (3)  
Charge Device Model  
VESD1  
VESD3  
±2000  
±750  
THERMAL RATINGS  
Operating Ambient Temperature (4)  
TA  
-40 to 85  
-65 to +150  
Note 6  
°C  
Storage Temperature  
TSTG  
TPPRT  
TJ(MAX)  
PD  
°C  
°C  
Peak Package Reflow Temperature During Reflow (5)  
Maximum Junction Temperature  
Power Dissipation (TA = 85 °C) (7)  
Notes  
,
(6)  
+150  
2.03  
°C  
W
1. Continuous output current capability so long as T is TJ(MAX)  
.
J
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device  
Model (CDM).  
3. SW1 pin complies with ±1000V Human Body Model.  
4. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.  
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
7. Maximum power dissipation at indicated ambient temperature.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings (continued)  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or  
permanent damage to the device.  
Ratings  
Symbol  
Value  
Unit  
THERMAL RESISTANCE (8)  
Thermal Resistance, Junction to Ambient, Single-Layer Board (1s) (9)  
Thermal Resistance, Junction to Ambient, Four-Layer Board (2s2p) (10)  
Thermal Resistance, Junction to Board (11)  
RθJA  
RθJMA  
RQJB  
93  
32  
°C/W  
°C/W  
°C/W  
13.6  
Notes  
8. The PVIN, SW, and PGND pins comprise the main heat conduction paths.  
9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.  
10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are thermal vias connecting the package to the two planes in the  
board. (per JESD51-5)  
11. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top  
surface of the board near the package.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
IC INPUT SUPPLY VOLTAGE (VIN)  
Symbol  
Min  
Typ  
Max  
Unit  
Input Supply Voltage Operating Range  
VIN  
IIN  
3.0  
-
-
-
6.0  
35  
V
Input DC Supply Current (12)  
mA  
(Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs)  
Input DC Supply Current (12)  
IINQ  
-
-
-
-
25  
mA  
µA  
(Standby Mode, SD = 1 & STBY = 0)  
Input DC Supply Current (12)  
IINOFF  
100  
(Shutdown Mode, SD = 0 & STBY = X)  
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)  
Internal Supply Voltage Range  
VDDI  
2.35  
2.5  
2.65  
V
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1)  
CH 1 High-side MOSFET Drain Voltage Range  
Output Voltage Adjustment Range (13)  
Output Voltage Accuracy (13), (14), (15)  
PVIN  
VOUTHI1  
-
2.5  
0.7  
-
-
-
-
6.0  
3.6  
1.0  
1.0  
V
V
-1.0  
-1.0  
%
%
Line Regulation (13)  
REGLN1  
(Normal Operation, VIN = 3.0 V to 6.0 V, IOUT1 = +5.0 A)  
Load Regulation (13)  
REGLD1  
-1.0  
-
1.0  
%
(Normal Operation, IOUT1 = 0.0 A to 5.0 A)  
Error Amplifier Reference Voltage (13)  
Output Undervoltage Threshold  
Output Overvoltage Threshold  
Continuous Output Current  
VREF1  
VUVR1  
-
-1.5  
1.5  
-
0.7  
-
-8.0  
8.0  
5.0  
-
V
%
%
A
-
VOVR1  
-
-
IOUT1  
Over Current Limit  
ILIM1  
-
6.5  
-
A
Soft Start Adjusting Reference Voltage Range  
Short Circuit Current Limit  
VILIM1  
1.25  
-
VDDI  
-
V
ISHORT1  
RDS(ON)HS1  
8.5  
-
A
(13)  
High-Side N-CH Power MOSFET (M4) RDS(ON)  
15  
50  
mΩ  
(IOUT1 = 1.0 A, VBOOT1 - VSW1= 3.3 V)  
Notes  
12. Section “MODES OF OPERATION”, page 15 has a detailed description of the different operating modes of the 34716  
13. Design information only, this parameter is not production tested.  
14. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended.  
15. ±1% is assured at room temperature.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
(16)  
Low-Side N-CH Power MOSFET (M5) RDS(ON)  
(IOUT1 = 1.0 A, VIN = 3.3 V)  
RDS(ON)LS1  
15  
-
50  
mΩ  
M2 RDS(ON)  
RDS(ON)M2  
2.0  
-10  
-
-
4.0  
10  
(VIN = 3.3 V, M2 is on)  
PVIN1 Pin Leakage Current  
(Shutdown Mode)  
IPVIN1  
µA  
INV1 Pin Leakage Current  
IINV1  
-1.0  
-
1.0  
µA  
°C  
°C  
Thermal Shutdown Threshold (16)  
Thermal Shutdown Hysteresis (16)  
TSDFET1  
TSDHYFET1  
-
-
170  
25  
-
-
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2)  
CH 2 High-side MOSFET Drain Voltage Range  
Output Voltage Adjustment Range (16)  
Output Voltage Accuracy (16), (17), (18)  
PVIN  
VOUTHI2  
-
2.5  
0.7  
-
-
-
-
6.0  
1.35  
1.0  
V
V
-1.0  
-1.0  
%
%
Line Regulation (16)  
REGLN2  
1.0  
(Normal Operation, VIN = 3.0 V to 6.0 V, IOUT2 = ±3.0 A)  
Load Regulation (16)  
REGLD2  
-1.0  
-
1.0  
%
(Normal Operation, IOUT2 = -3.0 A to 3.0 A)  
Error Amplifier Common Mode Voltage Range (16), (19)  
Output Undervoltage Threshold  
VREF2  
VUVR2  
VOVR2  
IOUT2  
ILIM2  
0.0  
-1.5  
1.5  
-3.0  
-
-
1.35  
-8.0  
8.0  
3.0  
-
V
%
%
A
-
-
Output Overvoltage Threshold  
Continuous Output Current  
-
Over Current Limit  
4.0  
A
(Sinking and Sourcing)  
Short Circuit Current Limit  
(Sinking and Sourcing)  
ISHORT2  
-
6.5  
-
-
A
(16)  
High-Side N-CH Power MOSFET (M6) RDS(ON)  
RDS(ON)HS2  
15  
50  
mΩ  
(IOUT2 = 1.0 A, VBOOT2 - VSW2= 3.3 V)  
(16)  
Low-Side N-CH Power MOSFET (M7) RDS(ON)  
RDS(ON)LS2  
RDS(ON)M3  
IPVIN2  
15  
2.0  
-10  
-
-
-
50  
4.0  
10  
mΩ  
(IOUT2 = 1.0 A, VIN = 3.3 V)  
M3 RDS(ON)  
(VIN = 3.3 V, M3 is on)  
PVIN2 Pin Leakage Current  
µA  
(Standby and Shutdown Modes)  
Notes  
16. Design information only, this parameter is not production tested.  
17. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended  
18. ±1% is assured at room temperature  
19. The 1 % output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7V  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
8
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
INV2 Pin Leakage Current  
IINV2  
-1.0  
-
1.0  
µA  
°C  
°C  
(20)  
Thermal Shutdown Threshold  
Thermal Shutdown Hysteresis  
OSCILLATOR (FREQ)  
TSDFET2  
TSDHYFET2  
-
-
170  
25  
-
-
(20)  
Oscillator Frequency Adjusting Reference Voltage Range  
VFREQ  
0.0  
-
VDDI  
V
TRACKING (VREFIN, VREFOUT, VOUT1, VOUT2)  
(20)  
VREFIN External Reference Voltage Range  
VREFIN  
VREFOUT  
-
0.0  
0.0  
-1.0  
0.0  
-
-
-
2.7  
1.35  
1.0  
8.0  
-
V
V
VREFOUT Buffered Reference Voltage Range  
VREFOUT Buffered Reference Voltage Accuracy (21)  
VREFOUT Buffered Reference Voltage Current Capability  
VREFOUT Buffered Reference Voltage Over Current Limit  
-
%
IREFOUT  
IREFOUTLIM  
RTDR(M10)  
RTDR(M8)  
RTDR(M9)  
IVOUTLKG2  
-
mA  
mA  
11  
50  
50  
50  
-
(20)  
VREFOUT Total Discharge Resistance  
-
-
(20)  
VOUT1 Total Discharge Resistance  
-
-
(20)  
VOUT2 Total Discharge Resistance  
-
-
VOUT2 Pin Leakage Current  
(Standby Mode, VOUT2 = 3.6 V)  
-1.0  
1.0  
µA  
CONTROL AND SUPERVISORY (STBY, SD, PG)  
STBY High Level Input Voltage  
STBY Low Level Input Voltage  
STBY Pin Internal Pull Up Resistor  
SD High Level Input Voltage  
VSTBYHI  
VSTBYLO  
RSTBYUP  
VSDHI  
2.0  
-
-
-
-
-
-
-
-
-
V
V
0.4  
2.0  
-
1.0  
2.0  
-
MΩ  
V
SD Low Level Input Voltage  
VSDLO  
0.4  
2.0  
0.4  
V
SD Pin Internal Pull Up Resistor  
RSDUP  
1.0  
-
MΩ  
V
PG Low Level Output Voltage  
(IPG = 3.0 mA)  
VPGLO  
PG Pin Leakage Current  
IPGLKG  
-
-
1.0  
µA  
(M1 is off, Pulled up to VIN)  
Notes  
20. Design information only, this parameter is not production tested.  
21. The 1 % accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions 3.0 V VIN 6.0 V, -40°C TA 85°C, GND = 0 V unless otherwise noted. Typical  
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1)  
Switching Node (SW1) Rise Time (22)  
tRISE1  
-
-
8.0  
5.0  
-
-
ns  
ns  
(PVIN = 3.3 V, IOUT1 = 5.0 A)  
Switching Node (SW1) Fall Time (22)  
tFALL1  
(PVIN = 3.3 V, IOUT1 = 5.0 A)  
Soft Start Duration (Normal Mode)  
tSS1  
ms  
ILIM1: 1.25V to 1.49V  
1.5V to 1.81V  
-
-
-
-
3.2  
1.6  
0.8  
0.4  
-
-
-
-
1.82V to 2.13V  
2.14V to 2.5V  
Over Current Limit Timer  
tLIM1  
-
10  
-
-
ms  
ms  
µs  
Over Current Limit Retry Time-out Period  
Output Undervoltage/Overvoltage Filter Delay Timer  
tTIMEOUT1  
tFILTER1  
80  
5.0  
120  
25  
-
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2)  
Switching Node (SW2) Rise Time (22)  
(PVIN = 3.3 V, IOUT2 = ±3.0 A)  
tRISE2  
-
-
28  
-
-
ns  
ns  
Switching Node (SW2) Fall Time (22)  
(PVIN = 3.3 V, IOUT2 = ±3.0 A)  
tFALL2  
12.0  
Soft Start Duration (Normal Mode)  
Over Current Limit Timer  
tSS2  
tLIM2  
tTIMEOUT2  
tFILTER2  
-
-
1.6  
10  
-
-
-
ms  
ms  
ms  
µs  
Over Current Limit Retry Time-out Period  
Output Undervoltage/Overvoltage Filter Delay Timer  
OSCILLATOR (FREQ) (23)  
80  
5.0  
120  
25  
-
Oscillator Default Switching Frequency  
(FREQ = GND)  
fSW  
-
1.0  
-
-
MHz  
kHz  
Oscillator Switching Frequency Range  
CONTROL AND SUPERVISORY (STBY, SD, PG)  
PG Reset Delay  
fSW  
200  
1000  
tPGRESET  
tTIMEOUT  
8.0  
80  
-
-
12  
ms  
ms  
Thermal Shutdown Retry Time-out Period (22)  
120  
Notes  
22. Design information only, this parameter is not production tested.  
23. Oscillator Frequency tolerance is ±10%.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
In modern microprocessor/memory applications, address  
continuous current from the other output. It provides  
commands and control lines require system level termination  
to a voltage (VTT) equal to 1/2 the memory supply voltage  
(VDDQ). Having the termination voltage at midpoint, the power  
supply insures symmetry for switching times. Also, a  
reference voltage (VREF) that is free of any noise or voltage  
variations is needed for the DDR SDRAM input receiver,  
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will  
effect the setup and hold time of the memory. To comply with  
DDR requirements and to obtain best performance, VTT and  
VREF need to be tightly regulated to track 1/2 VDDQ across  
voltage, temperature, and noise margins. VTT should track  
any variations in the DC VREF value (VTT = VREF +/- 40 mV),  
(See Figure 4) for a DDR system level diagram.  
protection against output overcurrent, overvoltage,  
undervoltage, and overtemperature conditions. It also  
protects the system from short circuit events. It incorporates  
a power good output signal to alert the host when a fault  
occurs.  
For boards that support the Suspend-To-RAM (S3) and  
the Suspend-To-Disk (S5) states, the 34716 offers the STBY  
and the SD pins respectively. Pulling any of these pins low,  
puts the IC in the corresponding state.  
By integrating the control/supervisory circuitry along with  
the Power MOSFET switches for the buck converter into a  
space-efficient package, the 34716 offers a complete, small-  
size, cost-effective, and simple solution to satisfy the needs  
of DDR memory applications.  
The 34716 supplies the VDDQ, VTT and a buffered VREF  
output. To ensure compliance with DDR specifications, the  
VDDQ line is applied to the VREFIN pin and divided by 2  
internally through a precision resistor divider. This internal  
voltage is then used as the reference voltage for the VTT  
output. The same internal voltage is also buffered to give the  
VREF voltage at the VREFOUT pin for the application to use  
without the need for an external resistor divider. The 34716  
provides the tight voltage regulation and power sequencing/  
tracking required along with handling the DDR peak transient  
current requirements. It gives the user a complete DDR  
power supply solution with optimum performance. Buffering  
the VREF output helps its immunity against noise and load  
changes.  
Besides DDR memory termination, the 34716 can be used  
to supply termination for other active buses and graphics card  
memory. It can be used in Netcom/Telecom applications like  
servers. It can also be used in desktop motherboards, game  
consoles, set top boxes, and high end high definition TVs.  
VDDQ  
VDDQ  
VTT  
RT  
RS  
VREF  
The 34716 utilizes a voltage mode synchronous buck  
switching converter topology with integrated low RDS(ON)  
(50 m) N-channel power MOSFETs to provide an output  
voltage with an accuracy of less than ±2.0 % output voltage.  
It has a programmable switching frequency that allows for  
flexibility and optimization over the operating conditions and  
can operate at up to 1.0 MHz to significantly reduce the  
external components size and cost. The 34716 can supply up  
to 5.0 A from one output and sink and source up to 3.0 A of  
BUS  
DDR Memory Input Receiver  
DDR Memory Controller  
Figure 4. DDR System Level Diagram  
FUNCTIONAL PIN DESCRIPTION  
SWITCHING NODE (SW1, SW2)  
BOOTSTRAP INPUT (BOOT1, BOOT2)  
Bootstrap capacitor input pin. Connect a capacitor (as  
discussed in Bootstrap capacitor on page 20) between this  
pin and the SW pin of the respective channel to enhance the  
gate of the high-side Power MOSFET during switching.  
Buck converter switching node. This pin is connected to  
the output inductor.  
POWER GROUND (PGND1, PGND2)  
Buck converter and discharge MOSFETs power ground. It  
is the source of the buck converter low-side power MOSFET.  
POWER INPUT VOLTAGE (PVIN1, PVIN2)  
Buck converter power input voltage. This is the drain of the  
buck converter high-side power MOSFET.  
COMPENSATION INPUT (COMP1, COMP2)  
Buck converter external compensation network connects  
to this pin. Use a type III compensation network.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
ERROR AMPLIFIER INVERTING INPUT (INV1, INV2)  
STANDBY INPUT (STBY)  
Buck converter error amplifier inverting input. Connect the  
VDDQ voltage (channel 1) to INV1 pin through a resistor  
divider and connect the VTT voltage (channel 2) directly to  
INV2 pin.  
If this pin is tied to the GND pin, the device will be in  
Standby Mode. If left unconnected or tied to the VIN pin, the  
device will be in Normal Mode. The pin has an internal pull up  
of 1.5 M. This input accepts the S3 (Suspend-To-RAM)  
control signal.  
OUTPUT VOLTAGE DISCHARGE PATH (VOUT1,  
VOUT2)  
SHUTDOWN INPUT (SD)  
If this pin is tied to the GND pin, the device will be in  
Shutdown Mode. If left unconnected or tied to the VIN pin, the  
device will be in Normal Mode. The pin has an internal pull up  
of 1.5 M. This input accepts the S5 (Suspend-To-Disk)  
control signal.  
Buck converters output voltage are connected to these  
pins. It only serves as the output discharge path once the SD  
signal is asserted.  
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)  
This is the output of the internal bias voltage regulator.  
Connect a 1.0 µF, 6 V low ESR ceramic filter capacitor  
between this pin and the GND pin. Filtering any spikes on this  
output is essential to the internal circuitry stable operation.  
REFERENCE VOLTAGE OUTPUT (VREFOUT)  
This is a buffered reference voltage output that is equal to  
1/2 VREFIN. It has a 10.0 mA current drive capability. This  
output is used as the VREF voltage rail and should be filtered  
against any noise. Connect a 0.1 µF, 6 V low ESR ceramic  
filter capacitor between this pin and the GND pin and  
between this pin and VDDQ rail. VREFOUT is also used as the  
reference voltage for the buck converter error amplifier.  
SIGNAL GROUND (GND)  
Analog ground of the IC. Internal analog signals are  
referenced to this pin voltage.  
INPUT SUPPLY VOLTAGE (VIN)  
REFERENCE VOLTAGE INPUT (VREFIN)  
IC power supply input voltage. Input filtering is required for  
the device to operate properly.  
The output of channel two will track 1/2 the voltage applied  
at this pin.  
POWER GOOD OUTPUT SIGNAL (PG)  
FREQUENCY ADJUSTMENT INPUT (FREQ)  
This is an active low open drain output that is used to  
report the status of the device to a host. This output activates  
after a successful power up sequence and stays active as  
long as the device is in normal operation and is not  
experiencing any faults. This output activates after a 10 ms  
delay and must be pulled up by an external resistor to a  
supply voltage like VIN.  
The buck converters switching frequency can be adjusted  
by connecting this pin to an external resistor divider between  
VDDI and GND pins. The default switching frequency (FREQ  
pin connected to ground, GND) is set at 1.0 MHz.  
CHANNEL 1 SOFT START ADJUSTMENT INPUT  
(ILIM1)  
Channel one Soft Start can be adjusted by applying a  
voltage between 1.25V and VDDI  
.
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
12  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
System Control  
& Logic  
Internal Bias  
Circuits  
Oscillator  
Control &  
Supervisory  
Functions  
Tracking &  
Sequencing  
Protection  
Functions  
2 x Buck Converter  
Figure 5. Block Illustration  
INTERNAL BIAS CIRCUITS  
PROTECTION FUNCTIONS  
This block contains all circuits that provide the necessary  
supply voltages and bias currents for the internal circuitry. It  
consists of:  
This block contains the following circuits:  
• Over Current Limit and Short Circuit Detection: This  
block monitors the output of the buck converters for  
over current conditions and short circuit events and  
alerts the system control for further command.  
• Thermal Limit Detection: This block monitors the  
temperature of the device for overheating events. If the  
temperature rises above the thermal shutdown  
threshold, this block will alert the system control for  
further commands.  
• Output Overvoltage and Undervoltage Monitoring: This  
block monitors the buck converters output voltages to  
ensure they are within regulation boundaries. If not, this  
block alerts the system control for further commands.  
• Internal Voltage Supply Regulator: This regulator  
supplies the VDDI voltage that is used to drive the digital/  
analog internal circuits. It is equipped with a Power-On-  
Reset (POR) circuit that watches for the right regulation  
levels. External filtering is needed on the VDDI pin. This  
block will turn off during the shutdown mode.  
• Internal Bandgap Reference Voltage: This supplies the  
reference voltage to some of the internal circuitry.  
• Bias Circuit: This block generates the bias currents  
necessary to run all of the blocks in the IC.  
SYSTEM CONTROL AND LOGIC  
CONTROL AND SUPERVISORY FUNCTIONS  
This block is the brain of the IC where the device  
processes data and reacts to it. Based on the status of the  
STBY and SD pins, the system control reacts accordingly and  
orders the device into the right status. It also takes inputs  
from all of the monitoring/protection circuits and initiates  
power up or power down commands. It communicates with  
the buck converter to manage the switching operation and  
protects it against any faults.  
This block is used to interface with an outside host. It  
contains the following circuits:  
• Standby Control Input: An outside host can put the  
34716 device into standby mode (S3 or Suspend-To-  
RAM mode) by sending a logic “0” to the STBY pin.  
• Shutdown Control Input: An outside host can put the  
34716 device into shutdown mode (S5 or Suspend-To-  
Disk mode) by sending a logic “0” to the SD pin.  
• Power Good Output Signal: The 34716 can  
communicate to an outside host that a fault has  
occurred by pulling the voltage on the PG pin high  
through a pull up resistor.  
OSCILLATOR  
This block generates the clock cycles necessary to run the  
IC digital blocks. It also generates the buck converters  
switching frequency. The switching frequency can be  
programmed by connecting a resistor divider to the FREQ  
pin, between VDDI and GND pins (See Figure 1, page 1).  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
operation. The buck converter is a high performance, fixed  
frequency (externally adjustable), Syncronous buck PWM  
voltage-mode control with a minimum on time of 100ns.  
It drives integrated 50 mN-channel power MOSFETs  
saving board space and enhancing efficiency. The switching  
regulator output voltage is adjustable with an accuracy of less  
than ±2 % to meet DDR requirements. The regulator's  
voltage control loop is compensated using a type III  
compensation network, with external components to allow for  
optimizing the loop compensation, for a wide range of  
operating conditions. A typical Bootstrap circuit with an  
internal PMOS switch is used to provide the voltage  
necessary to properly enhance the high-side MOSFET gate.  
TRACKING AND SEQUENCING  
This block allows the output of channel 2 of the 34716 to  
track 1/2 the voltage applied at the VREFIN pin. This allows  
the VREF and VTT voltages to track 1/2 VDDQ and assures that  
none of them will be higher than VDDQ at any point during  
normal operating conditions. For power down during a  
shutdown (S5) mode, the 34716 uses internal discharge  
MOSFETs (M8, M9, and M10 on Figure 2, page 2) to  
discharge VDDQ, VTT, and VREF respectively. These  
discharge MOSFETs are only active during shutdown mode.  
Using this block along with controlling the SD and STBY pins  
can offer the user the device for power sequencing by  
controlling when to turn the 34716 outputs on or off.  
The 34716 is designed to address DDR memory power  
supplies. The integrated converter has the ability to supply up  
to 5.0 A out of channel 1 and sink and source up to 3.0 A of  
continuous current from channel 2, providing a full power  
supply solution for DDR applications.  
BUCK CONVERTER  
This block provides the main function of the 34716: DC to  
DC conversion from an un-regulated input voltage to a  
regulated output voltage used by the loads for reliable  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
VIN < 3.0V  
SD = 1 &  
STBY = 0  
SD = 0 &  
STBY = x  
Power Off  
VDDQ = OFF  
VTT = OFF  
VShuDtdisocwhanrge  
Standby  
VDDQ = ON  
VTT = OFF  
V
REF = OFF  
PG = 1  
DDQ  
V
= Discharge  
TT  
V = Discharge  
VDDQ < = VUVF1  
VTT < = VUVF2  
V
REF = ON  
PG = 1  
REF  
PG = 1  
3.0V < = VIN < = 6.0V  
VDDQ  
Undervoltage  
VDDQ = ON  
SD = 1 &  
STBY = 1  
SD = 1 &  
STBY = 1  
VTT  
Undervoltage  
VDDQ = ON  
TT = ON  
VREF = ON  
PG = 1  
VTT > = VOVR2  
VTT = ON  
REF = ON  
PG = 1  
VDDQ > = VOVR1  
V
V
VTT > = VUVR2  
VDDQ  
Overvoltage  
VDDQ = ON  
VTT = ON  
REF = ON  
PG = 1  
VDDQ > = VUVR1  
VTT  
Overvoltage  
VDDQ = ON  
VTT = ON  
REF = ON  
PG = 1  
Normal  
VTT < = VOVF2  
FSW is programmed  
I
, is programmed  
LM1  
Vand V  
t
= 1  
VDDQ < = VOVF1  
TJ < = 145˚C  
V
V
DDQTTss
V
= ON  
DDQ
= ON  
TJ > = 170˚C  
TJ > = 170˚C  
TJ < = 145˚C  
tTIMEOUT Expired  
V
TT
Channel 1  
Thermal Shutdown  
Channel 2  
Thermal Shutdown  
t
TIMEOUT Expired  
V
= ON  
REF
PG = 0  
VDDQ = OFF  
TT = ON  
VDDQ = ON  
TT = OFF  
VREF = ON  
PG = 1  
tTIMEOUT  
Expired  
V
tTIMEOUT  
Expired  
V
V
REF = ON  
PG = 1  
Channel 1  
Channel 2  
Overcurrent  
VDDQ = ON  
tTIMEOUT  
Expired  
tTIMEOUT  
Expired  
Overcurrent  
VDDQ = OFF  
TT = ON  
IOUT1 > = ILIM1  
For > = 10ms  
IOUT2 > = ILIM2  
For > = 10ms  
VTT  
V
VTT = OFF  
VDDQ  
Short Circuit  
VDDQ = OFF  
VTT = ON  
VREF = ON  
PG = 1  
V
REF = ON  
PG = 1  
Short Circuit  
VDDQ = ON  
VTT = OFF  
VREF = ON  
PG = 1  
t
TIMEOUT = 1  
tTIMEOUT = 1  
V
REF = ON  
PG = 1  
t
TIMEOUT = 1  
tTIMEOUT = 1  
IOUT2 > = ISHORT2  
IOUT1 > = ISHORT1  
Figure 6. Operation Modes Diagram  
Shutdown Mode  
MODES OF OPERATION  
The 34716 has three primary modes of operation:  
In this mode, activated by pulling the SD pin low, the chip  
is in a shutdown state and the outputs are all disabled and  
discharged. This is the S4/S5 power state or Suspend-To-  
Disk state, where the DRAM will loose all of its data content  
(no power supplied to the DRAM). The reason to discharge  
the VTT and VREF lines is to ensure upon exiting, the  
Normal Mode  
In normal mode, all functions and outputs are fully  
operational. To be in this mode, the VIN needs to be within its  
operating range, both Shutdown and Standby inputs are  
high, and no faults are present. This mode consumes the  
most amount of power.  
Shutdown Mode that VTT and VREF are lower than VDDQ  
,
otherwise VTT can remain floating high, and be higher than  
VDDQ upon powering up. In this mode, the 34716 consumes  
the least amount of power since almost all of the internal  
blocks are disabled.  
Standby Mode  
This mode is predominantly used in Desktop memory  
solutions where the DDR supply is desired to be ACPI  
compliant (Advanced Configuration and Power Interface).  
When this mode is activated by pulling the STBY pin low, VTT  
is put in High Z state, IOUT2 = 0 A while VDDQ and VREF stay  
active. This is the S3 state Suspend-To-Ram or Self Refresh  
mode and it is the lowest DRAM power state. In this mode,  
the DRAM will preserve the data. While in this mode, the  
34716 consumes less power than in the normal mode,  
because the buck converter and most of the internal blocks  
are disabled.  
START-UP SEQUENCE  
When power is first applied, the 34716 checks the status  
of the SD and STBY pins. If the device is in a shutdown mode,  
no block will power up and the output will not attempt to ramp.  
If the device is in a standby mode, only the VDDI internal  
supply voltage and the bias currents are established and no  
further activities will occur. Once the SD and STBY pins are  
released to enable the device, the internal VDDI POR signal is  
also released. The rest of the internal blocks will be enabled,  
and the buck converters switching frequency and the VDDQ  
Soft start values are determined by reading the FREQ and  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
ILIM1 pins respectively. A soft start cycle is then initiated to  
ramp up the outputs. While channel 1 buck converter uses an  
internal reference, channel 2 converter error amplifier uses  
the voltage on the VREFOUT pin (VREF) as its reference  
voltage. VREF is equal to 1/2 VDDQ, where VDDQ is applied to  
the VREFIN pin. This way, the 34716 assures that VREF and  
VTT voltages track 1/2 VDDQ to meet DDR requirements.  
avoid erroneous undervoltage conditions, a 20 µs filter is  
implemented. The buck converter will use its feedback loop  
to attempt to correct the fault. Once the output voltage rises  
above the rising undervoltage threshold (VUVR), the fault is  
cleared and the power good output signal is pulled low, the  
device is back in normal operation. The condition is the same  
for both outputs.  
Soft start is used to prevent the output voltage from  
overshooting during startup. At initial startup, the output  
capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage  
across the inductor will be PVIN during the capacitor charge  
phase which will create a very sharp di/dt ramp. Allowing the  
inductor current to rise too high can result in a large  
difference between the charging current and the actual load  
current that can result in an undesired voltage spike once the  
capacitor is fully charged. The soft start is active each time  
the IC goes out of standby or shutdown mode, power is  
recycled, or after a fault retry.  
Output Over Current  
This block detects over current in the Power MOSFETs of  
the buck converter. It is comprised of a sense MOSFET and  
a comparator for each channel. The sense MOSFET acts as  
a current detecting device by sampling a ratio of the load  
current. That sample is compared via the comparator with an  
internal reference to determine if the output is in over current  
or not. If the peak current in the output inductor reaches the  
over current limit (ILIM), the converter will start a cycle-by-  
cycle operation to limit the current, and a 10 ms over current  
limit timer (tLIM) starts. The converter will stay in this mode of  
operation until one of the following occurs:  
To fully take advantage of soft starting, it is recommended  
not to enable the VTT output before introducing VDDQ on the  
VREFIN pin. If this happens after a soft start cycle expires  
and the VREFIN voltage has a high dv/dt, the output will  
naturally track it immediately and ramp up with a fast dv/dt  
itself and that will defeat the purpose of soft starting. For  
reliable operation, it is best to have the VDDQ voltage  
available before enabling the VTT output.  
• The current is reduced back to the normal level before  
tLIM expires, and in this case normal operation is  
regained.  
• tLIM expires without regaining normal operation, at  
which point the device turns off the output and the  
power good output signal is pulled high. At the end of a  
time-out period of 100 ms (tTIMEOUT), the device will  
attempt another soft start cycle.  
After a successful start-up cycle where the device is  
enabled, no faults have occurred, and the output voltages  
have reached their regulation point, the 34716 pulls the  
power good output signal low after a 10 ms reset delay, to  
indicate to the host that the device is in normal operation.  
• The device reaches the thermal shutdown limit (TSDFET  
and turns off the output. The power good (PG) output  
signal is pulled high.  
)
• The output current keeps increasing until it reaches the  
short circuit current limit (ISHORT). See below for more  
details.  
PROTECTION FUNCTIONS  
The 34716 monitors the application for several fault  
conditions to protect the load from overstress. The reaction of  
the IC to these faults ranges from turning off the outputs to  
just alerting the host that something is wrong. In the following  
paragraphs, each fault condition is explained:  
Short Circuit Current Limit  
This block uses the same current detection mechanism as  
the over current limit detection block. If the load current  
reaches the ISHORT value, the device reacts by shutting down  
the output immediately. This is necessary to prevent damage  
in case of a permanent short circuit. Then, at the end of a  
time-out period of 100 ms (tTIMEOUT), the device will attempt  
another soft start cycle.  
Output Overvoltage  
An overvoltage condition occurs once the output voltage  
goes higher than the rising overvoltage threshold (VOVR). In  
this case, the power good output signal is pulled high, alerting  
the host that a fault is present, but the outputs will stay active.  
To avoid erroneous overvoltage conditions, a 20 µs filter is  
implemented. The buck converter will use its feedback loop  
to attempt to correct the fault. Once the output voltage falls  
below the falling overvoltage threshold (VOVF), the fault is  
cleared and the power good output signal is pulled low, the  
device is back in normal operation. The condition is the same  
for both outputs.  
Thermal Shutdown  
Each channel has its own thermal shutdown block.  
Thermal limit detection block monitors the temperature of the  
device and protects against excessive heating. If the  
temperature reaches the thermal shutdown threshold  
(TSDFET), the converter output switches off and the power  
good output signal indicates a fault by pulling high. The  
device will stay in this state until the temperature has  
decreased by the hysteresis value and then After a time-out  
period (TTIMEOUT) of 100 ms, the device will retry  
Output Undervoltage  
An undervoltage condition occurs once the output voltage  
falls below the falling undervoltage threshold (VUVF). In this  
case, the power good output signal is pulled high, alerting the  
host that a fault is present, but the outputs will stay active. To  
automatically and the output will go through a soft start cycle.  
If successful normal operation is regained, the power good  
output signal is asserted low to indicate that.  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
16  
TYPICAL APPLICATIONS  
TYPICAL APPLICATIONS  
VDDI  
GND  
FREQ  
C14  
0.1uF  
VIN  
ILIM1  
STBY  
STBY  
VIN  
U1  
BOOT1  
BOOT1  
BOOT2  
BOOT2  
C28  
SW1  
C15  
SW2  
1
2
2
3
3
4
4
5
18  
17  
17  
16  
16  
15  
15  
14  
BOOT1  
PVIN1  
PVIN1  
SW1  
BOOT2  
PVIN2  
PVIN2  
SW2  
0.1uF  
0.1uF  
PVIN1  
PVIN2  
PVIN2  
PVIN1  
SW1  
SW2  
SW2  
MC34716  
SW1  
SW2  
GND  
GND  
GND  
VO2  
PGND1  
PGND1  
VOUT1  
PGND2  
PGND2  
VOUT2  
C27  
C11  
0.1uF  
VO1  
0.1uF  
VOUT1  
VOUT2  
INV1  
PG  
COMP2  
INV2  
COMP1  
VREFIN  
SD  
VREFOUT  
C13  
0.1uF  
C12  
0.1uF  
COMPENSATION  
NETWORK SW1  
COMPENSATION  
NETWORK SW2  
VO1  
VO2  
C20  
C23  
1nF  
0.910nF  
R1  
R4  
INV1  
INV2  
20k  
20k  
C18  
C21  
20pF  
COMP1  
R14  
COMP2  
R18  
300  
560  
15pF  
R15  
R19  
15k  
C19  
R2  
C22  
R17  
12.7k  
17.4k_nopop  
22k  
0.75nF  
1.8nF  
BUCK CONVERTER 1  
BUCK CONVERTER 2  
Vo1_1  
Vo1_2  
Vo2_1  
VO2_2  
L1  
L2  
SW1  
VO1  
SW2  
VO2  
1
2
1
2
1uH  
1.5uH  
R20  
R3  
D3  
PMEG2010EA_nopop  
C10  
100uF  
C24  
100uF  
C25  
100uF  
D2  
PMEG2010EA_nopop  
C6  
100uF  
C7  
100uF  
C8  
100uF  
4.7_nopop  
4.7_nopop  
C26  
C9  
1nF_nopop  
1nF_nopop  
Figure 7. 34716 Typical Application  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
TYPICAL APPLICATIONS  
I/O SIGNALS VIN CAPACITORS PGOOD LED VMASTER  
VIN  
J2  
VIN  
VM  
PVIN1  
C17  
C16  
3
2
1
VO1  
GND  
R7  
10uF  
0.1uF  
R8  
1k  
10k  
J3  
J4  
D1  
VMASTER  
LED  
PVIN2  
3
2
1
VO2  
GND  
R9  
10k  
LED  
VM  
3
2
1
VIN  
GND  
JUMPERS  
ILIM1,FREQ  
J1  
VO1  
VMASTER  
VREFIN  
1
3
5
7
9
2
4
6
8
10  
R16  
10k  
STBY  
LED  
PG  
R12  
10k_nopop  
STBY  
1
1
2
SD  
ILIM1  
FREQ  
CON10A  
R22  
10k_nopop  
R11  
10k  
2
SD  
PVIN1 CAPACITORS  
PVIN2 CAPACITORS  
PVIN1  
PVIN2  
C1  
0.1uF  
C2  
1uF  
C3  
100uF  
C4  
100uF  
C5  
100uF  
C30  
0.1uF  
C31  
1uF  
C32  
100uF  
C33  
100uF  
C29  
100uF  
TRIMPOTS nopop  
VDDI  
ILIM1  
FREQ  
R21  
POT_50K_nopop  
R6  
POT_50K_nopop  
Figure 8. 34716 Typical Application  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
18  
TYPICAL APPLICATIONS  
CONFIGURING THE OUTPUT VOLTAGE:  
680  
733  
787  
840  
893  
947  
1000  
0.936 - 1.092  
Channel 1 of the 34716 is a general purpose DC-DC  
converter, the resistor divider to the -INV1 node is  
responsible for setting the output voltage, according to the  
following equation:  
0.781 - 0.936  
0.625 - 0.780  
0.469 - 0.624  
0.313 - 0.468  
0.157 - 0.312  
0.000 - 0.156  
R1  
VOUT = VREF  
+1  
R2  
Where VREF is the internal VBG=0.7V.  
Table 5. Frequency Selection Table  
SOFT START ADJUSTMENT  
Channel 2 is a DDR specific voltage power supply, and the  
output voltage is given by the equation:  
Table 6 shows the voltage that should be applied to the  
ILIM1 terminal to get the desired desired sort start timing on  
channel 1 only.  
VREFIN  
VTT =  
2
SOFT START [MS]  
VOLTAGE APPLIED TO ILIM  
1.19 - 1.49V  
Where VREFIN is equal to VDDQ  
.
3.2  
1.6  
0.8  
0.4  
1.50 - 1.81V  
SWITCHING FREQUENCY CONFIGURATION  
The switching frequency will have a value of 1.0 MHz by  
connecting the FREQ terminal to the GND. If the smallest  
frequency value of 200 KHz is desired, then connect the  
FREQ terminal to VDDI. To program the switching frequency  
to another value, an external resistor divider will be  
connected to the FREQ terminal to achieve the voltages  
given by Table 5.  
1.82 - 2.13V  
2.14 - 2.50V  
Table 6. Soft Start Configurations  
FREQUENCY  
200  
VOLTAGE APPLIED TO PIN FREQ  
2.341 – 2.500  
253  
2.185 - 2.340  
307  
2.029 - 2.184  
360  
1.873 - 2.028  
413  
1.717 – 1.872  
466  
1.561 – 1.716  
Figure 9. Resistor divider for Frequency and Soft Start  
adjustment  
520  
1.405 - 1.560  
573  
1.249 - 1.404  
627  
1.093 - 1.248  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
TYPICAL APPLICATIONS  
SELECTING INDUCTOR  
T * IOUT  
Inductor calculation process is the same for both  
Channels. The equation is the following:  
dt _ I _ rise =  
IOUT _ step  
The following formula will be helpful to find the maximum  
allowed ESR.  
(Vout + Iout *(Rds(on) _ ls + r _ w))  
L = D'MAX T ∗  
Iout  
Vout  
Maximum Off Time Percentage  
D'MAX =1−  
VOUT * Fsw* L  
VOUT (1D min)  
ESRmax  
=
Vin _ max  
Switching Period  
T
Drain – to – Source  
Rds(on) _ ls  
The effects of the ESR is often neglected by the design-  
ers and may present a hidden danger to the ultimate supply  
stability. Poor quality capacitors have widely disparate ESR  
value, which can make the closed loop response inconsis-  
tent.  
Resistance of FET  
r _ w  
Winding Resistance of Inductor  
IOUT = 0.4*IOUT  
Output Current Ripple  
BOOTSTRAP CAPACITOR  
If channel 1 will be serving as power supply for channel 2,  
it is necessary to locate the LC poles at different frequencies  
in order to ensure that the input impedance of the second  
converter is always higher than the output impedance of the  
first converter, and thus, ensure system stability. This can be  
achieved by selecting different values for L1 and L2 slightly  
higher than the calculated value.  
The bootstrap capacitor is needed to supply the gate  
voltage for the high side MOSFET. This N-Channel MOSFET  
needs a voltage difference between its gate and source to be  
able to turn on. The high side MOSFET source is the SW  
node, so it is not at ground and it is floating and shifting in  
voltage. We cannot just apply a voltage directly to the gate of  
the high side that is referenced to ground. We need a voltage  
referenced to the SW node. This is why the bootstrap  
capacitor is needed. This capacitor charges during the high-  
side off time. Since the low side will be on during that time,  
the SW node and the bottom of the bootstrap capacitor will be  
connected to ground, and the top of the capacitor will be  
connected to a voltage source. The capacitor will charge up  
to that voltage source (for example 5V). Now when the low  
side MOSFET switches off and the high side MOSFET  
switches on, the SW nodes rise to VIN, and the voltage on the  
boot pin will be VCAP + VIN. The gate of the high side will have  
VCAP across it and it will be able to stay enhanced. A 0.1µF  
capacitor is a good value for this bootstrap element.  
SELECTING THE OUTPUT FILTER CAPACITOR  
For the output capacitor, the following considerations are  
most important and not the actual Farad value: the physical  
size, the ESR of the capacitor, and the voltage rating.  
Calculate the minimum output capacitor using the  
following formula:  
IOUT *dt _ I _ rise  
Co =  
TR _V _ dip  
Transient Response percentage:  
TR_%  
TYPE III COMPENSATION NETWORK  
Power supplies are desired to offer accurate and tight  
regulation output voltages. A high DC gain is required to  
accomplish this, but with high gain comes the possibility of  
instability. The purpose of adding compensation to the  
internal error amplifier is to counteract some of the gains and  
phases contained in the control-to-output transfer function  
that could jeopardized the stability of the power supply. The  
Type III compensation network used for 34716 is comprised  
of two poles (one integrator and one high frequency, to  
cancel the zero generated from the ESR of the output  
capacitor) and two zeros to cancel the two poles generated  
from the LC filter as shown in Figure 10.  
Maximum Transient Voltage:  
TR_V_dip = VOUT*TR_%  
Maximum Current Step:  
(Vin _ minVout)* D _ max  
Iout _ step =  
Fsw* L  
Inductor Current Rise Time:  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
20  
TYPICAL APPLICATIONS  
This gives the result  
1
RF =  
1
CS =  
2π *CF FZ1  
2π * R1FZ 2  
4. Calculate RS by placing the first pole at the ESR zero  
frequency  
1
FESR  
=
= FP1  
Figure 10. Type III compensation network  
2π *CoX *ESR  
1
1
1. Choose a value for R1 (R2only applies to Channel 1)  
RS =  
FP1 =  
2π * FP1CS  
2π *RSCS  
2. Consider a Crossover frequency of one tenth of the  
switching frequency, set the Zero pole frequency to  
Fcross/10  
5. Equating pole 2 at the Crossover Frequency to achieve  
a faster response and a proper phase margin  
1
1
FP0  
=
FCROSS  
=
10  
2π * R1CF  
1
1
FCROSS = FP2  
=
CF =  
CF Cx  
2π *R1FPO  
2π * RF  
CF + Cx  
CF  
3. Knowing the LC frequency, the Frequency of Zero 1  
and Zero 2 in the compensation network is equal to  
FLC  
CX =  
2π * RF CF FP2 1  
TRACKING CONFIGURATIONS  
The 34716 allows default Ratiometric tracking on channel  
2 by connecting VDDQ to the VREFIN terminal. It has an  
internal resistor divider that allows an output of VDDQ/2.  
1
FLC =  
= FZ1 = FZ 2  
FZ 2 =  
2π LX COX  
1
1
FZ1 =  
2π * R1CS  
2π * RF CF  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
21  
PACKAGING  
PACKAGING DIMENSIONS  
PACKAGING  
PACKAGING DIMENSIONS  
EP SUFFIX  
26-PIN  
98ASA10728D  
ISSUE 0  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
22  
PACKAGING  
PACKAGING DIMENSIONS  
EP SUFFIX  
26-PIN  
98ASA10728D  
ISSUE 0  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
23  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
Pre-release version  
2/2006  
1.0  
Implemented Revision History page  
Initial release  
2/2007  
5/2007  
2.0  
3.0  
Converted format from Market Assessment to Product Preview  
Major updates to the data, form, and style  
Changed Feature fom 2% to 1%, relabeled to include soft start  
Change references for 45 mIntegrated N-Channel Power MOSFETs to 50 mΩ  
Removed Machine Model in Maximum Ratings  
Changed Input DC Supply Current (12) , Input DC Supply Current (12), and Input DC Supply Current  
(12)  
Added CH 1 High-side MOSFET Drain Voltage Range  
(14) (15)  
Changed Output Voltage Accuracy (13)  
,
,
Changed Soft Start Adjusting Reference Voltage Range and Short Circuit Current Limit  
Changed High-Side N-CH Power MOSFET (M4) RDS(ON) (13) and Low-Side N-CH Power  
MOSFET (M5) RDS(ON) (16)  
Changed M2 RDS(ON) and PVIN1 Pin Leakage Current  
Added CH 2 High-side MOSFET Drain Voltage Range  
(17) (18)  
Changed Output Voltage Accuracy (16)  
,
,
Changed Short Circuit Current Limit (Sinking and Sourcing)  
Changed High-Side N-CH Power MOSFET (M6) RDS(ON) (16) and Low-Side N-CH Power  
MOSFET (M7) RDS(ON) (16)  
Changed M3 RDS(ON) and PVIN2 Pin Leakage Current  
Changed VREFOUT Buffered Reference Voltage Accuracy (21), VREFOUT Buffered Reference  
Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over Current Limit  
Changed STBY Pin Internal Pull Up Resistor and SD Pin Internal Pull Up Resistor  
Changed Soft Start Duration (Normal Mode)  
Changed Over Current Limit Retry Time-out Period and Output Undervoltage/Overvoltage Filter  
Delay Timer  
Changed Oscillator Default Switching Frequency, PG Reset Delay, and Thermal Shutdown Retry  
Time-out Period (22)  
Changed definition for Channel 1 Soft Start ADJUStment input (ILIM1)  
Changed drawings in 34716 Typical Application  
Changed table for Soft Start Adjustment  
Removed PC34716EP/R2 from the ordering information and added MC34716EP/R2  
Changed data sheet status to Advance Information  
34716  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
24  
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MC34716  
Rev. 3.0  
5/2007