CS is pulled low. The device will enter shutdown mode if CS
is pulled high before the tenth falling edge of SCLK after CS
is pulled low, or will stay in normal mode if CS remains low.
Once in shutdown mode, the device will stay there until CS is
brought low again. By varying the ratio of time spent in the
normal and shutdown modes, a system may trade-off
throughput for power consumption.
Applications Information (Continued)
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC081S051’s input
channels is shown in Figure 7. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should any
input go beyond (VA + 300 mV) or (GND − 300 mV), as these
ESD diodes will begin conducting, which could result in
erratic operation.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC081S051 in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode con-
tinuously, CS must be kept low until after the 10th falling
edge of SCLK after the start of a conversion (remember that
a conversion is initiated by bringing CS low).
The capacitor C1 in Figure 7 has a typical value of 4 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC081S051 sam-
pling capacitor and is typically 26 pF. The ADC081S051 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when
using the ADC081S051 to sample AC signals. Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic
performance.
If CS is brought high after the 10th falling edge, but before
the 16th falling edge, the device will remain in normal mode,
but the current conversion will be aborted, and SDATA will
return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after tQUIET has
elapsed, by bringing CS low again.
7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade through-
put for power consumption. When the ADC081S051 is in
shutdown mode, all of the analog circuitry is turned off.
20145514
FIGURE 7. Equivalent Input Circuit
To enter shutdown mode, a conversion must be interrupted
by bringing CS back high anytime between the second and
tenth falling edges of SCLK, as shown in Figure 8. Once CS
has been brought high in this manner, the device will enter
shutdown mode; the current conversion will be aborted and
SDATA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC081S051 digital inputs (SCLK and CS) are not
limited by the same absolute maximum ratings as the analog
inputs. The digital input pins are instead limited to +6.5V with
respect to GND, regardless of VA, the supply voltage. This
allows the ADC081S051 to be interfaced with a wide range
of logic levels, independent of the supply voltage.
7.0 MODES OF OPERATION
The ADC081S051 has two possible modes of operation:
normal mode, and shutdown mode. The ADC081S051 en-
ters normal mode (and a conversion process is begun) when
20145516
FIGURE 8. Entering Shutdown Mode
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