33390--Datasheet/数据表在线中文翻译

Document Number: MC33390

Rev 7.0, 11/2006

Freescale Semiconductor

Technical Data

Class B Serial Transceiver

33390

The 33390 is a serial transceiver designed to provide bi-directional

half-duplex communication meeting the automotive SAE Standard J-

1850 Class B Data Communication Network Interface specification. It

is designed to interface directly to on-board vehicle microcontrollers

and serves to transmit and receive data on a single-wire bus at data

rates of 10.4 kbps using Variable Pulse Width Modulation (VPWM).

The 33390 operates directly from a vehicle's 12 V battery system and

functions in a logic fashion as an I/O interface between the

microcontroller's 5.0 V CMOS logic level swings and the required 0 V

to 7.0 V waveshaped signal swings of the bus. The bus output driver

is short circuit current limited.

J-1850 SERIAL TRANSCEIVER

Features

D SUFFIX

EF SUFFIX (PB-FREE)

98ASB42564B

• Designed for SAE J-1850 Class B Data Rates

• Full Operational Bus Dynamics Over a Supply Voltage of 9.0 to

16 V

8-LEAD SOICN

• Ambient Operating Temperature of -40°C to 125°C

• Interfaces Directly to Standard 5.0 V CMOS Microcontroller

• BUS Pin Protected Against Shorts to Battery and Ground

• Thermal Shutdown with Hysteresis

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

• Voltage Waveshaping of Bus Output Driver

• 40 V Max V_BATCapability

• Pb-Free Packaging Designated by Suffix Code EF

MC33390D/DR2

MCZ33390EF/R2

-40°C to 125°C

8 SOICN

V

Primary

Node

PWR

33390

+VBAT

BUS

LOAD

SLEEP

TX

MCU

RX

4X/Loop

GND

Secondary

Nodes

Figure 1. 33390 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

INTERNAL BLOCK DIAGRAM

33390

Bus

Driver

BUS

VBAT

Voltage

Regulator

SLEEP

Thermal

Shutdown

4.5 V

Reference

Waveshaping

Filter

TX

RX

Digital Output

Driver

Loss of Ground

Protection

LOAD

GND

4X Enable

Loopback

4X/LOOP

Note This device contains approximately 400 active transistors and 250 gates.

Figure 2. 33390 Simplified Internal Block Diagram

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

1

8

1

SLEEP

GND

RX

2

7

TX

3

6

LOAD

BUS

3

4X/LOOP

VBAT

4

5

Figure 3. 33390 Pin Connections

Table 1. 33390 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.

Pin Number

Pin Name

Definition

Enables the transceiver when Logic 1 and disables the transceiver when Logic 0.

Device ground pin.

1

2

3

4

5

6

SLEEP

GND

Accommodates an external pull-down resistor to ground to provide loss of ground protection.

Waveshaped SAE Standard J-1850 Class B transmitter output and receiver input.

Provides device operating input power.

LOAD

BUS

VBAT

Tristate input mode control; Logic 0 = normal waveshaping, Logic 1 = waveshaping disabled for 4X

transmitting, high impedance = loopback mode.

4X/LOOP

Serial data input (DI) from the microcontroller to be transmitted onto Bus.

Bus received serial data output (DO) sent to the microcontroller.

7

8

TX

RX

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

VBAT DC Supply Voltage ⁽¹⁾

Input I/O Pins ⁽²⁾

V

-0.3 to 40

-0.3 to 7.0

-2.0 to 16

V

BAT

V

I/O(CPU)

BUS and LOAD Outputs

V

BUS

ESD Voltage ⁽³⁾

Human Body Model

Machine Model

V

±2000

±200

ESD1

ESD2

Storage Temperature

T

-65 to 150

-40 to 125

-40 to 150

Note 5.

°C

STG

Operating Ambient Temperature

Operating Junction Temperature

T

A

T

°C

J

Peak Package Reflow Temperature During Reflow ⁽⁴⁾

Thermal Resistance (Junction-to-Ambient)

Notes

,

T_PPRT

(5)

°C

R

180

°C/W

θJ-A

1. An external series diode must be used to provide reverse battery protection of the device.

2. SLEEP, TX, RX, and 4X/LOOP are normally connected to a microcontroller.

3. ESD1 testing is performed in accordance with the Human Body Model (C

=100 pF, R

=1500 Ω), ESD2 testing is performed in

ZAP

accordance with the Machine Model (C

=200 pF, R

=0 Ω).

ZAP

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 7.0 V ≤ V_BAT≤ 16 V, -40°C ≤ T_A≤ 125°C, SLEEP = 5.0 V unless otherwise noted.

Typical values reflect the parameter's approximate midpoint average value with V_BAT= 13 V, T_A= 25°C. All positive currents are

into the pin. All negative currents are out of the pin.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER CONSUMPTION

Operational Battery Current (RMS with Tx = 7.812 kHz Square Wave)

BUS Load = 1380 Ω to GND, 3.6 nF to GND

mA

–

3.0

11.5

32

I_BAT(OP1)

I_BAT(OP2)

BUS Load = 257 Ω to GND, 20.2 nF to GND

22.4

Battery Bus Low Input Current

mA

µA

After SLEEP Toggle Low to High; Prior to Tx Toggling

After Tx Toggle High to Low

I

–

1.1

6.4

3.0

8.5

BAT(BUS L1)

BAT(BUS L2)

Sleep State Battery Current

V_SLEEP= 0 V

I

BAT(SLEEP)

–

38.2

65

BUS

BUS Input Receiver Threshold ⁽⁶⁾

V

Threshold High (Bus Increasing until Rx ≥ 3.0 V)

Threshold Low (Bus Decreasing until Rx ≤ 3.0 V)

Threshold in Sleep State (SLEEP = 0 V)

V

4.25

–

3.9

3.7

3.0

0.2

–

BUS(IH)

V

3.5

3.4

0.6

BUS(IL)

BUS

2.4

0.1

TH(SLEEP)

Hysteresis (V

- V

, SLEEP = 0 V)

BUS(IH)

BUS(IL)

V

BUS(HYST)

BUS-Out Voltage (257 Ω ≤ R_BUS(L)to GND ≤ 1380 Ω)

8.2 V ≤ V

≤ 16 V, Tx = 5.0 V

≤ 8.2 V, Tx = 5.0 V

6.25

6.9

–

8.0

V_BUS(OUT1)

V_BUS(OUT2)

V_BUS(OUT3)

BAT

4.25 V ≤ V

V

- 1.6

V

BAT

0.7

–

0.27

Tx = 0 V

BUS Short Circuit Output Current

I_BUS(SHORT)

mA

µA

Tx = 5.0 V, -2.0 V ≤ V_BUS≤ 4.8 V

60

129

170

BUS Leakage Current

-2.0 V ≤ V

0 V ≤ V

≤ 0 V

-500

–

-55

–

I

BUS

BUS(LEAK1)

≤ V

189

500

I

BUS

BAT

BUS(LEAK2)

BUS Thermal Shutdown ⁽⁷⁾(Tx = 5.0 V, I

= -0.1 mA)

T_BUS(LIM)

°C

BUS

Increase Temperature until V

≤ 2.5 V

150

10

170

12

190

15

BUS

BUS Thermal Shutdown Hysteresis ⁽⁸⁾

T_BUS(LIM)- T_BUS(REEN)

T_BUS(LIMHYS)

BUS and LOAD Current with Loss of V

Figure 4)

or GND (I = 0 µA) (see

BAT

mA

BAT

I_{BUS (LOSS)}

–

0.00

0.1

-18 V ≤ V

≤ 9.0 V

BUS

I_{LOAD (LOSS)}

≤ 9.0 V

LOAD

Notes

6. Typical threshold value is the approximate actual occurring switch point value with V

= 13 V, T = 25°C.

A

BAT

7. Device characterized but not production tested for thermal shutdown.

8. Device characterized but not production tested for thermal shutdown hysteresis.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions of 7.0 V ≤ V_BAT≤ 16 V, -40°C ≤ T_A≤ 125°C, SLEEP = 5.0 V unless otherwise noted.

Typical values reflect the parameter's approximate midpoint average value with V_BAT= 13 V, T_A= 25°C. All positive currents are

into the pin. All negative currents are out of the pin.

Characteristic

Symbol

Min

Typ

Max

Unit

BUS (CONTINUED)

LOAD Output

L

V

ON

I = 6.0 mA

L

–

0.07

0.56

0.2

0.9

Unpowered LOAD Output

L

DIO

V

= 0 V, I = 6.0 mA

L

0.3

BAT

TX

Tx Input Voltage

V

Tx Input Logic Low Level

V

–

0.8

–

Tx(IL)

Tx Input Logic High Level

V

3.5

Tx(IH)

Tx Input Current

µA

V

= 5.0 V

50

106

200

2.0

I

Tx

Tx(IH)

V

= 0 V

-2.0

0.23

I

Tx(IL)

LOOP

4X/LOOP Input Current

µA

V

= 0 V (Normal Mode)

-200

-60

200

I

4X/LOOP

4X/LOOP(IL)

V

= 5.0 V (4X Mode)

110

4X/LOOP(IH)

4X/LOOP Input Threshold (Tx = 4096 Hz Square Wave)

Normal Mode to Loopback Mode

1.1

3.2

1.31

3.43

1.5

3.6

V

4X/LOOP(IL)

Loopback Mode to 4X Mode

V

4X/LOOP(IH)

RX

Rx Output Voltage Low

= 0 V, I = 1.6 mA

V

Rx(LOW)

V

0.01

4.25

2.0

0.18

4.58

3.67

0.4

4.75

8.0

BUS

R

x

Rx Output Voltage High

= 7.0 V, I = -200 µA

V

Rx(HIGH)

V

BUS

Rx

Rx Output Current

V_R= High; Short Circuit Protection Limits

I

mA

Rx

x

SLEEP

SLEEP Input Current

µA

V

= 0 V

I_SLEEP(IL)

I_SLEEP(IH)

–

-0.23

6.21

-2.0

20

SLEEP

= 5.0 V

1.0

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions of 7.0 V ≤ V_BAT≤ 16 V, -40°C ≤ T_A≤ 125°C, SLEEP = 5.0 V unless otherwise noted.

Typical values reflect the parameter's approximate midpoint average value with V_BAT= 13 V, T_A= 25°C. All positive currents are

into the pin. All negative currents are out of the pin.

Characteristic

Symbol

Min

Typ

Max

Unit

BUS

BUS Voltage Rise Time ⁽⁹⁾(9.0 V ≤ V

(see Figure 5)

≤ 16 V, Tx = 7.812 kHz Square Wave)

t

µs

BAT

RISE(BUS)

BUS Load = 3,300 pF and 1.38 kΩ to GND

BUS Load = 16,500 pF and 300 Ω to GND

9.0

11.15

11.86

15

BUS Voltage Fall Time ⁽⁹⁾(9.0 V ≤ V

(see Figure 5)

≤ 16 V, Tx = 7.812 kHz Square Wave)

t

µs

BAT

FALL(BUS)

BUS Load = 3,300 pF and 1.38 kΩ to GND

BUS Load = 16,500 pF and 300 Ω to GND

9.0

10.50

11.17

15

Pulse Width Distortion Time (9.0 V ≤ V

Wave) (see Figure 6)

≤ 16 V, Tx = 7.812 kHz Square

t

µs

BAT

PWD(BUS)

BUS Load = 3,300 pF and 1.38 kΩ to GND

35

–

62

93

25

Propagation Delay

t

PD(BUS)

Tx Threshold to Rx Threshold

17.7

TX

Tx to BUS Delay Time (Tx = 2.5 V to V

4X Mode

= 3.875 V) (see Figure 7)

t

µs

BUS

TXDELAY

–

2.6

4.0

24

Normal Mode

13

17.3

SLEEP to Tx Setup Time (see Figure 7)

RX

t

80

40

–

µs

SLEEPTXSU

Rx Output Delay Time (Tx = 2.5 V to V

Low-to-Output High

= 3.875 V) (see Figure 8)

BUS

T

–

0.11

0.38

2.0

RXDELAY/L–H

High-to-Output Low

RXDELAY/H–L

Rx Output Transition Time (C = 50 pF to GND, 10% and 90% Points)

Rx

(see Figure 9)

µs

Low-to-Output High

High-to-Output Low

t

–

0.34

0.08

1.0

RXTRANS/L–H

t

RXTRANS/H–L

Rx Output Transition Time ⁽¹⁰⁾(C = 50 pF to GND, SLEEP = 0 V, 10% and

Rx

90% Points) (see Figure 9)

Low-to-Output High

t

–

0.32

0.08

5.0

RXTRANS/L–H

High-to-Output Low

t

RXTRANS/H–L

Notes

9. Typical is the parameter's approximate average value with V

10. Rx Output Transition Time from a sleep state.

= 13 V, T = 25°C.

A

BAT

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Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

TEST FIGURES

33390

SLEEP

Tx

2.5 V

I_BUS(LOSS)

-18 V to 9.0 V

VBAT

GND

BUS

t

SLEEPTxSU

2.5 V

-18 V to 9.0 V

I_LOAD(LOSS)

LOAD

t

3.875 V

TxDelay

BUS

Figure 4. Loss of Ground or V_BATTest Circuit

Figure 7. SLEEP to Tx Delay Times

3.5 V

122 µs

3.875 V

BUS

Tx

64 µs

0.8 V

t

RxDelay/low-

to-output high

t

RxDelay/high-to-

80%

output low

BUS

Rx

2.5 V

20%

t

FALL

RISE

Figure 8. BUS-to-Rx Delay Time

Figure 5. BUS Rise and Fall Times

5.0 V

Tx

64 µs

t

/

RXTRANS L–

0 V

t

/

RXTRANS H–L

90%

t

PWD(MIN)

Rx

t

PWD

1.5 V

t

10%

PWD(MAX

)

10%

Figure 9. Rx Rise and Fall Time

Figure 6. Pulse Width Distortion

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

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FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33390 is a serial transceiver device designed to meet

the SAE Standard J-1850 Class B performance for bi-

directional half-duplex communication. The device is

packaged in an economical surface-mount SOIC plastic

package. An internal block diagram of the device is shown in

Figure 2.

incorporating CMOS logic, bipolar/MOS analog circuitry, and

DMOS power FETs. Though the 33390 was principally

designed for automotive applications requiring SAE J-1850

Class B standards, it is suited for other serial communication

applications. It is parametrically specified over an ambient

temperature range of -40°C ≤ T_A≤ 125°C and 7.0 V ≤ V_BAT

≤

16 V supply. The economical 8-pin SOICN surface mount

plastic package makes the device a cost-effective solution.

The 33390 derives its robustness to temperature and

voltage extremes from being built on a SMARTMOS process,

FUNCTIONAL PIN DESCRIPTION

down resistor. No matter how many secondary nodes are on

the Class B bus, the RC time constant of the Class B bus is

maintained at approximately 5.0 µs. The minimum and

maximum capacitance and resistance on the Class B bus is

given by the expressions shown in Table 5, page 10.

Input Power (VBAT)

This is the only required input power source necessary to

operate the 33390. The internal voltage reference of the

33390 will remain fully operational with a minimum of 9.0 V

on this pin. Bus transmissions can continue with battery

voltages down to 5.0 V. The bus output voltage will follow the

battery voltage down and, in doing so, track approximately

1.6 V below the battery voltage. The device will continue to

receive and transmit bus data to the microcontroller with

battery voltages as low as 4.25 V. The pin can withstand

voltages from -0.3 V to 40 V. If reverse battery protection is

required, an appropriate diode must be placed in series with

this pin to protect the IC.

One Primary Node

470 pF

1.5 kΩ

3300 pF

10.6 kΩ

Figure 10. Minimum Bus Load

Sleep Input (SLEEP)

This input is used to enable and disable the Class B

transmitter. The Class B receiver is always enabled so long

as adequate V_BATpin voltage is applied. When the SLEEP pin

voltage is 5.0 V, the Class B transmitter is enabled. If this

input is 0 V, the Class B transmitter will be disabled and less

than 65 µA of current will be drawn by the V_BATpin. The pin

also provides a 5.0 V reference, internal to the device, used

to establish the Rx output level and slew rate times.

Primary Node

3300 pF

470 pF

1.5 kΩ

10.6 kΩ

24 Secondary Nodes

Class B Functional Description

The transmitter provides an analog waveshaped 0 V to

7.0 V waveform on the BUS output. It also receives

11280 pF

442 Ω

waveforms and transmits a digital level signal back to a logic

IC. The transmitter can drive up to 32 secondary Class B

transceivers (see Figures 10 and 11). These secondary

nodes may be at ground potentials that are ±2.0 V relative to

the control assembly. Waveshaping will only be maintained

during 2 of the 4 corners when the 0 to ±2.0 V ground

potential difference condition exists. The 33390 is a

Figure 11. Maximum Number of Nodes

31 Secondary Nodes

secondary node on the Class B bus. Each secondary

transceiver has a 470 ±10% pF capacitor on its output for

EMI suppression purposes, as well as a 10.6 kΩ ±5% pull-

down resistor to ground. The primary node has a 3300 ±10%

pF capacitor on its output for EMI suppression, as well as a

1.5 kΩ ±5% pull-down resistor to ground. With more than 26

nodes, there is no primary node (see Figure 12). All nodes

will have a 470 ±10% pF capacitor and a 10.6 kΩ ±5% pull-

470 pF

342 Ω

14570 pF

10.6 kΩ

Figure 12. Maximum Bus Load

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Analog Integrated Circuit Device Data

Freescale Semiconductor

9

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Table 5. Class B Bus Capacitance and Resistance Expressions

Level

Minimum

Maximum

Capacitance

Resistance to Ground

(3.3 x 0.9) + (0.47 x 0.9) = 3.39 nF

(3.3 x 1.1) + 25(0.47 x 1.1) = 16.55 nF

(1.5 x 0.95) || (10.6 x 0.95) / 25 = 314 Ω

(1.5 x 1.05) || (10.6 x 1.05) = 1.38 kΩ

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10

TYPICAL APPLICATIONS

Receiver Output to the Microcontroller (Rx)

Class B Module Inputs

This is a 5.0 V CMOS compatible push-pull output used to

send received data to the microcontroller. It does not require

an external pull-up resistor to be used. The receiver is always

enabled and draws less than 65 µA of current from V_BAT. The

receive threshold is dependent on the state of the SLEEP pin.

The receiver circuitry is able to operate with V_BATvoltages as

low as 4.25 V and still remains capable of “waking up” the

33390 when remote Class B activity is detected.

Transmitter Data from the MCU (Tx)

The Tx input is a push-pull (N-channel/P-channel FETs)

buffer with hysteresis for noise immunity purposes. This pin

is a 5.0 V CMOS logic level input from the MCU following a

true logic protocol. A logic [0] input drives the BUS output to

0 V (via the external pull-down resistor to ground on each

node), while a logic [1] input produces a high voltage at the

BUS output. A logic [0] input level is guaranteed when the Tx

input pin is open-circuited by virtue of an internal 40 kΩ pull-

down resistor. No external resistor is required for its

operation.

When the SLEEP pin is 0 V and message activity occurs

on the bus, the receiver passes the bus message through to

the microcontroller. The 33390 does not automatically “wake

up” from a sleep state when bus activity occurs: the

microcontroller must tell it to do so.

Waveshaping and 4X/Loop

In the Static Electrical Characteristics table, the maximum

voltage for Rx is specified as 4.75 V over an operating range

of -40°C to 125°C temperature and 7.0 V to 16 V V_BAT. This

maximum Rx voltage is compatible with the minimum V_DD

voltage of microcontrollers to prevent the 33390 from

sourcing current to the microcontroller's output.

This input is a tristateable input: 0 V = normal

waveshaping, 5.0 V = waveshaping is disabled for 4X

transmitting, and high impedance = loopback mode of

operation. This is a logic level input used to select whether

waveshaping for the Class B output is enabled or disabled. A

logic [0] enables waveshaping, while a logic [1] disables

waveshaping. In the 4X mode, the BUS output rise time is

less than 2.0 µs and the fall time is less than 5.0 µs (owing to

the external RC pull-down to ground). In the loopback

condition, the Tx signal is fed back to the Rx output after

waveshaping without being transmitted onto the BUS. This

mode of operation is useful for system diagnostic purposes.

Switched Ground Output (LOAD)

Normally this output is a saturated switch to ground, which

pulls down the external resistor between the BUS and LOAD

outputs. In the event ground is lost to the assembly, the

LOAD output will bias itself “off” and will not leak more than

100 µA of current out of this pin.

Class B Module Outputs

Transceiver Output (BUS)

Overtemperature Shutdown

If the BUS output becomes shorted to ground for any

duration, an overtemperature shutdown circuit “latches off”

the output source transistor whenever the die temperature

exceeds 150°C to 190°C. The output transistor remains

latched off until the Tx input is toggled from a logic [0] to a

logic [1]. The rising edge provides the clearing function,

provided the locally sensed temperature is 10°C to 15°C

below the latch-off temperature trip temperature.

This is the output driver stage that sources current to the

bus. Its output follows the waveshaped waveform input. Its

output voltage is limited to 6.25 V to 8.0 V under normal

battery level conditions. The limited level is controlled by an

internal regulator/clamp circuit. Once the battery voltage

drops below 9.0 V, the regulator/clamp circuit saturates,

causing the bus voltage to track the battery voltage. A 1.5 kΩ

±5% external resistor (as well as any 10.6 kΩ pull-down

resistors of any secondary nodes) sinks the current to

discharge the capacitors during high-to-low transitions. This

sourcing output is short circuit-protected (60 mA to 170 mA)

against a short to -2.0 V and sinks less than 1.0 mA when

shorted to VBAT. If a short occurs, the overtemperature

shutdown circuit protects the source driver of the device. In

the event battery power is lost to the assembly, the bus

transmitter's output stage will be disabled and the leakage

current from the BUS output will not source or sink more than

100 µA of current. The transceiver will operate with a remote

ground offset of ±2.0 V, but the lower corners of transmission

will not be rounded during this condition.

Waveshaping

Waveshaping is incorporated into the 33390 to minimize

radiated EMI emissions.

Receiver Protocol

The Class B communication scheme uses a variable pulse

width (VPW) protocol. The microcontroller provides the VPW

decoding function. Once the receiver detects a transition on

Rx, it starts an internal counter. The initial “start of frame” bit

is a logic [1] and lasts 200 µs. For subsequent bits, if there is

a bus transition before 96 µs, one logic state is inferred. If

there is a bus transition after 96 µs, the other logic state is

inferred. The “end of data” bit is a logic [0] and lasts 200 µs.

If there is no activity on the bus for 280 µs to 320 µs following

a broadcast message, multiple unit nodes may arbitrate for

control of the next message. During an arbitration, after the

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

TYPICAL APPLICATIONS

“start of frame” bit has been transmitted, the secondary node

transmitting the most consecutive logic [0] bits will be granted

sole transmission access to the bus for that message.

to flow in the LOAD pin. During such a loss of assembly

ground condition, the BUS and LOAD pins exhibit a high

impedance to VBAT; all other pins will exhibit a low

impedance to V_BAT. During this condition the BUS pin is

prevented from sourcing any current or loading the bus,

which would cause a corruption of any data being transmitted

on the bus. While a particular assembly is experiencing a loss

of ground, all other assembly nodes are permitted to function

normally. It should be noted that with other nodes existing on

the bus, the bus will always have some minimum/maximum

impedance to ground as shown in Table 5, page 10.

Loss of Assembly Ground Connection

The definition of a loss of assembly ground condition at the

device level is that all pins of the 33390, with the exception of

BUS and LOAD, see a very low impedance to VBAT.

The LOAD pin of the device has an internal transistor

switch connected to it that is normally saturated to ground.

This pulls the LOAD-side of the external resistor (tied from

BUS to LOAD) to ground under normal conditions. The LOAD

pin switch is essentially that of an “upside down” FET, which

is normally biased “on” so long as module ground is present

and biased “off” when loss-of-ground occurs. When a loss of

assembly ground occurs, the load transistor switch is self-

biased “off”, allowing no more than 100 µA of leakage current

Loss of Assembly Battery Connection

The definition of a loss of assembly battery condition at the

device level is that the VBAT pin of the 33390 sees an infinite

impedance to VBAT, but there is some undefined impedance

between these pins and ground.

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

TYPICAL APPLICATIONS

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below.

EF SUFFIX (PB-FREE)

8-LEAD SOIC NARROW BODY

PLASTIC PACKAGE

98ASB42564B

ISSUE U

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Converted to Freescale format

Implemented revision history page.

Added Part Numbers MC33390EF/EFR2 to Ordering Information on Page 1.

4/2006

5.0

•

Updates document form and style

Removed MC33390EF and replaced with MCZ33390EF in the number Ordering Information

10/2006

6.0

7.0

•

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Maximum Ratings on page 4. Added note with instructions to obtain this information from

www.freescale.com.

11/2006

33390

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

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MC33390

Rev 7.0

11/2006