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Document Number: MC33395  
Rev 4.0, 2/2007  
Freescale Semiconductor  
Technical Data  
Three-Phase Gate Driver IC  
33395  
33395T  
The 33395 simplifies the design of high-power BLDC motor control  
design by combining the gate drive, charge pump, current sense, and  
protection circuitry necessary to drive a three-phase bridge  
configuration of six N-channel power MOSFETs. Mode logic is  
incorporated to route a pulse width modulation (PWM) or a  
complementary PWM output signal to either low-side or high-side  
MOSFETs of the bridge.  
THREE-PHASE  
GATE DRIVER IC  
Detection and drive circuitry are also incorporated to control a  
reverse battery protection high-side MOSFET switch. PWM  
frequencies up to 28 kHz are possible. Built-in protection circuitry  
prevents damage to the MOSFET bridge as well as the drive IC and  
includes overvoltage shutdown, overtemperature shutdown,  
overcurrent shutdown, and undervoltage shutdown.  
DWB SUFFIX  
EW SUFFIX (Pb-FREE)  
98ARH99137A  
The device is parametrically specified over ambient temperature  
range of -40°C TA 125°C and 5.5 V VIGN 24 V supply.  
32-PIN SOICW  
Features  
• Drives Six N-Channel Low RDS(ON) Power MOSFETs  
• Built-In Charge Pump Circuitry  
• Built-In Current Sense Comparator and Output Drive Current  
Limiting  
ORDERING INFORMATION  
Temperature  
Device  
Package  
• Built-In PWM Mode Control Logic  
Range (T )  
A
• Built-In Circuit Protection  
MC33395DWB/R2  
MC33395EW/R2  
MCZ33395EW/R2  
MC33395TDWB/R2  
MC33395TEW/R2  
32 SOICW  
• Designed for Fractional to Integral HP BLDC Motors  
• 32-Pin SOIC Wide Body Surface Mount Package  
• 33395 Incorporates a <5.0 µs Shoot-Through Suppression Timer  
• 33395T Incorporates a <1.0 µs Shoot-Through Suppression Timer  
• Pb-Free Packaging Designated by Suffix Code EW  
32 SOICW  
(Pb-Free)  
-40°C to 125°C  
32 SOICW  
32 SOICW  
(Pb-Free)  
VPWR  
33395  
VIGNP  
VGDH  
VIGN  
VDD  
CP1H  
CP1L  
CP2H  
CP2L  
VDD  
GDH1  
GDH2  
GDH3  
SRC1  
H
N
S
S
SRC2  
SRC3  
CRES  
N
H
3
2
HSE1–3  
MODE0–1  
PWM  
LSE1–3  
GDL1  
MCU  
GDL2  
GDL3  
-ISENS  
3
VDD  
AGND  
PGND  
+ISENS  
Figure 1. 33395 Simplified Application Diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
VIGN  
VDD  
Osc.  
CP1H  
CP1L  
Charge  
Pump  
CP2H  
CP2L  
Low  
Overvoltage  
Shutdown  
Voltage  
Reset
CPRES  
+ISENS  
-ISENS  
+
-
DriveLimiting
L
H
MODE0  
MODE1  
VGDH  
VIGNP  
GDH1  
PWM  
HSE1  
Control  
Logic  
HSE2  
HSE3  
GDH2  
GDH3  
SRC1  
SRC2  
SRC3  
Gate  
LSE1  
LSE2  
LSE3  
Drive  
Circuits  
AGND  
GDL1  
GDL2  
Overtemperature  
TEST  
Shutdown  
GDL3  
PGND  
Figure 2. 33395 Simplified Internal Block Diagram  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
PIN CONNECTIONS  
PIN CONNECTIONS  
CP2H  
CPRES  
VIGN  
1
CP2L  
CP1H  
CP1L  
LSE1  
LSE2  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
3
VGDH  
VIGNP  
SRC1  
GDH1  
GDL1  
SRC2  
GDH2  
GDL2  
SRC3  
GDH3  
GDL3  
PGND  
TEST  
4
5
6
LSE3  
7
HSE1  
HSE2  
HSE3  
MODE0  
MODE1  
PWM  
8
9
10  
11  
12  
13  
14  
15  
16  
VDD  
AGND  
+ISENS  
-ISENS  
Figure 3. 33395 Pin Connections  
Table 1. 33395 Pin Definitions  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
High potential pin connection for secondary charge pump capacitor  
Input from external reservoir capacitor for charge pump  
1
2
CP2H  
Charge Pump Cap  
CPRES  
Input  
Charge Pump  
Reserve Cap  
Input from ignition level supply voltage for power functions  
3
4
VIGN  
Input  
Input Voltage  
Output full-time gate drive for auxiliary high-side power MOSFET switch  
VGDH  
Output  
High-Side Gate  
Voltage  
Input from protected ignition level supply for power functions  
5
VIGNP  
Input  
Input Voltage  
Protected  
Sense for high-side source voltage, phase 1  
Output for gate high-side, phase 1  
6
SRC1  
GDH1  
GDL1  
SRC2  
GDH2  
GDL2  
SRC3  
GDH3  
GDL3  
PGND  
Test  
Sensor  
Output  
Output  
Sensor  
Output  
Output  
Sensor  
Output  
Output  
Ground  
N/A  
High-Side Sense  
Gate Drive High  
Output for Gate  
High-Side Sense  
Gate Drive High  
Output for Gate  
High-Side Sense  
Gate Drive High  
Gate Drive Low  
Power Ground  
Test Pin  
7
Output for gate drive low-side, phase 1  
Sense for high-side source voltage, phase 2  
Output for gate high-side, phase 2  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
Output for gate drive low-side, phase 2  
Sense for high-side source voltage, phase 3  
Output for gate drive high-side, phase 3  
Output for gate drive low-side, phase 3  
Ground pins for power functions  
This should be connected to ground or left open  
Inverting input for current limit comparator  
Non-inverting input for current limit comparator  
Ground pin for logic functions  
-ISENS  
+ISENS  
AGND  
VDD  
Input  
IS Minus  
Input  
IS Plus  
Ground  
Power  
Input  
Analog Ground  
Logic Supply Voltage  
Pulse Width Modulator  
Supply voltage for logic functions  
Input for pulse width modulated driver duty cycle  
PWM  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
Table 1. 33395 Pin Definitions (continued)  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.  
Pin Number Pin Name Pin Function  
Formal Name  
Definition  
Input for mode control selection  
22  
23  
24  
25  
26  
27  
28  
29  
30  
MODE1  
MODE0  
HSE3  
HSE2  
HSE1  
LSE3  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Mode Control Bit 1  
Mode Control Bit 0  
High-Side Enable  
High-Side Enable  
High-Side Enable  
Low-Side Enable  
Low-Side Enable  
Low-Side Enable  
Input for mode control selection  
Input for high-side enable logic, phase 3  
Input for high-side enable logic, phase 2  
Input for high-side enable logic, phase 1  
Input for low-side enable logic, phase 3  
Input for low-side enable logic, phase 2  
Input for low-side enable logic, phase 1  
Input from external pump capacitor for charge pump and secondary pins  
LSE2  
LSE1  
CP1L  
External Pump  
Capacitor  
Input from external pump capacitor for charge pump and secondary pins  
31  
32  
CP1H  
CP2L  
Input  
Input  
External Pump  
Capacitor  
Input from external reservoir, external pump capacitors for charge pump,  
and secondary pins  
Charge Pump  
Capacitor  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted.  
Rating  
Symbol  
Value  
Unit  
VIGN Supply Voltage  
VIGN  
-15.5 to 40  
-0.3 to 65  
-0.3 to 7.0  
0.3 to 7.0  
100  
VDC  
VDC  
VDC  
VDC  
mA  
V
VIGNP Load Dump Survival  
IGNP  
VDD  
VIN  
LD  
VDD Logic Supply Voltage (Fail Safe)  
Logic Input Voltage (LSEn, HSEn, PWM, and MODEn)  
Start Up Current VIGNP  
IVIGNSTARTUP  
ESD Voltage (1)  
Human Body Model  
Machine Model  
V
VESD1  
VESD2  
TSTG  
TA  
±500  
±200  
Storage Temperature  
-65 to 160  
-40 to 125  
-40 to 125  
150  
°C  
°C  
°C  
°C  
Operating Ambient Temperature  
Operating Case Temperature  
Maximum Junction Temperature  
TC  
TJ  
Power Dissipation (T = 25°C)  
A
P
D
1.5  
W
(3)  
Peak Package Reflow Temperature During Reflow (2)  
Thermal Resistance, Junction-to-Ambient  
Notes  
,
TPPRT  
RΘJA  
Note 3  
°C  
65  
°C/W  
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in  
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ).  
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),  
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions -40°C TA 125°C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect  
approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
POWER INPUT  
VIGN Current @ 5.5 V–24 V, V  
= 5.5 V  
= 5.5 V  
IIGN  
0.2  
1.0  
100  
36.5  
24  
mA  
mA  
V
DD  
VIGNP Current @ 5.5 V–24 V, V  
VIGNP Overvoltage Shutdown  
VIGNP Voltage  
IIGNP  
DD  
V
IGNP  
25  
5.5  
33  
SD  
VIGNP  
V
I
V
V
V
Current @ 5.5 VDC, 5.5 V VIGNP 24 V  
Low-Voltage Reset Level  
V
1.8  
3.2  
4.0  
4.0  
mA  
V
DD  
DD  
DD  
DD  
V
2.5  
7.0  
DD(RESET)  
One-Time Fuse (Logic Supply)  
V
INPUT/OUTPUT  
Input Current at VDD = 5.5 V  
IIN  
µA  
LSEn, HSEn, PWM, and MODEn = 3.0 V  
5.0  
1.0  
12  
25  
Input Threshold at VDD = 5.5 V  
VTH  
V
LSEn, HSEn, PWM, and MODEn (4)  
2.0  
3.0  
V
Source Sense Voltage  
V
V
SCRn  
SCRn  
SRC1, SRC2, SRC3  
-0.3  
5.0  
V
24  
20  
IGNP  
14  
Comparator Input Offset Voltage  
Comparator Input Bias Current  
Comparator Input Offset Current  
Common Mode Voltage (5)  
VINP(OFFSET)  
VINP(BIAS)  
IINP(OFFSET)  
VCMR  
mV  
nA  
nA  
VDC  
V
-500  
-300  
0
-170  
-3.0  
500  
300  
VDD-2.0  
+VDD  
Comparator Differential Input Voltage (5)  
VINPdiff  
-VDD  
(6)  
Charge Pump Voltage VIGN  
VCRES-VIGNP  
V
VIGNP = 5.5 V, ICRES = 1.0 mA  
VIGNP = 9.0 V, ICRES = 1.0 mA  
VIGNP = 12 V, ICRES = 5.0 mA  
4.0  
4.0  
4.5  
8.0  
4.5  
6.0  
7.5  
10  
18  
18  
18  
18  
18  
16  
VIGNP = 24 V, I RES = 1.0 mA  
C
12  
VIGNP = 24 V, ICRES = 5.0 mA  
VGDH Output Voltage with GDHn in ON State  
VIGNP = 5.5 V, IGDHn = 1.0 mA  
VGDHn( )-VSRCn  
on  
V
V
4.0  
4.0  
4.5  
5.2  
9.0  
11  
18  
18  
18  
VIGNP = 12 V, IGDHn = 5.0 mA  
VIGNP = 24 V, IGDHn = 5.0 mA  
VGDH Output Voltage with GDHn in OFF State  
VIGNP = SRCn = 14 V, IGDHn = 1.0 mA  
VGDHn(  
)
off  
-1.0  
0.6  
1.0  
Notes  
4. Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 µA internal sinks.  
5. Guaranteed by design and characterization. Not production tested.  
6. The Charge Pump has a positive temperature coefficient. Therefore the Min’s occur at -40°C, Typ’s at 25°C, and Max’s at 125°C.  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions -40°C TA 125°C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect  
approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.  
Characteristic  
INPUT/OUTPUT (CONTINUED)  
Symbol  
Min  
Typ  
Max  
Unit  
VGDL Low-Side Output Voltage GDHn in ON State  
VIGNP = 5.5 V, IGDLn = 1.0 mA  
VGDL(  
on  
V
)
5.0  
8.0  
8.0  
8.0  
8.0  
14  
17  
16  
18  
18  
19  
19  
VIGNP = 12 V, IGDLn = 5.0 mA  
VIGNP = 24 V, IGDLn = 0.0 mA  
VIGNP = 24 V, IGDLn = 5.0 mA  
VGDL Output Voltage GDHn in OFF State  
VIGNP = 14 V, IGDLn = 1.0 mA  
VGDL(off)  
V
-1.0  
160  
0.3  
1.0  
Thermal Shutdown (7)  
TLIM  
190  
°C  
Notes  
7. Guaranteed by design and characterization. Not production tested.  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
Characteristics noted under conditions -40°C TA 125°C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values  
reflect approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time  
(25% to 75%), CISS Value = 2000 pF (8)  
tRH  
µs  
0.35  
1.5  
High-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time  
tFH  
µs  
µs  
(75% to 25%), CISS Value = 2000 pF (8)  
0.25  
1.5  
(9)  
Shoot-Through Suppression Time Delay (33395) (8)  
,
tD1, tD2  
33395  
1.0  
0.2  
3.0  
5.5  
1.0  
33395T  
0.65  
Current Limit Time Delay (10)  
tILIMDELAY  
1.5  
2.8  
5.0  
µs  
Notes  
8. See Figure 4, page 8.  
9. Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being on  
simultaneously.  
10. Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOW  
and sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay.  
TIMING DIAGRAM  
100  
75  
25  
0
tRH tFH  
tD1  
tFL  
tD2  
tRL  
100  
75  
25  
0
TIME  
Figure 4. Shoot-Through Suppression  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
8
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 33395 and 33395T devices are designed to provide  
the necessary drive and control signal buffering and  
amplification to enable a DSP or MCU to control a three-  
phase array of power MOSFETs such as would be required  
to energize the windings of powerful brushless DC (BLDC)  
motors. It contains built-in charge pump circuitry so that the  
MOSFET array may consist entirely of N-Channel  
MOSFETs. It also contains feedback sensing circuitry and  
control circuitry to provide a robust overall motor control  
design.  
FUNCTIONAL PIN DESCRIPTION  
CHARGE PUMP CAPACITOR (CP2H)  
IS MINUS (-ISENS)  
High potential pin connection for secondary charge pump  
capacitor  
Inverting input for current limit comparator  
IS PLUS (+ISENS)  
CHARGE PUMP RESERVE CAPACITOR (CPRES)  
Non-Inverting input for current limit comparator  
Input from external reservoir capacitor for charge pump  
ANALOG GROUND (AGND)  
INPUT VOLTAGE (VIGN)  
Ground pin for logic functions  
Input from ignition level supply voltage for power functions  
LOGIC SUPPLY VOLTAGE (VDD)  
HIGH-SIDE GATE VOLTAGE (VGDH)  
Supply voltage for logic functions  
Output full-time gate drive for auxiliary high-side power  
MOSFET switch  
PULSE WIDTH MODULATOR (PWM)  
Input for pulse width modulated driver duty cycle  
INPUT VOLTAGE PROTECTED (VIGNP)  
Input from protected ignition level supply for power  
functions  
MODE CONTROL BIT 1 (MODE1)  
Input for mode control selection  
HIGH-SIDE SENSE (SRC1, SRC2, SRC3)  
MODE CONTROL BIT 0 (MODE0)  
Sense for high-side source voltage, phase 1/2/3  
Input for mode control selection  
GATE DRIVE HIGH (GDH1, GDH2, GDH3)  
HIGH-SIDE ENABLE (HSE3, HSE2, HSE1)  
Output for gate high-side, phase 1/2/3  
Input for high-side enable logic, phase 1/2/3  
OUTPUT FOR GATE (GDL1, GDL2, GDL3)  
LOW-SIDE ENABLE (LSE3, LSE2, LSE1)  
Output for gate drive low-side, phase 1  
Input for low-side enable logic, phase 1/2/3  
POWER GROUND (PGND)  
EXTERNAL PUMP CAPACITOR (CP1L, CP1H)  
Ground pins for power functions  
Input from external pump capacitor for charge pump and  
secondary pins  
TEST PIN (TEST)  
This should be connected to ground or left open  
CHARGE PUMP CAPACITOR (CP2L)  
Input from external reservoir, external pump capacitors for  
charge pump, and secondary pins  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
GATE DRIVE CIRCUITS  
LOW VOLTAGE RESET FUNCTION  
The gate drive outputs (GDH1, GDH2, etc.) supply the  
peak currents required to turn ON and hold ON the  
MOSFETs, as well as turn OFF and hold OFF the MOSFETs.  
When the logic supply voltage (VDD) drops below the  
minimum voltage level or when the part is initially powered  
up, this function will turn OFF and hold OFF the external  
MOSFETs until the voltage increases above the minimum  
voltage level required for normal operation.  
CHARGE PUMP  
The current capability of the charge pump is sufficient to  
supply the gate drive circuit’s demands when PWMing at up  
to 28 kHz. Two external charge pump capacitors and a  
reservoir capacitor are required to complete the charge  
pump’s circuitry.  
CONTROL LOGIC  
The control logic block controls when the low-side and  
high-side drivers are enabled. The logic implements the Truth  
Table found in the specification and monitors the M0, M1,  
PWM, CL, OT, OV, LSE, and HSE pins. Note that the drivers  
are enabled 3 µs after the PWM edge. During complimentary  
chop mode the high-side and low-side drives are alternatively  
enabled and disabled during the PWM cycle. To prevent  
shoot-through current, the high-side drive turn-on is delayed  
by tD1, and the low-side drive turn on is delayed by tD2 (see  
Figure 4, page 8).  
Charge reservoir capacitance is a function of the total  
MOSFET gate charge (QG) gate drive voltage level relative to  
the source (VGS) and the allowable sag of the drive level  
during the turn-on interval (VSAG). CRES can be expressed by  
the following formula:  
QG x VGS  
CRES  
=
2
2 x VGS x VSAG - VSAG  
Note that the drivers are disabled during an  
overtemperature or overvoltage fault. A flip-flop keeps the  
drive off until the following PWM cycle. This prevents erratic  
operation during fault conditions. The current limit circuit also  
uses a flip-flop for latching the drive off until the following  
PWM cycle.  
For example, for QG = 60 nC, VGS = 14 V, VSAG = 0.2 V:  
(60 nC) x (14 V)  
CRES  
=
= 0.15 µF  
2 x (14 V) x (0.2 V) - (0.2)2  
Note PWM must be toggled after POR, Thermal Limit, or  
overvoltage faults to re-enable the gate drivers.  
Proper charge pump capacitance is required to maintain,  
and provide for, adequate gate drive during high demand  
turn-ON intervals. Use the following formula to determine  
VGDH  
values for CP1 and CP2  
For example, for the above determination of CRES  
0.15 µF:  
:
The VGDH pin is used to provide a gate drive signal to a  
reverse battery protection MOSFET. If reverse battery  
protection is desired, VIGN would be applied to the source of  
an external MOSFET, and the drain of the MOSFET would  
then deliver a "protected" supply voltage (VIGNP) to the three  
phase array of external MOSFETs as well as the supply  
voltage to the VIGNP pin of the IC.  
=
CRES  
20  
CRES  
10  
< CP1 = CP2  
<
By averaging these two values, the proper CP value can  
n
In a reverse polarity event (e.g., an erroneous installation  
of the system battery), the VGDH signal will not be supplied to  
the external protection MOSFET, and the MOSFET will  
remain off and thus prevent reverse polarity from being  
applied to the load and the VIGNP supply pin of the IC.  
be determined:  
0.15 µF  
0.15 µF  
= .015 µF, upper lim  
= 0.075 µF, lower limit; and  
20  
10  
CP1 and CP2 =(0.0075 µF + 0.015 µF) ÷ 2 = 0.01 µF  
HIGH-SIDE GATE DRIVE CIRCUITS  
THERMAL SHUTDOWN FUNCTION  
Outputs GDH1, GDH2, and GDH3 provide the elevated  
drive voltage to the high-side external MOSFETs (HS1, HS2,  
and HS3; see Figure 5, page 13). These gate drive outputs  
supply the peak currents required to turn ON and hold ON the  
high-side MOSFETs, as well as turn OFF the MOSFETs.  
These gate drive circuits are powered from an internal charge  
pump, and therefore compensate for voltage dropped across  
the load that is reflected to the source-gate circuits of the  
high-side MOSFETs.  
The device has internal temperature sensing circuitry  
which activates a protective shutdown function should the die  
reach excessively elevated temperatures. This function  
effectively limits power dissipation and thus protects the  
device.  
OVERVOLTAGE SHUTDOWN FUNCTION  
When the supply voltage (VIGN) exceeds the specified  
over- voltage shutdown level, the part will automatically shut  
down to protect both internal circuits as well as the load.  
Operation will resume upon return of VIGN to normal  
operating levels.  
LOW-SIDE GATE DRIVE CIRCUITS  
Outputs GDL1, GDL2, and GDL3 provide the drive voltage  
to the low-side external MOSFETs (LS1, LS2, and LS3; see  
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FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
Figure 5). These gate drive outputs supply the peak currents  
required to turn ON and hold ON the low-side MOSFETs, as  
well as turn OFF the MOSFETs.  
to occur on both the high-side and low-side MOSFETs as  
"complementary chopping".  
TEST PIN  
V
FUSE  
DD  
This pin should be grounded or left floating (i.e., do not  
connect it to the printed circuit board). It is used by the  
automated test equipment to verify proper operation of the  
internal overtemperature shut down circuitry. This pin is  
susceptible to latch-up and therefore may cause erroneous  
operation or device failure if connected to external circuitry.  
The VDD supply of the 33395 IC has an internal fuse, which  
will blow and set all outputs of the device to OFF, if the VDD  
voltage exceeds that stated in the maximum rating section of  
the data sheet. When this fuse blows, the device is  
permanently disabled.  
I
INPUTS  
SENS  
The +Isens and -Isens pins are inputs to the internal  
current sense comparator. In a typical application, these  
would receive a a low-pass filtered voltage derived from a  
current sense resistor placed in series with the ground return  
of the three-phase output bridge. When triggered by the  
comparator, the CL (current limit) bit of the internal error  
register is set, and the output gate drive pairs (i.e., GDH1 and  
GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled  
such that current will cease flowing through the load (refer to  
Table 5, Truth Table, page 12).  
OVERTEMPERATURE AND OVERVOLTAGE  
SHUTDOWN CIRCUITS  
Internal monitoring is provided for both over temperature  
conditions and over voltage conditions. When any of these  
conditions presents itself to the IC, the corresponding  
internally set bits of the error register are set, and the output  
gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2,  
GDH3 and GDL3), are controlled such that current will cease  
flowing through the load (refer to Table 5).  
LSE AND HSE INPUT CIRCUITS  
The low-side enable input pins (LSE1, LSE2, LSE3) and  
high-side enable input pins (HSE1, HSE2, HSE3) form the  
input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and  
LSE3) which set the logic states of the output gate drive pairs  
(i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3)  
in accordance with the logic set forth in the Truth Table  
(page 12). Typically these inputs are supplied from an MCU  
or DSP to provide the phasing of the currents applied to a  
brushless dc motor's stator coils via the output MOSFET  
pairs.  
PWM INPUT  
The pulse width modulation input provides a single input  
pin to accomplish PWM modulation of the output pairs in  
accordance with the states of the Mode 0 and Mode 1 inputs  
as set forth in the Truth Table (page 12).  
MODE SELECTION INPUTS  
The mode selection inputs (Mode 0 and Mode 1)  
determine the PWM implementation of the output pairs in  
accordance with the logic set forth in the Truth Table  
(page 12). PWMing can thus be set to occur either on the  
high-side MOSFETs or the low-side MOSFETs, or can be set  
33395  
Analog Integrated Circuit Device Data  
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11  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Table 5. Truth Table  
The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn  
(n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT),  
overvoltage (OV), and current limit (CL) bits provided in this table.  
NORMAL OPERATION  
Switching Modes  
Internally Set Bits  
Input Pairs  
Output Pairs  
(e.g., LSE2 and HSE2)  
(e.g., GDL2 and GDH2)  
MODE1  
MODE0  
OT  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OV  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSEn  
HSEn  
GDLn  
GDHn  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
PWM  
0
0
0
0
0
0
1
PWM  
PWM  
0
0
0
0
0
PWM  
1
0
0
0
0
PWM  
1
0
PWM  
0
0
0
FAULT MODE OPERATION  
Internally Set Bits Input Pairs  
(e.g., LSE2 and HSE2)  
Switching Modes  
Output Pairs  
(e.g., GDL2 and GDH2)  
MODE1  
MODE0  
OT  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
OV  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
CL  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
LSEn  
HSEn  
GDLn  
GDHn  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
x
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
12  
TYPICAL APPLICATIONS  
OPERATIONAL MODES  
TYPICAL APPLICATIONS  
12 V  
+
+
HS1  
HS2  
HS3  
-
CP2H  
CPRES  
VIGN  
VGDH  
VIGNP  
CP2L  
1
2
3
4
5
6
32  
CP1H  
31  
CP1L  
30  
LSE1  
29  
LSE2  
28  
SRC1  
LSE3  
27  
GDH1  
GDL1  
HSE1  
26  
7
8
HSE2  
MCU  
25  
24  
23  
22  
21  
20  
19  
18  
17  
LS1  
LS2  
LS3  
SRC2  
GDH2  
GDL2  
SRC3  
GDH3  
GDL3  
PGND  
TEST  
HSE3  
MODE0  
9
10  
11  
12  
13  
14  
15  
16  
5.0 V  
+
MODE1  
PWM  
VDD  
AGND  
+ISENS  
-ISENS  
Figure 5. Typical Application Diagram  
33395  
Analog Integrated Circuit Device Data  
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13  
PACKAGING  
PACKAGE DIMENSIONS  
PACKAGING  
PACKAGE DIMENSIONS  
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARH99137A listed below.  
NOTES:  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
2. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
3. DATUMS B AND C TO BE DETERMINED AT THE  
PLANEWHERETHEBOTTOM OFTHELEADS EXIT  
THE PLASTIC BODY.  
4. THIS DIMENSION DOES NOT INCLUDE MOLD  
10.3  
FLASH, PROTRUSION OR GATE BURRS. MOLD  
7.6  
7.4  
FLASH, PROTRUSION OR GATE BURRS SHALL  
NOT EXCEED 0.15 MM PER SIDE. THIS  
DIMENSION IS DETERMINED AT THE PLANE  
WHERE THE BOTTOM OF THE LEADS EXIT THE  
PLASTIC BODY.  
C
B
2.65  
2.35  
5
9
30X  
5. THIS DIMENSION DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSIONS.  
INTERLEAD FLASH AND PROTRUSIONS SHALL  
NOT EXCEED 0.25 MM PER SIDE. THIS  
DIMENSION IS DETERMINED AT THE PLANE  
WHERE THE BOTTOM OF THE LEADS EXIT THE  
PLASTIC BODY.  
1
32  
0.65  
PIN 1 ID  
4
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
11.1  
10.9  
C
L
9
PROTRUSION SHALL NOT CAUSE THE LEAD  
WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR  
CANNOT BE LOCATED ON THE LOWER RADIUS  
OR THE FOOT. MINIMUM SPACE BETWEEN  
PROTRUSION AND ADJACENT LEAD SHALL NOT  
LESS THAN 0.07 MM.  
B
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.  
8. THESE DIMENSIONS APPLY TO THE FLAT  
SECTION OF THE LEAD BETWEEN 0.10 MM AND  
0.3 MM FROM THE LEAD TIP.  
9. THE PACKAGE TOP MAY BE SMALLER THAN THE  
PACKAGE BOTTOM. THIS DIMENSION IS  
DETERMINED AT THE OUTERMOST EXTREMES  
OF THE PLASTIC BODY EXCLUSIVE OF MOLD  
FLASH, TIE BAR BURRS, GATE BURRS AND  
INTER-LEAD FLASH, BUT INCLUDING ANY  
MISMATCH BETWEEN THE TOP AND BOTTOM OF  
THE PLASTIC BODY.  
16  
17  
SEATING  
A
PLANE  
5.15  
2X 16 TIPS  
32X  
0.10 A  
0.3 A B C  
A
(0.29)  
BASE METAL  
0.25  
0.19  
(0.203)  
R0.08 MIN  
A
0.25  
GAUGE PLANE  
°
0
0.38  
0.22  
0.29  
0.13  
MIN  
PLATING  
6
M
M
0.13  
C A  
B
8
0.9  
0.5  
°
°
8
0
SECTION A-A  
ROTATED 90 CLOCKWISE  
°
SECTION B-B  
DWB SUFFIX  
EW SUFFIX (PB-FREE)  
32-PIN  
PLASTIC PACKAGE  
98ARH99137A  
ISSUE A  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
Implemented Revision History page  
Converted to Freescale format  
Added Pin Definitions  
7/2005  
3.0  
Updated Freescale data sheet form and style  
Added MCZ33395EW/R2 to the Ordering Information block  
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter and added  
notes (2) and (3) to Maximum Ratings on page 5  
2/2007  
4.0  
33395  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
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MC33395  
Rev 4.0  
2/2007