转到网站首页
转为中文步骤：
1、请用电脑端360浏览器打开本页地址，如您电脑未安装360浏览器，请点这里下载;
2、点击360浏览器右上角的翻译插件，如右图红圈中所示:
3、点击所弹出窗口里的右下角的按钮 “翻译当前网页”;
4、弹窗提示翻译完毕后关闭弹窗即可；
S25FL040A  
4 Megabit CMOS 3.0 Volt Flash Memory  
with 50MHz SPI (Serial Peripheral Interface) Bus  
and Small Sector for Boot and Parameter Storage  
S25FL040A Cover Sheet  
Data Sheet (Preliminary)  
Notice to Readers: This document states the current technical specifications regarding the Spansion  
product(s) described herein. Each product described herein may be designated as Advance Information,  
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.  
Publication Number S25FL040A_00  
Revision B0  
Issue Date August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Notice On Data Sheet Designations  
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of  
product information or intended specifications throughout the product life cycle, including development,  
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify  
that they have the latest information before finalizing their design. The following descriptions of Spansion data  
sheet designations are presented here to highlight their presence and definitions.  
Advance Information  
The Advance Information designation indicates that Spansion Inc. is developing one or more specific  
products, but has not committed any design to production. Information presented in a document with this  
designation is likely to change, and in some cases, development on the product may discontinue. Spansion  
Inc. therefore places the following conditions upon Advance Information content:  
“This document contains information on one or more products under development at Spansion Inc.  
The information is intended to help you evaluate this product. Do not design in this product without  
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed  
product without notice.”  
Preliminary  
The Preliminary designation indicates that the product development has progressed such that a commitment  
to production has taken place. This designation covers several aspects of the product life cycle, including  
product qualification, initial production, and the subsequent phases in the manufacturing process that occur  
before full production is achieved. Changes to the technical specifications presented in a Preliminary  
document should be expected while keeping these aspects of production under consideration. Spansion  
places the following conditions upon Preliminary content:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. The Preliminary status of this document indicates that product qualification has been  
completed, and that initial production has begun. Due to the phases of the manufacturing process that  
require maintaining efficiency and quality, this document may be revised by subsequent versions or  
modifications due to changes in technical specifications.”  
Combination  
Some data sheets contain a combination of products with different designations (Advance Information,  
Preliminary, or Full Production). This type of document distinguishes these products and their designations  
wherever necessary, typically on the first page, the ordering information page, and pages with the DC  
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first  
page refers the reader to the notice on this page.  
Full Production (No Designation on Document)  
When a product has been in production for a period of time such that no changes or only nominal changes  
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include  
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed  
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a  
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following  
conditions to documents in this category:  
“This document states the current technical specifications regarding the Spansion product(s)  
described herein. Spansion Inc. deems the products to have been in sufficient production volume such  
that subsequent versions of this document are not expected to change. However, typographical or  
specification corrections, or modifications to the valid combinations offered may occur.”  
Questions regarding these document designations may be directed to your local sales office.  
ii  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
S25FL040A  
4 Megabit CMOS 3.0 Volt Flash Memory  
with 50MHz SPI (Serial Peripheral Interface) Bus  
and Small Sector for Boot and Parameter Storage  
Data Sheet (Preliminary)  
Distinctive Characteristics  
„ Process Technology  
Architectural Advantages  
„ Single power supply operation  
– Manufactured on 0.20 µm MirrorBitTM process technology  
„ Package Option  
– Full voltage range: 2.7 to 3.6 V read and program operations  
– Industry Standard Pinouts  
– 8-pin SO package (150 mils)  
– 8-pin SO package (208 mils)  
– 8-Contact WSON Package (5 x 6 mm)  
„ Memory Architecture  
– 4Mb uniform 64KB sector product: Backward compatible with  
S25FL004A 4Mb device; same pin out, command set and uniform  
sector size (64KB)  
– 4Mb small sector product: Offer Top Boot & Bottom Boot devices;  
Seven sectors of 64KB and One 64KB sector (Top or bottom)  
broken into two sectors of 16KB each, two sectors of 4KB each, and  
two sectors of 12KB each.  
Performance Characteristics  
„ Speed  
– 50 MHz clock rate (maximum)  
„ Program  
„ Power Saving Standby Mode  
– Standby Mode 20 µA (max)  
– Page Program (up to 256 bytes) in 1.5 ms (typical)  
– Program operations are on a page by page basis  
– Deep Power Down Mode 1.5 µA (typical)  
„ Erase  
– 0.5 s typical sector erase time  
– 3 s typical bulk erase time  
Memory Protection Features  
„ Memory Protection  
„ Cycling Endurance  
– 100,000 cycles per sector typical  
„ Data Retention  
– W# pin works in conjunction with Status Register Bits to protect  
specified memory areas  
– Status Register Block Protection bits (BP2, BP1, BP0) in status  
register configure parts of memory as read-only  
– 20 years typical  
„ Device ID  
Software Features  
– JEDEC standard two-byte electronic signature  
– RES command one-byte electronic signature for backward  
compatibility  
– SPI Bus Compatible Serial Interface  
Publication Number S25FL040A_00  
Revision B0  
Issue Date August 31, 2006  
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-  
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document  
may be revised by subsequent versions or modifications due to changes in technical specifications.  
D a t a S h e e t ( P r e l i m i n a r y )  
General Description  
The S25FL040A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device with with erasable  
sectors for boot code and parameter storage.  
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are  
designed to be programmed in-system with the standard system 3.0 volt VCC supply.  
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device  
supports Sector Erase and Bulk Erase commands.  
Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally  
generated and regulated voltages are provided for the program operations. This device does not require a  
VPP supply. The S25FL040A device in uniform 64KB sector configuration is compatible with the S25FL004A  
device.  
2
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Table of Contents  
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.  
2.  
3.  
4.  
5.  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Input/Output Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
5.1  
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
6.  
7.  
Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
8.  
9.  
Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
9.1  
9.2  
9.3  
9.4  
9.5  
9.6  
9.7  
9.8  
9.9  
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Read Identification (RDID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Read Identification (Read_ID) [RDID Alternate] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Write Status Register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
9.10 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
9.11 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
9.12 Deep Power Down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
9.13 Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
9.13.1 Release from Deep Power Down and Read Electronic Signature (RES). . . . . . . . . .24  
10. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
11. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
13. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
15. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
16. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
17. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
17.1 SOA 008—Narrow 8-pin Plastic Small Outline 150 mils Body Width Package . . . . . . . . . . . 31  
17.2 SOC 008—Wide 8-pin Plastic Small Outline 208 mils Body Width Package. . . . . . . . . . . . . 32  
17.3 USON 8L (5 x 6 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
18. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
3
D a t a S h e e t ( P r e l i m i n a r y )  
List of Figures  
Figure 2.1  
8-pin Plastic Small Outline Package (SO 150 mil, SO 208 mil). . . . . . . . . . . . . . . . . . . . . . . . 6  
8L USON (5 x 6 mm) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 15  
Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 16  
READ_ID Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 2.2  
Figure 6.1  
Figure 6.2  
Figure 7.1  
Figure 9.1  
Figure 9.2  
Figure 9.3  
Figure 9.4  
Figure 9.5  
Figure 9.6  
Figure 9.7  
Figure 9.8  
Figure 9.9  
Figure 9.10 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 9.11 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Figure 9.12 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 9.13 Release from Deep Power Down (RES) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 9.14 Release from Deep Power Down and  
Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 10.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 15.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Figure 16.1 SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 16.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 16.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 30  
List of Tables  
Table 5.1  
S25FL040A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8  
S25FL040A Protected Area Sizes (Top Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
S25FL040A Protected Area Sizes (Bottom Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
S25FL040A Protected Area Sizes (Uniform Sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
S25FL040A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
Sector Address Table - S25FL040A (Top Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
Sector Address Table - S25FL040A (Bottom Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
S25FL040A Sector Address Table (Uniform Sectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
READ_ID Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
S25FL040A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
Table 7.1  
Table 7.2  
Table 7.3  
Table 8.1  
Table 8.2  
Table 8.3  
Table 8.4  
Table 9.1  
Table 9.2  
Table 9.3  
Table 9.4  
Table 9.5  
Table 10.1  
Table 12.1  
Table 13.1  
Table 14.1  
Table 15.1  
Table 16.1  
4
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
1. Block Diagram  
SRAM  
PS  
X
D
E
C
Array - L  
Array - R  
Logic  
RD  
DATA PATH  
IO  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
5
D a t a S h e e t ( P r e l i m i n a r y )  
2. Connection Diagrams  
Figure 2.1 8-pin Plastic Small Outline Package (SO 150 mil, SO 208 mil)  
VCC  
8
1
2
CS#  
SO  
7
HOLD#  
SCK  
SI  
3
W#  
6
5
4
GND  
Figure 2.2 8L USON (5 x 6 mm) Package  
CS#  
SO  
VCC  
8
7
6
1
2
HOLD#  
SCK  
W#  
3
4
GND  
SI  
5
6
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
3. Input/Output Descriptions  
Signal Name  
I/O  
Description  
SO (Signal Data Output)  
Output  
Transfers data serially out of the device on the falling edge of SCK.  
Transfers data serially into the device. Device latches commands, addresses, and  
program data on SI on the rising edge of SCK.  
SI (Serial Data Input)  
SCK (Serial Clock)  
Input  
Input  
Provides serial interface timing. Latches commands, addresses, and data on SI on rising  
edge of SCK. Triggers output on SO after the falling edge of SCK.  
Places device in active power mode when driven low. Deselects device and places SO  
at high impedance when high. After power-up, device requires a falling edge on CS#  
before any command is written. Device is in standby mode when a program, erase, or  
Write Status Register operation is not in progress.  
CS# (Chip Select)  
Input  
Pauses any serial communication with the device without deselecting it. When driven  
low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that  
CS# also be driven low.  
HOLD# (Hold)  
Input  
Input  
Protects the memory area specified by Status Register bits BP2:BP0. When driven low,  
prevents any program or erase command from altering the data in the protected  
memory area.  
W# (Write Protect)  
VCC  
Input  
Input  
Supply Voltage  
Ground  
GND  
4. Logic Symbol  
V
CC  
SO  
SI  
SCK  
CS#  
W#  
HOLD#  
GND  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
7
D a t a S h e e t ( P r e l i m i n a r y )  
5. Ordering Information  
The ordering part number is formed by a valid combination of the following:  
S25FL  
040  
A
0L  
M
A
I
00  
1
PACKING TYPE (Note 1)  
0
1
3
=
=
=
Tray  
Tube  
13” Tape and Reel  
MODEL NUMBER (Additional Ordering Options)  
00  
01  
02  
=
=
=
64 KBytes Uniform Sector  
Top Boot Sector  
Bottom Boot Sector  
TEMPERATURE RANGE  
Industrial (–40°C to + 85°C)  
I
=
PACKAGE MATERIALS  
A
=
Standard  
F
=
Lead (Pb)-free  
PACKAGE TYPE  
V
M
N
=
=
=
8-Pin Plastic Small Outline Package (150 mil)  
8-Pin Plastic Small Outline Package (208 mil)  
8-contact WSON Package  
SPEED  
0L  
=
50 MHz  
DEVICE TECHNOLOGY  
A
=
0.20 µm MirrorBit™ Process Technology  
DENSITY  
040  
=
4 Mbit  
DEVICE FAMILY  
S25FL  
SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory  
Table 5.1 S25FL040A Valid Combinations Table  
S25FL040A Valid Combinations  
Package Marking  
(Note 2)  
Base Ordering  
Part Number  
Speed Option Package & Temperature Model Number Packing Type  
MAI, MFI,  
VAI, VFI,  
NAI, NFI  
FL040A +  
S25FL040A  
0L  
00, 01, 02  
0, 1, 3 (Note 1)  
(Note 3) + (Note 4)  
Notes  
1. Contact your local sales office for availability.  
2. Package marking omits leading “S25” and speed, package, and model number form.  
3. A for standard package (non-Pb free); F for Pb-free package.  
4. I for Uniform Sector product; T for Top Boot product; B for Bottom Boot product.  
5.1  
Valid Combinations  
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.  
8
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
6. Spansion SPI Modes  
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:  
„ CPOL = 0, CPHA = 0 (Mode 0)  
„ CPOL = 1, CPHA = 1 (Mode 3)  
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for  
both modes.  
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:  
„ SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)  
„ SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)  
Figure 6.1 Bus Master and Memory Devices on the SPI Bus  
SO  
SPI Interface with  
(CPOL, CPHA) =  
(0, 0) or (1, 1)  
SI  
SCK  
SCK SO SI  
SCK SO SI  
SCK SO SI  
Bus Master  
SPI Memory  
SPI Memory  
SPI Memory  
Device  
Device  
Device  
CS3 CS2 CS1  
CS#  
W# HOLD#  
CS#  
W# HOLD#  
CS#  
W# HOLD#  
Note  
The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.  
Figure 6.2 SPI Modes Supported  
CS#  
CPOL CPHA  
Mode 0  
SCK  
0
0
1
1
Mode 3  
SCK  
SI  
MSB  
SO  
MSB  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
9
D a t a S h e e t ( P r e l i m i n a r y )  
7. Device Operations  
All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time).  
7.1  
Byte or Page Programming  
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program  
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up  
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.  
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1  
requires an erase operation.  
7.2  
7.3  
7.4  
Sector Erase / Bulk Erase  
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array  
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a  
sector-wide (SE) or array-wide (BE) level.  
Monitoring Write Operations Using the Status Register  
The host system can determine when a Write Status Register, program, or erase operation is complete by  
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command  
provides the state of the WIP bit.  
Active Power and Standby Power Modes  
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the  
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status  
Register operations have completed. The device then goes into the Standby Power mode, and power  
consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against  
inadvertent signals. After writing the DP command, the device ignores any further program or erase  
commands, and reduces its power consumption to IDP  
.
7.5  
Status Register  
The Status Register contains the status and control bits that can be read or set by specific commands  
(Table 9.3, S25FL040A Status Register on page 18):  
„ Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or  
erase operation.  
„ Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.  
„ Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected  
against program and erase commands.  
„ Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit  
is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD,  
BP2, BP1, BP0) become read-only bits.  
7.6  
Data Protection Modes  
Spansion SPI Flash memory devices provide the following data protection methods:  
„ The Write Enable (WREN) command: Must be written prior to any command that modifies data. The  
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up  
or after the device completes the following commands:  
– Page Program (PP)  
– Sector Erase (SE)  
– Bulk Erase (BE)  
10  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
– Write Disable (WRDI)  
– Write Status Register (WRSR)  
„ Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the  
memory array that can be read but not programmed or erased. Table 7.1 and Table 7.2 show the sizes and  
address ranges of protected areas that are defined by Status Register bits BP2:BP0.  
„ Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable  
(SRWD) bit together provide write protection.  
„ Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands  
consist of a clock pulse count that is a multiple of eight before executing them.  
Table 7.1 S25FL040A Protected Area Sizes (Top Boot)  
Status Register  
Block Protect Bits  
Memory Array  
Protected  
BP2 BP1 BP0 Address Range  
Protected  
Unprotected  
Unprotected Protected Portion of  
Sectors  
Address Range  
Sectors  
SA12:SA0  
SA11:SA0  
SA10:SA0  
SA6:SA0  
SA5:SA0  
SA3:SA0  
None  
Total Memory Area  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None  
(0) None  
00000–7FFFF  
00000–7BFFF  
00000–77FFF  
00000–6FFFF  
00000–5FFFF  
00000–3FFFF  
None  
None (0)  
7C000–7FFFF  
78000–7FFFF  
70000–7FFFF  
60000–7FFFF  
40000–7FFFF  
00000–7FFFF  
00000–7FFFF  
(1) SA12  
Upper 1/32 (16 KB)  
Upper 1/16 (32 KB)  
Upper 1/8 (64 KB)  
Upper 1/4 (128 KB)  
Upper 1/2 (256 KB)  
All (512 KB)  
(2) SA12:SA11  
(6) SA12:SA7  
(7) SA12:SA6  
(9) SA12:SA4  
(13) SA12:SA0  
(13) SA12:SA0  
None  
None  
All (512 KB)  
Table 7.2 S25FL040A Protected Area Sizes (Bottom Boot)  
Status Register  
Block Protect Bits  
Memory Array  
Protected  
BP2 BP1 BP0 Address Range  
Protected  
Sectors  
Unprotected  
Unprotected Protected Portion of  
Address Range  
Sectors  
SA12:SA0  
SA12:SA1  
SA12:SA2  
SA12:SA4  
SA12:SA5  
SA12:SA7  
None  
Total Memory Area  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None  
(0)  
00000–7FFFF  
04000–7FFFF  
08000–7FFFF  
10000–7FFFF  
20000–7FFFF  
40000–7FFFF  
None  
0
00000–03FFF  
00000–07FFF  
00000–0FFFF  
00000–1FFFF  
00000–3FFFF  
00000–7FFFF  
00000–7FFFF  
(1) SA0  
Lower 1/32 (16 KB)  
Lower 1/16 (32 KB)  
Lower 1/8 (64 KB)  
Lower 1/4 (128 KB)  
Lower 1/2 (256 KB)  
All (512 KB)  
(2) SA1:SA0  
(6) SA5:SA0  
(7) SA6:SA0  
(9) SA8:SA0  
(13) SA12:SA0  
(13) SA12:SA0  
None  
None  
All (512 KB)  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
11  
D a t a S h e e t ( P r e l i m i n a r y )  
Table 7.3 S25FL040A Protected Area Sizes (Uniform Sector)  
Status Register  
Block Protect Bits  
Memory Array  
Protected  
BP2 BP1 BP0 Address Range  
Protected  
Sectors  
Unprotected  
Unprotected Protected Portion of  
Address Range  
Sectors  
SA7:SA0  
SA6:SA0  
SA5:SA0  
SA3:SA0  
None  
Total Memory Area  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None  
(0)  
00000–7FFFF  
00000–6FFFF  
00000–5FFFF  
00000–3FFFF  
None  
0
70000–7FFFF  
60000–7FFFF  
40000–7FFFF  
00000–7FFFF  
00000–7FFFF  
00000–7FFFF  
00000–7FFFF  
(1) SA7  
Upper 1/8 (64 KB)  
Lower 1/4 (128 KB)  
Lower 1/2 (256 KB)  
All (512 KB)  
(2) SA7:SA6  
(4) SA7:SA4  
(8) SA7:SA0  
(8) SA7:SA0  
(8) SA7:SA0  
(8) SA7:SA0  
None  
None  
All (512 KB)  
None  
None  
All (512 KB)  
None  
None  
All (512 KB)  
7.7  
Hold Mode (HOLD#)  
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write  
Status Register, program or erase operation that is currently in progress.  
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, on page 12, standard  
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling  
edge of SCK (non-standard use).  
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge  
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-  
standard use) See Figure 7.1.  
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the  
Hold mode.  
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains  
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the  
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,  
followed by driving CS# low.  
Figure 7.1 Hold Mode Operation  
SCK  
HOLD#  
Hold  
Hold  
Condition  
Condition  
(standard use)  
(non-standard use)  
12  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
8. Sector Address Table  
Table 8.1 shows the size of the memory array, sectors, and pages. The device uses pages to cache the  
program data before the data is programmed into the memory array. Each page or byte can be individually  
programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or  
device-wide basis using the SE or BE commands. Table 8.4 shows the starting and ending address for each  
sector. The complete set of sectors comprises the memory array of the Flash device.  
Table 8.1 S25FL040A Device Organization  
Each Device has  
Each Sector has  
Each Page has  
65,536 (64 KB sector)  
16,384 (16 KB sector)  
12,288 (12 KB sector)  
4,096 (4 KB sector)  
524,288  
256  
bytes  
256 (64 KB sector)  
64 (16 KB sector)  
48 (12 KB sector)  
16 (4 KB sector)  
2,048  
—
—
pages  
12 (boot), 7 (uniform)  
—
sectors  
Table 8.2 Sector Address Table - S25FL040A (Top Boot)  
Sector  
SA12  
SA11  
SA10  
SA9  
Size  
Address Range  
16K Byte  
16K Byte  
4K Byte  
7C000h  
78000h  
77000h  
76000h  
73000h  
70000h  
60000h  
50000h  
40000h  
30000h  
20000h  
10000h  
00000h  
7FFFFh  
7BFFFh  
77FFFh  
76FFFh  
75FFFh  
72FFFh  
6FFFFh  
5FFFFh  
4FFFFh  
3FFFFh  
2FFFFh  
1FFFFh  
0FFFFh  
4K Byte  
SA8  
12K Byte  
12K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
SA7  
SA6  
SA5  
SA4  
SA3  
SA2  
SA1  
SA0  
Table 8.3 Sector Address Table - S25FL040A (Bottom Boot)  
Sector  
SA12  
SA11  
SA10  
SA9  
Size  
Address Range  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
64K Byte  
12K Byte  
12K Byte  
4K Byte  
70000h  
60000h  
50000h  
40000h  
30000h  
20000h  
10000h  
0D000h  
0A000h  
09000h  
08000h  
04000h  
00000h  
7FFFFh  
6FFFFh  
5FFFFh  
4FFFFh  
3FFFFh  
2FFFFh  
1FFFFh  
0FFFFh  
0CFFFh  
09FFFh  
08FFFh  
07FFFh  
03FFFh  
SA8  
SA7  
SA6  
SA5  
SA4  
SA3  
SA2  
4K Byte  
SA1  
16K Byte  
16K Byte  
SA0  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
13  
D a t a S h e e t ( P r e l i m i n a r y )  
Table 8.4 S25FL040A Sector Address Table (Uniform Sectors)  
Sector  
SA7  
SA6  
SA5  
SA4  
SA3  
SA2  
SA1  
SA0  
Address Range  
070000h  
060000h  
050000h  
040000h  
030000h  
020000h  
010000h  
000000h  
07FFFFh  
06FFFFh  
05FFFFh  
04FFFFh  
03FFFFh  
02FFFFh  
01FFFFh  
00FFFFh  
9. Command Definitions  
The host system must shift all commands, addresses, and data in and out of the device, beginning with the  
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte  
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on  
the rising edge of SCK. Table 9.5 on page 24 lists the complete set of commands.  
Every command sequence begins with a one-byte command code. The command may be followed by  
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the  
command sequence has been written.  
The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed  
(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence  
on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.  
The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable  
(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise  
the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high  
when the number of clock pulses after CS# is driven low is an exact multiple of eight.  
The device ignores any attempt to access the memory array during a Write Status Register, program, or  
erase operation, and continues the operation uninterrupted.  
9.1  
Read Data Bytes (READ)  
The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented  
at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving  
CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is  
latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a  
frequency fSCK, on the falling edge of SCK.  
Figure 9.1 and Table 9.5 detail the READ command sequence. The first byte specified can be at any location.  
The device automatically increments to the next higher address after each byte of data is output. The entire  
memory array can therefore be read with a single READ command. When the highest address is reached, the  
address counter reverts to 00000h, allowing the read sequence to continue indefinitely.  
The READ command is terminated by driving CS# high at any time during data output. The device rejects any  
READ command issued while it is executing a program, erase, or Write Status Register operation, and  
continues the operation uninterrupted.  
14  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.1 Read Data Bytes (READ) Command Sequence  
CS#  
SCK  
0
1
2
3
4
5
6
7
8
9 10  
28 29 30 31 32 33 34 35 36 37 38 39  
Mode 3  
Mode 0  
Command  
24-Bit Address  
23 22 21  
2
0
1
3
SI  
MSB  
Data Out 1  
Data Out 2  
Hi-Z  
SO  
6
4
2
7
1 0  
7
5
3
MSB  
9.2  
Read Data Bytes at Higher Speed (FAST_READ)  
The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK  
input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# low. The  
FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each  
bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at  
a frequency fSCK, on the falling edge of SCK.  
The FAST_READ command sequence is shown in Figure 9.2 and Table 9.5. The first byte specified can be at  
any location. The device automatically increments to the next higher address after each byte of data is output.  
The entire memory array can therefore be read with a single FAST_READ command. When the highest  
address is reached, the address counter reverts to 00000h, allowing the read sequence to continue  
indefinitely.  
The FAST_READ command is terminated by driving CS# high at any time during data output. The device  
rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register  
operation, and continues the operation uninterrupted.  
Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence  
CS#  
33  
0
1
2
5
6
7
8
9
29 30  
32  
38 39 40 41  
44 45 46  
42 43  
Mode 3  
31  
34 35 36 37  
3
4
10  
28  
47  
SCK  
Mode 0  
24-Bit Address  
Dummy Byte  
Command  
23  
3
2
22 21  
1
0
6
5
4
2
0
1
7
3
SI  
Hi-Z  
3
7
6
4
2
1
0
5
7
SO  
MSB  
MSB  
DATA OUT 1  
DATA OUT 2  
9.3  
Read Identification (RDID)  
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the  
two-byte device identification, to the host system.  
JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer  
assigns the device identification: the first byte provides the memory type; the second byte indicates the  
memory capacity. See Table 9.1 or Table 9.5 for device ID data.  
The host system must first select the device by driving CS# low. The RDID command is then written to SI,  
and each bit is latched on the rising edge of SCK. The 24-bit device identification data is output from the  
memory array on SO at a frequency fSCK, on the falling edge of SCK.  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
15  
D a t a S h e e t ( P r e l i m i n a r y )  
The RDID command sequence is shown in Figure 9.3 and Table 9.5.  
Driving CS# high after the device identification data has been read at least once terminates the READ_ID  
command. Driving CS# high at any time during data output also terminates the RDID operation.  
The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register  
operation, and continues the operation uninterrupted.  
Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence  
CS#  
1
28  
30  
29  
31  
2
3
4
5
6
18  
17  
Mode 3  
Mode 0  
0
7
14 15 16  
8
9
10 11  
13  
12  
SCK  
SI  
Command  
Manufacturer Identification  
Device Identification  
Hi-Z  
0
1
3
2
14  
13  
SO  
15  
MSB  
Table 9.1 READ_ID Data  
Data  
Bottom  
Boot  
Address  
00000h  
00001h  
Uniform  
01h  
Top Boot  
01h  
Manufacturer Identification  
Device Identification (Memory Capacity)  
01h  
26h  
12h  
25h  
9.4  
Read Identification (Read_ID) [RDID Alternate]  
The READ_ID instruction provides the S25FL040A manufacturer and device information. This command  
should be used as default device identification when multiple versions of SPI Serial Flash devices are used in  
a design.  
The device information can be read from by writing the 8-bit command (90H) follwed by address bits.  
Following the READ_ID instruction, the manufacturer’s ID is located at address 00000H and the device ID  
(Memory Capacity) is located at address 00001H. Once the device is in READ_ID mode, the manufacturer’s  
and device ID output data toggles between address 00000H and 00001H until CE# is driven high.  
16  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.4 READ_ID Command Timing Diagram  
CS#  
SCK  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
Instruction  
24-Bit Address  
SI  
23  
21  
2
22  
3
1
0
MSB  
Manufacture Identification  
Device Identification  
High Impedance  
7
6
5
4
3
2
1
SO  
0
Table 9.2 READ_ID Data-Out Sequence  
Data  
Address  
00000h  
00001h  
Uniform  
01h  
Top Boot  
01h  
Bottom Boot  
Manufacturer Identification  
01h  
26h  
Device Identification (Memory Capacity)  
12h  
25h  
9.5  
Write Enable (WREN)  
The Write Enable (WREN) command (see Figure 9.5) sets the Write Enable Latch (WEL) bit to a 1, which  
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set  
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.  
The host system must first drive CS# low, write the WREN command, and then drive CS# high.  
Figure 9.5 Write Enable (WREN) Command Sequence  
CS#  
6
5
7
0
1
2
3
4
Mode 3  
SCK  
Mode 0  
Command  
SI  
SO  
Hi-Z  
9.6  
Write Disable (WRDI)  
The Write Disable (WRDI) command (see Figure 9.6) resets the Write Enable Latch (WEL) bit to a 0, which  
disables the device from accepting a Write Status Register, program, or erase command. The host system  
must first drive CS# low, write the WRDI command, and then drive CS# high.  
Any of following conditions resets the WEL bit:  
„ Power-up  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
17  
D a t a S h e e t ( P r e l i m i n a r y )  
„ Write Disable (WRDI) command completion  
„ Write Status Register (WRSR) command completion  
„ Page Program (PP) command completion  
„ Sector Erase (SE) command completion  
„ Bulk Erase (BE) command completion  
Figure 9.6 Write Disable (WRDI) Command Sequence  
CS#  
0
3
4
7
6
1 2  
5
Mode 3  
SCK  
SI  
Mode 0  
Command  
Hi-Z  
SO  
9.7  
Read Status Register (RDSR)  
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.3 shows  
the status register bits and their functions.  
The RDSR command may be written at any time, even while a program, erase, or Write Status Register  
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new  
command to the device if an operation is already in progress. Figure 9.7 shows the RDSR command  
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven  
high.  
Table 9.3 S25FL040A Status Register  
Bit  
Status Register Bit  
Bit Function  
Description  
1 = Protects when W# is low  
7
SRWD  
Status Register Write Disable  
0 = No protection, even when W# is low  
6
5
4
3
2
—
—
—
Not used  
Not used  
—
BP2  
BP1  
BP0  
000–111 = Protects upper half of address range in 5 sizes. See  
Table 7.1.  
Block Protect  
1 = Device accepts Write Status Register, program, or erase  
commands  
1
0
WEL  
WIP  
Write Enable Latch  
Write in Progress  
0 = Ignores Write Status Register, program, or erase commands  
1 = Device Busy. A Write Status Register, program, or erase  
operation is in progress  
0 = Ready. Device is in standby mode and can accept commands.  
18  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.7 Read Status Register (RDSR) Command Sequence  
CS#  
SCK  
7
0
2
3
4
5
6
9
11  
12 13 14  
15  
1
8
10  
Mode 3  
Mode 0  
Command  
SI  
Hi-Z  
SO  
6
4
2
6
5
7
5
3
1
0
4
2
7
0
7
3
1
MSB  
MSB  
Status Register Out  
Status Register Out  
The following describes the status and control bits of the Status Register.  
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register,  
program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of  
these operations is in progress; if WIP is 0, no such operation is in progress.  
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status  
Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0,  
the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the  
WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program,  
or erase operation. WEL cannot be directly set by the WRSR command.  
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against  
any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are  
non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see Table 7.1 on  
page 11) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware  
Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if  
all Block Protect (BP2, BP1, BP0) bits are 0.  
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write  
Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected  
mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the  
device ignores any Write Status Register (WRSR) command.  
9.8  
Write Status Register (WRSR)  
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable  
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to  
writing the WRSR command. Table 9.3, S25FL040A Status Register on page 18 shows the status register  
bits and their functions.  
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI  
(Figure 9.8).  
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must  
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always  
read as 0 and have no user significance.  
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit  
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR  
commands once it enters the Hardware Protected Mode (HPM). Table 9.4 shows that W# must be driven low  
and the SRWD bit must be 1 for this to occur.  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
19  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.8 Write Status Register (WRSR) Command Sequence  
CS#  
SCK  
8
9
10  
12 13 14 15  
11  
4
6
7
Mode 3  
0
1
2
3
5
Mode 0  
Command  
Register In  
Status  
7
6
5
4
3
2
1
0
SI  
MSB  
Hi-Z  
SO  
Table 9.4 Protection Modes  
Protected Area  
(See Note)  
Unprotected Area  
(See Note)  
W# Signal  
SRWD Bit  
Mode  
Write Protection of the Status Register  
1
1
0
1
0
0
Status Register is writable (if the WREN  
command has set the WEL bit). The values in  
the SRWD, BP2, BP1 and BP0 bits can be  
changed.  
Software  
Protected  
(SPM)  
Ready to accept Page  
Program and Sector Erase  
commands  
Protected against program  
and erase commands  
Hardware  
Protected  
(HPM)  
Status Register is Hardware write protected.  
The values in the SRWD, BP2, BP1 and BP0  
bits cannot be changed.  
Ready to accept Page  
Program and Sector Erase  
commands  
Protected against program  
and erase commands  
0
1
Note  
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 11.  
Table 9.4 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM  
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.  
However, the device disables HPM only when W# is driven high.  
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in  
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no  
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).  
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status  
Register) can be used.  
9.9  
Page Program (PP)  
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN  
command is required prior to writing the PP command.  
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one  
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence  
is shown in Figure 9.9 and Table 9.5.  
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this  
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256  
bytes sent at the starting address of the specified page. This may result in data being programmed into  
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they  
are correctly programmed at the requested addresses.  
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the  
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The  
device internally controls the timing of the operation, which requires a period of tPP. The Status Register may  
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP  
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the  
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).  
The device does not execute a Page Program (PP) command that specifies a page that is protected by the  
Block Protect bits (BP2:BP0) (see Table 7.1 on page 11).  
20  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.9 Page Program (PP) Command Sequence  
CS#  
SCK  
5
8
34  
37 38 39  
35 36  
0
2
4
6
7
10  
28 32 33  
29 30 31  
1
3
9
Mode 3  
Mode 0  
24-Bit Address  
22 21  
Data Byte 1  
Command  
4
3
2
3
2
1
0
7
6
5
1
0
23  
MSB  
SI  
MSB  
CS#  
SCK  
53 54 55  
52  
49 50 51  
46  
44 45  
40  
47 48  
41 42 43  
Data Byte 2  
Data Byte 3  
Data Byte 256  
0
7
6
0
1
7
MSB  
7
6
5
4
3
2
1
0
6
5
4
3
2
1
5
4
3
2
SI  
MSB  
MSB  
9.10 Sector Erase (SE)  
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN  
command is required prior to writing the PP command.  
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any  
address within the sector (see Table 7.1 on page 11) is a valid address for the SE command. CS# must be  
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.10 and  
Table 9.5.  
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise  
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The  
device internally controls the timing of the operation, which requires a period of tSE. The Status Register may  
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP  
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the  
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).  
The device does not execute an SE command that specifies a sector that is protected by the Block Protect  
bits (BP2:BP0) (see Table 7.1 on page 11).  
Figure 9.10 Sector Erase (SE) Command Sequence  
CS#  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
Mode 3  
SCK  
Mode 0  
Command  
24-bit Address  
1
SI  
23 22 21  
MSB  
3
2
0
Hi-Z  
SO  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
21  
D a t a S h e e t ( P r e l i m i n a r y )  
9.11 Bulk Erase (BE)  
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command  
is required prior to writing the PP command.  
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the  
entire duration of the BE sequence. The command sequence is shown in Figure 9.11 and Table 9.5.  
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise  
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The  
device internally controls the timing of the operation, which requires a period of tBE. The Status Register may  
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP  
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the  
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).  
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1 on page 11).  
Otherwise, the device ignores the command.  
Figure 9.11 Bulk Erase (BE) Command Sequence  
CS#  
Mode 3  
0
1
2
3
4
5
6
7
SCK  
Mode 0  
Command  
SI  
Hi-Z  
SO  
9.12 Deep Power Down (DP)  
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is  
intended for periods when the device is not in active use, and ignores all commands except for the Release  
from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection  
against unintended write operations. The standard standby mode, which the device goes into automatically  
when CS# is high (and all operations in progress are complete), should generally be used for the lowest  
power consumption when the quickest return to device activity is required.  
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the  
entire duration of the DP sequence. The command sequence is shown in Figure 9.12 and Table 9.5.  
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise  
the device does not execute the command. After a delay of tDP, the device enters the DP mode and current  
reduces from ISB to IDP (see Table 14.1 on page 26).  
Once the device has entered the DP mode, all commands are ignored except the RES command (which  
releases the device from the DP mode). The RES command also provides the Electronic Signature of the  
device to be output on SO, if desired (see sections 9.13 and 9.13.1).  
DP mode automatically terminates when power is removed, and the device always powers up in the standard  
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write  
Status Register operation, and continues the operation uninterrupted.  
22  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.12 Deep Power Down (DP) Command Sequence  
CS#  
SCK  
t
DP  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
Command  
SI  
Hi-Z  
SO  
Standby Mode  
Deep Power-down Mode  
9.13 Release from Deep Power Down (RES)  
The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down  
mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.  
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire  
duration of the sequence. The command sequence is shown in Figure 9.13 and Table 9.5.  
The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions  
from DP mode to the standby mode after a delay of tRES (see Table 16.1 on page 27). In the standby mode,  
the device can execute any read or write command.  
Figure 9.13 Release from Deep Power Down (RES) Command Sequence  
CS#  
7
0
2
3
5
1
4
6
Mode 3  
SCK  
Mode 0  
tRES  
Command  
SI  
Hi-Z  
SO  
Deep Power-down Mode  
Standby Mode  
9.13.1  
Release from Deep Power Down and Read Electronic Signature (RES)  
The device features an 8-bit Electronic Signature, which can be read using the RES command. See  
Figure 9.14 and Table 9.5 for the command sequence and signature value. The Electronic Signature is not to  
be confused with the identification data obtained using the RDID command. The device offers the Electronic  
Signature so that it can be used with previous devices that offered it; however, the Electronic Signature  
should not be used for new designs, which should read the RDID data instead.  
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each  
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is  
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the  
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to  
output the Electronic Signature repeatedly.  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
23  
D a t a S h e e t ( P r e l i m i n a r y )  
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as  
previously described. The RES command always provides access to the Electronic Signature of the device  
and can be applied even if DP mode has not been entered.  
Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the  
operation continues uninterrupted.  
Figure 9.14 Release from Deep Power Down and  
Read Electronic Signature (RES) Command Sequence  
CS#  
SCK  
2
28 29 30  
31 32 33 34  
1
8
36 37  
9
35  
38  
0
3
4
5
6
7
10  
t
RES  
3 Dummy Bytes  
Command  
SI  
3
1
0
2
23 22  
MSB  
21  
Hi-Z  
7
6
5
4
3
2
1
SO  
0
MSB  
Electronic ID out  
Standby Mode  
Deep Power-down Mode  
Table 9.5 Command Definitions  
One-Byte  
Address  
Bytes  
Dummy  
Byte  
Operation  
Command  
READ  
Description  
Command Code  
03H (0000 0011)  
0BH (0000 1011)  
9FH (1001 1111)  
Data Bytes  
Read Data Bytes  
3
3
0
0
1
0
1 to ∞  
1 to ∞  
1 to 3  
FAST_READ  
RDID  
Read Data Bytes at Higher Speed  
Read Identification (Note 1)  
Read  
Read Manufacture and  
Device Identification (Note 1)  
READ_ID  
90H (1001 0000)  
3
0
1 to ∞  
WREN  
WRDI  
SE  
Write Enable  
06H (0000 0110)  
04H (0000 0100)  
D8H (1101 1000)  
C7H (1100 0111)  
02H (0000 0010)  
05H (0000 0101)  
01H (0000 0001)  
B9H (1011 1001)  
ABH (1010 1011)  
0
0
3
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write Control  
Write Disable  
0
Sector Erase  
0
Erase  
Program  
BE  
Bulk (Chip) Erase  
Page Program  
0
PP  
1 to 256  
RDSR  
WRSR  
DP  
Read from Status Register  
Write to Status Register  
Deep Power Down  
Release from Deep Power Down  
1 to ∞  
Status Register  
1
0
0
Power Saving  
RES  
Release from Deep Power Down and  
Read Electronic Signature (Note 2)  
ABH (1010 1011)  
0
3
1 to ∞  
Notes  
1. The S25FL040A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (12h for uniform sector, 25h for  
top boot, 26h for bottom boot).  
2. The S25FL040A has an Electronic Signature ID of 12h.  
10. Power-up and Power-down  
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied  
on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows  
(see Figure 10.1 and Table 10.1):  
„ At power-up, VCC (min) plus a period of tPU  
„ At power-down, VSS  
24  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.  
No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC  
min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the  
WEL bit is reset (0).  
Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the  
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed.  
When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all  
operations are disabled and the device does not respond to any commands. Note that data corruption may  
result if a power-down occurs while a Write Register, program, or erase operation is in progress.  
Figure 10.1 Power-Up Timing Diagram  
Vcc  
(max)  
cc  
V
(min)  
cc  
V
tPU  
Full Device Access  
Time  
Table 10.1 Power-Up Timing Characteristics  
Symbol  
Parameter  
Min  
2.7  
10  
Max  
Unit  
V
V
V
(minimum)  
CC(min)  
CC  
t
V
(min) to device operation  
CC  
ms  
PU  
11. Initial Delivery State  
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status  
Register contains 00h (all Status Register bits are 0).  
12. Absolute Maximum Ratings  
Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device  
may result. These are stress ratings only and device operation at these or any other conditions beyond those  
indicated in this section and in the Operating Ranges section of this document is not implied. Device  
operation for extended periods at the limits listed in this section may affect device reliability.  
Table 12.1 Absolute Maximum Ratings  
Description  
Ambient Storage Temperature  
Voltage with Respect to Ground: All Inputs and I/Os  
Rating  
–65°C to +150°C  
–0.3 V to 4.5 V  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
25  
D a t a S h e e t ( P r e l i m i n a r y )  
13. Operating Ranges  
Table 13.1 Operating Ranges  
Description  
Commerical  
Industrial  
Rating  
Ambient Operating Temperature (T )  
0°C to +70°C  
–40°C to +85°C  
2.7 V to 3.6 V  
A
Positive Power Supply  
Voltage Range  
Note  
Operating ranges define those limits between which functionality of the device is guaranteed.  
14. DC Characteristics  
This section summarizes the DC Characteristics of the device. Designers should check that the operating  
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 15.1  
on page 27, when relying on the quoted parameters.  
Table 14.1 DC Characteristics (CMOS Compatible)  
Parameter  
Description  
Test Conditions (See Note)  
Min  
Typ.  
Max  
Unit  
VCC  
Supply Voltage  
2.7  
3
3.6  
V
SCK = 0.1 VCC/0.9VCC  
33 MHz  
9
mA  
mA  
ICC1  
Active Read Current  
VCC = 3.0V,  
50 MHz  
SCK = 0.1 VCC/0.9VCC  
13  
ICC2  
ICC3  
ICC4  
ICC5  
Active Page Program Current  
Active WRSR Current  
CS# = VCC  
CS# = VCC  
CS# = VCC  
CS# = VCC  
13.5  
22  
24  
24  
24  
mA  
mA  
mA  
mA  
Active Sector Erase Current  
Active Bulk Erase Current  
V
CC = 3.0 V  
ISB  
IDP  
Standby Current  
20  
50  
5
µA  
µA  
CS# = VCC  
VCC = 3.0 V  
Deep Power Down Current  
1.5  
CS# = VCC  
ILI  
ILO  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
VIN = GND to VCC  
VIN = GND to VCC  
1
1
µA  
µA  
V
VIL  
–0.3  
0.3 VCC  
VCC + 0.5  
0.4  
VIH  
VOL  
VOH  
Input High Voltage  
0.7 VCC  
V
Output Low Voltage  
Output High Voltage  
IOL = 1.6 mA, VCC = VCC min  
IOH = –0.1 mA  
V
VCC – 0.2  
V
Note  
Typical values are at T = 25°C and 3.0 V.  
A
15. Test Conditions  
Figure 15.1 AC Measurements I/O Waveform  
0.8 VCC  
Input Levels  
0.2 VCC  
0.7 VCC  
0.5 VCC  
0.3 VCC  
Input and Output  
26  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Table 15.1 Test Specifications  
Symbol  
Parameter  
Min  
Max  
Unit  
pF  
ns  
V
C
Load Capacitance  
30  
L
Input Rise and Fall Times  
Input Pulse Voltage  
5
0.2 V to 0.8 V  
CC  
CC  
CC  
Input Timing Reference Voltage  
Output Timing Reference Voltage  
0.3 V to 0.7 V  
V
CC  
0.5 V  
V
CC  
16. AC Characteristics  
Table 16.1 AC Characteristics  
Typ  
(Notes)  
Max  
(Notes)  
Symbol  
(Notes)  
Parameter  
SCK Clock Frequency READ command  
Min  
Unit  
F
D.C.  
25  
MHz  
SCK  
SCK  
CRT  
SCK Clock Frequency for:  
FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR  
F
D.C.  
50  
MHz  
t
Clock Rise Time (Slew Rate)  
Clock Fall Time (Slew Rate)  
SCK High Time  
0.1  
0.1  
9
V/ns  
V/ns  
ns  
t
CFT  
t
WH  
t
SCK Low Time  
9
ns  
WL  
t
CS# High Time  
100  
5
ns  
CS  
t
(3)  
(3)  
(3)  
(3)  
CS# Setup Time  
ns  
CSS  
CSH  
t
CS# HOLD Time  
5
ns  
t
t
HOLD# Setup Time (relative to SCK)  
HOLD# Hold Time (relative to SCK)  
HOLD# Setup Time (relative to SCK)  
HOLD# Hold Time (relative to SCK)  
Output Valid  
5
ns  
HD  
CD  
5
ns  
t
t
5
ns  
HC  
CH  
5
ns  
t
10  
10  
ns  
V
t
Output Hold Time  
0
5
5
ns  
HO  
t
Data in Hold Time  
ns  
HD:DAT  
t
Data in Setup Time  
ns  
SU:DAT  
t
Input Rise Time  
5
ns  
R
t
Input Fall Time  
5
ns  
F
t
(3)  
HOLD# to Output Low Z  
HOLD# to Output High Z  
Output Disable Time  
10  
10  
10  
ns  
LZ  
t
(3)  
(3)  
ns  
HZ  
t
ns  
DIS  
t
(3)  
(3)  
Write Protect Setup Time  
Write Protect Hold Time  
Write Status Register Time  
CS# High to Deep Power Down Mode  
Release DP Mode  
15  
15  
ns  
WPS  
WPH  
t
ns  
t
67  
150  
3
ms  
μs  
μs  
ms  
sec  
sec  
W
t
DP  
t
30  
RES  
t
t
t
Page Programming Time  
Sector Erase Time  
1.5 (1)  
0.5 (1)  
3 (1)  
3 (2)  
3 (2)  
24 (2)  
PP  
SE  
BE  
Bulk Erase Time  
Notes  
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V; 10,000 cycles; checkerboard data pattern  
CC  
2. Under worst-case conditions of 90°C; V = 2.7V; 100,000 cycles  
CC  
3. Not 100% tested  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
27  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 16.1 SPI Mode 0 (0,0) Input Timing  
tCS  
CS#  
SCK  
SI  
tCSH  
tCSS  
tCSS  
tCSH  
tSU:DAT  
tCRT  
tHD:DAT  
tCFT  
MSB IN  
LSB IN  
Hi-Z  
SO  
Figure 16.2 SPI Mode 0 (0,0) Output Timing  
CS#  
tWH  
SCK  
tV  
tWL  
tDIS  
tV  
tHO  
tHO  
SO  
LSB OUT  
28  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
Figure 16.3 HOLD# Timing  
CS#  
tHC  
tHD  
tCH  
SCK  
SO  
tCD  
tHZ  
tLZ  
SI  
HOLD#  
Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1  
W#  
tWPS  
tWPH  
CS#  
SCK  
SI  
Hi-Z  
SO  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
29  
D a t a S h e e t ( P r e l i m i n a r y )  
17. Physical Dimensions  
17.1 SOA 008—Narrow 8-pin Plastic Small Outline 150 mils Body Width Package  
3
4
0.20  
C
A-B  
D
H
D
A
5
SEE  
DETAIL B  
WITH  
PLATING  
b1  
9
c
c1  
3
4
E
E1  
(b)  
BASE  
E1/2  
7
E/2  
METAL  
SECTION A-A  
0.33  
D
C
e
b
q2  
0.07 R MIN.  
0.25  
M
C
A-B  
B
5
H
0.10  
C
GAUGE  
PLANE  
A
0.10  
C
A2  
A
SEATING  
PLANE  
SEATING PLANE  
A
q1  
C
L2  
A1  
C
L
q
L1  
DETAIL B  
NOTES:  
1.  
2.  
3.  
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.  
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.  
DIMENSION D DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm  
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1  
DIMENSIONS ARE DETERMINED AT DATUM H.  
.
4.  
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE  
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE  
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF  
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD  
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
5.  
6.  
DATUMS A AND B TO BE DETERMINED AT DATUM H.  
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR  
THE SPECIFIED PACKAGE LENGTH.  
7.  
8.  
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD  
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.  
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL  
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL  
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OF THE LEAD FOOT.  
9.  
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,  
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX  
AREA INDICATED.  
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED  
FROM THE SEATING PLANE.  
3432 \ 16-038.03 \ 10.28.04  
30  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
17.2 SOC 008—Wide 8-pin Plastic Small Outline 208 mils Body Width Package  
3
4
0.20  
C
A-B  
D
H
D
A
5
SEE  
DETAIL B  
WITH  
PLATING  
b1  
9
c
c1  
3
4
E
E1  
(b)  
BASE  
E1/2  
7
E/2  
METAL  
SECTION A-A  
0.33  
D
C
e
b
q2  
0.07 R MIN.  
0.25  
M
C
A-B  
B
5
H
0.10  
C
GAUGE  
PLANE  
A
0.10  
C
A2  
A
SEATING  
PLANE  
SEATING PLANE  
A
q1  
C
L2  
A1  
C
L
q
L1  
DETAIL B  
NOTES:  
1.  
2.  
3.  
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.  
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.  
PACKAGE SOC 008 (inches)  
JEDEC  
SOC 008 (mm)  
DIMENSION D DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm  
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1  
DIMENSIONS ARE DETERMINED AT DATUM H.  
SYMBOL  
MIN  
MAX  
0.085  
0.0098  
0.075  
0.019  
0.018  
MIN  
MAX  
2.159  
0.249  
1.91  
A
A1  
A2  
b
0.069  
0.002  
0.067  
0.014  
0.013  
1.753  
0.051  
1.70  
.
0.356  
0.330  
0.191  
0.152  
0.483  
0.457  
0.241  
0.203  
4.  
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE  
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE  
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF  
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD  
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
b1  
c
0.0075 0.0095  
0.006 0.008  
0.208 BSC  
c1  
D
5.283 BSC  
5.  
6.  
DATUMS A AND B TO BE DETERMINED AT DATUM H.  
E
0.315 BSC  
0.208 BSC  
.050 BSC  
8.001 BSC  
5.283 BSC  
1.27 BSC  
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR  
THE SPECIFIED PACKAGE LENGTH.  
E1  
e
7.  
8.  
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD  
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.  
L
0.020  
0.030  
0.508  
0.762  
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL  
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL  
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OF THE LEAD FOOT.  
L1  
L2  
N
.055 REF  
1.40 REF  
0.25 BSC  
8
.010 BSC  
8
θ
0˚  
5˚  
8˚  
15˚  
0˚  
0˚  
5˚  
8˚  
9.  
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,  
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX  
AREA INDICATED.  
θ1  
θ2  
15˚  
0˚  
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED  
FROM THE SEATING PLANE.  
3432 \ 16-038.03 \ 10.28.04  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
31  
D a t a S h e e t ( P r e l i m i n a r y )  
17.3 USON 8L (5 x 6 mm) No-Lead Package  
NOTES:  
QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC  
DIMENSIONS  
1. DIMENSIONING AND TOLERANCING CONFORMS TO  
ASME Y14.5M-1994.  
SYMBOL  
MIN  
NOM  
1.27 BSC  
8
MAX  
NOTE  
2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.  
3. N IS THE TOTAL NUMBER OF TERMINALS.  
e
N
3
5
4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS  
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.  
IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER  
END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE  
MEASURED IN THAT RADIUS AREA.  
ND  
L
4
0.55  
0.35  
3.90  
3.30  
0.60  
0.65  
0.45  
4.10  
3.50  
b
0.40  
4
D2  
E2  
D
4.00  
5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.  
6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.  
3.40  
5.00 BSC  
6.00 BSC  
0.50  
7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.  
8. PIN #1 ID ON TOP WILL BE LASER MARKED.  
E
A
0.45  
0.00  
0.55  
0.05  
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED  
HEAT SINK SLUG AS WELL AS THE TERMINALS.  
A1  
K
0.02  
0.20 MAX.  
---  
θ
0
12  
2
3448\ 16-038.28 \ 04.15.05  
32  
S25FL040A  
S25FL040A_00_B0 August 31, 2006  
D a t a S h e e t ( P r e l i m i n a r y )  
18. Revision History  
Section  
Revision A (January 26, 2006)  
Global  
Description  
Initial release.  
Revision A4 (June 29, 2006)  
DC Characteristics  
Added typical specification and changed maximum specification for ICC2  
.
Revision B0 (August 31, 2006)  
Global  
Rewrote entire document for better flow and clarity. No specifications were changed.  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without  
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as  
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to  
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal  
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,  
the prior authorization by the respective government entity will be required for export of those products.  
Trademarks and Notice  
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under  
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this  
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,  
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any  
damages of any kind arising out of the use of the information in this document.  
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are  
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
33