ASDL-3212-021--Datasheet/数据表在线中文翻译

ASDL-3212

IrDA Data Compliant Low Power ꢀ.ꢀ52 Mbit/s Infrared Transceiver

Data Sheet

Description

General Features

TheꢀASDL-3212ꢀisꢀaꢀnewꢀgenerationꢀultraꢀsmallꢀlowꢀcostꢀ •ꢀ Operatingꢀtemperatureꢀfromꢀ-25°Cꢀ~ꢀ85°C

infraredꢀtransceiverꢀmoduleꢀwhichꢀisꢀcomplianceꢀtoꢀIrDAꢀ

Physicalꢀ Layersꢀ speciﬁcationsꢀ versionꢀ 1.4ꢀ lowꢀ powerꢀ

fromꢀ9.6Kbits/sꢀtoꢀ1.152Mbit/sꢀ(MIR)ꢀwithꢀextendedꢀlinkꢀ

distance.ꢀ Itꢀ isꢀ IEC825-Classꢀ 1ꢀ eyeꢀ safeꢀ andꢀ designedꢀ forꢀ

veryꢀ lowꢀ powerꢀ consumptionꢀ whichꢀ isꢀ idealꢀ forꢀ batteryꢀ

operatedꢀ handheldꢀ devices.ꢀ ASDL-3212ꢀ featuresꢀ lowerꢀ

pinꢀcountꢀthroughꢀintegratedꢀinput-outputꢀfunctionꢀforꢀ

interfacingꢀwithꢀlowꢀvoltageꢀ1.5V

-ꢀ Criticalꢀparametersꢀareꢀguaranteedꢀoverꢀ

temperatureꢀandꢀsupplyꢀvoltage

•ꢀ VccꢀSupplyꢀ2.4ꢀtoꢀ3.6ꢀVꢀ

•ꢀ InterfaceꢀtoꢀVariousꢀSuperꢀI/OꢀandꢀControllerꢀDevices

ꢀ-ꢀSupportꢀIntegratedꢀInput/OutputꢀInterfaceꢀVoltageꢀ

ofꢀ1.5ꢀV

•ꢀ MiniatureꢀPackageꢀ

-ꢀ Heightꢀ:ꢀ1.64ꢀmm

Applications

-ꢀ Widthꢀ:ꢀ7.00mm

•ꢀ Mobileꢀdataꢀcommunicationꢀ

-ꢀ MobileꢀPhones

-ꢀ Depthꢀ:ꢀ2.73mm

•ꢀ MoistureꢀLevelꢀ3

-ꢀ PDAs

•ꢀ NoꢀProgrammingꢀrequired

•ꢀ LEDꢀStuck-HighꢀProtection

•ꢀ HighꢀEMIꢀPerformance

-ꢀ DigitalꢀStillꢀCameras

-ꢀ Printer

-ꢀ HandyꢀTerminals

-ꢀ IndustrialꢀandꢀMedicalꢀInstrument

•ꢀ DesignedꢀtoꢀAccommodateꢀLightꢀLossꢀwithꢀCosmeticꢀ

Windows

•ꢀ IECꢀ825-Classꢀ1ꢀEyeꢀSafe

Application Support Information

TheꢀApplicationꢀEngineeringꢀGroupꢀisꢀavailableꢀtoꢀassistꢀ

youꢀ withꢀ theꢀ applicationꢀ designꢀ associatedꢀ withꢀ ASDL-

3212ꢀinfraredꢀtransceiverꢀmodule.ꢀYouꢀcanꢀcontactꢀthemꢀ

throughꢀ yourꢀ localꢀ salesꢀ representativesꢀ forꢀ additionalꢀ

details.

IrDA Features

•ꢀ FullyꢀCompliantꢀtoꢀIrDAꢀ1.4ꢀPhysicalꢀLayerꢀLowꢀPowerꢀ

Speciﬁcationsꢀfromꢀ9.6ꢀkbit/sꢀtoꢀꢀ1.15ꢀMbit/sꢀ

ꢀ-ꢀTypicalꢀLinkꢀDistanceꢀ>ꢀ50cm

•ꢀ Completeꢀshutdownꢀ

•ꢀ LowꢀPowerꢀConsumption

-ꢀ Lowꢀshutdownꢀcurrentꢀ

-ꢀ Lowꢀidleꢀcurrent

ꢀ

Order Information

Part Number

Packaging Type

Package

Quantity

ASDL-32ꢀ2-02ꢀ

Tape and Reel

Front Option

2500

Marking Information

Theꢀunitꢀisꢀmarkedꢀwithꢀ‘.PYWWLL’

ꢀ

Pꢀ

Yꢀ

=ꢀProductꢀcode

=ꢀ1ꢀdigitꢀnumericꢀcodeꢀforꢀyear

WWꢀ =ꢀ2ꢀdigitsꢀnumericꢀcodeꢀforꢀworkꢀweek

LLꢀ =ꢀ2ꢀdigitsꢀhexadecimalꢀcodeꢀforꢀlotꢀinformation

Vcc

CX2

CX1

GnD

5

6

PD

Low

Pass

Filter

RXD

3

Ambient DC Cancellation

Regulated

Voltage

Supply

VLED

SD

4

AGC

LEDA

R1

1

2

CX3

Stuck One

Protection

TXD

ASDL-3212 Transceiver Module

Figure 1. Functional Block Diagram

2

Recommended Application Circuit Components

Recommended Value

Note

Rꢀ

2.7Ω 5ꢁ,0.25 watt for 2.4 ≤ VLED < 2.6

3.3Ω 5ꢁ,0.25 watt for 2.6 ≤ VLED < 2.8

3.9Ω 5ꢁ,0.25 watt for 2.8 ≤ VLED < 3.0

4.7Ω 5ꢁ,0.25 watt for 3.0 ≤ VLED < 3.3

5.6Ω 5ꢁ,0.25 watt for 3.3 ≤ VLED < 3.5

6.8Ω 5ꢁ,0.25 watt for 3.5 ≤ VLED < 3.8

8.2Ω 5ꢁ,0.25 watt for 3.8 ≤ VLED < 4.2

ꢀ0Ω 5ꢁ,0.25 watt for 4.2 ≤ VLED < 4.7

ꢀ2Ω 5ꢁ,0.25 watt for 4.7 ≤ VLED < 5.0

ꢀ00 nF, 20ꢁ, X7R Ceramic

CX2

7

CXꢀ, CX3

6.8 mF, 20ꢁ, Tantalum

Note:

7.ꢀ CX1ꢀ &ꢀ CX2ꢀ mustꢀ beꢀ placedꢀ withinꢀ 0.7cmꢀ ofꢀ ASDL-3212ꢀ toꢀ obtainꢀ

optimumꢀnoiseꢀimmunity

I/O Pins Conﬁguration Table

ꢀ

Symbol

LEDA

TxD

Description

I/O Type

Notes

Note ꢀ

Note 2

Note 3

Note 4

Note 5

Note 6

Rear View

LED Anode

2

IrDA transmitter data input.

IrDA receive data

Shutdown

Input, Active High

Output, Active Low

Input, Active High

3

RxD

4

SD

6

5

4

3

2

1

5

Vcc

Supply Voltage

Ground

Figure 2. Pin out

6

GND

Note:

1.ꢀ Tiedꢀthroughꢀexternalꢀresistor,ꢀR1,ꢀtoꢀVled.ꢀReferꢀtoꢀtheꢀtableꢀbelowꢀforꢀrecommendedꢀseriesꢀresistorꢀvalue.

2.ꢀ ThisꢀpinꢀisꢀusedꢀtoꢀtransmitꢀserialꢀdataꢀwhenꢀSDꢀpinꢀisꢀlow.ꢀIfꢀheldꢀhighꢀforꢀlongerꢀthanꢀ50ꢀms,ꢀtheꢀLEDꢀisꢀturnedꢀoﬀ.ꢀDoꢀNOTꢀﬂoatꢀthisꢀpin.

3.ꢀ ThisꢀpinꢀisꢀcapableꢀofꢀdrivingꢀaꢀstandardꢀCMOSꢀorꢀTTLꢀload.ꢀNoꢀexternalꢀpull-upꢀorꢀpull-downꢀresistorꢀisꢀrequired.ꢀTheꢀpinꢀisꢀinꢀtri-stateꢀwhenꢀtheꢀ

transceiverꢀisꢀinꢀshutdownꢀmode

4.ꢀ CompleteꢀshutdownꢀofꢀICꢀandꢀPINꢀdiode.ꢀDoꢀNOTꢀﬂoatꢀthisꢀpin.ꢀ

5.ꢀ Regulated,ꢀ2.4Vꢀtoꢀ3.6V

6.ꢀ Connectꢀtoꢀsystemꢀground.

CAUTION: The BiCMOS inherent to the design of this component increases the component’s susceptibility to

damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling

and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

3

Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

+ꢀ00

+85

6

Units

°C

Conditions

Ref

Storage Temperature

Junction Temperature

Operating Temperature

LED Anode Voltage

Supply Voltage

T

S

-40

T

J

°C

T

A

-25

0

°C

V

LEDA

V

0

6

V

CC

Input Voltage : TXD, SD/Mode

Output Voltage : RXD

Peak LED Current

0

6

V

I

0

6

V

O

I

300

60

mA

≤ 20ꢁ duty cycle, ≤ 2ꢀ7ns pulse width

Fig. 5

Fig. 6

LED (PK)

LED (DC)

DC LED Current

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

+85

3.6

Units

Conditions

Operating Temperature

Supply Voltage

T

A

-25

2.4

°C

V

CC

V

IH

V

IL

V

Logic Input Voltage for TXD, SD/Mode

ꢀ.3

ꢀ.8

V

0

0.5

V

2

[8]

Receiver Input Irradiance

Logic High EI

0.0090

500

mW/cm

For in-band signals≤ ꢀꢀ5.2kbit/s

H

0.576 Mbit/s ≤ in-band signals ≤ꢀ.ꢀ52

[8]

0.0225

0.0096

500

0.3

Mbit/s

2

[8]

Logic Low

EI

L

mW/cm

For in-band signals

LED (Logic High) Current Pulse

Amplitude

I

250

mA

V

I

= 3.0V, R = 4.7W,

LEDA

LED LED

V (TxD) ≥V

IH

Receiver Data Rate

Ambient Light

ꢀ.ꢀ52

Mbit/s

See IrDA Serial Infrared Physical Layer

Link Speciﬁcation, Appendix A for

ambient levels

Noteꢀ :ꢀ [8]ꢀ Anꢀ in-bandꢀ opticalꢀ signalꢀ isꢀ aꢀ pulse/sequenceꢀ whereꢀ theꢀ peakꢀ wavelength,ꢀ lp,ꢀ isꢀ deﬁnedꢀ asꢀ 850ꢀ ≤ꢀ mpꢀ ≤ꢀ 900ꢀ nm,ꢀ andꢀ theꢀ pulseꢀ

characteristicsꢀareꢀcompliantꢀwithꢀtheꢀIrDAꢀSerialꢀInfraredꢀPhysicalꢀLayerꢀLinkꢀSpeciﬁcationꢀv1.4.

4

Electrical and Optical Speciﬁcations

Speciﬁcationsꢀ(Min.ꢀ&ꢀMax.ꢀvalues)ꢀholdꢀoverꢀtheꢀrecommendedꢀoperatingꢀconditionsꢀunlessꢀotherwiseꢀnoted.ꢀUnspeci-

ﬁedꢀtestꢀconditionsꢀmayꢀbeꢀanywhereꢀinꢀtheirꢀoperatingꢀrange.ꢀAllꢀtypicalꢀvaluesꢀ(Typ.)ꢀareꢀatꢀ25°CꢀandꢀVccꢀsetꢀtoꢀ3.0Vꢀ

unlessꢀotherwiseꢀnoted.

Receiver

Parameter

Symbol

2q

Min.

Typ.

Max.

Units

°

Conditions

Viewing Angle

30

ꢀ/2

Peak Sensitivity Wavelength

RxD_IrDA Output Voltage

l

875

nm

V

P

Logic High

Logic Low

V

OH

ꢀ.3

0

ꢀ.8

0.4

I = -ꢀ00 mA, EI ≤ 0.3 mW/cm2

OH

V

OL

V

[9, ꢀ0]

RxD_IrDA Pulse Width (SIR)

RxD_IrDA Pulse Width (MIR)

RxD_IrDA Rise & Fall Times

t

ꢀ.5

250

60

ms

ns

q

≤ ꢀ5°, C =9pF, EI = ꢀ0 mW/cm2

L

RPW(SIR)

RPW(MIR)

ꢀ/2

[9, ꢀꢀ]

≤ ꢀ5°, C =9pF, EI = ꢀ0 mW/cm2

L

t , t

r f

ns

CL=9pF

[ꢀ2]

Receiver Latency Time

t

ꢀ20

200

ms

EI = 9.0 mW/cm2

EI = ꢀ0 mW/cm2

L

[ꢀ3]

Receiver Wake Up Time

RW

Infrared (IR) Transmitter

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

IR Radiant Intensity

I

EH

9

80

mW/sr

I

= 250mA,

LEDA

q

ꢀ/2

≤ ꢀ5°, VI (TxD) ≤ VIH,

IR Viewing Angle

2q

ꢀ/2

30

60

°

IR Peak Wavelength

TxD_IrDA Logic Levels

l

870

nm

V

P

High

Low

High

Low

V

ꢀ.3

0

ꢀ.8

0.5

ꢀ0

IH

IL

V

TxD_IrDA Input Current

I

mA

ns

ms

ns

V ≥V

I IH

H

ꢀ0

0 ≤ V ≤ V

I IL

L

[ꢀ4]

Wake Up Time

t

200

70

TW

[ꢀ5]

Maximum Optical Pulse Width

TXD Pulse Width (SIR)

PW(Max)

PW(SIR)

PW(MIR)

ꢀ.6

2ꢀ7

t

=ꢀ.6ms at ꢀꢀ5.2 kbit/s

PW (TXD)

TXD Pulse Width (MIR)

=2ꢀ7ns at ꢀ.ꢀ52 Mbit/s

PW (TXD)

TxD Rise & Fall Times (Optical)

t , t

r f

600

40

ns

t

=ꢀ.6ms at ꢀꢀ5.2 kbit/s

=2ꢀ7ns at ꢀ.ꢀ5 Mbit/s

PW(TXD)

IR LED Anode On-State Voltage

V

2.0

V

I

= 250mA,

ON (LEDA)

LEDA

V

I(TxD)

≥V

IH

Transceiver

Parameters

Symbol Min.

Typ.

Max.

Units

mA

Conditions

V ≥V

Input Current

High

I

ꢀ

H

I

IH

Low

ꢀ

mA

0 ≤ V ≤ V

I IL

L

Supply Current

Shutdown

ꢀ

mA

V

> V -ꢀ.3, T =25°C, no DC ambient

CCꢀ

CC5

SD

CC

A

Idle (Standby)

445

570

mA

≤ V

I(TxD)

IL, EI=0

5

Note:

[9]ꢀAnꢀin-bandꢀopticalꢀsignalꢀisꢀaꢀpulse/sequenceꢀwhereꢀtheꢀpeakꢀwavelength,ꢀl ,ꢀisꢀdeﬁnedꢀasꢀ850ꢀnmꢀ≤ꢀl ꢀ≤ꢀ900ꢀnm,ꢀandꢀtheꢀpulseꢀcharacteristicsꢀ

P

areꢀcompliantꢀwithꢀtheꢀIrDAꢀSerialꢀInfraredꢀPhysicalꢀLayerꢀLinkꢀSpeciﬁcationꢀversionꢀ1.4.

[10]ꢀForꢀin-bandꢀsignalsꢀ115.2ꢀkbit/sꢀwhereꢀ9ꢀmW/cm2ꢀ≤ꢀEIꢀ≤ꢀ500ꢀmW/cm2.

[11]ꢀForꢀin-bandꢀsignalsꢀ1.152ꢀMbit/sꢀwhereꢀ22ꢀmW/cm2ꢀ≤ꢀEIꢀ≤ꢀ500ꢀmW/cm2.

[12]ꢀLatencyꢀisꢀdeﬁnedꢀasꢀtheꢀtimeꢀfromꢀtheꢀlastꢀTxDꢀlightꢀoutputꢀpulseꢀuntilꢀtheꢀreceiverꢀhasꢀrecoveredꢀfullꢀsensitivity.

[13]ꢀReceiverꢀWakeꢀUpꢀTimeꢀisꢀmeasuredꢀfromꢀVccꢀpowerꢀONꢀtoꢀvalidꢀRxDꢀoutput.

[14]ꢀTransmitterꢀWakeꢀUpꢀTimeꢀisꢀmeasuredꢀfromꢀVccꢀpowerꢀONꢀtoꢀvalidꢀlightꢀoutputꢀinꢀresponseꢀtoꢀaꢀTxDꢀpulse.

[15]ꢀTheꢀMaxꢀOpticalꢀPWꢀisꢀdeﬁnedꢀasꢀtheꢀmaximumꢀtimeꢀwhichꢀtheꢀIRꢀLEDꢀwillꢀturnꢀon,ꢀthis,ꢀisꢀtoꢀpreventꢀtheꢀlongꢀTurnꢀOnꢀtimeꢀforꢀtheꢀIRꢀLED.

2.20

2.10

2.00

1.90

1.80

1.70

1.60

1.50

1.40

120

100

80

60

40

20

0

000.0E+0 50.0E-3 100.0E-3 150.0E-3 200.0E-3 250.0E-3 300.0E-3 350.0E-3

ILED (A)

Figure 3. VLED_A vs. ILED

Figure 4. Radiant Intensity vs ILED

Max. Permissible DC LED Current

70

Max. Permissible Peak LED Current

350

300

250

200

150

100

50

60

50

40

Rθja = 400degC/W

30

20

10

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

T_A- Ambient Temperature - ^oC

o

T_A- Ambient Temperature - C

Figure 6 Maximum DC LED current vs. ambient temperature. Derated based

on T_JMAX= 100°C.

Figure 5. Maximum Peak LED current vs. ambient temperature. Derated

based on T_JMAX= 100°C.

6

ASDL-3212 (Option -021) Package Dimensions

Figure 7. Package Dimension for ASDL-3212-021

7

ASDL-3212 (Option -021) Tape & Reel Dimensions

4.0 ± 0.1

2.0 ± 0.1

Unit: mm

1.75 ± 0.1

7.5 ± 0.1

+0.1

0

∅ 1.5

POLARITY

Pin 6: GND

16.0 ± 0.2

Pin 1: LEDA

7.4 ± 0.1

0.3 ± 0.05

2.7 ± 0.1

1.85 ± 0.1

8.0 ± 0.1

Progressive Direction

Empty

Parts Mounted

Leader

(400mm min)

(40mm min)

Empty

(40mm min)

Option #

021

"B"

330

"C" Quantity

80

2500

Unit: mm

Detail A

2.0 ± 0.5

B

C

∅ 13.0 ± 0.5

R1.0

LABEL

21 ± 0.8

Detail A

+2

16.4

0

2.0 ± 0.5

Figure 8. Tape and Reel dimensions

8

Moisture Proof Packaging

ASDL-3212ꢀ optionsꢀ areꢀ shippedꢀ inꢀ moistureꢀ proofꢀ

package.ꢀOnceꢀopened,ꢀmoistureꢀabsorptionꢀbegins.

ThisꢀpartꢀisꢀcompliantꢀtoꢀJEDECꢀLevelꢀ3.

Units in A Sealed

Mositure-Proof

Package

Package Is

Opened (Unsealed)

Environment

less than 30 deg C, and

less than 60% RH ?

Yes

Package Is

Opened less

than 168 hours ?

Yes

No Baking

Is Necessary

No

Perform Recommended

Baking Conditions

Figure 9. Baking Conditions Chart

Recommended Storage Conditions

Baking Conditions

Ifꢀtheꢀpartsꢀareꢀnotꢀstoredꢀinꢀdryꢀconditions,ꢀtheyꢀmustꢀbeꢀ

bakedꢀbeforeꢀreﬂowꢀtoꢀpreventꢀdamageꢀtoꢀtheꢀparts.ꢀ

Storage Temperature

Relative Humidity

ꢀ0°C to 30°C

below 60ꢁ RH

Package

In reels

In bulk

Temp

60 °C

Time

Time from unsealing to soldering

≥ 48hours

≥ 4hours

ꢀ00 °C

Afterꢀremovalꢀfromꢀtheꢀbag,ꢀtheꢀpartsꢀshouldꢀbeꢀsolderedꢀ

withinꢀ7ꢀdaysꢀifꢀstoredꢀatꢀtheꢀrecommendedꢀstorageꢀcon-

ditions.ꢀIfꢀtimesꢀlongerꢀthanꢀ7ꢀdaysꢀareꢀneeded,ꢀtheꢀpartsꢀ

Bakingꢀshouldꢀonlyꢀbeꢀdoneꢀonce.

9

Recommended Reﬂow Proﬁle

MAX 260C

R3

255

R4

230

220

200

R2

60 sec

MAX

Above 220 C

180

160

R5

R1

120

80

25

0

100

P2

150

200

P3

SOLDER

REFLOW

250

P4

COOL DOWN

300

50

P1

HEAT

UP

t-TIME

(SECONDS)

SOLDER PASTE DRY

Process Zone

Heat Up

Symbol

DT

Maximum DT/Dtime

Pꢀ, Rꢀ

P2, R2

25°C to ꢀ60°C

ꢀ60°C to 200°C

3°C/s

Solder Paste Dry

Solder Reﬂow

0.5°C/s

P3, R3

P3, R4

200°C to 255°C (260°C at ꢀ0 seconds max)

255°C to 200°C

4°C/s

-6°C/s

Cool Down

P4, R5

200°C to 25°C

-6°C/s

Theꢀ reﬂowꢀ proﬁleꢀ isꢀ aꢀ straight-lineꢀ representationꢀ ofꢀ

aꢀ nominalꢀ temperatureꢀ proﬁleꢀ forꢀ aꢀ convectiveꢀ reﬂowꢀ

solderꢀ process.ꢀ Theꢀ temperatureꢀ proﬁleꢀ isꢀ dividedꢀ intoꢀ

fourꢀ processꢀ zones,ꢀ eachꢀ withꢀ diﬀerentꢀ DT/Dtimeꢀ tem-

peratureꢀ changeꢀ rates.ꢀTheꢀ DT/Dtimeꢀ ratesꢀ areꢀ detailedꢀ

inꢀtheꢀaboveꢀtable.ꢀTheꢀtemperaturesꢀareꢀmeasuredꢀatꢀtheꢀ

componentꢀtoꢀprintedꢀcircuitꢀboardꢀconnections.

Process zone P3ꢀ isꢀ theꢀ solderꢀ reﬂowꢀ zone.ꢀ Inꢀ zoneꢀ P3,ꢀ

theꢀ temperatureꢀ isꢀ quicklyꢀ raisedꢀ aboveꢀ theꢀ liquidusꢀ

pointꢀofꢀsolderꢀtoꢀ255°Cꢀ(491°F)ꢀforꢀoptimumꢀresults.ꢀTheꢀ

dwellꢀtimeꢀaboveꢀtheꢀliquidusꢀpointꢀofꢀsolderꢀshouldꢀbeꢀ

betweenꢀ 20ꢀ andꢀ 60ꢀ seconds.ꢀ Itꢀ usuallyꢀ takesꢀ aboutꢀ 20ꢀ

secondsꢀ toꢀ assureꢀ properꢀ coalescingꢀ ofꢀ theꢀ solderꢀ ballsꢀ

intoꢀliquidꢀsolderꢀandꢀtheꢀformationꢀofꢀgoodꢀsolderꢀcon-

nections.ꢀBeyondꢀaꢀdwellꢀtimeꢀofꢀ60ꢀseconds,ꢀtheꢀinter-

metallicꢀgrowthꢀwithinꢀtheꢀsolderꢀconnectionsꢀbecomesꢀ

excessive,ꢀ resultingꢀ inꢀ theꢀ formationꢀ ofꢀ weakꢀ andꢀ un-

reliableꢀ connections.ꢀ Theꢀ temperatureꢀ isꢀ thenꢀ rapidlyꢀ

reducedꢀtoꢀaꢀpointꢀbelowꢀtheꢀsolidusꢀtemperatureꢀofꢀtheꢀ

solder,ꢀ usuallyꢀ 200°Cꢀ (392°F),ꢀ toꢀ allowꢀ theꢀ solderꢀ withinꢀ

theꢀconnectionsꢀtoꢀfreezeꢀsolid.ꢀ

In process zone P1,ꢀ theꢀ PCꢀ boardꢀ andꢀ ASDL-3212ꢀ cas-

tellationꢀ pinsꢀ areꢀ heatedꢀ toꢀ aꢀ temperatureꢀ ofꢀ 160°Cꢀ toꢀ

activateꢀ theꢀ ﬂuxꢀ inꢀ theꢀ solderꢀ paste.ꢀ Theꢀ temperatureꢀ

rampꢀupꢀrate,ꢀR1,ꢀisꢀlimitedꢀtoꢀ3°Cꢀperꢀsecondꢀtoꢀallowꢀforꢀ

evenꢀheatingꢀofꢀbothꢀtheꢀPCꢀboardꢀandꢀASDL-3212ꢀcastel-

lations.

Process zone P2ꢀshouldꢀbeꢀofꢀsuﬃcientꢀtimeꢀdurationꢀ(60ꢀ

toꢀ120ꢀseconds)ꢀtoꢀdryꢀtheꢀsolderꢀpaste.ꢀTheꢀtemperatureꢀ

isꢀ raisedꢀ toꢀ aꢀ levelꢀ justꢀ belowꢀ theꢀ liquidusꢀ pointꢀ ofꢀ theꢀ

solder,ꢀusuallyꢀ200°Cꢀ(392°F).ꢀ

Process zone P4ꢀ isꢀ theꢀ coolꢀ downꢀ afterꢀ solderꢀ freeze.ꢀ

Theꢀ coolꢀ downꢀ rate,ꢀ R5,ꢀ fromꢀ theꢀ liquidusꢀ pointꢀ ofꢀ theꢀ

solderꢀtoꢀ25°Cꢀ(77°F)ꢀshouldꢀnotꢀexceedꢀ6°Cꢀperꢀsecondꢀ

maximum.ꢀ Thisꢀ limitationꢀ isꢀ necessaryꢀ toꢀ allowꢀ theꢀ PCꢀ

boardꢀandꢀASDL-3212ꢀcastellationsꢀtoꢀchangeꢀdimensionsꢀ

evenly,ꢀputtingꢀminimalꢀstressesꢀonꢀtheꢀASDL-3212ꢀtrans-

ceiver.

ꢀ0

Appendix A: ASDL-3212 (Option -021) SMT Assembly Application Note

Solder Pad, Mask and Metal Stencil

Metal Stencil

for Solder

Paste Printing

Aperture As Per

Land Dimensions

t

Stencil

Aperture

Land

Pattern

w

l

Solder

Mask

Figure A3. Solder stencil aperture

PCBA

Aperture size (mm)

Stencil thickness,

t (mm)

Length, l

Width, w

0.ꢀ27mm

0.ꢀꢀ0mm

ꢀ.75 +/- 0.05

2.40 +/- 0.05

0.55 +/- 0.05

Figure A1. Stencil and PCBA

Recommended land pattern

Adjacent Land Keepout and Solder Mask Areas

C

L

Adjacentꢀlandꢀkeepoutꢀisꢀtheꢀmaximumꢀspaceꢀoccupiedꢀ

byꢀtheꢀunitꢀrelativeꢀtoꢀtheꢀlandꢀpattern.ꢀThereꢀshouldꢀbeꢀ

noꢀotherꢀSMDꢀcomponentsꢀwithinꢀthisꢀarea.ꢀTheꢀminimumꢀ

solderꢀresistꢀstripꢀwidthꢀrequiredꢀtoꢀavoidꢀsolderꢀbridgingꢀ

adjacentꢀpadsꢀisꢀ0.2mm.ꢀItꢀisꢀrecommendedꢀthatꢀtwoꢀﬁ-

duciallyꢀcrossesꢀbeꢀplacedꢀatꢀmidꢀlengthꢀofꢀtheꢀpadsꢀforꢀ

unitꢀalignment.

Mounting

Center

0.10

0.775

j

1.75

fiducial

0.60

h

1.425

k

2.375

0.95

Unit: mm

Pitch

l

Figure A2. Land Pattern

Solder mask

Units: mm

Recommended Metal Solder Stencil Aperture

Itꢀ isꢀ recommendedꢀ thatꢀ onlyꢀ aꢀ 0.11mmꢀ (0.004ꢀ inch)ꢀ orꢀ

aꢀ 0.127mmꢀ (0.005ꢀ inch)ꢀ thickꢀ stencilꢀ beꢀ usedꢀ forꢀ solderꢀ

pasteꢀprinting.ꢀThisꢀisꢀtoꢀensureꢀadequateꢀprintedꢀsolderꢀ

pasteꢀvolumeꢀandꢀnoꢀshorting.ꢀSeeꢀtheꢀtableꢀbelowꢀtheꢀ

drawingꢀforꢀcombinationsꢀofꢀmetalꢀstencilꢀapertureꢀandꢀ

metalꢀstencilꢀthicknessꢀthatꢀshouldꢀbeꢀused.ꢀComparedꢀtoꢀ

0.127mmꢀstencilꢀthicknessꢀ0.11mmꢀstencilꢀthicknessꢀhasꢀ

longerꢀ lengthꢀ inꢀ landꢀ pattern.ꢀ Itꢀ isꢀ extendedꢀ outwardlyꢀ

fromꢀ transceiverꢀ toꢀ captureꢀ moreꢀ solderꢀ pasteꢀ volume.ꢀ

Seeꢀﬁgureꢀ3.

Dimension

mm

0.2

3.0

8.6

h

l

k

j

Note:ꢀWet/LiquidꢀPhoto-imaginableꢀsolderꢀresist/maskꢀisꢀrecommended.

Figure A4. Adjacent Land Keepout and solder mask areas

ꢀꢀ

Appendix B: PCB Layout Suggestion

Theꢀ ASDL-3212ꢀisꢀ aꢀ shieldlessꢀ partꢀ andꢀ henceꢀ doesꢀ notꢀ

containꢀaꢀshieldꢀtraceꢀunlikeꢀtheꢀotherꢀtransceivers.ꢀTheꢀ

eﬀectsꢀ ofꢀ EMIꢀ andꢀ powerꢀ supplyꢀ noiseꢀ canꢀ potentiallyꢀ

reduceꢀtheꢀsensitivityꢀofꢀtheꢀreceiver,ꢀresultingꢀinꢀreducedꢀ

linkꢀdistance.ꢀTheꢀfollowingꢀPCBꢀlayoutꢀguidelinesꢀshouldꢀ

beꢀ followedꢀ toꢀ obtainꢀ aꢀ goodꢀ PSRRꢀ andꢀ EMꢀ immunityꢀ

resultingꢀinꢀgoodꢀelectricalꢀperformance.ꢀThingsꢀtoꢀnote:

Theꢀareaꢀunderneathꢀtheꢀmoduleꢀatꢀtheꢀsecondꢀlayer,ꢀandꢀ

3cmꢀinꢀallꢀdirectionꢀaroundꢀtheꢀmoduleꢀisꢀdeﬁnedꢀasꢀtheꢀ

criticalꢀgroundꢀplaneꢀzone.ꢀTheꢀgroundꢀplaneꢀshouldꢀbeꢀ

maximizedꢀinꢀthisꢀzone.ꢀTheꢀlayoutꢀbelowꢀisꢀbasedꢀonꢀaꢀ

2-layerꢀPCB.

1.ꢀ Theꢀ groundꢀ planeꢀ shouldꢀ beꢀ continuousꢀ underꢀ theꢀ

part.

2.ꢀ VLEDꢀ andꢀVccꢀ canꢀ beꢀ connectedꢀ toꢀ eitherꢀ unﬁlteredꢀ

orꢀ unregulatedꢀ powerꢀ supply.ꢀ IfꢀVLEDꢀ andꢀVccꢀ shareꢀ

theꢀ sameꢀ powerꢀ supply,ꢀ CX3ꢀ needꢀ notꢀ beꢀ used.ꢀTheꢀ

connectionsꢀ forꢀ CX1ꢀ andꢀ CX2ꢀ shouldꢀ beꢀ connectedꢀ

beforeꢀtheꢀcurrentꢀlimitingꢀresistorꢀR1.ꢀ

3.ꢀ CX2ꢀisꢀgenerallyꢀaꢀceramicꢀcapacitorꢀofꢀlowꢀinductanceꢀ

providingꢀaꢀwideꢀfrequencyꢀresponseꢀwhileꢀCX1ꢀandꢀ

CX3ꢀ areꢀ tantalumꢀ capacitorꢀ ofꢀ bigꢀ volumeꢀ andꢀ fastꢀ

frequencyꢀresponse.ꢀTheꢀuseꢀofꢀaꢀtantalumꢀcapacitorꢀ

isꢀmoreꢀcriticalꢀonꢀtheꢀVLEDꢀline,ꢀwhichꢀcarriesꢀaꢀhighꢀ

current.ꢀ

Top Layer

Bottom Layer

4.ꢀ Preferablyꢀ aꢀ multi-layeredꢀ boardꢀ shouldꢀ beꢀ usedꢀ

toꢀ provideꢀ suﬃcientꢀ groundꢀ plane.ꢀ Useꢀ theꢀ layerꢀ

underneathꢀ andꢀ nearꢀ theꢀ transceiverꢀ moduleꢀ asꢀVcc,ꢀ

andꢀsandwichꢀthatꢀlayerꢀbetweenꢀgroundꢀconnectedꢀ

boardꢀ layers.ꢀ Theꢀ diagramsꢀ belowꢀ demonstrateꢀ anꢀ

exampleꢀofꢀaꢀ4-layerꢀboardꢀ:

Top layer

Connect the module ground pin to

bottom ground layer

Layer 2

Critical ground plane zone. Do not connect

directly to the module ground pin

Layer 3

Keep data bus away from critical ground

plane zone

Bottom layer (GND)

ꢀ2

Appendix C: General Application Guide for the ASDL-3212 Infrared IrDA® Compliant 1.15Mb/s Transceiver

Description

Selection of Resistor R1

Theꢀ ASDL-3212ꢀ isꢀ aꢀ low-costꢀ andꢀ ultraꢀ smallꢀ infraredꢀ

transceiverꢀmoduleꢀthatꢀprovidesꢀtheꢀinterfaceꢀbetweenꢀ

logicꢀandꢀinfraredꢀ(IR)ꢀsignalsꢀforꢀthroughꢀair,ꢀserial,ꢀhalfꢀ

duplexꢀIRꢀdataꢀlink.ꢀTheꢀdeviceꢀisꢀdesignedꢀtoꢀaddressꢀtheꢀ

mobileꢀcomputingꢀmarketꢀsuchꢀasꢀPDAs,ꢀasꢀwellꢀasꢀsmallꢀ

embeddedꢀmobileꢀproductsꢀsuchꢀasꢀdigitalꢀcamerasꢀandꢀ

cellularꢀphones.ꢀItꢀisꢀfullyꢀcompliantꢀtoꢀIrDAꢀ1.4ꢀlowꢀpowerꢀ

speciﬁcationꢀ fromꢀ 9.6kb/sꢀ toꢀ 1.15Mb/s.ꢀ Theꢀ designꢀ ofꢀ

ASDL-3212ꢀalsoꢀincludesꢀtheꢀfollowingꢀuniqueꢀfeatures:

ResistorꢀR1ꢀshouldꢀbeꢀselectedꢀtoꢀprovideꢀtheꢀappropri-

ateꢀpeakꢀpulseꢀLEDꢀcurrentꢀatꢀdiﬀerentꢀrangesꢀofꢀVccꢀasꢀ

shownꢀ underꢀ“Recommendedꢀ Applicationꢀ Circuitꢀ Com-

ponents”.

Interface to the Recommended I/O chip

Theꢀ ASDL-3212’sꢀ TXDꢀ dataꢀ inputꢀ isꢀ buﬀeredꢀ toꢀ allowꢀ

forꢀ CMOSꢀ driveꢀ levels.ꢀ Noꢀ peakingꢀ circuitꢀ orꢀ capacitorꢀ

isꢀ required.ꢀ Dataꢀ rateꢀ fromꢀ 9.6kb/sꢀ upꢀ toꢀ 1.15Mb/sꢀ isꢀ

availableꢀatꢀRXDꢀpin.ꢀ

•ꢀ Lowꢀpassiveꢀcomponentꢀcount;

•ꢀ Shutdownꢀ modeꢀ forꢀ lowꢀ powerꢀ consumptionꢀ

FiguresꢀC1ꢀandꢀC2ꢀshowꢀhowꢀASDL-3212ꢀﬁtsꢀintoꢀaꢀmobileꢀ

phoneꢀandꢀPDAꢀplatformꢀrespectively.

requirement;

•ꢀ DirectꢀinterfaceꢀwithꢀSuperꢀI/Oꢀlogicꢀcircuit.

Key Pad

STN/TFT LCD Panel

LCD Control

Peripherial

PWM

LCD Backlight Contrast

interface

Touch Panel

A/D

*ASDL -

3212

Mobile Application

chipset

IrDA

interface

AC97

sound

PCM Sound

Audio Input

Memory I/F

Memory Expansion

Logic Bus Driver

I2S

Baseband

controller

ROM

Power Management

Antenna

FLASH

SDRAM

Figure C1. Mobile Application Platform

ꢀ3

Color

Co

Display

LCD Data/Timing

Control

*ASDL-3212

Camera

Antenna

LCD

Interface

Key Pad

Flash/

ROM/DRAM

OS/Apps

Configuration

EEPROM

Smart Card

MMC SD

PDA Application Chipset

Stereo

Speaker

Stereo

Audio

Stereo

Headphone

Wired

Connectivity

USB

USB Controller

Reset

Microphone

Touch

Screen

Controller

To Battery

Fuel Gauge

Figure C2. PDA Platform

Theꢀ linkꢀ distanceꢀ testingꢀ wasꢀ doneꢀ usingꢀ typicalꢀ ASDL-

3212ꢀunitsꢀwithꢀSMC’sꢀFDC37C669ꢀandꢀFDC37N769ꢀSuperꢀ

I/Oꢀ controllers.ꢀ Anꢀ IRꢀ linkꢀ distanceꢀ ofꢀ upꢀ toꢀ 50ꢀ cmꢀ wasꢀ

demonstrated.

ꢀ4

Appendix D: Window Design for ASDL-3212

Window Dimension

OPAQUE MATERIAL

IR Transparent Window

Y

IR Transparent Window

OPAQUE MATERIAL

X

K

Z

A

D

Figure D1. Window Design for ASDL-3212

Theꢀ aboveꢀ equationsꢀ assumeꢀ thatꢀ theꢀ thicknessꢀ ofꢀ theꢀ

windowꢀ isꢀ negligibleꢀ comparedꢀ toꢀ theꢀ distanceꢀ ofꢀ theꢀ

moduleꢀfromꢀtheꢀbackꢀofꢀtheꢀwindowꢀ(Z).ꢀIfꢀtheyꢀareꢀcom-

parable,ꢀZ’ꢀreplacesꢀZꢀinꢀtheꢀaboveꢀequation.ꢀZ’ꢀisꢀdeﬁnedꢀ

asꢀ

Toꢀ ensureꢀ IrDAꢀ compliance,ꢀ someꢀ constraintsꢀ onꢀ theꢀ

heightꢀ andꢀ widthꢀ ofꢀ theꢀ windowꢀ exist.ꢀ Theꢀ minimumꢀ

dimensionsꢀ ensureꢀ thatꢀ theꢀ IrDAꢀ conesꢀ anglesꢀ areꢀ metꢀ

withoutꢀvignetting.ꢀTheꢀmaximumꢀdimensionsꢀminimizeꢀ

theꢀeﬀectsꢀofꢀstrayꢀlight.ꢀTheꢀminimumꢀsizeꢀcorrespondsꢀ

toꢀ aꢀ coneꢀ angleꢀ ofꢀ 300ꢀ andꢀ theꢀ maximumꢀ sizeꢀ corre-

spondsꢀtoꢀaꢀconeꢀangleꢀofꢀ600.

Z’=Z+t/n

whereꢀ‘t’ꢀisꢀtheꢀthicknessꢀofꢀtheꢀwindowꢀandꢀ‘n’ꢀisꢀtheꢀre-

fractiveꢀindexꢀofꢀtheꢀwindowꢀmaterial.

InꢀﬁgureꢀD1,ꢀXꢀisꢀtheꢀwidthꢀofꢀtheꢀwindow,ꢀYꢀisꢀtheꢀheightꢀ

ofꢀtheꢀwindowꢀandꢀZꢀisꢀtheꢀdistanceꢀfromꢀtheꢀASDL-3212ꢀ

toꢀtheꢀbackꢀofꢀtheꢀwindow.ꢀTheꢀdistanceꢀfromꢀtheꢀcenterꢀ

ofꢀtheꢀLEDꢀlensꢀtoꢀtheꢀcenterꢀofꢀtheꢀphotodiodeꢀlens,ꢀK,ꢀ

isꢀ5.1mm.ꢀꢀTheꢀequationsꢀforꢀcomputingꢀtheꢀwindowꢀdi-

mensionsꢀareꢀasꢀfollows:ꢀ

TheꢀdepthꢀofꢀtheꢀLEDꢀimageꢀinsideꢀtheꢀASDL-3212,ꢀD,ꢀisꢀ

4.32mm.ꢀ‘A’ꢀisꢀtheꢀrequiredꢀhalfꢀangleꢀforꢀviewing.ꢀForꢀIrDAꢀ

compliance,ꢀ theꢀ minimumꢀ isꢀ 150ꢀ andꢀ theꢀ maximumꢀ isꢀ

300.ꢀAssumingꢀtheꢀthicknessꢀofꢀtheꢀwindowꢀtoꢀbeꢀneg-

ligible,ꢀ theꢀ equationsꢀ resultꢀ inꢀ theꢀ followingꢀ tableꢀ andꢀ

ﬁgures:

Xꢀ=ꢀKꢀ+ꢀ2*(Z+D)*tanA

Yꢀ=ꢀ2*(Z+D)*tanA

ꢀ5

Theꢀrecommendedꢀminimumꢀapertureꢀwidthꢀandꢀheightꢀ

isꢀbasedꢀonꢀtheꢀassumptionꢀthatꢀtheꢀcenterꢀofꢀtheꢀwindowꢀ

andꢀtheꢀcenterꢀofꢀtheꢀmoduleꢀareꢀtheꢀsame.ꢀItꢀisꢀrecom-

mendedꢀ thatꢀ theꢀ toleranceꢀ forꢀ assemblyꢀ beꢀ consideredꢀ

asꢀwell.ꢀTheꢀminimumꢀwindowꢀsizeꢀwhichꢀwillꢀtakeꢀintoꢀ

accountꢀofꢀtheꢀassemblyꢀtoleranceꢀisꢀdeﬁnedꢀas:

Module Depth

Aperture Width (x, mm) Aperture height (y, mm)

(z) mm

Max

min

Max

4.99

Min

2.32

2.85

3.39

3.92

4.46

4.99

5.53

6.07

6.60

7.ꢀ4

0

ꢀ

2

3

4

5

6

7

8

9

ꢀ0.09

ꢀꢀ.24

ꢀ2.40

ꢀ3.55

ꢀ4.7ꢀ

ꢀ5.86

ꢀ7.02

ꢀ8.ꢀ7

ꢀ9.33

20.48

7.42

7.95

6.ꢀ4

Xꢀ (minꢀ +ꢀ assemblyꢀ tolerance)ꢀ =ꢀ Xminꢀ +ꢀ 2*(assemblyꢀ

tolerance)ꢀ(Dimensionsꢀareꢀinꢀmm)

8.49

7.30

9.02

8.45

Yꢀ (minꢀ +ꢀ assemblyꢀ tolerance)ꢀ =ꢀ Yminꢀ +ꢀ 2*(assemblyꢀ

tolerance)ꢀ(Dimensionsꢀareꢀinꢀmm)

9.56

9.6ꢀ

ꢀ0.09

ꢀ0.63

ꢀꢀ.ꢀ7

ꢀꢀ.70

ꢀ2.24

ꢀ0.76

ꢀꢀ.92

ꢀ3.07

ꢀ4.23

ꢀ5.38

Window Material

Almostꢀ anyꢀ plasticꢀ materialꢀ willꢀ workꢀ asꢀ aꢀ windowꢀ

material.ꢀ Polycarbonateꢀ isꢀ recommended.ꢀ Theꢀ surfaceꢀ

ﬁnishꢀ ofꢀ theꢀ plasticꢀ shouldꢀ beꢀ smooth,ꢀ withoutꢀ anyꢀ

texture.ꢀ Anꢀ IRꢀ ﬁlterꢀ dyeꢀ mayꢀ beꢀ usedꢀ inꢀ theꢀ windowꢀ toꢀ

makeꢀitꢀlookꢀblackꢀtoꢀtheꢀeye,ꢀbutꢀtheꢀtotalꢀopticalꢀlossꢀ

ofꢀ theꢀ windowꢀ shouldꢀ beꢀ 10%ꢀ orꢀ lessꢀ forꢀ bestꢀ opticalꢀ

performance.ꢀLightꢀlossꢀshouldꢀbeꢀmeasuredꢀatꢀ885ꢀnm.ꢀ

Theꢀrecommendedꢀplasticꢀmaterialsꢀforꢀuseꢀasꢀaꢀcosmeticꢀ

windowꢀareꢀavailableꢀfromꢀGeneralꢀElectricꢀPlastics.ꢀ

25

20

15

10

5

Xmax

Xmin

Recommended Plastic Materials:

Material #

Lexan ꢀ4ꢀ

Lexan 920A

Lexan 940A

Haze

ꢀꢁ

Refractive Index

ꢀ.586

88ꢁ

85ꢁ

ꢀꢁ

ꢀ.586

ꢀꢁ

ꢀ.586

Note:ꢀ920Aꢀandꢀ940Aꢀareꢀmoreꢀﬂameꢀretardantꢀthanꢀ141.

0

1

2

3

4

5

6

7

8

9

RecommendedꢀDye:ꢀVioletꢀ#21051ꢀ(IRꢀtransmissantꢀaboveꢀ

625mm)

Module Depth (z) mm

Figure D2. Aperture Height (x) vs. Module Depth (z)

Shape of the Window

Fromꢀ anꢀ opticsꢀ standpoint,ꢀ theꢀ windowꢀ shouldꢀ beꢀ ﬂat.ꢀ

Thisꢀ ensuresꢀ thatꢀ theꢀ windowꢀ willꢀ notꢀ alterꢀ eitherꢀ theꢀ

radiationꢀpatternꢀofꢀtheꢀLED,ꢀorꢀtheꢀreceiveꢀpatternꢀofꢀtheꢀ

photodiode.ꢀIfꢀtheꢀwindowꢀmustꢀbeꢀcurvedꢀforꢀmechani-

calꢀorꢀindustrialꢀdesignꢀreasons,ꢀplaceꢀtheꢀsameꢀcurveꢀonꢀ

theꢀbacksideꢀofꢀtheꢀwindowꢀthatꢀhasꢀanꢀidenticalꢀradiusꢀasꢀ

theꢀfrontꢀside.ꢀWhileꢀthisꢀwillꢀnotꢀcompletelyꢀeliminateꢀtheꢀ

lensꢀeﬀectꢀofꢀtheꢀfrontꢀcurvedꢀsurface,ꢀitꢀwillꢀsigniﬁcantlyꢀ

reduceꢀtheꢀeﬀects.ꢀTheꢀamountꢀofꢀchangeꢀinꢀtheꢀradiationꢀ

patternꢀ isꢀ dependentꢀ uponꢀ theꢀ materialꢀ chosenꢀ forꢀ theꢀ

window,ꢀtheꢀradiusꢀofꢀtheꢀfrontꢀandꢀbackꢀcurves,ꢀandꢀtheꢀ

distanceꢀfromꢀtheꢀbackꢀsurfaceꢀtoꢀtheꢀtransceiver.ꢀOnceꢀ

theseꢀitemsꢀareꢀknown,ꢀaꢀlensꢀdesignꢀcanꢀbeꢀmadeꢀwhichꢀ

willꢀ eliminateꢀ theꢀ eﬀectꢀ ofꢀ theꢀ frontꢀ surfaceꢀ curve.ꢀTheꢀ

followingꢀdrawingsꢀshowꢀtheꢀeﬀectsꢀofꢀaꢀcurvedꢀwindowꢀ

onꢀtheꢀradiationꢀpattern.ꢀInꢀallꢀcases,ꢀtheꢀcenterꢀthicknessꢀ

ofꢀtheꢀwindowꢀisꢀ1.5ꢀmm,ꢀtheꢀwindowꢀisꢀmadeꢀofꢀpolycar-

bonateꢀplastic,ꢀandꢀtheꢀdistanceꢀfromꢀtheꢀtransceiverꢀtoꢀ

theꢀbackꢀsurfaceꢀofꢀtheꢀwindowꢀisꢀ3ꢀmm.

18

Ymax

Ymin

16

14

12

10

8

6

4

2

0

1

2

3

4

5

6

7

8

9

Module Depth (z) mm

Figure D3. Aperture Height (y) vs. Module Depth (z)

ꢀ6

Curved Front and Back, (Second Choice)

Curved Front, Flat Back, (Do not use)

Flat Window, (First Choice)

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.

AV02-0055EN - January 3ꢀ, 2007