M62501P--Datasheet/数据表在线中文翻译

M62501P/FP

PWM IC for the Synchronized Deflection System Control

REJ03D0857-0200

Rev.2.00

Jun 14, 2006

General Description

The M62501P/FP is a controller for a deflection system of CRT display monitors. It performs a stable PWM control

over a wide fluctuation of external signals, thanks to the built-in trigger mode oscillator. The IC is suitable for an

application to a high voltage drive of monitors because of its following circuits and functions;

•

low voltage malfunction protection circuit,

over or under voltage protection circuit for a control line,

soft-start function.

It is also applicable to a horizontal output correction.

Features

•

PWM output synchronized with external signals

Wide pulse width modulation control frequency

15 kHz to 150 kHz

•

Soft start function

The under voltage output malfunction protection circuit

start V_CC> 9 V

stop V_CC< 6 V

•

Built-in over voltage protection (OVP) and under voltage protection (UVP) control

Application

CRT display monitor

Block Diagram

V_REF

15

GND

16

DTC

14

FB

13

IN−

IN+

BO

10

BI

9

12

11

+

−

V_CC

VREF

Amp

−

Comp

−

+

Latch

V_REF

Comp

UVLO

GEN

AGC

0.5 V

1

2

3

4

5

6

7

OVP

8

PWM OUT

V_CC

T_IN

C_OSC

C_AGC

P_OUT

UVP

Rev.2.00 Jun 14, 2006 page 1 of 10

M62501P/FP

Pin Arrangement

M62501P/FP

PWM OUT

V_CC

1

2

3

4

5

6

7

8

16 GND

V_REF

15

T_IN

C_OSC

14 DTC

13 FB

12 IN−

11 IN+

10 BO

C_AGC

P. OUT

OVP

UVP

9

BI

(Top view)

Outline: PRDP0016AA-A (16P4) [P]

PRSP0016DA-A (16P2S-A) [FP]

Terminal Number and The Facility

PIN No.

Symbol

PWM OUT

V_CC

Functional Description

1

2

PWM output

Power supply

Trigger input

3

T_IN

4

C_OSC

C_AGC

P.OUT

OVP

UVP

BI

Setting oscillating frequency

AGC setting

5

6

Error signal output

7

Input of over voltage protection

Input of under voltage protection

Positive input of buffer Amp.

Output of buffer Amp.

8

9

10

11

12

13

14

15

16

BO

IN+

Positive input of Op-Amp.

Negative input of Op-Amp.

Output of Op-Amp.

IN−

FB

DTC

V_REF

Dead time control (Soft start function)

Output of reference voltage (5 V)

Ground

GND

Absolute Maximum Ratings

(Ta = 25°C, unless otherwise noted)

Item

Supply voltage

Symbol

V_CC

Ratings

15

Unit

V

Conditions

Output voltage

V_OUT

I_OUT

V_ICM

V_ID

15

V

Output current

±100

mA

V

Error amplifier input common mode voltage

Error amplifier differential input voltage

Power dissipation

−0.3 to V_CC

V_CC

V

Pd

P

FP

650

FP

mW

1200

P

Thermal derating

Kθ

mW/°C Ta ≥ 25°C

9.6

5.2

Operating temperature

Storage temperature

Topr

Tstg

−20 to +75

−40 to +150

°C

Rev.2.00 Jun 14, 2006 page 2 of 10

M62501P/FP

Electrical Characteristics

(V_CC= 12 V, TIN = 40 kHz, Ta = 25°C, unless otherwise noted)

Limits

Block

Item

Range of power supply

Circuit current

Symbol

V_CC

Unit

V

Test Conditions

Min

Typ

Max

All device

V_CCOFF

14

I_CC

20

5.00

1.0

mA

V

Output off mode

I_REF= −5 mA

Reference

voltage

Reference voltage

Input regulation

V_REF

4.80

5.20

10

Reg-in

mV

V_CC= 7 to 14 V

section

I

_REF= −5 mA

Load regulation

Reg-L

2.0

20

mV

I_REF= 0 to −5 mA

Reference voltage thermal

coefficient

TC_VREF

0.01

%/°C

Maximum reference current

Short-circuit current

Input offset voltage

Input bias current

I_{REF MAX}

Is

−30

mA

mV

nA

V

Error Amp.

V_IO

7

I_Ib

−100

−0.3

Input offset current

I_IO

100

Common mode input

voltage range

V_ICM

V

_CC− 2

Open loop transmission gain AV

70

110

4

dB

V/µs

V

Slew rate

SR

Output voltage range

Output sink current

Output source current

V_OR

0.3

10

V

_REF− 1.5

Isink

Isource

Ib

mA

nA

−10

Buffer Amp. Input bias current

Slew rate

−20

SR

4

V/µs

V

Output voltage

V_OR

0.3

2

V

_CC− 2.5

Output sink current

Output source current

Isink

Isource

f_OSC

mA

kHz

V

−10

Oscillator

Oscillation frequency

15

150

The oscillator waveform

bound voltage

V_{OSC H}

3.5

1.5

The oscillator waveform

lower limit voltage

V_{OSC L}

V

High level of TIN

Low level of TIN

V_{TIN H}

V_{TIN L}

2.5

V_CC

1.0

1.4

V

PWM output Output saturation voltage L

V_{sat L}

0.7

10.5

9.0

I_O= 100 mA

section

Output saturation voltage H

ON threshold voltage

V_{sat H}

9.5

8.0

I_O= −100 mA

UVLO

section

V_{TH ON}

V_{TH OFF}

V_{TH OVP}

10.0

6.6

OFF threshold voltage

5.4

6.0

OVP section OVP terminal threshold

voltage

4.75

5.00

5.25

OVP terminal input current

UVP section Input offset voltage

UVP terminal input current

I_{IN OVP}

V_UVPO

I_{IN UVP}

Vsat

I_L

1.0

7

µA

mV

µA

V

1.0

0.4

1.0

P.OUT

section

Output saturation voltage

Output leakage current

I_PO= 10 mA

V_PO= 12 V

µA

Rev.2.00 Jun 14, 2006 page 3 of 10

M62501P/FP

Terminal Functional Description and Equivalent Circuit

Terminal

No.

Symbol

Function and Terminal Circumscription Circuitry

1

PWM

OUT

PWM output terminal

2 V_CC

•

The PWM output synchronized with the T_IN

input.

PWM

Output "H" level = 10.5 V typ

(The output load current: −100 mA, V_CC= 12 V)

1

OUT

Output "L" level = 0.7 V typ

(The output load current: +100 mA, V_CC= 12 V)

GND

16

2

3

V_CC

T_IN

Power supply terminal

Trigger input terminal

V_CC

V_REF

15

2

3

•

Frequency range

15 kHz to 150 kHz

•

It takes in a start edge.

T_IN

T_INinput waveform

Max 2.5 V

Min 1.0 V

16

GND

4

5

C_OSC

Cosc terminal

•

It generates a saw wave by connecting capacitor between 4-pin and GND.

Recommended capacitor value is 1000 pF.

C_AGC

C_AGCterminal

•

It sets up sensitivity of AGC by connecting capacitor between 5-pin and GND.

Recommended capacitor value is 1 µF.

V_REF

15

C_OSC

4

5

C_AGC

GND 16

Rev.2.00 Jun 14, 2006 page 4 of 10

M62501P/FP

Terminal

No.

Symbol

Function and Terminal Circumscription Circuitry

The abnormal state detection output terminal

6

P.OUT

V_CC

2

•

The output becomes "H" from "L" when an abnormality is detected

in the OVP or UVP terminal. Then the PWM output terminal

becomes "H" settlement, too.

•

Do OFF of power supply (V_CC) to remove latch of abnormal state.

In abnormal state detection;

Output "H" level = 10.5 V typ

(The output load current: no-load, V_CC= 12 V)

Output "L" level = 1.5 V typ

P. OUT

6

(The output load current: −1 mA, V_CC= 12 V)

In normal state ;

Output "L" level = 0.4 V typ

•

16 GND

(The output load current: +10 mA, V_CC= 12 V)

7

8

OVP

UVP

Over voltage protection of the control line (OVP)

•

Setting terminal voltage;

GND ≤ V_OVP< V_REF

Under voltage protection of the control line (UVP)

•

Setting terminal voltage;

GND ≤ V_UVP< V_OVP

V_CC

2

UVP

8

V_REF

15

OVP

7

GND 16

To latch Input

Note: lt is connected to GND when the abnormal detection terminal is not used.

9

BI

The input terminal of a buffer Amp. (BI)

The output terminal of a buffer Amp. (BO)

V_CC

2

10

BO

10 BO

BI

9

Rev.2.00 Jun 14, 2006 page 5 of 10

M62501P/FP

Terminal

No.

Symbol

IN+

Function and Terminal Circumscription Circuitry

Positive input terminal of an Op-Amp. (IN+)

11

12

V_CC

2

IN−

Negative input terminal of an Op-Amp. (IN−)

IN+ 11

12 IN−

13

14

FB

Output terminal of an Op-Amp. (FB)

Dead time control terminal (DTC)

DTC

•

It can do soft start during power-on under keeping time constant.

V_REF

15

DTC 14

FB 13

C_OSC

4

PWM comparator section

16 GND

15

V_REF

Reference voltage terminal

V_CC

2

•

5 V output voltage

(The terminal can begin to take

outside connected load 5 mA.)

15 V_REF

−

+

16

GND

16

GND

Ground terminal

Rev.2.00 Jun 14, 2006 page 6 of 10

M62501P/FP

Timing Chart

PWM OUT ON Duty is fixed in the voltage of higher one between DTC terminal and FB terminal voltage.

T_IN

DTC

FB

PWM OUT

•

Waveform at "H" was taken from "L", and having put T_INup.

(PWM output is fixed in "H", too when fix T_INterminal in "H")

T_IN

PWM OUT

Approximately 150 µs

•

Waveform at "L" was taken from "H", and having put T_INup.

(PWM output is fixed in "L", too when fix T_INterminal in "L")

T_IN

PWM OUT

Rev.2.00 Jun 14, 2006 page 7 of 10

M62501P/FP

M62501 Application

IN−

IN+

BO

BI

R2

C5

R3

C3

R1

VR1

C2

C4

D1

R4

16

15

14

13

12

11

10

9

+

V_CC

+

−

VREF

−

Comp

+

Latch

V_REF

UVLO

+

GEN

4

AGC

5

V_CC

1

6

2

3

7

8

C_OSC

C_AGC

PWM OUT

T_IN

P. OUT

OVP

UVP

C1

C1, C2: Stabilization capacitors of V_CCand V_REF

.

VR1: It is decided considering a load capacity of V_REF

(A load capacity is approximately 5 mA.)

Recommended value is around 10 kΩ.

.

C3, Dl: They are for the soft start function. A time constant is decided considering VR1.

C_AGC

:

This capacitor is for stabilization of AGC. A larger capacitor improves a stability of the system, however

a system response is degraded.

Recommended value is around 1 µF.

C_OSC

:

This capacitor is for a saw wave generation. Recommended value is around 1000 pF.

R1, R2, R3, R4, C4, C5:

They are for a gain setting of the error Amp. R2 should be several kΩ to dozens of kΩ to set a voltage gain

20 dB to 40 dB at f = 1 kHz, so that the feed back loop is stable.

When the voltage gain is too low, it causes jitter.

Recommended values of C4, C5 and R1 are ;

C4 = dozens of pF to several hundreds pF

C5 = several thousands pF to tens of thousands pF

R1 = dozens of kΩ to several hundreds kΩ.

Note: Connect 7-pin and 8-pin terminal to GND when don't use under voltage protection. (UVP)

Rev.2.00 Jun 14, 2006 page 8 of 10

M62501P/FP

Example of Application Circuit

IN−

16

15

14

13

12

11

10

9

+

−

VCC

VREF

−

+

Comp

Latch

V_REF

UVLO

+

GEN

4

AGC

5

V_CC

1

2

3

6

7

8

C_OSC

C_AGC

T_IN

P. OUT

Rev.2.00 Jun 14, 2006 page 9 of 10

M62501P/FP

Package Dimensions

JEITA Package Code

P-DIP16-6.3x19-2.54

RENESAS Code

PRDP0016AA-A

Previous Code

16P4

MASS[Typ.]

1.0g

16

9

1

8

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

*2

D

Dimension in Millimeters

Reference

Symbol

Min Nom Max

e₁

D

7.32 7.62 7.92

18.8 19.0 19.2

E

6.15

6.3

6.45

4.5

A

A₁

A₂

b_p

b₂

b₃

c

0.51

3.3

0.5

1.0

1.5

*3

0.4

0.9

1.4

0.6

1.3

1.8

b_p

b₃

b₂

e

SEATING PLANE

0.22 0.27 0.34

0° 15°

e

L

2.29 2.54 2.79

3.0

JEITA Package Code

P-SOP16-4.4x10-1.27

RENESAS Code

PRSP0016DA-A

Previous Code

16P2S-A

MASS[Typ.]

0.15g

16

9

F

NOTE)

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

A2

A1

1

8

Index mark

*2

D

Dimension in Millimeters

Reference

Symbol

Min Nom Max

D

E

9.8 10.0 10.2

4.2 4.4 4.6

1.5

A₂

A₁

A

*3

Detail F

e

bp

0.05

y

1.9

0.35 0.4 0.5

0.13 0.15 0.2

b_p

c

0°

10°

H_E

e

5.9 6.2 6.5

1.07 1.27 1.47

0.1

y

L

0.2 0.4 0.6

Rev.2.00 Jun 14, 2006 page 10 of 10

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of

publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is

therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product

information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor

home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to

evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes

no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life

is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a

product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater

use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and

cannot be imported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon .6.0