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DATASHEET  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
ICS1894-32  
Description  
Features  
The ICS1894-32 is a low-power, physical-layer device  
(PHY) that supports the ISO/IEC 10Base-T and  
100Base-TX Carrier-Sense Multiple Access/Collision  
Detection (CSMA/CD) Ethernet standards, ISO/IEC  
8802.3. It is intended for RMII/MII, Node/Repeater  
applications and includes the Auto-MDIX feature that  
automatically corrects crossover errors in plant wiring.  
• Supports category 5 cables and above with attenuation in  
excess of 24dB at 100 MHz.  
• Single-chip, fully integrated PHY provides PCS, PMA,  
PMD, and AUTONEG sub layers functions of IEEE  
standard.  
• 10Base-T and 100Base-TX IEEE 8802.3 compliant  
• MIIM (MDC/MDIO) management bus for PHY register  
The ICS1894-32 incorporates Digital-Signal Processing  
(DSP) control in its Physical-Medium Dependent (PMD)  
sub-layer. As a result, it can transmit and receive data on  
unshielded twisted-pair (UTP) category 5 cables with  
attenuation in excess of 24 dB at 100MHz.  
configuration  
• RMII interface support with external 50 MHz system clock  
• Single 3.3V power supply  
• Highly configurable, supports:  
The ICS1894-32 provides a Serial-Management Interface  
for exchanging command and status information with a  
Station-Management (STA) entity. The ICS1894-32  
Media-Dependent Interface (MDI) can be configured to  
provide either half-duplex or full-duplex operation at data  
rates of 10 Mb/s or 100Mb/s.  
– Media Independent Interface (MII)  
– Auto-Negotiation with Parallel detection  
– Node applications, managed or unmanaged  
– 10M or 100M full and half-duplex modes  
– Loopback mode for Diagnostic Functions  
• Auto-MDI/MDIX crossover correction  
• Low-power CMOS (typically 300 mW)  
• Power-Down mode (typically 21mW)  
• Clock and crystal supported in MII mode  
• Programmable LEDs  
In addition, the ICS1894-32 includes a programmable LED  
and interrupt output function. The LED outputs can be  
configured through registers to indicate the occurance of  
certain events such as LINK, COLLISION, ACTIVITY, etc.  
The purpose of the programmable interrupt output is to  
notify the PHY controller device immediately when a certain  
event happens instead of having the PHY controller  
continuously poll the PHY. The events that could be used to  
generate interrupts are: receiver error, Jabber, page  
received, parallel detect fault, link partner acknowledge, link  
status change, auto-negotiation complete, remote fault,  
collision, etc.  
• Interrupt output pin  
• Fully integrated, DSP-based PMD includes:  
– Adaptive equalization and baseline-wander  
correction  
The ICS1894-32 has deep power modes that can result in  
significant power savings when the link is broken.  
– Transmit wave shaping and stream cipher  
scrambler  
– MLT-3 encoder and NRZ/NRZI encoder  
• Core power supply (3.3 V)  
Applications: NIC cards, PC motherboards, switches,  
routers, DSL and cable modems, game machines, printers,  
network connected appliances, and industrial equipment.  
• 3.3 V/1.8 V VDDIO operation supported  
• Smart power control with deep power down feature  
• Available in 32-pin (5mm x 5mm) QFN package, Pb-free  
• Available in Industrial Temp and Lead Free  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
1
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Block Diagram  
100Base-T  
PCS  
PMA  
TP_PMD  
•
•
Framer  
CRS/COL  
Detection  
Parallel to Serial  
4B/5B  
•
•
•
•
Clock Recovery  
Link Monitor  
Signal Detection  
Error Detection  
•
•
•
•
MLT-3  
10/100 MII/RMII  
MAC  
Twisted-  
Pair  
Interface to  
Magnetics  
Modulesand  
RJ45  
Interface  
MUX  
Integrated  
Switch  
Stream Cipher  
Adaptive Equalizer  
Baseline Wander  
Correction  
Interface  
•
•
10Base-T  
Connector  
MII  
Low-Jitter  
Clock  
Synthesizer  
Smart Power  
Control  
Auto-  
Negotiation  
Configuration  
and Status  
Extended  
Register  
Set  
MII  
Management  
Interface  
Block  
Clock  
Power  
LEDs and PHY  
Address  
Pin Assignment  
25  
1
TXD0  
TXEN  
TP_AP  
TP_AN  
VSS  
SPEED/TXCLK  
NOD/RXER  
NLG32 With Ground  
VDD  
Connecting to Thermal Pad  
ANSEL/RXCLK  
VDDIO  
TP_BN  
TP_BP  
RMII/RXDV  
FDPX/RXD0  
VDD  
17  
TCSR  
9
32-pin 5mm x 5mm QFN  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
2
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin  
Pin Description  
Type1  
1
2
3
4
5
6
7
8
TP_AP  
TP_AN  
VSS  
AIO  
AIO  
Twisted pair port A (for either transmit or receive) positive signal  
Twisted pair port A (for either transmit or receive) negative signal  
Ground Connect to ground.  
Power 3.3V Power Supply  
VDD  
TP_BN  
TP_BP  
VDD  
AIO  
AIO  
Twisted pair port B (for either transmit or receive) negative signal  
Twisted pair port B (for either transmit or receive) positive signal  
Power 3.3V Power Supply  
AIO Transmit Current bias pin, connected to Vdd and ground via resistors (see  
TCSR  
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).  
9
VSS  
Ground Connect to ground.  
10  
11  
RESET_N  
P2/INT  
Input Hardware reset for the entire chip (active low)  
IO/Ipd PHY address Bit 2 as input (during power on reset/hardware reset)  
Interrupt output as output (default active low, can be programmed to active high)  
12  
13  
14  
MDIO  
MDC  
IO  
Management Data Input/Output  
Input Management Data Clock  
AMDIX/RXD3  
IO/Ipu AMDIX enable as input (during power on reset/hardware reset)  
Receive data Bit 3 in MII mode as output.  
15  
16  
17  
18  
P3/RXD2  
IO/Ipd PHY address Bit 3 as input (during power on reset/hardware reset)  
Receive data Bit 2 in MII mode as output.  
RXTRI/  
RXD1  
IO/Ipu RX tri-state enable as input (during power on reset/hardware reset)  
Receive data Bit 1 in both RMII and MII mode as output.  
FDPX/  
RXD0  
IO/Ipu Full duplex enable as input (during power on reset/hardware reset)  
Receive data Bit 0 in both RMII and MII mode as output  
RMII/RXDV  
IO/Ipd RMII/MII select as input (during power on reset/hardware reset)  
Receive data valid in MII mode and CRS_DV in RMII mode as output.  
19  
20  
VDDIO  
Power 3.3 V/1.8 V IO Power Supply.  
ANSEL/  
RXCLK  
IO/Ipu Auto-negotiation enable as input (during power on reset/hardware reset)  
Receive clock in MII mode as output.  
21  
22  
NOD/  
RXER  
IO/Ipd Node/repeater select as input (during power on reset/hardware reset)  
Receive error in MII/RMII mode as output  
SPEED/  
TXCLK  
IO/Ipu 10M/100M select as input (during power on reset/hardware reset)  
Transmit clock in MII mode as output  
23  
24  
25  
26  
27  
28  
TXEN  
TXD0  
VDDD  
TXD1  
TXT2  
TXD3  
Input Transmit enable in RMII/MII mode  
Input Transmit data Bit 0 in RMII/MII mode  
Power 3.3 V Power Supply  
Input Transmit data Bit 1 in RMII/MII mode  
Input Transmit data Bit 2 in MII mode  
Input Transmit data Bit 3 in MII mode  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
3
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Pin  
Number  
Pin  
Name  
Pin  
Pin Description  
Type1  
29  
30  
31  
REFOUT  
REFIN  
Output 25 MHz crystal output, floating in RMII mode  
Input 25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.  
P0/LED0  
IO  
PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0  
(function configurable, default is "activity/no activity") as output  
32  
P1/LED1  
VSS  
IO  
PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1  
(function configurable, default is "10/100 mode") as output  
PADDLE  
Ground Connect to ground.  
Notes:  
1. AIO: Analog input/output PAD.  
IO: Digital input/output.  
IN/Ipu: Digital input with internal 20k pull-up.  
IN/Ipd: Digital input with internal 20k pull-down.  
IO/Ipu: Digital input/output with internal 20k pull-up.  
IO/Ipd: Digital input/output with internal 20k pull-down.  
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents  
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.  
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is  
asserted, two bits of recovered data are sent from the PHY to the MAC.  
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid  
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.  
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is  
asserted, two bits of data are received by the PHY from the MAC.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
4
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Strapping Options  
Pin  
Number  
Pin  
Name  
Pin  
Pin Function  
Type1  
1 = AMDIX enable  
0 = AMDIX disable  
14  
AMDIX/RXD3  
IO/Ipu  
15  
11  
31  
32  
16  
17  
P3/RXD2  
P2/INT  
IO/Ipd The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external  
pull-up or pull-down to set address at start up.  
IO/Ipd  
P0/LED0  
IO  
P1/LED1  
IO  
RXTRI/RXD1  
FDPX/RXD0  
IO/Ipd 1 = Receiver Tristate Enable; 0 = Receiver Tristate Disable  
1=Full duplex  
0=Half duplex  
IO/Ipu  
Ignored if Auto negotiation is enabled  
1 = RMII mode  
0 = MII mode  
18  
20  
21  
22  
RMII/RXDV  
IO/Ipd  
1=Enable auto negotiation  
0=Disable auto negotiation  
ANSEL/RXCLK IO/Ipu  
NOD/RXER IO/Ipd  
SPEED/TXCLK IO/Ipu  
0=Node mode  
1=repeater mode  
1=100M mode  
0=10M mode  
Ignored if Auto negotiation is enabled  
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.  
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.  
• Physical Medium Dependent sublayer (PMD)  
• Auto-Negotiation sublayer  
The ICS1894-32 is transparent to the next layer of the OSI  
model, the link layer. The link layer has two sublayers: the  
Logical Link Control sublayer and the MAC sublayer. The  
ICS1894-32 can interface directly with the MAC via MII/RMII  
interface signals.  
Functional Description  
The ICS1894-32 is an ethernet PHYceiver. During data  
transmission, it accepts sequential nibbles/di-bits from the  
MAC (Media Access Control), converts them into a serial bit  
stream, encodes them, and transmits them over the medium  
through an external isolation transformer. When receiving  
data, the ICS1894-32 converts and decodes a serial bit  
stream (acquired from an isolation transformer that  
interfaces with the medium) into sequential nibbles/di-bits. It  
subsequently presents these nibbles/di-bits to the MAC  
Interface.  
The ICS1894-32 transmits framed packets acquired from its  
MAC Interface and receives encapsulated packets from  
another PHY, which it translates and presents to its MAC  
Interface.  
The ICS1894-32 implements the OSI model’s physical  
layer, consisting of the following, as defined by the ISO/IEC  
8802-3 standard:  
Note: As per the ISO/IEC standard, the  
ICS1894-32 does not affect, nor is it  
affected by, the underlying structure of the  
MAC frame it is conveying.  
• Physical Coding sublayer (PCS)  
• Physical Medium Attachment sublayer (PMA)  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
5
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
to be established and then reported to the ICS1894-32’s  
SME.  
100Base-TX Operation  
During 100Base-TX data transmission, the ICS1894-32  
accepts packets from the MAC and inserts Start-of-Stream  
Delimiters (SSDs) and End-of-Stream Delimiters (ESDs)  
into the data stream. The ICS1894-32 encapsulates each  
MAC frame, including the preamble, with an SSD and an  
ESD. As per the ISO/IEC Standard, the ICS1894-32  
replaces the first octet of each MAC preamble with an SSD  
and appends an ESD to the end of each MAC frame.  
Auto-Negotiation  
The ICS1894-32 conforms to the auto-negotiation protocol,  
defined in Clause 28 of the IEEE 802.3u specification.  
Autonegotiation is enabled by either hardware pin strapping  
(pin 20) or software (register 0h bit 12).  
Auto-negotiation allows link partners to select the highest  
common mode of operation. Link partners advertise their  
capabilities to each other, and then compare their own  
capabilities with those they received from their link partners.  
The highest speed and duplex setting that is common to the  
two link partners is selected as the mode of operation.  
When receiving data from the medium, the ICS1894-32  
removes each SSD and replaces it with the pre-defined  
preamble pattern before presenting the data on the MAC  
Interface. When the ICS1894-32 encounters an ESD in the  
received data stream, signifying the end of the frame, it ends  
the presentation of data on the MAC Interface. Therefore,  
the local MAC receives an unaltered copy of the transmitted  
frame sent by the remote MAC.  
The following list shows the speed and duplex operation  
mode from highest to lowest.  
During periods when MAC frames are being neither  
transmitted nor received, the ICS1894-32 signals and  
detects the IDLE condition on the Link Segment. In the  
100Base-TX mode, the ICS1894-32 transmit channel sends  
a continuous stream of scrambled ones to signify the IDLE  
condition. Similarly, the ICS1894-32 receive channel  
continually monitors its data stream and looks for a pattern  
of scrambled ones. The results of this signaling and  
monitoring provide the ICS1894-32 with the means to  
establish the integrity of the Link Segment between itself  
and its remote link partner and inform its Station  
• Priority 1: 100Base-TX, full-duplex  
• Priority 2: 100Base-TX, half-duplex  
• Priority 3: 10Base-T, full-duplex  
• Priority 4: 10Base-T, half-duplex  
If auto-negotiation is not supported or the ICS1894-32 link  
partner is forced to bypass auto-negotiation, the  
ICS1894-32 sets its operating mode by observing the signal  
at its receiver. This is known as parallel detection, and  
allows the ICS1894-32 to establish link by listening for a  
fixed signal protocol in the absence of auto-negotiation  
advertisement protocol.  
Management Entity (SME) of the link status.  
10Base-T Operation  
MII Management (MIIM) Interface  
During 10Base-T data transmission, the ICS1894-32 inserts  
only the IDL delimiter into the data stream. The ICS1894-32  
appends the IDL delimiter to the end of each MAC frame.  
However, since the 10Base-T preamble already has a  
Start-of-Frame delimiter (SFD), it is not required that the  
ICS1894-32 insert an SSD-like delimiter.  
The ICS1894-32 supports the IEEE 802.3 MII Management  
Interface, also known as the Management Data Input /  
Output (MDIO) Interface. This interface allows upper-layer  
devices to monitor and control the state of the ICS1894-32.  
An external device with MIIM capability is used to read the  
PHY status and/or configure the PHY settings. Additional  
details on the MIIM interface can be found in Clause  
22.2.4.5 of the IEEE 802.3u Specification.  
When receiving data from the medium (such as a  
twisted-pair cable), the ICS1894-32 uses the preamble to  
synchronize its receive clock. When the ICS1894-32  
receive clock establishes lock, it presents the preamble  
nibbles to the MAC Interface.  
The MIIM interface consists of the following:  
• A physical connection that incorporates the clock line  
(MDC) and the data line (MDIO).  
In 10M operations, during periods when MAC frames are  
being neither transmitted nor received, the ICS1894-32  
signals and detects Normal Link Pulses. This action allows  
the integrity of the Link Segment with the remote link partner  
• A specific protocol that operates across the  
aforementioned physical connection that allows an  
external controller to communicate with one or more  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
6
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
ICS1894-32 devices. Each ICS1894-32 device is  
assigned a PHY address between 1 and 7 by the P[4:0]  
strapping pins. P3 and P4 address bits are hardcoded to  
‘0’ in design.  
additional registers are provided for expanded  
functionality.  
The ICS1894-32 supports MIIM in both MII mode and RMII  
mode.  
• An internal addressable set of thirty-one 8-bit MDIO  
registers. Register [0:6] are required, and their functions  
are defined by the IEEE 802.3u Specification. The  
The following table shows the MII Management frame  
format for the ICS1894-32.  
MII Management Frame Format  
Preamble Start of Read/Write PHY Address REG Address  
TA  
Data Bits  
[15:0]  
Idle  
Frame  
OP Code  
Bits [4:0]  
Bits [4:0]  
Read  
Write  
32 1’s  
32 1’s  
01  
10  
01  
00AAA  
RRRRR  
Z0  
10  
DDDDDDDD_DDDDDDDD  
DDDDDDDD_DDDDDDDD  
Z
Z
01  
00AAA  
RRRRR  
Interrupt (INT)  
P2/INT (pin 11) is an optional interrupt signal that is used to  
inform the external controller that there has been a status  
update in the ICS1894-32 PHY register. Register 23 shows  
the status of the various interrupts while register 22 controls  
the enabling/disabling of the interrupts.  
MII Data Interface  
The Media Independent Interface (MII) is specified in  
Clause 22 of the IEEE 802.3u Specification. It provides a  
common interface between physical layer and MAC layer  
devices, and has the following key characteristics:  
• Supports 10Mbps and 100Mbps data rates.  
• Uses a 25MHz reference clock, sourced by the PHY.  
• Provides independent 4-bit wide (nibble) transmit and  
receive data paths.  
• Contains two distinct groups of signals: one for  
transmission and the other for reception.  
The ICS1894-32 is configured for MII mode upon power-up  
or hardware reset with the following:  
• A 25MHz crystal connected to REFIN, REFOUT (pins 30,  
29), or an external 25MHz clock source (oscillator)  
connected to REFIN  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
7
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
MII Signal Definition  
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.  
MII Signal Name  
Direction  
Direction  
Description  
(with respect to PHY, (with respect to MAC)  
ICS1894-32 signal)  
TXCLK  
Output  
Input  
Transmit Clock  
(2.5MHz for 10Mbps; 25MHz for 100Mbps)  
TXEN  
TXD[3:0]  
RXCLK  
Input  
Input  
Output  
Output  
Input  
Transmit Enable  
Transmit Data [3:0]  
Output  
Receive Clock  
(2.5MHz for 10Mbps; 25MHz for 100Mbps)  
RXDV  
RXD[3:0]  
RXER  
Output  
Output  
Output  
Input  
Receive Data Valid  
Receive Data [3:0]  
Receive Error  
Input  
Input, or (not required)  
• In 10Mbps mode, RXCLK is recovered from the line while  
carrier is active. RXCLK is derived from the PHY’s  
reference clock when the line is idle, or link is down.  
Transmit Clock (TXCLK)  
TXCLK is sourced by the PHY. It is a continuous clock that  
provides the timing reference for TXEN and TXD[3:0].  
TXCLK is 2.5MHz for 10Mbps operation and 25MHz for  
100Mbps operation.  
• In 100Mbps mode, RXCLK is continuously recovered  
from the line. If link is down, RXCLK is derived from the  
PHY’s reference clock.  
Transmit Enable (TXEN)  
RXCLK is 2.5MHz for 10Mbps operation and 25MHz for  
100Mbps operation.  
TXEN indicates the MAC is presenting nibbles on TXD[3:0]  
for transmission. It is asserted synchronously with the first  
nibble of the preamble and remains asserted while all  
nibbles to be transmitted are presented on the MII, and is  
negated prior to the first TXCLK following the final nibble of  
a frame. TXEN transitions synchronously with respect to  
TXCLK.  
Receive Data Valid (RXDV)  
RXDV is driven by the PHY to indicate that the PHY is  
presenting recovered and decoded nibbles on RXD[3:0].  
• In 10Mbps mode, RXDV is asserted with the first nibble of  
the SFD (Start of Frame Delimiter), and remains asserted  
until the end of the frame.  
Transmit Data (TXD[3:0])  
TXD[3:0] transitions synchronously with respect to TXCLK.  
When TXEN is asserted, TXD[3:0] are accepted for  
transmission by the PHY. TXD[3:0] is ”00” to indicate idle  
when TXEN is de-asserted. Values other than “00” on  
TXD[3:0] while TXEN is de-asserted are ignored by the  
PHY.  
• In 100Mbps mode, RXDV is asserted from the first nibble  
of the preamble to the last nibble of the frame.  
RXDV transitions synchronously with respect to RXCLK.  
Receive Data (RXD[3:0])  
RXD[3:0] transitions synchronously with respect to RXC.  
For each clock period in which RXDV is asserted, RXD[3:0]  
transfers a nibble of recovered data from the PHY.  
Receive Clock (RXCLK)  
RXCLK provides the timing reference for RXDV, RXD[3:0],  
and RXER.  
Receive Error (RXER)  
RXER is asserted for one or more RXCLK periods to  
indicate that an error (e.g. a coding error or any error that a  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
8
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
PHY is capable of detecting, and that may otherwise be  
undetectable by the MAC sub-layer) was detected  
somewhere in the frame presently being transferred from  
the PHY. RXER transitions synchronously with respect to  
RXC. While RXDV is de-asserted, RXER has no effect on  
the MAC.  
Reduced MII (RMII) Data Interface  
The Reduced Media Independent Interface (RMII) specifies  
a low pin count Media Independent Interface (MII). It  
provides a common interface between physical layer and  
MAC layer devices, and has the following key  
characteristics:  
• Supports 10Mbps and 100Mbps data rates.  
• Uses a single 50MHz reference clock provided by the  
MAC or the system board.  
• Provides independent 2-bit wide (di-bit) transmit and  
receive data paths.  
• Contains two distinct groups of signals: one for  
transmission and the other for reception.  
In RMII mode, a 50 MHz reference clock is connected to  
REFIN(pin 30).  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
9
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
RMII Signal Definition  
The following table describes the RMII signals. Refer to RMII Specification for detailed information.  
RMII Signal Name  
Direction  
Direction  
Description  
(with respect to PHY, (with respect to MAC)  
ICS1894-32 signal)  
REFIN  
Input  
Input or Output  
Synchronous 50 MHz clock reference for  
receive, transmit and control interface  
TX_EN  
TXD[1:0]  
Input  
Input  
Output  
Transmit Enable  
Output  
Transmit Data [1:0]  
Receive Data [1:0]  
Receive Error  
RXD[1:0  
Output  
Output  
Output  
Input  
RX_ER  
Input, or (not required)  
Input  
CRS_DV[RXDV]  
Carrier Sense/Data Valid  
Loss of carrier shall result in the deassertion of CRS_DV  
synchronous to the cycle of REFIN which presents the first  
di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted  
only on nibble boundaries). If the PHY has additional bits to  
be presented on RXD[1:0] following the initial deassertion of  
CRS_DV, then the PHY shall assert CRS_DV on cycles of  
REFIN which present the second di-bit of each nibble and  
deassert CRS_DV on cycles of REFIN which present the  
first di-bit of a nibble. The result is: Starting on nibble  
boundaries CRS_DV toggles at 25 MHz in 100Mb/s mode  
and 2.5 MHz in 10Mb/s mode when the Carrier event ends  
before the RX_DV signal internal to the PHY is deasserted  
(i.e. the FIFO still has bits to transfer when the carrier event  
ends.) Therefore, the MAC can accurately recover RX_DV  
and the Carrier event end time. During a false carrier event,  
CRS_DV shall remain asserted for the duration of carrier  
activity.  
Reference Clock (REFIN)  
REFIN is sourced by the MAC or system board. It is a  
continuous 50MHz clock that provides the timing reference  
for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.  
Transmit Enable (TX_EN)  
TX_EN indicates that the MAC is presenting di-bits on  
TXD[1:0] for transmission. It is asserted synchronously with  
the first nibble of the preamble and remains asserted while  
all di-bits to be transmitted are presented on the RMII, and  
is negated prior to the first REFIN following the final di-bit of  
a frame. TX_EN transitions synchronously with respect to  
REFIN.  
Transmit Data [1:0] (TXD[1:0])  
TXD[1:0] transitions synchronously with respect to REFIN.  
When TX_EN is asserted, TXD[1:0] are accepted for  
transmission by the PHY. TXD[1:0] is ”00” to indicate idle  
when TX_EN is de-asserted. Values other than “00” on  
TXD[1:0] while TX_EN is de-asserted are ignored by the  
PHY.  
The data on RXD[1:0] is considered valid once CRS_DV is  
asserted. However, since the assertion of CRS_DV is  
asynchronous relative to REFIN, the data on RXD[1:0] shall  
be "00" until proper receive signal decoding takes place (see  
definition of RXD[1:0] behavior).  
Carrier Sense/Data Valid (CRS_DV[RXDV])  
*Note: CRS_DV is asserted asynchronously in order to  
minimize latency of control signals through the PHY.  
CRS_DV, identified as RXDV (pin 18), shall be asserted by  
the PHY when the receive medium is non-idle. The specifics  
of the definition of idle for 10BASE-T and 100BASE-X are  
contained in IEEE 802.3 [1] and IEEE 802.3u [2]. CRS_DV  
is asserted asynchronously on detection of carrier due to  
the criteria relevant to the operating mode. That is, in  
10BASE-T mode, when squelch is passed or in 100BASE-X  
mode when 2 non-contiguous zeroes in 10 bits are detected  
carrier is said to be detected.  
Receive Data [1:0] (RXD[1:0])  
RXD[1:0] transitions synchronously to REFIN. For each  
clock period in which CRS_DV is asserted, RXD[1:0]  
transfers two bits of recovered data from the PHY. RXD[1:0]  
is "00" to indicate idle when CRS_DV is de-asserted. Values  
other than “00” on RXD[1:0] while CRS_DV is de-asserted  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 10  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
are ignored by the MAC.  
cross  
transmit = TP_BP & TP_BN  
receive = TP_AP & TP_AN  
AMDIX_EN (Pin 14) AMDIX enable pin with 20 kOhm  
Receive Error (RX_ER)  
pull-up resistor  
RX_ER is asserted for one or more REFIN periods to  
indicate that an error (e.g. a coding error or any error that a  
PHY is capable of detecting, and that may otherwise be  
undetectable by the MAC sub-layer) was detected  
somewhere in the frame presently being transferred from  
the PHY. RX_ER transitions synchronously with respect to  
REFIN. While CRS_DV is de-asserted, RX_ER has no  
effect on the MAC.  
AMDIX_EN [19:9] MDIO register 19h bit 9  
MDI_MODE [19:8] MDIO register 19h bit 8  
Auto-MDI/MDIX Crossover  
The ICS1894-32 includes the auto-MDI/MDIX crossover  
feature. In a typical CAT 5 Ethernet installation the transmit  
twisted pair signal pins of the RJ45 connector are crossed  
over in the CAT 5 wiring to the partners receive twisted pair  
signal pins and receive twisted pair to the partners transmit  
twisted pair. This is usually accomplished in the wiring plant.  
Hubs generally wire the RJ45 connector crossed to  
accomplish the crossover. Two types of CAT 5 cables  
(straight and crossed) are available to achieve the correct  
connection. The Auto-MDI/MDIX feature automatically  
corrects for miss-wired installations by automatically  
swapping transmit and receive signal pairs at the PHY when  
no link results. Auto-MDI/MDIX is automatic, but may be  
disabled for test purposes by writing MDIO register 19 Bits  
9:8 in the MDIO register. The Auto-MDI/MDIX function is  
independent of Auto-Negotiation and preceeds  
Auto-Negotiation when enabled.  
Auto MDI/MDIX Table  
AMDIX_EN AMDIX_EN MDI_MODE  
Tx/Rx MDI  
(pin 14)  
[Reg 19:9]  
[Reg 19:8]  
Configuration  
x
x
0
1
0
0
1
1
0
1
x
x
straight  
cross  
straight  
straight/cross (auto  
select)  
Default  
1
1
0
straight/cross (auto  
select)  
Definitions:  
straight  
transmit = TP_AP & TP_AN  
receive = TP_BP & TP_BN  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 11  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Power Management  
The ICS1894-32 supports a Deep Power Mode (DPD) that  
is enabled under the following conditions:  
1. The Phy is not Receiving any signal from the partner (Link  
Down)  
2. The MAC is not transmitting data to the Phy (TXEN Low)  
Once the above conditions are met, the Phy goes into DPD  
mode after 32s (typical).  
The logic internal to the device can be selectively shut down  
in DPD mode depending on Register 24 Bits 8-4.  
Block Diagram of the Different Sections of the PHY as Affected by Register 24 bits  
Reference Clock  
TPLL  
Controlled by Register 24.7  
10/100M Drive Clock  
TX_STRUCTURE  
XMIT_DAC  
Controlled  
by Register  
24.5  
RX and  
Equalizer  
Controlled by  
Register 24.6  
OUT  
IN  
If XMIT_DAC is  
powered down,  
this block is  
High_Z  
CDR  
Controlled by  
Register 24.4  
Bias for 10/100M  
Vbg  
Bias for Rx  
BGAP  
Bias Current  
Clock Reference Interface  
The REFIN pin provides the ICS1894-32 Clock Reference  
Interface. The ICS1894-32 requires a single clock reference  
with a frequency of 25 MHz 50 parts per million. This  
accuracy is necessary to meet the interface requirements of  
the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1  
and 24.2.3.4. The ICS1894-32 supports two clock source  
configurations: a CMOS oscillator or a CMOS driver. The  
input to REFIN is CMOS (10% to 90% VDD), not TTL.  
Alternately, a 25MHz crystal may be used.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 12  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Crystal or Oscillator Connection  
ICS1894CK-32  
MII w/ Crystal Input  
REFOUT  
29  
REFIN  
30  
25.000MHz  
25 pF  
25 pF  
ICS1894CK-32  
REFOUT  
REFIN  
30  
MII w/ Oscillator Input  
29  
NC  
33 Ohm (optional)  
CMOS  
25.000  
MHz  
10 pF (optional)  
ICS1894CK-32  
REFOUT  
29  
REFIN  
30  
RMII w/ Oscillator Input  
NC  
33 Ohm (optional)  
CMOS  
50.000  
MHz  
10 pF (optional)  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 13  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
If a crystal is used as the clocking source, connect it to both  
the REFIN (pin 30) and REFOUT (pin 29) pins of the  
ICS1894-32. A pair of bypass capacitors on either side of  
the crystal are connected to ground. The crystal is used in  
the parallel resonance or anti-resonance mode. The value  
of the load caps serve to adjust the final frequency of the  
crystal oscillation. Typical applications would use 25 pF load  
caps. The exact value will be affected by the board routing  
capacitance on REFIN and REFOUT pins. Smaller load  
capacitors raise the frequency of oscillation.  
Once the exact value of load capacitance is established it  
will be the same for all boards using the same specification  
crystal. The best way to measure the crystal frequency is to  
measure the frequency of TXCLK (pin 22) using a frequency  
counter with a 1 second gate time. Using the buffered output  
TXCLK prevents the crystal frequency from being affected  
by the measurement. The crystal specification is shown in  
the 25MHz Crystal Specification table.  
25 MHz Crystal Specification Table  
Specifications  
Symbol Minimum  
Typical Maximum  
Unit  
MHz  
ppm  
pF  
Fundamental Frequency  
Freq. Tolerance  
F0  
24.99875 25.00000 25.00125  
∆F/f  
Cin  
50  
Input Capacitance  
3
25 MHz Oscillator Specification table  
Specifications  
Symbol Minimum  
Typical Maximum  
Unit  
MHz  
ppm  
%
Output Frequency  
Freq. Stability (including aging)  
Duty cycle CMOS level one-half VDD  
VIH  
F0  
24.99875 25.00000 25.00125  
50  
∆F/f  
Tw/T  
35  
65  
2.79  
Volts  
Volts  
pS  
VIL  
0.33  
500  
Period Jitter  
Tjitter  
CIN  
Input Capacitance  
3
pF  
50 MHz Oscillator Specification table  
Specifications  
Symbol Minimum  
Typical Maximum  
Unit  
MHz  
ppm  
%
Output Frequency  
Freq. Stability (including aging)  
Duty cycle CMOS level one-half VDD  
VIH  
F0  
49.9975 50.00000  
50.0025  
50  
∆F/f  
Tw/T  
35  
65  
2.79  
Volts  
Volts  
pS  
VIL  
0.33  
Period Jitter  
Tjitter  
CIN  
500  
Input Capacitance  
3
pF  
intended for driving LEDs. Configuration is set by Bank0  
Register 20.  
Status Interface  
The ICS1894-32 has two multi-function configuration pins  
that report the PHY status by providing signals that are  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 14  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
resistors to provide a designated status indicator as  
described in the Pins for Monitoring the Data Link table. Use  
1KΩ resistors.  
Pins for Monitoring the Data Link table  
Pin  
Status Events that drive the LEDs  
Caution: Pins listed in the Pins for Monitoring the Data Link  
table must not float.  
P0/LED0 Link, Activity, Tx, Rx, COL, Mode, Dplx  
P1/LED1 Link, Activity, Tx, Rx, COL, Mode, Dplx  
4. As outputs, the asserted state of a multi-function  
configuration pin is the inverse of the sense sampled during  
reset. This inversion provides a signal that can illuminate an  
LED during an asserted state. For example, if a  
multi-function configuration pin is pulled down to ground  
through an LED and a current-limiting resistor, then the  
sampled sense of the input is low. To illuminate this LED for  
the asserted state, the output is driven high.  
Note:  
1. During either power-on reset or hardware reset, each  
multi-function configuration pin is an input that is sampled  
when the ICS1894-32 exits the reset state. After sampling is  
complete, these pins are output pins that can drive status  
LEDs.  
2. A software reset does not affect the state of a  
multi-function configuration pin. During a software reset, all  
multi-function configuration pins are outputs.  
5. Adding 10KΩresistors across the LEDs ensures the PHY  
address is fully defined during slow VDD power-ramp  
conditions.  
3. Each multi-function configuration pin must be pulled  
either up or down with a resistor to establish the address of  
the ICS1894-32. LEDs may be placed in series with these  
6. PHY address 00 tri-states the MII interface. (Do not select  
PHY address 00 unless you want the MII tri-stated.)  
The following figure shows typical biasing and LED connections for the ICS1894-32.  
ICS1894CK-32  
P1/LED1  
32  
P0/LED0  
31  
VDD  
1KΩ  
LED1  
10KΩ  
LED0  
10KΩ  
1KΩ  
The above circuit decodes the PHY address = 1  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 15  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Register Map  
Register Address  
Register Name  
Basic / Extended  
Basic  
0
Control  
1
Status  
Basic  
2,3  
PHY Identifier  
Extended  
Extended  
Extended  
Extended  
Extended  
Extended  
Extended  
Extended  
4
Auto-Negotiation Advertisement  
Auto-Negotiation Link Partner Ability  
Auto-Negotiation Expansion  
5
6
7
Auto-Negotiation Next Page Transmit  
Auto-Negotiation Next Page Link Partner Ability  
Reserved by IEEE  
8
9 through 15  
16 through 31  
Vendor-Specific (IDT) Registers  
Register Description  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Register 0h - Control  
0.15  
0.14  
0.13  
0.12  
0.11  
0.10  
0.9  
Reset  
No effect  
Disable Loopback mode Enable Loopback mode  
10 Mbps operation 100 Mbps operation  
Reset mode  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
SC  
–
0
0
3
Loopback enable  
Speed select1  
–
1
Auto-Negotiation enable DisableAuto-Negotiation Enable Auto-Negotiation  
–
1
Low-power mode  
Isolate  
Normal power mode  
No effect  
Low-power mode  
–
0
0/4†  
Isolate from MII  
–
0/1†  
0
Auto-Negotiation restart No effect  
Restart Auto-Negotiation  
SC  
–
0.8  
Duplex mode1  
Half-duplex operation  
Full-duplex operation  
0
0.7  
Collision test  
No effect  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Enable collision test  
–
0
0
0.6  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
–
0‡  
0‡  
0‡  
0‡  
0‡  
0‡  
0‡  
0.5  
–
0.4  
–
0.3  
–
0
0.2  
–
0.1  
–
0.0  
–
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 16  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Register 1h - Control  
1.15  
100Base-T4  
Always 0. (Not  
N/A  
RO  
–
0
7
supported.)  
1.14  
1.13  
1.12  
1.11  
1.10  
1.9  
100Base-TX full duplex  
Mode not supported  
Mode supported  
Mode supported  
Mode supported  
Mode supported  
N/A  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
RO  
–
–
–
–
–
–
–
–
–
1
1
100Base-TX half duplex Mode not supported  
10Base-T full duplex  
10Base-T half duplex  
IEEE reserved  
Mode not supported  
Mode not supported  
Always 0  
1
1
8
0
0†  
0†  
0†  
0†  
0
IEEE reserved  
Always 0  
N/A  
1.8  
IEEE reserved  
Always 0  
N/A  
1.7  
IEEE reserved  
Always 0  
N/A  
1.6  
MF Preamble  
suppression  
PHY requires MF  
Preambles  
PHY does not require MF  
Preambles  
1.5  
Auto-Negotiation  
complete  
Auto-Negotiation is in  
process, if enabled  
Auto-Negotiation is  
completed  
RO  
LH  
0
1.4  
1.3  
Remote fault  
No remote fault detected Remote fault detected  
RO  
RO  
LH  
–
0
1
Auto-Negotiation ability  
N/A  
Always 1: PHY has  
9
Auto-Negotiation ability  
1.2  
1.1  
1.0  
Link status  
Link is invalid/down  
No jabber condition  
N/A  
Link is valid/established  
Jabber condition detected  
RO  
RO  
RO  
LL  
LH  
–
0
0
1
Jabber detect  
Extended capability  
Always 1: PHY has  
extended capabilities  
Register 2h - PHY Identifier  
2.15  
2.14  
2.13  
2.12  
2.11  
2.10  
2.9  
OUI bit 3 | c  
OUI bit 4 | d  
OUI bit 5 | e  
OUI bit 6 | f  
OUI bit 7 | g  
OUI bit 8 | h  
OUI bit 9 | I  
OUI bit 10 | j  
OUI bit 11 | k  
OUI bit 12 | l  
OUI bit 13 | m  
OUI bit 14 | n  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
2.8  
2.7  
2.6  
2.5  
2.4  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 17  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
2.3  
2.2  
2.1  
2.0  
Definition  
OUI bit 15 | o  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
–
–
–
–
0
1
0
1
5
OUI bit 16 | p  
OUI bit 17 | q  
OUI bit 18 | r  
Register 3h - PHY Identifier  
3.15  
3.14  
3.13  
3.12  
3.11  
3.10  
3.9  
OUI bit 19 | s  
OUI bit 20 | t  
OUI bit 21 | u  
OUI bit 22 | v  
OUI bit 23 | w  
OUI bit 24 | x  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
–
–
–
–
–
–
–
1
1
1
1
0
1
0
F
4
Manufacturer’s Model  
Number bit 5  
3.8  
3.7  
3.6  
3.5  
3.4  
Manufacturer’s Model  
Number bit 4  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
CW  
–
–
–
–
–
0
0
1
0
1
Manufacturer’s Model  
Number bit 3  
5
Manufacturer’s Model  
Number bit 2  
Manufacturer’s Model  
Number bit 1  
Manufacturer’s Model  
Number bit 0  
3.3  
3.2  
3.1  
3.0  
Revision Number bit 3  
Revision Number bit 2  
Revision Number bit 1  
Revision Number bit 0  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
–
–
–
–
0
0
0
0
0
Register 4h - Auto-Negotiation Advertisement  
4.15  
4.14  
4.13  
Next Page  
Next page not supported Next page supported  
R/W  
CW  
–
–
–
0
0†  
0
0
1
IEEE reserved  
Remote fault  
Always 0  
N/A  
Locally, no faults  
detected  
Local fault detected  
R/W  
4.12  
4.11  
4.10  
4.9  
IEEE reserved  
IEEE reserved  
IEEE reserved  
100Base-T4  
Always 0  
Always 0  
Always 0  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
–
–
–
–
0†  
0†  
0†  
0
Always 0. (Not  
supported.)  
4.8  
100Base-TX, full duplex Do not advertise ability  
Advertise ability  
R/W  
–
1
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 18  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
4.7  
4.6  
4.5  
4.4  
Definition  
When Bit = 0  
When Bit = 1  
Advertise ability  
Access 2 SF2  
Default3  
Hex  
100Base-TX, half duplex Do not advertise ability  
R/W  
R/W  
R/W  
CW  
–
–
–
–
1
1
1
0
E
10Base-T, full duplex  
10Base-T half duplex  
Selector Field bit S4  
Do not advertise ability  
Do not advertise ability  
Advertise ability  
Advertise ability  
N/A  
IEEE 802.3-specified  
default  
4.3  
4.2  
4.1  
4.0  
Selector Field bit S3  
Selector Field bit S2  
Selector Field bit S1  
Selector Field bit S0  
IEEE 802.3-specified  
default  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
–
–
–
–
0
0
0
1
1
IEEE 802.3-specified  
default  
IEEE 802.3-specified  
default  
N/A  
IEEE 802.3-specified  
default  
Register 5h - Auto-Negotiation Link Partner Ability  
5.15  
5.14  
5.13  
5.12  
5.11  
5.10  
5.9  
Next Page  
Next Page disabled  
Always 0  
Next Page enabled  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
–
–
–
–
–
–
–
0
0
0
0
Acknowledge  
Remote fault  
IEEE reserved  
IEEE reserved  
IEEE reserved  
100Base-T4  
N/A  
No faults detected  
Always 0  
Remote fault detected  
0
N/A  
N/A  
N/A  
N/A  
0†  
0†  
0†  
0
Always 0  
Always 0  
Always 0. (Not  
supported.)  
5.8  
5.7  
5.6  
5.5  
5.4  
5.3  
5.2  
5.1  
5.0  
100Base-TX, full duplex Link partner is not  
capable  
Link partner is capable  
RO  
RO  
RO  
RO  
RO  
CW  
CW  
CW  
CW  
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
100Base-TX, half duplex Link partner is not  
capable  
Link partner is capable  
0
10Base-T, full duplex  
10Base-T, half duplex  
Selector Field bit S4  
Selector Field bit S3  
Selector Field bit S2  
Selector Field bit S1  
Selector Field bit S0  
Link partner is not  
capable  
Link partner is capable  
Link partner is not  
capable  
Link partner is capable  
IEEE 802.3 defined.  
Always 0.  
N/A  
N/A  
N/A  
N/A  
IEEE 802.3 defined.  
Always 0.  
0
IEEE 802.3 defined.  
Always 0.  
IEEE 802.3 defined.  
Always 0.  
N/A  
IEEE 802.3 defined.  
Always 1.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 19  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Register 6h - Auto-Negotiation Expansion  
6.15  
6.14  
6.13  
6.12  
6.11  
6.10  
6.9  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
IEEE reserved  
Parallel detection fault  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
Always 0  
No Fault  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
CW  
RO  
–
–
0†  
0†  
0†  
0†  
0†  
0†  
0†  
0†  
0†  
0†  
0†  
0
0
–
–
–
0
0
–
–
6.8  
–
6.7  
–
6.6  
–
6.5  
–
6.4  
Multiple technologies  
detected  
LH  
6.3  
6.2  
Link partner Next Page  
able  
Link partner is not Next  
Page able  
Link partner is Next Page  
able  
RO  
RO  
–
–
0
1
4
Next Page able  
Local device is not Next Local device is Next Page  
Page able  
able  
6.1  
6.0  
Page received  
Next Page not received  
Next Page received  
RO  
RO  
LH  
–
0
0
Link partner  
Link partner is not  
Link partner is  
Auto-Negotiation able  
Auto-Negotiation able  
Auto-Negotiation able  
Register 7h - Auto-Negotiation Next Page Transmit  
7.15  
7.14  
7.13  
7.12  
Next Page  
Last Page  
Additional Pages follow  
N/A  
RW  
RO  
RW  
RW  
–
–
–
–
0
0†  
1
2
0
IEEE reserved  
Message Page  
Acknowledge 2  
Always 0  
Unformatted Page  
Message Page  
Cannot comply with  
Message  
Can comply with Message  
0
7.11  
7.10  
7.9  
Toggle  
Previous Link Code  
Word was zero  
Previous Link Code Word  
was one  
RO  
RW  
RW  
RW  
–
–
–
–
0
0
0
0
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
7.8  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 20  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
7.7  
7.6  
7.5  
7.4  
7.3  
7.2  
7.1  
7.0  
Message code field  
/Unformatted code field  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
1
0
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
1
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
Register 8h - Auto-Negotiation Next Page Link Partner Ability  
8.15  
8.14  
8.13  
8.12  
Next Page  
Last Page  
Additional Pages follow  
N/A  
RO  
RO  
RO  
RO  
–
–
–
–
0
0†  
0
0
0
IEEE reserved  
Message Page  
Acknowledge 2  
Always 0  
Unformatted Page  
Message Page  
Cannot comply with  
Message  
Can comply with Message  
0
8.11  
8.10  
8.9  
8.8  
8.7  
8.6  
8.5  
8.4  
Toggle  
Previous Link Code  
Word was zero  
Previous Link Code Word  
was one  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
RO  
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
0
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
Message code field  
/Unformatted code field  
Bit value depends on the Bit value depends on the  
particular message particular message  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 21  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
particular message particular message  
Bit value depends on the Bit value depends on the  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
8.3  
8.2  
8.1  
8.0  
Message code field  
/Unformatted code field  
RO  
RO  
RO  
RO  
–
–
–
–
0
0
0
0
0
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
Message code field  
/Unformatted code field  
particular message  
particular message  
Register 9 through 15h - Reserved by IEEE  
Register 16h - Extended Control Register  
16.15  
Command Override  
Write enable  
Disabled  
Enabled  
RW  
SC  
0
–
16.14  
16.13  
16.12  
16.11  
16.10  
16.9  
ICS reserved  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
RW/0  
RW/0  
RW/0  
RW/0  
RO  
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
L
L
L
0
ICS reserved  
ICS reserved  
ICS reserved  
–
–
PHY Address Bit 4  
PHY Address Bit 3  
PHY Address Bit 2  
PHY Address Bit 1  
PHY Address Bit 0  
RO  
16.8  
RO  
16.7  
RO  
16.6  
RO  
16.5  
Stream Cipher Test  
Mode  
Normal operation  
Test mode  
RW  
16.4  
16.3  
16.2  
16.1  
16.0  
ICS reserved  
Read unspecified  
NRZ encoding  
Read unspecified  
NRZI encoding  
Enabled  
RW/0  
RW  
–
–
–
–
–
–
1
0
0
0
NRZ/NRZI encoding  
Transmit invalid codes  
ICS reserved  
8
–
Disabled  
RW  
Read unspecified  
Stream Cipher enabled  
Read unspecified  
Stream Cipher disabled  
RW/0  
RW  
Stream Cipher disable  
Register 17h - Quick Poll Detailed Status Register  
17.15  
17.14  
17.13  
Data rate  
Duplex  
10 Mbps  
100 Mbps  
RO  
RO  
RO  
–
–
–
–
0
Half duplex  
Full duplex  
Auto-Negotiation  
Progress Monitor Bit 2  
Reference Decode Table Reference Decode Table  
LM  
X
17.12  
Auto-Negotiation  
Progress Monitor Bit 1  
Reference Decode Table Reference Decode Table  
RO  
LM  
X
0
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 22  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
17.11  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Auto-Negotiation  
Progress Monitor Bit 0  
Reference Decode Table Reference Decode Table  
RO  
LM  
X
0
0
17.10  
17.9  
17.8  
17.7  
17.6  
17.5  
100Base-TX signal lost  
Valid signal  
Signal lost  
RO  
RO  
RO  
RO  
RO  
RO  
LH  
LH  
LH  
LH  
LH  
LH  
0
0
0
0
0
0
100BasePLL Lock Error PLL locked  
False Carrier detect Normal Carrier or Idle  
PLL failed to lock  
False Carrier  
Invalid symbol detected Valid symbols observed Invalid symbol received  
Halt Symbol detected No Halt Symbol received Halt Symbol received  
Premature End detected Normal data stream  
0
0
Stream contained two  
IDLE symbols  
17.4  
17.3  
Auto-Negotiation  
complete  
Auto-Negotiation in  
process  
Auto-Negotiation  
complete  
RO  
RO  
–
–
0
0
100Base-TX signal  
detect  
Signal present  
No signal present  
17.2  
17.1  
17.0  
Jabber detect  
Remote fault  
Link Status  
No jabber detected  
Jabber detected  
RO  
RO  
RO  
LH  
LH  
LL  
0
0
0
No remote fault detected Remote fault detected  
Link is not valid  
Link is valid  
Register 18h - 10Base-T Operations Register  
18.15  
Remote Jabber Detect  
No Remote Jabber  
Condition detected  
Remote Jabber Condition  
Detected  
RO  
LH  
0
–
18.14  
18.13  
18.12  
Polarity reversed  
Data Bus Mode  
Normal polarity  
Polarity reversed  
RO  
R0  
R0  
LH  
–
0
–
L
Bit18.13 is latched pin RXTRI  
Bit18.12 is latched SI  
[1x]=RMII mode  
–
[01]=SI mode (Serial interface mode)  
[00]=MII mode  
18.11  
18.10  
AMDIXEN  
RXTRI  
AMDIX disable  
AMDIX enable  
RW  
RW  
–
–
L
L
–
RX output enable  
RX tri-state for MII/RMII  
interface  
18.9  
REGEN  
Vender reserved register Vender reserved register  
RW  
–
L
access enable  
(byte25~byte31) access  
disable  
18.8  
18.7  
18.6  
18.5  
18.4  
TM_SWITCH  
ICS reserved  
ICS reserved  
Jabber inhibit  
ICS reserved  
Switch TMUX2 to TMUX1, test control  
RW  
RW/0  
RW/0  
RW  
–
–
–
–
–
0
–
–
0
1
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
–
Normal Jabber behavior Jabber Check disabled  
Read unspecified Read unspecified  
RW/1  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 23  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
18.3  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Auto polarity inhibit  
Polarity automatically  
corrected  
Polarity not automatically  
corrected  
RW  
RW  
RW  
RW  
–
–
–
–
0
0
0
0
0
18.2  
18.1  
18.0  
SQE test inhibit  
Link Loss inhibit  
Squelch inhibit  
Normal SQE test  
behavior  
SQE test disabled  
Normal Link Loss  
behavior  
Link Always = Link Pass  
Normal squelch behavior No squelch  
Register 19h - Extended Control Register  
19.15  
19.14  
Node Mode  
Node mode  
Repeater mode  
RW  
RW  
–
–
L
L
–
2
Hardware/Software  
Mode Speed Select  
Use bit00.13 to select  
speed  
Use real time input pin 22  
only to select speed  
19.13  
19.12  
19.11  
Remote Fault  
No faults detected  
Remote fault detected  
RO  
RW  
RW  
–
–
–
0
0
0
Register Bank select  
[01]=Bank1, access register0x00~0x13 and  
ICS1893CF registers 0x14~0x1F  
[00]=Bank0, access register0x00~0x13, new defined  
registers 0x14~0x25  
[1x]=Bank0, same as [00]  
19.10  
19.9  
19.8  
19.7  
ICS reserved  
AMDIX_EN  
MDI_MODE  
Read unspecified  
Read unspecified  
RO  
RW  
RW  
RW  
–
–
–
–
0
1
0
0
See Table on page 11  
See Table on page 11  
See Table on page 11  
See Table on page 11  
Twisted Pair Tri-State  
Enable, TPTRI  
Twisted Pair Signals are Twisted Pair Signals are  
not Tri-Stated or No  
effect  
0
1
Tri-Stated  
19.6  
19.5  
19.4  
19.3  
19.2  
19.1  
19.0  
ICS reserved  
ICS reserved  
ICS reserved  
ICS reserved  
ICS reserved  
ICS reserved  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Power down automatically  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
–
–
–
–
–
–
–
0
0
0
0
0
0
1
Automatic 100Base-TX  
Power Down  
Do not automatically  
power down  
Register 20h - Extended Control Register  
20.15  
Str_enhance  
Normal digital output  
strength  
Enhance digital output  
strength in 1.8V condition  
RW  
0
3
20.14  
20.13  
20.12  
ICS reserved  
ICS reserved  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
RW  
RW  
–
–
0
1
1
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 24  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
20.11  
20.10  
20.9  
20.8  
20.7  
20.6  
Definition  
ICS reserved  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Read unspecified  
Read unspecified  
RW  
–
1
1
1
1
1
1
F
LED2 Mode  
LED1 Mode  
LED0 Mode  
000 = Link Integrity  
001 = activity/no activity  
010 = Transmit Data  
011 = Receive Data  
100 = Collision  
101 = 10/100 mode  
110 = Full Duplex  
111 = OFF (Default LED2)  
RW  
E
20.5  
20.4  
20.3  
000 = Link Integrity  
001 = activity/no activity  
010 = Transmit Data  
011 = Receive Data  
100 = Collision  
101 = 10/100 mode (Default LED1)  
110 = Full Duplex  
111 = OFF  
RW  
1
0
1
9
20.2  
20.1  
20.0  
000 = Link Integrity  
001 = activity/no activity (Default LED0)  
010 = Transmit Data  
011 = Receive Data  
100 = Collision  
RW  
0
0
1
101 = 10/100 mode  
110 = Full Duplex  
111 = LINK_STAT  
Register 21h - Extended Control Register  
21.15:0 RXER_CNT  
Receive error count for RMII mode  
RW  
0
0
Register 22h - Extended Control Register  
22.15  
22.14  
Interrupt output enable Disable interrupt output  
Enable interrupt output  
RW  
RW  
0
0
Interrupt flag read clear Interrupt flag clear by  
Interrupt flag clear by read  
enable  
enable  
read disable  
22.13  
22.12  
Interrupt polarity  
Output low when  
interrupt occur  
Output high when  
interrupt occur  
RW  
RW  
0
0
Interrupt flag auto clear Interrupt flag unchanged Interrupt flag cleared  
enable when interrupt condition when interrupt condition  
removed removed  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 25  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
22.11  
Interrupt flag re-setup  
enable  
Interrupt flag always  
cleared when write 1 to  
flag bit  
Interrupt flag remains  
unchanged when  
interrupt condition exists  
when a 1 is written to flag  
bit.  
RW  
0
0
22.10  
22.9  
22.8  
Interrupt Enable  
Interrupt Enable  
Interrupt Enable  
Disable Deep power  
down wake up Interrupt  
Enable Deep power down  
wake up Interrupt  
RW  
RW  
RW  
0
0
0
Disable Deep power  
down Interrupt  
Enable Deep power down  
Interrupt  
DisableAuto-Negotiation Enable Auto-Negotiation  
Complete Interrupt Complete Interrupt  
22.7  
22.6  
Interrupt Enable  
Interrupt Enable  
Disable Jabber Interrupt Enable Jabber Interrupt  
RW  
RW  
0
0
0
0
Disable Receive Error  
Interrupt  
Enable Receive Error  
Interrupt  
22.5  
22.4  
22.3  
22.2  
22.1  
22.0  
Interrupt Enable  
Interrupt Enable  
Interrupt Enable  
Interrupt Enable  
Interrupt  
Disable Page Received  
Interrupt  
Enable Page Received  
Interrupt  
RW  
RW  
RW  
RW  
RW  
RW  
0
0
0
0
0
0
Disable Parallel Detect  
Fault Interrupt  
Enable Parallel Detect  
Fault Interrupt  
Disable Link Partner  
Enable Link Partner  
Acknowledge Interrupt  
Acknowledge Interrupt  
Disable Link Down  
Interrupt  
Enable Link Down  
Interrupt  
Disable Remote Fault  
Interrupt  
Enable Remote Fault  
Interrupt  
Enable  
Disable Link Up Interrupt Enable Link Up Interrupt  
Register 23h - Extended Control Register  
23.15:11  
23.10  
Reserved  
Reserved  
RO  
0
0
0
0
Deep power down wake Deep power down wake Deep power down wake  
RO/SC  
up Interrupt  
up did not occur  
up occurred  
23.9  
23.8  
Deep power down  
Interrupt  
Deep power down did  
not occur  
Deep power down  
occurred  
RO/SC  
RO/SC  
0
0
Auto-Negotiation  
Interrupt  
Auto-Negotiation  
Complete did not occur  
Auto-Negotiation  
Complete occurred  
23.7  
23.6  
Jabber Interrupt  
Jabber did not occur  
Jabber occurred  
RO/SC  
RO/SC  
0
0
0
Receive Error Interrupt Receive Error did not  
occur  
Receive Error occurred  
23.5  
23.4  
Page Receive Interrupt Page Receive did not  
occur  
Page Receive occurred  
RO/SC  
RO/SC  
0
0
Parallel Detect Fault  
Interrupt  
Parallel Detect Fault did Parallel Detect Fault  
not occur occurred  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 26  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
Link Partner  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
23.3  
Link Partner  
Acknowledge Interrupt Acknowledge did not  
occur  
Link Partner Acknowledge  
occurred  
RO/SC  
0
0
23.2  
23.1  
Link Down Interrupt  
Link Down did not occur Link Down occurred  
RO/SC  
RO/SC  
0
0
Remote Fault Interrupt Remote Fault did not  
occur  
Remote Fault occurred  
23.0  
Link Up Interrupt  
Link Up did not occur  
Link Up occurred  
RO/SC  
0
Register 24h - Extended Control Register  
24.15:12  
24.11:9  
24.8  
FIFO Half  
Reserved  
RMII FIFO half full bits ((n+3)*2 bit), RMII  
RW  
RW  
RW  
2
0
0
2
0
Reserved  
Deep Power down  
enable  
Deep power down(DPD) Deep power down(DPD)  
disable  
enable  
24.7  
24.6  
Tpll10_100 DPD Enable Don't power down  
Controlled auto power  
down10/100 PLL in DPD  
mode  
RW  
RW  
RW  
RW  
0
0
0
0
0
0
10/100 PLL in DPD  
mode  
RX 100 DPD Enable  
Don't power down RX  
block in DPD mode  
Controlled auto power  
down of RX block in DPD  
mode  
24.5  
Admix_TX DPD Enable Don't power down  
Control auto power down  
admix_dac block in DPD of admix_dac block in  
mode DPD mode  
24.4  
Cdr100_cdr DPD Enable don't power down in DPD Control auto power down  
mod  
of CDR block in DPD  
mode  
24.3:0  
Reserved  
Reserved  
0
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 27  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Access 2 SF2  
Default3  
Hex  
Register 25h - Extended Control Register  
25.15:12  
25.11  
25.10  
25.9  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
RW  
RW  
RW  
RW  
0
0
1
1
0
0
0
6
Reserved  
TX10BIAS_SET  
The normal output current of the Bias block for  
10BaseT is 540uA. Changing the register can modify  
the current with a step size of 5%  
000: output 80% current  
25.8  
25.7  
4
001: output 85% current  
010: output 90% current  
011: output 95% current  
100: output 100% current  
101: output 105% current  
110: output 110% current  
111: output 115% current  
25.6  
25.5  
25.4  
TX100BIAS_SET  
The normal output current of the Bias block for  
100BaseTX is 180uA. Changing the register can  
modify the current with a step size of 5%  
000: output 80% current  
RW  
1
0
0
001: output 85% current  
010: output 90% current  
011: output 95% current  
100: output 100% current  
101: output 105% current  
110: output 110% current  
111: output 115% current  
25.3  
25.2  
OUTDLY_CTL  
Reserved  
This register controls the delay time of the digital  
control signal for xmit_dac.  
00: Longest delay time (same as original design)  
01: Long delay time  
10: Short delay time  
11: Shortest delay time  
RW  
RW  
0
1
25.1  
25.0  
Reserved  
0
1
Register 26 - 31h - Extended Control Register (Reserved)  
Note 1: Ignored if Auto negotiation is enabled.  
Note 2: CW = Command Override Write  
LH = Latching High  
LL = Latching Low  
LMX = Latching Maximum  
RO = Read Only  
RW = Read/Write  
RW/0 = Read/Write Zero  
RW/1 = Read/Write One  
SC = Self-clearing  
SF = Special Functions  
Note 3: L = Latched on power-up/hardware reset  
† = the default state of the pin at reset  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 28  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
DC and AC Operating Conditions  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the ICS1894-32. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these  
or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical  
parameters are guaranteed only over the recommended operating temperature range.  
Parameter  
Rating  
VDD (measured to VSS)  
Digital Inputs / Outputs  
Storage Temperature  
Junction Temperature  
Soldering Temperature  
Power Dissipation  
-0.3 V to 3.6V  
-0.3 V to VDD +0.3 V  
-55° C to +150° C  
125° C  
260° C  
See section “DC Operating Conditions for Supply Current”  
Recommended Operating Conditions  
Parameter  
Symbol  
Min. Max. Units  
Ambient Operating Temperature - Commercial  
Ambient Operating Temperature - Industrial  
Power Supply Voltage (measured to VSS)  
T
0
+70  
+85  
°C  
°C  
V
A
T
-40  
A
VDD  
+3.14 +3.47  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 29  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Recommended Component Values  
Parameter  
Minimum  
Typical  
Maximum  
Tolerance  
Units  
TCSR Resistor Value  
–
1.82k to GND  
18.2k to VDD  
–
1%  
Ω
LED Resistor Value  
1k  
–
Ω
ICS1894-32 TCSR  
ICS1894CK-32  
VDD  
7
TCSR  
8
18.2KΩ 1%  
VDD  
1.82KΩ 1%  
Note:  
1. The bias resistor network sets the 10baseT and 100baseTX output amplitude levels.  
2. Amplitude is directly related to current sourced out of the TCSR pin.  
3. Resistor values shown above are typical. User should check amplitudes and adjust for transformer effects.  
4. The 18.2K resistor provides negative feedback to compensate for VDD changes. Reducing the value of  
this resistor will lower the 100baseT amplitude. Reducing the value of the resistor to ground on the other  
hand will increase the output signal amplitude.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 30  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
DC Operating Characteristics for Supply Current  
The table below lists the DC operating characteristics for the supply current to the ICS1894-32 under various  
conditions.  
Condition  
VDDIO (V) VDD and VDDD (V) Current (mA) (typical)  
Autonegotiation  
3.3  
1.8  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
3.3  
68  
66  
100BaseTX FD and Linked  
10BaseTX FD and Linked  
Power Down (Reg0:11 = 1)  
102  
97  
16  
Deep Power Down Current Consumption Table  
Case 1 Case 2 Case 3 Case 4 Case 5  
Register 24:8  
Register 24:7  
Register 24:6  
Register 24:5  
Register 24:4  
DPD Enable  
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
TPLL_100 DPD Enable  
RX_100 DPD Enable  
Admix_TX DPD Enable  
CDR100_cdr DPD Enable  
Current (mA) (typical)  
68  
39  
26  
24  
16  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 31  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
DC Operating Characteristics for Inputs and Outputs  
Unless otherwise specified, the table below lists the 3.3V/1.8 V DC operating characteristics of the ICS1894-32  
inputs and outputs.  
For 3.3 V Signals  
Parameter  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Symbol  
Conditions  
Min. Max. Units  
V
2.0  
–
–
V
V
V
V
IH  
V
0.8  
–
IL  
V
I
= –4 mA  
= +4 mA  
OL  
2.4  
–
OH  
OH  
V
I
0.4  
OL  
For 1.8 V Signals  
Parameter  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Symbol  
Conditions  
Min. Max. Units  
V
0.8  
–
–
V
V
V
V
IH  
V
0.7  
–
IL  
V
I
= –4 mA  
= +4 mA  
OL  
1.6  
–
OH  
OH  
V
I
0.1  
OL  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 32  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
DC Operating Characteristics for REFIN  
The table below lists the 3.3V DC characteristics for the REFIN pin.  
Parameter  
Input High Voltage  
Input Low Voltage  
Symbol  
Min.  
2.97  
–
Max.  
–
Units  
V
V
V
IH  
V
0.33  
IL  
DC Operating Characteristics for MII Pins  
The table below lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1894-32.  
Parameter  
Conditions  
Min.  
Typ.  
–
Max.  
Units  
pF  
MII Input Pin Capacitance  
MII Output Pin Capacitance  
MII Output Drive Impedance  
–
–
–
–
8
14  
–
–
–
pF  
VDDIO = 3.3V  
20  
Ω
Timing Diagrams  
Timing for Clock Reference (REFIN) Pin  
The table below lists the significant time periods for signals on the clock reference (REFIN) pin. The REFIN Timing  
Diagram figure shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
t2  
t1  
t2  
REFIN Duty Cycle (MII)  
REFIN Period (MII)  
–
–
–
–
45  
–
50  
40  
50  
20  
55  
–
%
ns  
%
REFIN Duty Cycle (RMII)  
REFIN Period (RMII)  
45  
–
55  
–
ns  
REFIN Timing Diagram  
t1  
REFIN  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 33  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Timing for Transmit Clock (TXCLK) Pin  
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock  
Timing Diagram figure shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
TXCLK Duty Cycle  
TXCLK Period  
–
35  
–
50  
40  
65  
–
%
ns  
ns  
t2a  
t2b  
100M MII (100Base-TX)  
10M MII (10Base-T)  
TXCLK Period  
–
400  
–
Transmit Clock Timing Diagram  
t1  
TXCLK  
t2x  
Timing for Receive Clock (RXCLK) Pin  
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock  
Timing Diagram figure shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
RXCLK Duty Cycle  
RXCLK Period  
–
35  
–
50  
40  
65  
–
%
ns  
ns  
t2a  
t2b  
100M MII (100Base-TX)  
10M MII (10Base-T)  
RXCLK Period  
–
400  
–
Receive Clock Timing Diagram  
t1  
RXCLK  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 34  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
100M MII: Synchronous Transmit Timing  
The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time  
periods consist of timings of signals on the following pins:  
• TXCLK  
• TXD[3:0]  
• TXEN  
• TXER  
The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for  
the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
TXD[3:0], TXEN, TXER Setup to TXCLK Rise  
TXD[3:0], TXEN, TXER Hold after TXCLK Rise  
–
–
15  
0
–
–
–
–
ns  
ns  
100M MII/100M Stream Interface Synchronous Transmit Timing Diagram  
TXCLK  
TXD[3:0]  
TXEN  
TXER  
t1  
t2  
10M MII: Synchronous Transmit Timing  
The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods  
consist of timings of signals on the following pins:  
• TXCLK  
• TXD[3:0]  
• TXEN  
• TXER  
The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
TXD[3:0], TXEN, TXER Setup to TXCLK Rise  
TXD[3:0], TXEN, TXER Hold after TXCLK Rise  
–
–
375  
0
–
–
–
–
ns  
ns  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 35  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10M MII Synchronous Transmit Timing Diagram  
TXCLK  
TXD[3:0]  
TXEN  
TXER  
t1  
t2  
100M/MII Media Independent Interface: Synchronous Receive Timing  
The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The  
time periods consist of timings of signals on the following pins:  
• RXCLK  
• RXD[3:0]  
• RXDV  
• RXER  
The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods.  
Time  
Parameter  
Min. Typ. Max. Units  
Period  
t1  
t2  
RXD[3:0], RXDV, and RXER Setup to RXCLK Rise  
RXD[3:0], RXDV, and RXER Hold after RXCLK Rise  
10.0  
10.0  
–
–
–
–
ns  
ns  
MII Interface: Synchronous Receive Timing  
RXCLK  
RXD[3:0]  
RXDV  
RXER  
t1  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
MII Management Interface Timing  
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings  
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing  
diagram for the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
t3  
t4  
t5  
t6  
MDC Minimum High Time  
–
–
–
–
–
–
160  
160  
400  
0
–
–
–
–
–
–
–
–
ns  
ns  
ns  
ns  
ns  
ns  
MDC Minimum Low Time  
MDC Period  
–
MDC Rise Time to MDIO Valid  
MDIO Setup Time to MDC  
MDIO Hold Time after MDC  
300  
–
10  
10  
–
MII Management Interface Timing Diagram  
MDC  
t1  
t2  
t3  
t4  
MDIO  
(Output)  
MDC  
MDIO  
(Input)  
t5  
t6  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 37  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10M Media Independent Interface: Receive Latency  
The table below lists the significant time periods for the 10M MII timing. The time periods consist of timings of  
signals on the following pins:  
• TP_RX (that is, the MII TP_RXP and TP_RXN pins)  
• RXCLK  
• RXD  
The 10M MII Receive Latency Timing Diagram shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
First Bit of /5/ on TP_RX to /5/D/ on RXD  
10M MII  
–
6.5  
7
Bit times  
10M MII Receive Latency Timing Diagram  
†
TP_RX  
RXCLK  
RXD  
5
5
5
D
t1  
†
Manchester encoding is not shown.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 38  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10M Media Independent Interface: Transmit Latency  
The table below lists the significant time periods for the 10M MII transmit latency. The time periods consist of  
timings of signals on the following pins:  
• TXEN  
• TXCLK  
• TXD (that is, TXD[3:0])  
• TP_TX (that is, TP_TXP and TP_TXN)  
The 10M MII Transmit Latency Timing Diagram shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
TXD Sampled to MDI Output of First Bit  
10M MII  
–
1.2  
2
Bit times  
10M MII Transmit Latency Timing Diagram  
TXEN  
TXCLK  
TXD  
5
5
5
†
TP_TX  
t1  
†
Manchester encoding is not shown.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 39  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
100M / MII Media Independent Interface: Transmit Latency  
The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods  
consist of timings of signals on the following pins:  
• TXEN  
• TXCLK  
• TXD (that is, TXD[3:0])  
• TP_TX (that is, TP_TXP and TP_TXN)  
The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max.  
Units  
Period  
t1  
TXEN Sampled to MDI Output of First  
Bit of /J/ †  
MII mode  
–
2.8  
3
Bit times  
†The IEEE maximum is 18 bit times.  
MII/100M Stream Interface Transmit Latency Timing Diagram  
TXEN  
TXCLK  
TXD  
Preamble /J/  
Preamble /K/  
†
TP_TX  
t1  
†
Shown  
unscrambled.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 40  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)  
The table below lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex  
transmission. The time periods consist of timings of signals on the following pins:  
• TXEN  
• TXCLK  
• CRS  
The 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing  
diagram for the time periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
t2  
TXEN Sampled Asserted to CRS Assert  
TXEN De-Asserted to CRS De-Asserted  
0
0
3
3
4
4
Bit times  
Bit times  
100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)  
t2  
TXEN  
TXCLK  
CRS  
t1  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 41  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)  
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex  
transmission. The time periods consist of timings of signals on the following pins:  
• TXEN  
• TXCLK  
• CRS  
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for  
the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
TXEN Asserted to CRS Assert  
0
0
–
2
2
4
Bit times  
Bit times  
TXEN De-Asserted to CRS De-Asserted  
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)  
t2  
TXEN  
TXCLK  
CRS  
t1  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
100M MII Media Independent Interface: Receive Latency  
The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time  
periods consist of timings of signals on the following pins:  
• TP_RX (that is, TP_RXP and TP_RXN)  
• RXCLK  
• RXD (that is, RXD[3:0])  
The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time  
periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max.  
Units  
Period  
t1  
First Bit of /J/ into TP_RX to /J/ on RXD  
100M MII  
–
16  
17  
Bit times  
100M MII/100M Stream Interface: Receive Latency Timing Diagram  
†
TP_RX  
RXCLK  
RXD  
t1  
†
Shown  
unscrambled.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 43  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion  
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time  
periods consist of timings of signals on the following pins:  
• TP_RX (that is, TP_RXP and TP_RXN)  
• CRS  
• COL  
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time  
periods.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
t2  
First Bit of /J/ into TP_RX to CRS Assert †  
–
10  
9
–
–
14  
13  
Bit times  
Bit times  
First Bit of /J/ into TP_RX while  
Half-Duplex Mode  
Transmitting Data to COL Assert †  
t3  
t4  
First Bit of /T/ into TP_RX to CRS  
De-Assert ‡  
–
13  
–
–
18  
18  
Bit times  
Bit times  
First Bit of /T/ Received into TP_RX to  
COL De-Assert ‡  
Half-Duplex Mode 13  
†The IEEE maximum is 20 bit times.  
‡The IEEE minimum is 13 bit times, and the maximum is 24 bit times.  
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram  
First bit  
First bit of /T/  
†
TP_RX  
t3  
t1  
CRS  
COL  
t4  
t2  
†
Shown  
unscrambled.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 44  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Reset: Power-On Reset  
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of  
signals on the following pins:  
• VDD  
• TXCLK  
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
VDD ≥ 2.7 V to Reset Complete  
–
40  
45  
500  
ms  
Power-On Reset Timing Diagram  
2.7 V  
VDD  
t1  
TXCLK  
Valid  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 45  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Reset: Hardware Reset and Power-Down  
The table below lists the significant time periods for the hardware reset and power-down reset. The time periods  
consist of timings of signals on the following pins:  
• REFIN  
• RESETn  
• TXCLK  
The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods.  
Time  
Period  
Parameter  
Conditions Min. Typ. Max Units  
.
t1  
t2  
t3  
RESETn Active to Device Isolation and Initialization  
Minimum RESETn Pulse Width  
–
–
–
–
200  
–
60  
–
–
ns  
ns  
RESETn Released to TXCLK Valid  
35  
500  
ms  
Hardware Reset and Power-Down Timing Diagram  
REFIN  
RESETn  
t1  
t2  
t3  
TXCLK Valid  
Power  
Consumption  
(AC only)  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 46  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10Base-T: Heartbeat Timing (SQE)  
The table below lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The  
time periods consist of timings of signals on the following pins:  
• TXEN  
• TXCLK  
• COL  
The 10Base-T Heartbeat (SQE) Timing Diagram shows the timing diagram for the time periods.  
Note:  
1. For more information on 10Base-T SQE operations, see the section “10Base-T Operation: SQE Test”.  
2. In 10Base-T mode, one bit time = 100 ns.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
t2  
COL Heartbeat Assertion Delay from  
TXEN De-Assertion  
10Base-T Half Duplex  
10Base-T Half Duplex  
–
–
850  
1500  
ns  
ns  
COL Heartbeat Assertion Duration  
1000 1500  
10Base-T Heartbeat (SQE) Timing Diagram  
TXEN  
TXCLK  
COL  
t1  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 47  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10Base-T: Jabber Timing  
The table below lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of  
signals on the following pins:  
• TXEN  
• TP_TX (that is, TP_TXP and TP_TXN)  
• COL  
The 10Base-T Jabber Timing Diagram shows the timing diagram for the time periods.  
Note: For more information on 10Base-T jabber operations, see the section, “10Base-T Operation: Jabber”.  
Time  
Parameter  
Conditions  
Min. Typ. Max. Units  
Period  
t1  
t2  
Jabber Activation Time  
10Base-T Half Duplex  
10Base-T Half Duplex  
20  
–
–
35  
ms  
ms  
Jabber De-Activation Time  
300  
325  
10Base-T Jabber Timing Diagram  
TXEN  
t1  
TP_TX  
COL  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 48  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
10Base-T: Normal Link Pulse Timing  
The table below lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of  
signals on the TP_TXP pins). The 10Base-T Normal Link Pulse Timing Diagram shows the timing diagram for the  
time periods.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
Normal Link Pulse Width  
Normal Link Pulse to Normal Link Pulse Period  
10Base-T  
10Base-T  
–
8
100  
20  
–
ns  
25  
ms  
10Base-T Normal Link Pulse Timing Diagram  
TP_TXP  
t1  
t2  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 49  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Auto-Negotiation Fast Link Pulse Timing  
The table below lists the significant time periods for the ICS1894-32 Auto-Negotiation Fast Link Pulse. The time  
periods consist of timings of signals on the following pins:  
• TP_TXP  
• TP_TXN  
The Auto-Negotiation Fast Link Pulse Timing Diagram shows the timing diagram for one pair of these differential  
signals, for example TP_TXP minus TP_TXN.  
Time  
Parameter  
Conditions Min. Typ. Max. Units  
Period  
t1  
t2  
t3  
t4  
t5  
t6  
Clock/Data Pulse Width  
–
–
–
–
–
–
–
55  
110  
–
90  
60  
125  
5
–
70  
140  
–
ns  
µs  
Clock Pulse-to-Data Pulse Timing  
Clock Pulse-to-Clock Pulse Timing  
Fast Link Pulse Burst Width  
µs  
ms  
Fast Link Pulse Burst to Fast Link Pulse Burst  
Number of Clock/Data Pulses in a Burst  
10  
15  
15  
20  
25  
30  
ms  
pulses  
Auto-Negotiation Fast Link Pulse Timing Diagram  
Clock  
Pulse  
Data  
Pulse  
Clock  
Pulse  
Differential  
Twisted Pair  
Transmit Signal  
t2  
t1  
t1  
t3  
FLP Burst  
FLP Burst  
Differential  
Twisted Pair  
Transmit Signal  
t4  
t5  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 50  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
RMII Timing  
Time  
Description  
Min. Typ. Max. Units  
Param  
tcyc  
t1  
Clock Cycle  
Setup time  
Hold time  
–
4
2
20  
ns  
ns  
ns  
t2  
tCYC  
Transmit  
Timing  
REFCLK  
t1  
t2  
TX_EN  
TXD[1:0]  
Marking Diagram  
ICS  
1894K32L  
YYWW  
ORIGIN  
######  
Notes:  
1. ‘L’ designates Pb (lead) free, RoHS compliant.  
1. ‘YYWW’ designates date code.  
2. ‘ORIGIN’ desigantes counrty of origin.  
3. ‘######’ desigantes the lot number.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 51  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
Package Outline and Package Dimensions (32-pin 5mm x 5mm QFN)  
Package dimensions are kept current with JEDEC Publication No. 95  
(Ref)  
Seating Plane  
(ND-1)x  
(Ref)  
e
ND & NE  
Even  
A1  
Index Area  
(Typ)  
If ND & NE  
are Even  
L
A3  
e
2
N
1
2
N
1
2
(NE-1)x  
(Ref)  
e
Sawn  
Singulation  
E2  
E
E2  
2
Top View  
b
A
C
(Ref)  
ND & NE  
Odd  
e
Thermal Base  
D
D2  
2
C
D2  
0.08  
Millimeters  
Max  
1.00  
0.05  
0.20 Reference  
Symbol  
Min  
0.80  
0
A
A1  
A3  
b
0.18  
0.30  
e
0.50 BASIC  
N
32  
N
N
8
8
D
E
D x E BASIC  
5.00 x 5.00  
D2  
E2  
L
3.00  
3.00  
0.3  
3.3  
3.3  
0.5  
Ordering Information  
Part / Order Number  
1894-32KLF  
Marking  
see page 52  
Shipping Packaging  
Tubes  
Package  
32-pin QFN  
32-pin QFN  
Temperature  
0 to +70° C  
0 to +70° C  
1894-32KLFT  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 52  
ICS1894-32  
REV F 110209  
ICS1894-32  
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE  
PHYCEIVER  
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www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
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www.idt.com  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device  
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered  
trademarks used to identify products or services of their respective owners.  
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