33937_09--Datasheet/数据表在线中文翻译

Document Number: 33937

Rev. 6.0, 9/2009

Freescale Semiconductor

Advance Information

Three Phase Field Effect

Transistor Pre-driver

33937

33937A

The 33937 and 33937A are Field Effect Transistor (FET) pre-

drivers designed for three phase motor control and similar

applications. The 33937A has been specifically enhanced to

improve performance when driving very high current loads. The

integrated circuit (IC) uses SMARTMOS™ technology.

THREE-PHASE PRE-DRIVER

The IC contains three High Side FET pre-drivers and three Low

Side FET pre-drivers.Three external bootstrap capacitors provide

gate charge to the High Side FETs.

The IC interfaces to a MCU via six direct input control signals,

an SPI port for device setup and asynchronous reset, enable and

interrupt signals. Both 5.0 and 3.0 V logic level inputs are

accepted and 5.0 V logic level outputs are provided.

EK SUFFIX (Pb-FREE)

98ASA99334D

Features

54-PIN SOICW-EP

• Fully specified from 8.0 to 40 V covers 12 and 24 V automotive

systems

• Extended operating range from 6.0 to 58 V covers 12 and 42 V

systems

• Greater than 1.0 A gate drive capability with protection

• Protection against reverse charge injection from CGD and CGS

of external FETs

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

MCZ33937EK/R2

MCZ33937AEK/R2

-40°C to 135°C

54 SOICW-EP

• Includes a charge pump to support full FET drive at low battery

voltages

• Deadtime is programmable via the SPI port

• Simultaneous output capability enabled via safe SPI command

• Pb-free packaging designated by suffix code EK

V

SYS

33937

VPUMP

PUMP

VSUP

PA_HS_G

PB_HS_G

PC_HS_G

VPWR

VLS

VDD

VSS

PA_HS_S

PB_HS_S

PC_HS_S

3

PX_HS

PX_LS

PHASEX

CS

PA_LS_G

PB_LS_G

PC_LS_G

MCU

SI

OR

DSP

SCLK

SO

PX_LS_S

RST

INT

EN1

EN2

AMP_P

AMP_N

AMP_OUT

R

SEN

GND

Figure 1. 33937 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

DEVICE VARIATIONS

Table 1. Device Variations

Freescale Part No.

Significant Device Variations

Loss of regulation during indeterminate RESET level

High Bootstrap initialization current causes reset

Reference Location

Note 2 on page 7

MCZ33937

Caution on page 28

MCZ33937A

Invalid zero length SPI commands cause Framing Errors

Framing Error on page 37

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

INTERNAL BLOCK DIAGRAM

PUMP

VPWR

VSUP

VPUMP

PGND

MAIN

CHARGE

PUMP

TRICKLE

HOLD

CHARGE

PUMP

-OFF

CIRCUIT

VLS

REG.

5.0 V

REG.

VDD

OSCILLATOR

VLS

VDD

UV

DETECT

3X

RST

INT

PX_BOOT

PX_HS_G

T-LIM

VSUP

EN1

HIGH

SIDE

DRIVER

+

1.4 V

-

EN2

DESAT.

COMP

3

CONTROL

LOGIC

PX_HS

PX_LS

CS

+

-

PX_HS_S

SI

+

-

SCLK

SO

PHASE

COMP.

VSUP

LOW

SIDE

3

PX_LS_G

PX_LS_S

PHASEX

OC_OUT

GND(2)

DRIVER

+

-

+

-

OVER-CUR.

COMP.

I-SENSE

AMP.

VSS OC_TH AMP_OUT

AMP_N

AMP_P

VLS_CAP

Figure 2. 33937 Simplified Internal Block Diagram

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

1

54

PHASEA

PGND

EN1

VPWR

N/C

VLS

N/C

2

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

.35

34

33

32

31

30

29

28

3

4

EN2

RST

N/C

5

6

7

PUMP

VPUMP

VSUP

PHASEB

PHASEC

PA_HS

PA_LS

VDD

PB_HS

PB_LS

INT

CS

SI

SCLK

SO

PA_BOOT

PA_HS_G

PA_HS_S

PA_LS_G

PA_LS_S

PB_BOOT

PB_HS_G

PB_HS_S

PB_LS_G

PB_LS_S

PC_BOOT

PC_HS_G

PC_HS_S

PC_LS_G

PC_LS_S

N/C

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Transparent

Top View

PC_LS

PC_HS

AMP_OUT

AMP_N

AMP_P

OC_OUT

VLS_CAP

GND1

GND0

VSS

OC_TH

Figure 3. 33937 Pin Connections

Table 2. 33937 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.

Pin Name Pin Function

Formal Name

Definition

Totem Pole output of Phase A comparator. This output is low when the

voltage on PA_HS_S (Source of High Side FET) is less than 50% of V_SUP

1

PHASEA

Digital Output

Phase A

Power ground for charge pump

2

3

PGND

EN1

Ground

Power Ground

Enable 1

Logic signal input must be high (ANDed with EN2) to enable any gate drive

output.

Digital Input

Logic signal input must be high (ANDed with EN1) to enable any gate drive

output

4

EN2

Digital Input

Enable 2

Reset input

5

RST

N/C

Digital Input

–

Reset

Do not connect these pins

6, 33, 49,

50, 52, 53

No Connect

Charge pump output

7

PUMP

Power Drive

Out

Pump

Charge pump supply

8

9

VPUMP

VSUP

Power Input

Analog Input

Voltage Pump

Supply Voltage

Supply voltage to the load. This pin is to be connected to the common

Drains of the external High Side FETs

Totem Pole output of Phase B comparator. This output is low when the

voltage on PB_HS_S (Source of High Side FET) is less than 50% of V_SUP

10

11

PHASEB

PHASEC

Digital Output

Phase B

Phase C

Totem Pole output of Phase C comparator. This output is low when the

voltage on PC_HS_S (Source of High Side FET) is less than 50% of V_SUP

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

PIN CONNECTIONS

Table 2. 33937 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.

Pin Name Pin Function

Formal Name

Definition

Active low input logic signal enables the High Side Driver for Phase A

Active high input logic signal enables the Low Side Driver for Phase A

VDD regulator output capacitor connection.

12

13

PA_HS

PA_LS

VDD

Digital Input

Analog Output

Digital Input

Digital Output

Digital Input

Digital Output

Digital Input

Phase A High Side

Phase A Low Side

VDD Regulator

Phase B High Side

Phase B Low Side

Interrupt

14

Active low input logic signal enables the High Side Driver for Phase B

Active high input logic signal enables the Low Side Driver for Phase B

Interrupt pin output

15

PB_HS

PB_LS

INT

16

17

Chip Select input. It frames SPI commands and enables SPI port

Input data for SPI port. Clocked on the falling edge of SCLK, MSB first

Clock for SPI port and typically is 3.0 MHz

18

CS

Chip Select

19

SI

Serial In

20

SCLK

SO

Serial Clock

Output data for SPI port. Tri-state until CS becomes low

Active high input logic signal enables the Low Side Driver for Phase C

Active low input logic signal enables the High Side Driver for Phase C

Output of the current-sensing amplifier

21

Serial Out

22

PC_LS

PC_HS

Phase C Low Side

Phase C High Side

Amplifier Output

Amplifier Invert

Amplifier Non-Invert

Over-current Out

23

24

AMP_OUT Analog Output

Inverting input of the current-sensing amplifier

25

AMP_N

AMP_P

OC_OUT

OC_TH

VSS

Analog Input

Digital Output

Non-inverting input of the current-sensing amplifier

Totem pole digital output of the Over-current Comparator

Threshold of the over-current detector

26

27

28

Analog Input Over-current Threshold

Ground reference for logic interface and power supplies

Substrate and ESD reference, connect to VSS

29

Ground

Voltage Source Supply

Ground

30, 31

32

GND

VLS Regulator connection for additional output capacitor, providing low

impedance supply source for Low Side Gate Drive

VLS_CAP Analog Output VLS Regulator Output

Capacitor

Source connection for Phase C Low Side FET

34

35

36

37

PC_LS_S

Power Input

Phase C Low Side

Source

Gate drive output for Phase C Low Side

PC_LS_G Power Output Phase C Low Side Gate

Drive

Source connection for Phase C High Side FET

Gate Drive for output Phase C High Side FET

PC_HS_S

Power Input

Phase C High Side

Source

PC_HS_G Power Output Phase C High Side

Gate Drive

Bootstrap capacitor for Phase C

38

39

PC_BOOT Analog Input

PB_LS_S Power Input

Phase C Bootstrap

Source connection for Phase B Low Side FET

Phase B Low Side

Source

Gate Drive for output Phase B Low Side

Source connection for Phase B High Side FET

Gate Drive for output Phase B High Side

40

41

42

PB_LS_G Power Output Phase B Low Side Gate

Drive

PB_HS_S

Power Input

Phase B High Side

Source

PB_HS_G Power Output

Phase B High Side

Gate Drive

Bootstrap capacitor for Phase B

43

44

PB_BOOT

PA_LS_S

Analog Input

Power Input

Phase B Bootstrap

Source connection for Phase A Low Side FET

Phase A Low Side

Source

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

PIN CONNECTIONS

Table 2. 33937 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.

Pin Name Pin Function

Formal Name

Definition

Gate Drive for output Phase A Low Side

45

PA_LS_G Power Output Phase A Low Side Gate

Drive

Source connection for Phase A High Side FET

Gate Drive for output Phase A High Side

46

47

PA_HS_S

Power Input

Phase A High Side

Source

PA_HS_G Power Output

Phase A High Side

Gate Drive

Bootstrap capacitor for Phase A

48

51

54

PA_BOOT

VLS

Analog Input

Analog Output

Power Input

Ground

Phase A Bootstrap

VLS Regulator

Voltage Power

Exposed Pad

VLS regulator output. Power supply for the gate drives

Power supply input for gate drives

VPWR

EP

Device will perform as specified with the Exposed Pad un-terminated

(floating) however, it is recommended that the Exposed Pad be terminated

to pin 29 (VSS) and system ground

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to V_SSunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

VSUP Supply Voltage

V_SUP

V

Normal Operation (Steady-state)

58

Transient Survival⁽¹⁾

-1.5 to 80

VPWR Supply Voltage

V_PWR

V

Normal Operation (Steady-state)

58

Transient Survival⁽¹⁾

-1.5 to 80

Charge Pump (PUMP, VPUMP)

V_PUMP

V_LS

-0.3 to 40

-0.3 to 18

-0.3 to 7.0

V

VLS Regulator Outputs (VLS_,VLS_CAP)⁽²⁾

Logic Supply Voltage

V_DD

Logic Output (INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT)⁽³⁾

Logic Input Pin Voltage (EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST) 10 mA

V_OUT

V_IN

Amplifier Input Voltage

V_{IN_A}

(Both Inputs-GND), (AMP_P - GND) or (AMP_N - GND) 6.0 mA source or sink

-7.0 to 7.0

-0.3 to 7.0

Over-current comparator threshold 10 mA

V_OC

V

Driver Output Voltage⁽⁴⁾

V_BOOT

V_{HS_G}

V_{LS_G}

75

16

High Side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT)

High Side (PA_HS_G, PB_HS_G, PC_HS_G)

Low Side (PA_LS_G, PB_LS_G, PC_LS_G)

Driver Voltage Transient Survival⁽⁵⁾

V

High Side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_S,

PC_HS_S)

V_{HS_G}

V_{HS_S}

V_{LS_G}

V_{LS_S}

-7.0 to 75.0

-7.0 to 18.0

-7.0 to 7.0

Low Side (PA_LS_G, PB_LS_G, PC_LS_G, PA_LS_S, PB_LS_S, PC_LS_S)

Notes

1. The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80 V.

2. Normal operation of the 33937 at VPWR voltages greater than 28V can result in degradation or failure of the VLS regulator due to

transients induced during a RESET. A 20 V transient suppressor is recommended on the VLS pin (pin 51) to prevent excessive stress

under these conditions. Using the 33937A will avoid this limitation.

3. Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range.

4. This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account.

5. Actual operational limitations may differ from survivability limits. The V_LS- V_{LS_S}differential and the V_BOOT- V_{HS_S}differential must be

greater than 3.0 V to insure the output gate drive will maintain a commanded OFF condition on the output.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings (continued)

All voltages are with respect to V_SSunless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

ESD Voltage⁽⁶⁾

V_ESD

V

Human Body Model - HBM (All pins except for the pins listed below)

Pins: PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G,

PC_Boot, PC_HS_S, PC_HS_G, VPWR

±2000

±1000

Charge Device Model - CDM

Corner pins

±750

±300

All other pins

THERMAL RATINGS

Storage Temperature

T_STG

T_J

-55 to +150

-40 to +150

°C

Operating Junction Temperature

Thermal Resistance⁽⁷⁾

Junction-to-Case

°C/W

R_θJC

3.0

Soldering Temperature⁽⁸⁾

T_SOLDER

Note 9

°C

Notes

6. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω) and the Charge Device

Model (CDM), Robotic (C_ZAP= 4.0 pF).

7. Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating

mode, the heat transfer characteristics of the board and layout and the operating voltage. See Figure 24 and Figure 25 for examples of

power dissipation profiles of two common configurations. Operation above the maximum operating junction temperature will result in a

reduction in reliability leading to malfunction or permanent damage to the device.

8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS

VPWR Supply Voltage Startup Threshold⁽¹⁰⁾

V_{PWR_ST}

I_SUP

–

6.0

8.0

V

VSUP Supply Current, V_PWR= V_SUP= 40 V

RST and ENABLE = 5.0 V

mA

No output loads on Gate Drive Pins, No PWM

No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle

–

1.0

–

10

VPWR Supply Current, V_PWR= V_SUP= 40 V

RST and ENABLE = 5.0 V

I_{PWR_ON}

mA

µA

No output loads on Gate Drive Pins, No PWM, Outputs initialized

–

11

–

20

95

Output Loads = 620 nC per FET, 20 kHz PWM⁽¹¹⁾

Sleep State Supply Current, RST = 0 V

V

_SUP= 40 V

I_SUP

–

14

56

30

V_PWR= 40 V

I_PWR

100

Sleep State Output Gate Voltage

IG < 100 µA

V_GATESS

V

–

1.3

Trickle Charge Pump (Bootstrap Voltage)

V_Boot

V

_SUP= 14 V

22

–

28

–

32

Bootstrap Diode Forward Voltage at 10 mA

V_F

V_DD

I_DD

1.2

V

VDD INTERNAL REGULATOR

V_DDOutput Voltage, V_PWR= 8 to 40 V, C = 0.47 µF⁽¹²⁾

External Load I_{DD_EXT}= 0 to 1.0 mA

4.5

–

5.5

12

Internal V_DDSupply Current, V_DD= 5.5 V, No External Load

mA

VLS REGULATOR

Peak Output Current, V

Linear Regulator Output Voltage, I_VLS= 0 to 60 mA⁽¹³⁾

VLS Disable Threshold⁽¹⁴⁾

= 16 V, V_LS= 10 V

I_PEAK

V_LS

350

13.5

7.5

600

15

800

17

mA

V

PWR

V_THVLS

8.0

8.5

V

Notes

10. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. V_PWRmust exceed this

threshold in order for the Charge Pump and V_DDregulator to startup and drive V_PWRto > 8.0 V. Once V_PWRexceeds 8.0 V, the circuits

will continue to operate even if system voltage drops below 6.0 V.

11. This parameter is guaranteed by design. It is not production tested.

12. Minimum external capacitor for stable V_DDoperation is 0.47 µF.

13. Recommended external capacitor for the V_LSregulator is 2.2 µF low ESR at each pin VLS and VLS_CAP.

14. When V_LSis less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery is automatic when V_LSrises

above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients

on V_LS

.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CHARGE PUMP

Charge Pump

High Side Switch On Resistance

Low Side Switch On Resistance

Ω

R_{DS(on)_HS}

R_{DS(on)_LS}

V_THREG

–

6.0

5.0

10

9.4

900

Regulation Threshold Difference^{(15), (17)}

Charge Pump Output Voltage^{(16), (17)}

I_OUT= 40 mA, 6.0 V < V_SYS< 8.0 V

I_OUT= 40 mA, V_SYS> = 8.0 V

mV

250

500

V_CP

V

8.5

12

9.5

–

GATE DRIVE

High Side Driver On Resistance (Sourcing)

R_{DS(ON)_H_SRC}

Ω

V

_PWR= V_SUP= 16 V, -40°C ≤ T_A≤ 25°C

–

6.0

8.5

V_PWR= V_SUP= 16 V, 25°C < T_A≤ 135°C

High Side Driver On Resistance (Sinking)

R_{DS(ON)_H_SINK}

V

_PWR= V_SUP= 16 V

–

3.0

0.5

High Side Current Injection Allowed Without Malfunction^{(17), (18)}

Low Side Driver On Resistance (Sourcing)

I_{HS_INJ}

A

R_{DS(ON)_L_SRC}

Ω

V

_PWR= V_SUP= 16 V, -40°C ≤ T_A≤ 25°C

–

6.0

8.5

V_PWR= V_SUP= 16 V, 25°C < T_A≤ 135°C

Low Side Driver On-Resistance (Sinking)

R_{DS(ON)_L_SINK}

Ω

V

_PWR= V_SUP= 16 V

–

3.0

0.5

Low Side Current Injection Allowed Without Malfunction^{(17), (18)}

Gate Source Voltage, V_PWR= V_SUP= 40 V

I_{LS_INJ}

Α

V

= 0⁽¹⁹⁾

= 0

V_{GS_H}

V_{GS_L}

13

14.8

15.4

16.5

17

High Side, I

GATE

Low Side, I

GATE

High Side Gate Drive Output Leakage Current, Per Output⁽²⁰⁾

I_{HS_LEAK}

–

18

µA

Notes

15. When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled.

16. _SYSis the system voltage on the input to the charge pump. With recommended external components (1.0 µF, MUR 120 diode). The

Charge Pump is designed to supply the gate currents of a system with 100 A FETs in a 12 V application.

V

17. This parameter is a design characteristic, not production tested.

18. Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of

approximately 1.0µs after an output switch transition. 1.0 µs is sufficient for all intended applications of this IC.

19. If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not

recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap

and the VLS capacitors.

20. A small internal charge pump will supply up to 30 μA nominal to compensate for leakage on the High Side FET gate output and maintain

voltages after bootstrap events. It is not intended for external components to be connected to the High Side FET gate, but small amounts

of additional leakage can be accommodated. See Figures 11 through 14 for typical load margins.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OVER-CURRENT COMPARATOR

Common Mode Input Range⁽²²⁾

Input Offset Voltage

Over-current Comparator Threshold Hysteresis⁽²¹⁾

V_CM

2.0

-50

50

–

V_DD-0.02

50

V

mV

V

V_{OS_OC}

V_{OC_HYST}

300

Output Voltage

High Level at I_OH= -500 µA

Low Level at I_OL= 500 µA

V_OH

V_OL

0.85 V_DD

–

V_DD

0.5

HOLD OFF CIRCUIT

Hold Off Current (At Each GATE Pin)

3.0 V < V_SUP< 40 V⁽²³⁾

I_HOLD

10

–

300

µA

PHASE COMPARATOR

High Level Input Voltage Threshold

Low Level Input Voltage Threshold

High Level Output Voltage at I_OH= -500 µA

Low Level Output Voltage at I_OL= 500 µA

High Side Source Input Resistance^{(21), (26)}

DESATURATION DETECTOR

V_{IH_TH}

V_{IL_TH}

V_OH

0.5 V_SUP

0.3 V_SUP

0.85 V_DD

–

0.65 V_SUP

0.45 V_SUP

V_DD

V

–

V

V_OL

–

0.5

V

R_IN

–

40

–

kΩ

Desaturation Detector Threshold⁽²⁴⁾

V_{DES_TH}

1.2

1.4

1.6

V

CURRENT SENSE AMPLIFIER

Recommended External Series Resistor (See Figure 9)

Recommended External Feedback Resistor (See Figure 9)⁽²⁷⁾

Limited by the Output Voltage Dynamic Range

R_S

–

1.0

–

kΩ

R_FB

5.0

15

Maximum Input Differential Voltage (See Figure 9)

V_ID

mV

V

_ID= V_{AMP_P}- V_{AMP_N}

-800

-0.5

–

+800

3.0

Input Common Mode Range^{(21), (25)}

Input Offset Voltage

V_CM

V_OS

V

mV

R

_S= 1.0 kΩ, V_CM= 0.0 V

-15

–

+15

–

Input Offset Voltage Drift⁽²¹⁾

Input Bias Current

δV_OS/δT

-10

µV/°C

nA

I_b

V

_CM= 2.0 V

Notes

21. This parameter is a design characteristic, not production tested.

22. As long as one input is in the common mode range there is no phase inversion on the output.

-200

–

+200

23. The hold off circuit is designed to operate over the full operating range of V_SUP. The specification indicates the conditions used in

production test. Hold off is activated at V_THRSTor V_THVLS.

24. Desaturation is measured as the voltage drop below V_SUP, thus the threshold is compared to the drain-source voltage of the external

High Side FET. See Figure 5.

25. As long as one input is within V_CMthe output is guaranteed to have the correct phase. Exceeding the common mode rails on one input

will not cause a phase inversion on the output.

26. Input resistance is impedance from High Side source and is referenced to V_SS. Approximate tolerance is ±±20%

27. The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CURRENT SENSE AMPLIFIER (CONTINUED)

Input Offset Current

I_OS

nA

I

_OS= I_{AMP_P}- I_{AMP_N}

-80

–

+80

–

Input Offset Current Drift ⁽²⁸⁾

Output Voltage

δI_OS/δT

40

pA/°C

V

High Level with R_LOAD= 10 kΩ to V_SS

Low Level with R_LOAD= 10 kΩ to V_DD

V_OH

V_OL

V_DD-0.2

–

V_DD

0.2

Differential Input Resistance

R_I

I_SC

1.0

5.0

–

MΩ

mA

pF

Output Short-circuit Current

Common Mode Input Capacitance at 10 kHz ^{(28), (29)}

C_I

10

Common Mode Rejection Ratio at DC

CMRR

dB

CMRR = 20*Log ((V_{OUT_diff}/V_IN__diff) * (V_IN__CM/V_OUT__CM))

60

–

80

78

–

Large Signal Open Loop Voltage Gain (DC) ^{(28), (29)}

Nonlinearity ^{(28), (29)}

A_OL

NL

dB

%

RL = 1.0 kΩ, C_L= 500 pF, 0.3 < V_O< 4.8 V, Gain = 5.0 to 15

Notes

28. This parameter is a design characteristic, not production tested.

29. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.

-1.0

–

+1.0

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPERVISORY AND CONTROL CIRCUITS

Logic Inputs (Px_LS, Px_HS, EN1, EN2) ⁽³¹⁾

High Level Input Voltage Threshold

Low Level Input Voltage Threshold

V

V_IH

V_IL

–

2.1

–

0.9

Logic Inputs (SI, SCLK, CS) ^{(30), (31)}

High Level Input Voltage Threshold

Low Level Input Voltage Threshold

V

V_IH

V_IL

–

2.1

–

0.9

Input Logic Threshold Hysteresis ⁽³⁰⁾

V_IHYS

mV

µA

Inputs Px_LS, SI, SCLK, CS, Px_HS, EN1, EN2

100

8.0

250

–

450

18

Input Pull-down Current, (Px_LS, SI, SCLK, EN1, EN2)

I_INPD

I_INPU

C_IN

0.3 V_DD≤ V_IN≤ V_DD

Input Pull-up Current, (CS, Px_HS) ⁽³²⁾

0 ≤ V_IN≤ 0.7 V_DD

Input Capacitance ⁽³⁰⁾

10

–

25

µA

pF

0.0 V ≤ V_IN≤ 5.5 V

RST Threshold ⁽³³⁾

–

15

–

V_{TH_RST}

R_RST

1.0

2.1

V

RST Pull-down Resistance

0.3 V_DD≤ V_IN≤ V_DD

kΩ

40

60

85

Power-ON RST Threshold, (V_DDFalling)

SO High Level Output Voltage

V_THRST

V_SOH

3.4

4.0

4.5

V

I

_OH= 1.0 mA

SO Low Level Output Voltage

_OL= 1.0 mA

0.9 V_DD

–

0.1 V_DD

1.0

V_SOL

I_{SO_LEAK_T}

C_{SO_T}

V_OH

V

µA

pF

V

I

–

SO Tri-state Leakage Current

CS = 0.7 V_DD, 0.3 V_DD= V_SO= 0.7 V_DD

-1.0

–

SO Tri-state Capacitance ^{(30), (34)}

0.0 V ≤ V_IN≤ 5.5 V

–

0.85 V_DD

–

15

–

INT High Level Output Voltage

I

_OH= -500 µA

INT Low Level Output Voltage

_OL= 500 µA

V_DD

0.5

V_OL

V

I

–

THERMAL WARNING

Thermal Warning Temperature ^{(30), (35)}

Thermal Hysteresis ⁽³⁰⁾

T_WARN

T_HYST

150

8.0

170

10

185

12

°C

Notes

30. This parameter is guaranteed by design, not production tested.

31. Logic threshold voltages derived relative to a 3.3 V 10% system.

32. Pull-up circuits will not allow back biasing of V_DD.

33. There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the

reset from the internal logic.

34. This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested.

35. The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to

generate an interrupt when overtemperature is detected, and the status bit will always indicate if any of the three individual Thermal

Warning circuits in the IC sense a fault.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

INTERNAL REGULATORS

V_DDPower-Up Time (Until INT High)

t_{PU_VDD}

ms

(36)

–

2.0

8.0 V ≤ V_PWR

VLS Power-Up Time

t_{PU_VDD}

(37)

16 V ≤ V

PWR

CHARGE PUMP

Charge Pump Oscillator Frequency

Charge Pump Slew Rate⁽³⁸⁾

GATE DRIVE

F_OSC

SR_CP

90

–

125

100

190

–

kHz

V/µs

High Side Turn On Time⁽³⁹⁾

t_ONH

t_{D_ONH}

t_OFFH

ns

Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)

–

130

–

20

265

20

35

386

35

High Side Turn On Delay⁽⁴⁰⁾

Delay from Command to 1.0 V, (Figure 7)

High Side Turn Off Time⁽³⁹⁾

Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)

High Side Turn Off Delay⁽⁴⁰⁾

t_{D_OFFH}

Delay from Command to 10 V, (Figure 8)

130

–

265

20

386

35

Low Side Turn On Time⁽³⁹⁾

t_ONL

Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)

Low Side Turn On Delay⁽⁴⁰⁾

t_{D_ONL}

Delay from Command to 1.0 V, (Figure 7)

130

–

265

20

386

35

Low Side Turn Off Time⁽³⁹⁾

t_OFFL

Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)

Low Side Turn Off Delay⁽⁴⁰⁾

t_{D_OFFL}

Delay from Command to 10 V, (Figure 8)

130

-20

8.0

265

0

386

+20

30

Same Phase Command Delay Match⁽⁴¹⁾

Thermal Filter Duration ⁽⁴²⁾

Notes

t_{D_DIFF}

t_DUR

ns

µs

–

36. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V_DD

.

37. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and

VLS_CAP. This delay includes the expected time for V_DDto rise.

38. The charge pump operating at 12 V V_SYS, 1.0μF pump capacitor, MUR120 diodes and 47 µF filter capacitor.

39. This parameter is guaranteed by characterization, not production tested.

40. These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes

one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and

output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision

block. Synchronization time accounts for up to one clock period of variation. See Figure 6.

41. The maximum separation or overlap of the High and Low Side gate drives, due to propagation delays when commanding one ON and

the other OFF simultaneously, is guaranteed by design.

42. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

GATE DRIVE (CONTINUED)

Duty Cycle ^{(43), (44)}

t_DC

0.0

–

96

%

s

100% Duty Cycle Duration ^{(43), (44)}

Maximum Programmable Deadtime ⁽⁴⁵⁾

OVER-CURRENT COMPARATOR

Over-current Protection Filter Time

Unlimited

19.6

t_MAX

10.2

15

µs

t_OC

0.9

10

–

3.5

µs

ns

Rise Time (OC_OUT)

10% - 90%

t_ROC

240

C_L= 100 pF

Fall Time (OC_OUT)

90% - 10%

t_FOC

10

–

200

ns

C_L= 100 pF

DESATURATION DETECTOR AND PHASE COMPARATOR

Phase Comparator Propagation Delay Time to 50% of V_DD; C_L≤ 100 pF

ns

Rising Edge Delay

Falling Edge Delay

t_R

t_F

–

200

350

Phase Comparator Match (Prop Delay Mismatch of Three Phases)

C_L= 100 pF ⁽⁴³⁾

t_MATCH

–

100

Desaturation and Phase Error Blanking Time⁽⁴⁶⁾

t_BLANK

t_FILT

4.7

7.1

9.1

µs

ns

Desaturation Filter Time (Filter Time is digital) ⁽⁴³⁾

Fault Must be Present for This Time to Trigger

640

937

1231

CURRENT SENSE AMPLIFIER

Output Settle Time to 99% ^{(43), (47)}

t_SETTLE

µs

RL = 1.0 kΩ, C_L= 500 pF, 0.3 V < V_O< 4.8 V, Gain = 5 to 15

–

1.0

2.0

Notes

43. This parameter is guaranteed by design, not production tested.

44. Maximum duty cycle is actually 100% because there is an internal charge pump to maintain the gate voltage in the 100% on condition.

However, in high duty cycle cases, there may not be sufficient time to recharge the bootstrap capacitors during the off time. Large

bootstrap capacitors will allow high duty cycles to be obtained for a short time. For applications needing closer to 100% duty cycle,

external diodes may optionally be used to provide high peak current charging capability to the bootstrap capacitors. These diodes would

be connected between VLS and the Px_BOOTSTRAP pins. In applications with lower gate charge requirements, the maximum duty

cycle can also be increased.

45. A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock

cycle duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this

value limits at this value.

46. Blanking time, t_BLANK, is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to

system noise during the switching event.

47. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CURRENT SENSE AMPLIFIER (CONTINUED)

Output Rise Time to 90% ⁽⁴⁹⁾

t_{IS_RISE}

t_{IS_FALL}

SR⁽⁵⁾

µs

RL = 1.0 kΩ, C_L= 500 pF, 0.3 V < V_O< 4.8 V, Gain = 5.0 to 15

–

1.0

Output Fall Time to 10% ⁽⁴⁹⁾

RL = 1.0 kΩ, C_L= 500 pF, 0.3 V < V_O< 4.8 V, Gain = 5.0 to 15

Slew Rate at Gain = 5.0⁽⁴⁸⁾

V/µs

RL = 1.0 kΩ, C_L= 20 pF

5.0

–

Phase Margin at Gain = 5.0⁽⁴⁸⁾

f

30

°

M

Unity Gain Bandwidth ⁽⁴⁸⁾

G_BW

BW_G

CMR

MHz

RL = 1.0 kΩ, C_L= 100 pF

–

20

–

Bandwidth at Gain = 15 ⁽⁴⁸⁾

MHz

dB

R_L= 1.0 kΩ, C_L= 50 pF

2.0

Common Mode Rejection (CMR) ⁽⁴⁸⁾with V_IN

V_{IN_CM}= 400 mV*sin(2*π*freq*t)

V_IN

__DIF= 0.0 V, RS = 1.0 kΩ

R_FB= 15 kΩ, V_REFIN= 0.0 V

CMR = 20*Log(V_OUT/V_IN

Freq = 100 kHz

_

)

CM

50

40

30

–

Freq = 1.0 MHz

Freq = 10 MHz

SUPERVISORY AND CONTROL CIRCUITS

EN1 and EN2 Propagation Delay

INT Rise Time CL = 100 pF

t_PROP

t_RINT

–

10

–

280

250

200

250

ns

INT Fall Time CL = 100 pF

t_FINT

INT Propagation Time

t_PROPINT

Notes

48. This parameter is guaranteed by design, not production tested.

49. Rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V ≤ V_PWR= V_SUP≤ 40 V, -40°C ≤ T_A≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE TIMING

Maximum Frequency of SPI Operation

f_OP

f_TB

–

13

-5.0

100

25

–

4.0

25

5.0

–

MHz

%

Internal Time Base

17

–

Internal Time Base drift from value at 25°C ⁽⁵⁰⁾

TC_TB

t_LEAD

t_LAG

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) ⁽⁵⁰⁾

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) ⁽⁵⁰⁾

SI to Falling Edge of SCLK (Required Setup Time) ⁽⁵⁰⁾

Falling Edge of SCLK to SI (Required Setup Time) ⁽⁵⁰⁾

SI, CS, SCLK Signal Rise Time ^{(50), (51)}

–

ns

–

ns

t_SISU

t_SIHOLD

t_RSI

–

ns

–

ns

5.0

55

100

80

–

ns

SI, CS, SCLK Signal Fall Time ^{(50), (51)}

t_FSI

–

ns

Time from Falling Edge of CS to SO Low-impedance ^{(50), (52)}

Time from Rising Edge of CS to SO High-impedance ^{(50), (53)}

Time from Rising Edge of SCLK to SO Data Valid ^{(50), (54)}

Time from Rising Edge of CS to Falling Edge of the next CS ⁽⁵⁰⁾

t_SOEN

t_SODIS

t_VALID

t_DT

–

100

125

–

ns

–

ns

–

ns

200

ns

Notes

50. This parameter is guaranteed by design, not production tested.

51. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

52. Time required for valid output status data to be available on SO pin.

53. Time required for output states data to be terminated at SO pin.

54. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

CS

0.2 V_DD

t_{L EAD}

t

LLAAGG

0.7 V_{D D}

0.2 V_{D D}

SCLK

t_DI(SU)t_{DI(HO LD)}

t_SISUt_SIHOLD

0.7 V_{D D}

0.2 V_{D D}

SI

MSB in

t_SOEN

t_DO(EN)

t_SODIS

t_{DO (DIS)}

t_VALID

0.7 V_{D D}

0.2 V_{D D}

SO

MSB out

LSB out

Figure 4. SPI Interface Timing

P _HS

X

DESATURATION

FAULT

P _LS

X

FROM DELAY

TIMER

Figure 5. Desaturation Blanking and Filtering Detail

B

MUX

STATE

MACHINE

P _HS

X

A

D

Q

D

Q

OUT

D

Q

P _HS_G

CLK

X

DEADTIME

CONTROL

P _HS_S

X

P _LS

X

^STPULSE

D

Q

D

Q

1

CLK

P _LS_G

X

Q

OUT

A

B

MUX

EN1

EN2

RST

Figure 6. Deadtime Control Delays

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

50%

Px_HS

10V

t

1.0V

D_ONH

ONH

Px_HS_G

Px_LS

50%

10V

t

1.0V

D_ONL

ONL

Px_LS_G

Figure 7. Driver Turn-On Time and Turn-On Delay

50%

Px_HS

10V

t

OFFH

1.0V

Px_HS_G

D_OFFH

50%

Px_LS

10V

t

OFFL

1.0V

D_OFFL

Px_LS_G

Figure 8. Driver Turn-off Time and Turn-off Delay

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

REF

R

FBP

To Protection Circuits

R

AMP_P

+

s

+

IN

-

V

R

sense

ID

-

AMP_N

R

s

OC_TH

AMP_OUT

R

FBN

ꢁꢂꢀꢀP9ꢃWRꢃꢄꢃꢂꢀꢀP9

ꢀ9

ꢀ6ꢃꢁꢃꢀꢅꢆ6 ꢀꢅꢆ6ꢃꢁꢃꢆꢀ6

ꢀꢅꢆ6ꢃꢁꢃꢆꢀ6

Figure 9. Current Amplifier and Input Waveform (V_INVoltage Across R_SENSE

)

Figure 10. Typical Amplifier Open-loop Gain and Phase Margin vs Frequency

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Typical Trickle Charge Pump Supply Voltage and Margin

24

20

16

12

8

12

10

8

6

4

2

0

5

10

15

20

25

30

35

40

HS_S/Vsup (V)

dV

I

Figure 11. Typical Trickle Charge Pump Supply Voltage and Current Margin vs Supply Voltage

Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=14V

17

16

15

14

13

12

11

10

9

13

12

11

10

9

8

7

6

5

8

4

7

3

20

40

60

80

100

120

140

160

180

Tj (C)

I

dV

Figure 12. Typical Voltage and Load Margin For Increasing Junction Temperature at 14 V on HS_S

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=24V

9

8.5

8

13

12

11

10

9

7.5

7

6.5

6

8

7

5.5

5

6

5

4.5

4

3

20

40

60

80

100

120

140

160

180

Tj (C)

I

dV

Figure 13. Typical Voltage and Load Margin For Increasing Junction Temperature at 24 V on HS_S

Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=36V

9

8

7

6

5

4

3

2

1

0

12

11

10

9

8

7

6

5

4

3

20

40

60

80

100

120

140

160

180

Tj (C)

I

dV

Figure 14. Typical Voltage and Load Margin For Increasing Junction Temperature at 36 V on HS_S

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

The 33937 provides an interface between an MCU and the

large FETs used to drive three phase loads. A typical load

FET may have an on resistance of 4.0 mΩ or less and could

require a gate charge of over 400 nC to fully turn on. The IC

can operate in automotive 12 to 42 V environments.

Because there are so many methods of controlling three

phase systems, the IC enforces few constraints on driving the

FETs. It does provide deadtime (cross-over) blanking and

logic, both of which can be overridden, ensuring both FETs in

a phase are not simultaneously enabled.

An SPI port is used to configure the IC modes.

FUNCTIONAL PIN DESCRIPTION

If the charge pump is not required this pin may be left

floating.

PHASE A (PHASEA)

This pin is the totem pole output of the Phase A

comparator. This output is low when the voltage on Phase A

High Side source (source of the High Side load FET) is less

than 50 percent of VSUP.

VSUP INPUT (VSUP)

The supply voltage pin should be connected to the

common connection of the High Side FETs. It is the reference

bias for the Phase Comparators and Desaturation

Comparator. It is also used to provide power to the internal

steady state trickle charge pump and to energize the hold off

circuit.

POWER GROUND (PGND)

This pin is power ground for the charge pump. It should be

connected to VSS, however routing to a single point ground

on the PCB may help to isolate charge pump noise.

PHASE B (PHASEB)

ENABLE 1 AND ENABLE 2 (EN1, EN2)

This pin is the totem pole output of the Phase B

comparator. This output is low when the voltage on Phase B

High Side source (source of the High Side load FET) is less

Both of these logic signal inputs must be high to enable

any gate drive output. When either or both are low, the

internal logic (SPI port, etc.) still functions normally, but all

gate drives are forced off (external power FET gates pulled

low). The signal is asynchronous.

than 50 percent of V_SUP

.

PHASE C (PHASEC)

When EN1 and EN2 return high to enable the outputs,

each LS driver must be pulsed on before the corresponding

HS driver can be commanded on. This ensures that the

bootstrap capacitors are charged.

This pin is the totem pole output of the Phase C

comparator. This output is low when the voltage on Phase C

High Side source (source of the High Side load FET) is less

than 50 percent of V_SUP

.

RESET (RST)

PHASE A HIGH SIDE INPUT (PA_HS)

When the reset pin is low the integrated circuit (IC) is in a

low power state. In this mode all outputs are disabled, internal

bias circuits are turned off, and a small pull-down current is

applied to the output gate drives. The internal logic will be

reset within 77 ns of RESET going low. When RST is low, the

IC will consume minimal current.

This input logic signal pin enables the High Side Driver for

Phase A. The signal is active low, and is pulled up by an

internal current source.

PHASE A LOW SIDE INPUT (PA_LS)

This input logic signal pin enables the Low Side Driver for

Phase A. The signal is active high, and is pulled down by an

internal current sink.

CHARGE PUMP OUT (PUMP)

This pin is the switching node of the charge pump circuit.

The output of the internal charge pump support circuit. When

the charge pump is used, it is connected to the external

pumping capacitor. This pin may be left floating if the charge

pump is not required.

VDD VOLTAGE REGULATOR (VDD)

VDD is an internally generated 5.0 V supply. The internal

regulator provides continuous power to the IC and is a supply

reference for the SPI port. A 0.47 µF (min) decoupling

capacitor must be connected to this pin.

CHARGE PUMP INPUT (VPUMP)

This pin is the input supply for the charge pump circuit.

When the charge pump is required, this pin should be

connected to a polarity protected supply. This input should

never be connected to a supply greater than 40 V.

This regulator is intended for internal IC use and can

supply only a small (1.0 mA) external load current.

33937

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23

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

A power-on-reset (POR) circuit monitors this pin and until

the voltage rises above the threshold, the internal logic will be

reset; driver outputs will be tri-stated and SPI communication

disabled.

PHASE C HIGH SIDE INPUT (PC_HS)

This input logic pin enables the High Side Driver for Phase

C. This signal is active low, and is pulled up by an internal

current source.

The VDD regulator can be disabled by asserting the RST

signal low. The VDD regulator is powered from the VPWR

pin.

AMPLIFIER OUTPUT (AMP_OUT)

This pin is the output for the current sensing amplifier. It is

also the sense input to the over-current comparator.

PHASE B HIGH SIDE CONTROL INPUT (PB_HS)

This pin is the input logic signal, enabling the High Side

driver for Phase B. The signal is active low, and is pulled up

by an internal current source.

AMPLIFIER INVERTING INPUT (AMP_N)

The inverting input to the current sensing amplifier.

AMPLIFIER NON-INVERTING INPUT (AMP_P)

PHASE B LOW SIDE INPUT (PB_LS)

The non-inverting input to the current sensing amplifier.

This pin is the input logic signal, enabling the Low Side

driver for Phase B. The signal is active high, and is pulled

down by an internal current sink.

OVER-CURRENT COMPARATOR OUTPUT

(OC_OUT)

The over-current comparator output is a totem pole logic

level output. A logic high indicates an over-current condition.

INTERRUPT (INT)

The Interrupt pin is a totem pole logic output. When a fault

is detected, this pin will pull high until it is cleared by

executing the Clear Interrupt command via the SPI port. The

faults capable of causing an interrupt can be masked via the

MASK0 and MASK1 SPI registers to customize the

response.

OVER-CURRENT COMPARATOR THRESHOLD

(OC_TH)

This input sets the threshold level of the over-current

comparator.

CHIP SELECT (CS)

VOLTAGE SOURCE SUPPLY (VSS)

Chip select is a logic input that frames the SPI commands

and enables the SPI port. This signal is active low, and is

pulled up by an internal current source.

VSS is the ground reference for the logic interface and

power supplies.

GROUND (GND0,GND1)

SERIAL IN (SI)

These two pins are connected internally to VSS by a 1.0 Ω

resistor. They provide device substrate connections and also

the primary return path for ESD protection.

The Serial In pin is used to input data to the SPI port.

Clocked on the falling edge of SCLK, it is the most significant

bit (MSB) first. This pin is pulled down by an internal current

sink.

VLS REGULATOR CAPACITOR (VLS_CAP)

This connection is for a capacitor which will provide a low-

impedance for switching currents on the gate drive. A low

ESR decoupling capacitor, capable of sourcing the pulsed

drive currents must be connected between this pin and VSS.

Use the 33937A to avoid the CAUTION on page 28 for

capacitances greater than 3.5 µF.

SERIAL CLOCK (SCLK)

This logic input is the clock is used for the SPI port. The

SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled

down by an internal current sink.

SERIAL OUT (SO)

This is the same DC node as VLS, but it is physically

placed on the opposite end of the IC to minimize the source

impedance to the gate drive circuits.

Output data for the SPI port streams from this pin. It is tri-

stated until CS is low. New data appears on rising edges of

SCLK in preparation for latching by the falling edge of SCLK

on the master.

PHASE C LOW SIDE SOURCE (PC_LS_S)

The phase C Low Side source is the pin used to return the

gate currents from the Low Side FET. Best performance is

realized by connecting this node directly to the source of the

Low Side FET for phase C.

PHASE C LOW SIDE INPUT (PC_LS)

This input logic pin enables the Low Side Driver for Phase

C. This pin is an active high, and is pulled down by an internal

current sink.

PHASE C LOW SIDE GATE (PC_LS_G)

This is the gate drive for the phase C Low Side output FET.

It provides high current through a low impedance to turn on

33937

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FUNCTIONAL DESCRIPTIONS

INTRODUCTION

and off the Low Side FET.. A low-impedance drive ensures

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FET. This output

has also been designed to resist the influence of negative

currents.

on or off. The gate voltage is limited to about 15 V above the

FET source voltage. A low-impedance drive is used, ensuring

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FETs. This

output has also been designed to resist the influence of

negative currents.

PHASE C HIGH SIDE SOURCE (PC_HS_S)

PHASE B BOOTSTRAP (PB_BOOT)

The source connection for the phase C High Side output

FET is the reference voltage for the gate drive on the High

Side FET and also the low voltage end of the bootstrap

capacitor.

This is the bootstrap capacitor connection for phase B. A

capacitor connected between PC_HS_S and this pin

provides the gate voltage and current to drive the external

FET gate. Typically, the boostrap capacitor selection is 10 to

20 times the gate capacitance. The voltage across this

capacitor is limited to about 15 V. Use the 33937A to avoid

the CAUTION on page 28 for bootstrap capacitances greater

than 100 nF.

PHASE C HIGH SIDE GATE (PC_HS_G)

This is the gate drive for the phase C High Side output

FET. This pin provides the gate bias to turn the external FET

on or off. The gate voltage is limited to about 15 V above the

FET source voltage. A low-impedance drive is used, ensuring

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FETs. This

output has also been designed to resist the influence of

negative currents.

PHASE A LOW SIDE SOURCE (PA_LS_S)

The phase A Low Side source is the pin used to return the

gate currents from the Low Side FET. Best performance is

realized by connecting this node directly to the source of the

Low Side FET for phase A.

PHASE C BOOTSTRAP (PC_BOOT)

PHASE A LOW SIDE GATE (PA_LS_G)

This is the bootstrap capacitor connection for phase C. A

capacitor connected between PC_HS_S and this pin

provides the gate voltage and current to drive the external

FET gate. Typically, the boostrap capacitor selection is 10 to

20 times the gate capacitance. The voltage across this

capacitor is limited to about 15 V. Use the 33937A to avoid

the CAUTION on page 28 for bootstrap capacitances greater

than 100 nF.

This is the gate drive for the phase A Low Side output FET.

It provides high current through a low impedance to turn on

and off the Low Side FET. A low-impedance drive ensures

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FET. This output

has also been designed to resist the influence of negative

currents.

PHASE B LOW SIDE SOURCE (PB_LS_S)

PHASE A HIGH SIDE SOURCE (PA_HS_S)

The phase B Low Side source is the pin used to return the

gate currents from the Low Side FET. Best performance is

realized by connecting this node directly to the source of the

Low Side FET for phase B.

The source connection for the phase A High Side output

FET is the reference voltage for the gate drive on the High

Side FET and also the low voltage end of the bootstrap

capacitor.

PHASE B LOW SIDE GATE (PC_LS_G)

PHASE A HIGH SIDE GATE (PA_HS_G)

This is the gate drive for the phase B Low Side output FET.

It provides high current through a low impedance to turn on

and off the Low Side FET. A low-impedance drive ensures

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FET. This output

has also been designed to resist the influence of negative

currents.

This is the gate drive for the phase A High Side output

FET. This pin provides the gate bias to turn the external FET

on or off. The gate voltage is limited to about 15 V above the

FET source voltage. A low-impedance drive is used, ensuring

transient currents do not overcome an off-state driver and

allow pulses of current to flow in the external FETs. This

output has also been designed to resist the influence of

negative currents.

PHASE B HIGH SIDE SOURCE (PB_HS_S)

PHASE A BOOTSTRAP (PA_BOOT)

The source connection for the phase B High Side output

FET is the reference voltage for the gate drive on the High

Side FET and also the low voltage end of the bootstrap

capacitor.

This is the bootstrap capacitor connection for phase A. A

capacitor connected between PC_HS_S and this pin

provides the gate voltage and current to drive the external

FET gate. Typically, the boostrap capacitor selection is 10 to

20 times the gate capacitance. The voltage across this

capacitor is limited to about 15 V. Use the 33937A to avoid

PHASE B HIGH SIDE GATE (PB_HS_G)

This is the gate drive for the phase B High Side output

FET. This pin provides the gate bias to turn the external FET

33937

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FUNCTIONAL DESCRIPTIONS

INTRODUCTION

the CAUTION on page 28 for bootstrap capacitances greater

than 100 nF.

VPWR INPUT (VPWR)

VPWR is the power supply input for VLS and VDD. Current

flowing into this input recharges the bootstrap capacitors as

well as supplying power to the Low Side gate drivers and the

VDD regulator. An internal regulator regulates the actual gate

voltages. This pin can be connected to system battery

voltage if power dissipation is not a concern.

VLS REGULATOR (VLS)

VLS is the gate drive power supply regulated at

approximately 15 V. This is an internally generated supply

from VPWR. It is the source for the Low Side gate drive

voltage, and also the High Side bootstrap source. A low ESR

decoupling capacitor, capable of sourcing the pulsed drive

currents, must be connected between this pin and VSS. Use

the 33937A to avoid the CAUTION on page 28 for

capacitances greater than 3.5 µF.

EXPOSED PAD (EP)

The primary function of the Exposed Pad is to conduct

heat out of the device. This pad may be connected electrically

to the substrate of the device.The device will perform as

specified with the Exposed Pad un-terminated (floating).

However, it is recommended that the Exposed Pad be

terminated to pin 29 (VSS) and the system ground.

33937

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26

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

MC33937 - Functional Block Diagram

Integrated Supply

Main Charge Pump

5V Regulator

Trickle Charge Pump

VLS Regulator

Sensing & Protection

High Side

and

Low Side

Hold-off

Under-voltage

De-sat

Temperature

Current Sense

Phase

Output

Pre-drivers

Over-current

Logic & Control

Fault Register

Phase Control

Dead Time

Mode Control

SPI Communication

Integrated Supply

Sensing & Protection

Logic& Control

Drivers

Figure 15. Functional Internal Block Description

All functions of the IC can be described as the following

five major functional blocks:

12 µs. Calibration of the delay, because of internal IC

variations, is performed via the SPI.

• Enabling of simultaneous operation of High Side and

Low Side FETs—Normally, both FETs would not be

enabled simultaneously. However, for certain applications

where the load is connected between the High Side and

Low Side FETs, this could be advantageous. If this mode

is enabled, the blanking time delay will be disabled. A

sequence of commands may be required to enable this

function to prevent inadvertent enabling. In addition, this

command can only be executed once after reset to enable

or disable simultaneous turn-on.

•

Logic Inputs and Interface

Bootstrap Supply

Low Side Drivers

High Side Drivers

Charge Pump

LOGIC INPUTS AND INTERFACE

This section contains the SPI port, control logic, and shoot-

through timers.

• Setting of various operating modes of the IC and

enabling of interrupt sources.

The IC logic inputs have Schmitt trigger inputs with

hysteresis. Logic inputs are 3.0 V compatible. The logic

outputs are driven from the internal supply of approximately

5.0 V.

The 33937 allows different operating modes to be set and

locked by an SPI command (FULLON, Desaturation Fault,

Zero Deadtime). SPI commands can also determine how

the various faults are (or are not) reported.

The SPI registers and functionality is described completely

in the LOGIC COMMANDS AND REGISTERS section of this

document. SPI functionality includes the following:

• Read back of internal registers.

The status of the 33937 Status Registers can be read back

by the Master (DSP or MCU).

• Programming of deadtime delay—This delay is

adjustable in approximately 50 ns steps from 0 ns to

The Px_HS and Px_LS logic inputs are edge sensitive.

This means the leading edge on an input will cause the

33937

Analog Integrated Circuit Device Data

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27

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

complementary output to immediately turn off and the

selected one to turn on after the deadtime delay as illustrated

in Figure 16. The deadtime delay timer starts when the

corresponding FET was commanded off (see Figure 6 and

Figure 16).

during periods of reduced current. Current limit is blanked

immediately after subsequent input state change in order to

ensure device stays off during dV/dt transients.

HIGH SIDE DRIVERS

These three drivers switch the voltage across the

bootstrap capacitor to the external High Side FETs. The

circuits provide a low-impedance drive to the gate, ensuring

the FETs remain off in the presence of high dV/dt transients

on their sources. Further, these output drivers isolate the

other portions of the IC from currents capable of being

injected into the substrate due to rapid dV/dt transients on the

FETs.

PA _HS

PA_LS

Deadtime

Delay

The High Side drivers deliver power from their bootstrap

capacitor to the gate of the external High Side FET, thus

turning the High Side FET on. The High Side driver uses a

level shifter, which allows the gate of the external High Side

FET to be turned off by switching to the High Side FET

source.

PA_HS_G

PA_LS_G

Figure 16. Edge Sensitive Logic Inputs (Phase A)

BOOTSTRAP SUPPLY (VLS)

The gate supply voltage for the High Side drivers is

obtained from the bootstrap supply, so, a short time is

required after the application of power to the IC to charge the

bootstrap capacitors. To ensure this occurrence, the internal

control logic will not allow a High Side switch to be turned on

after entering the ENABLE state until the corresponding Low

Side switch is enabled at least once. Caution must be

exercised after a long period of inactivity of the Low Side

switches to verify the bootstrap capacitor is not discharged. It

will be charged by activating the Low Side switches for a brief

period, or by attaching external bleed resistors from the

HS_S pins to GND.

This is the portion of the IC providing current to recharge

the bootstrap capacitors. It also supplies the peak currents

required for the Low Side gate drivers.

The power for the gate drive circuits is provided by VLS

which is supplied from the VPWR pin. This pin can be

connected to system battery voltage and is capable of

withstanding up to the full load dump voltage of the system.

However, the IC only requires a low-voltage supply on this

pin, typically 13 to 16 V. Higher voltages on this pin will

increase the IC power dissipation.

CAUTION for 33937 only (Use the 33937A to avoid this

CAUTION)

In 12 V systems the supply voltage can fall as low as 6.0 V.

This limits the gate voltage capable of being applied to the

FETs and reduces system performance due to the higher

FET on-resistance. To allow a higher gate voltage to be

supplied, the IC also incorporates a charge pump. The

switches and control circuitry are internal; the capacitors and

diodes are external (see Figure 22).

Using the 33937 in applications which use large value

bootstrap capacitors requires extra care to insure the

transient induced when charging fully depleted capacitors

does not cause an unintended power on reset. The 33937A

has been modified to eliminate the need for these special

considerations. Factors which affect the sensitivity to this

effect are, bootstrap capacitor size, VLS filter capacitor size,

VLS voltage and the junction temperature. The effect is more

pronounced for greater values of these parameters. It is also

more pronounced if all phases charge depleted capacitors

simultaneously. For balanced capacitance on VLS and

VLS_CAP of greater than 3.5 µF (total of 7.0 µF VLS

filtering), 1.2 µF bootstrap capacitance on each phase could

cause a POR at room temperature with VLS at 13 V. At the

worst case conditions of 15.4 V VLS voltage and 150°C

junction temperature, with the same total VLS capacitance of

7.0 µF, approximately 0.3 µF total (0.1µF each) on Px_BOOT

could cause the same effect. Since this characteristic is

intrinsic to the bootstrap diode integrated on the device, a

valid solution to prevent an undesired reset during

LOW SIDE DRIVERS

These three drivers turn on and off the external Low Side

FETs. The circuits provide a low-impedance drive to the gate,

ensuring the FETs remain off in the presence of high dV/dt

transients on their drains. Additionally, these output drivers

isolate the other portions of the IC from currents capable of

being injected into the substrate due to rapid dV/dt transients

on the FET drains.

Low Side drivers switch power from VLS to the gates of the

Low Side FETs. The Low Side drivers are capable of

providing a typical peak current of 2.0 A. This gate drive

current may be limited by external resistors in order to

achieve a good trade-off between the efficiency and EMC

(Electro-Magnetic Compatibility) compliance of the

application. the Low Side driver uses High Side PMOS for

turn on and Low Side isolated LDMOS for turn off. The circuit

ensures the impedance of the driver remains low, even

initialization would be to use external diodes between VLS

and the Px_BOOT pin.

33937

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28

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

In order to achieve a 100% duty cycle operation of the High

Side external FETs, a fully integrated trickle charge pump

provides the charge necessary to maintain the external FET

gates at fully enhanced levels. The trickle charge pump has

limited ability to supply external leakage paths while

performing it’s primary function. The graphs in Figures 11

through 14 beginning on page 21 show the typical margin for

supplying external current loads. These limits are based on

maintaining the voltage at CBOOT at least 3.0 V greater than

the voltage on the HS_S for that phase. If this voltage

differential becomes less than 3.0 V, the corresponding high

side FET will most likely not remain fully enhanced and the

high side driver may malfunction due to insufficient bias

voltage between CBOOT and HS_S.

33927

Phase x

Output

Px_HS_S

D

VLS

Discrete

FET

Package

C

DG

Low

-Side

Driver

i

CDG

LS

Control

G

-

+

Z

o

C

Px_LS_G

DS

R

g

C

GS

S

Px_LS_S

Phase

Return

The slew rate of the external output FET is limited by the

driver output impedance, overall (external and internal) gate

resistance and the load capacitance. To ensure the Low Side

FET is not turned on by a large positive dV/dt on the drain of

the Low Side FET, the turn-on slew rate of the High Side

should be limited. If the slew rate of the High Side is limited

by the gate-drain capacitance of the High Side FET, then the

displacement current injected into the Low Side gate drive

output will be approximately the same value. Therefore, to

ensure the Low Side drivers can be held off, the voltage drop

across the Low Side gate driver must be lower than the

threshold voltage of the Low Side FET (see Figure 17).

Px_HS_G

Px_LS_G

Deadtime

Phase x Output Voltage

V

SUP

dV/dt

-V

D

Figure 17. Positive DV/dt Transient

Similarly, during large negative dV/dt, the High Side FET

will be able to remain off if its gate drive Low Side switch,

develops a voltage drop less than the threshold voltage of the

High Side FET. The gate drive Low Side switch discharges

the gate to the source.

DRIVER FAULT PROTECTION

The 33937 IC integrates several protection mechanisms

against various faults. The first of them is the Current Sense

Amplifier with the Over-current Comparator. These two

blocks are common for all three driver phases.

Additionally, during negative dV/dt the Low Side gate drive

could be forced below ground. The Low Side FETs must not

inject detrimental substrate currents in this condition.

Current Sense Amplifier

This amplifier is usually connected as a differential

amplifier (see Figure 9). It senses a current flowing through

the external FETs as a voltage across the current sense

resistor R_SENSE. Since the amplifier common mode range

does not extend below ground, it is necessary to use an

external reference to permit measuring both positive and

negative currents.

The occurrence of these cases depends on the polarity of

the load current during switching.

The amplifier output can be monitored directly (e.g. by the

microcontroller’s ADC) at the AMP_OUT pin, providing the

means for closed loop control with the 33937.

The output voltage is internally compared with the Over-

current Comparator threshold voltage (see Figure 22).

Over-current Comparator

The amplified voltage across R_SENSEis compared with the

pre-set threshold value by the over-current comparator input.

If the Current Sense Amplifier output voltage exceeds the

threshold of the Over-current Comparator it would change

the status of its output (OC_OUT pin) and the fault condition

would be latched (see Figure 20).

The occurrence of this fault would be signalled by the

return value of the Status Register 0. If the proper Interrupt

Mask has been set, this fault condition will generate an

33937

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29

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

interrupt - the INT pin will be asserted High. The INT will be

held in the High state until the fault is removed, and the

appropriate bit in the Status Register 0 is cleared by the

CLINT0 command. This fault reporting technique is

described in detail in the Logic Commands and Registers

section.

Valid faults are registered in the fault status register, which

can be retrieved by way of the SPI. Additional SPI commands

will mask the INT flag and disable output stage shutdown,

due to desaturation and phase errors. See the Logic

Commands and Registers section for details on masking INT

behavior and disabling the protective function.

Desaturation Detector

V

SUP

The Desaturation Detector is a comparator integrated into

the output driver of each phase channel. It provides an

additional means to protect against “Short-to-Ground” fault

condition when the output node gets shorted to the supply

voltage (short across the High Side FET).

VLS

3 x

T-Lim

High

-Side

Driver

Px_BOOT

Px_HS_G

HS

Control

Phase x Output

Shorted to V

VSUP

SUP

(High-Side

FET Shorted)

+

Desat.

Comp.

1.4V

-

V

SUP

Px_HS_S

Phase x

Output

VLS

3 x

Low

-Side

Driver

VSUP

R

LS

Control

Phase

Comp.

T-Lim

High

-Side

Driver

Px_LS_G

Px_LS_S

Px_BOOT

Px_HS_G

R

HS

Control

Phase

Return

VSUP

+

1.4V

-

Desat.

Comp.

Phase x

Output

To Current

Sense Amplif.

R

Sense

VLS_CAP

Px_HS_S

Phase x Output

Shorted to Ground

Low

-Side

Driver

(Low-Side

VSUP

R

LS

Control

FET Shorted)

Phase

Comp.

Px_HS_G

Px_LS_G

Px_LS_S

R

Deadtime

Phase

Return

t

BLANK

Px_LS_G

V

Phase x Output Voltage Shorted to V

SUP

To Current

Sense Amplif.

R

Sense

VLS_CAP

0.5V

SUP

Correct Phase x Output Voltage

-V

Px_HS_G

Px_LS_G

D

t

BLANK

Fault

Correct

Deadtime

t

FILT

PHASEx

V

Correct Phase x Output Voltage

SUP

Phase Error

Figure 19. Short to Supply Detection

0.5V

SUP

Phase x Output

Voltage Shorted to Ground

Phase Comparator

-V

D

Correct

Fault

Faults could also be detected as Phase Errors. A phase

error is generated if the output signal (at Px_HS_S) does not

properly reflect the drive conditions.

PHASEx

Phase Error

Desaturation Error

A phase error is detected by a Phase Comparator. The

Phase Comparator compares the voltage at the Px_HS_S

node with a reference of one half the voltage at the VSUP pin.

A High Side phase error (which will also trigger the

Desaturation Detector) occurs when the High Side FET is

commanded on, and Px_HS_S is still low at the end of the

deadtime and blanking time duration. Similarly, a LS phase

error occurs when the Low Side FET is commanded on, and

the Px_HS_S is still high at the end of the deadtime and

blanking time duration.

Figure 18. Short to Ground Detection

When switching from Low Side to High Side, the High Side

will be commanded ON after the end of the deadtime. The

deadtime period starts when the Low Side is commanded

OFF. If the voltage at Px_HS_S is less than 1.4V below V_SUP

after the blanking time (t_BLANK) a desaturation fault is

initiated. An additional 1.0 μs digital filter is applied from the

initiation of the desaturation fault before it is registered, and

all phase drivers are turned OFF (Px_HS_G clamped to

Px_HS_S and Px_LS_G clamped to Px_LS_S). If the

desaturation fault condition clears before the filter time

expires, the fault is ignored and the filter timer resets.

The Phase Error Flag is the triple OR of phase errors from

each phase. Each phase error is the OR of the High Side and

Low Side phase errors. This flag can generate an interrupt if

33937

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FUNCTIONAL INTERNAL BLOCK DESCRIPTION

the appropriate mask bit is set. The INT will be held in the

High state until the fault is removed, and the appropriate bit

in the Status Register 0 is cleared by the CLINT1 command.

This fault reporting mechanism is described in detail in the

Logic Commands and Registers section.

for VLS includes the charge pump and a linear regulator. The

regulation set point for the linear regulator is nominally at

15.34 V. As long as VLS output voltage (VLS_OUT) is greater

than the VLS analog regulator threshold (VLS_ATH) minus

V_THREG, the charge pump is not active.

If VLS_OUT< VLS_ATH– V_THREGthe charge pump turns ON

until VLS_OUT> VLS_ATH– V_THREG+ V_HYST

HOLD OFF CIRCUIT

The IC guarantees the output FETs are turned off in the

absence of V_DDor V_PWRby means of the Hold off circuit. A

small current source, generated from VSUP, typically

100 µA, is mirrored and pulls all the output gate drive pins low

when V_DDis less than about 3.0 V, RST is active (low), or

when VLS is lower than the VLS_Disable threshold. A

minimum of approximately 3.0 V is required on VSUP to

energize the Hold off circuit.

V_HYSTis approximately 200 mV. VLS_ATHwill not interfere

with this cycle even when there is overlap in the thresholds,

due to the design of the regulator system.

The maximum current the charge pump can supply is

dependent on the pump capacitor value and quality, the

pump frequency (nominally 130 kHz), and the Rdson of the

pump FETs. The effective charge voltage for the pump

capacitor would be V_SYS– 2 * V_DIODE. The total charge

transfer would then be C_PUMP* (V_SYS– 2*V_DIODE).

Multiplying by the switch frequency gives the theoretical

CHARGE PUMP

current the pump can transfer: F_PUMP* C_PUMP* (V_SYS

2*V_DIODE).

–

The Charge Pump circuit provides the basic switching

elements required to implement a charge pump, when

combined with external capacitors and diodes for enhanced

low voltage operation.

NOTE: There is also another smaller, fully integrated

charge pump (Trickle Charge Pump - see Figure 2), which is

used to maintain the High Side drivers’ gate V_GSin 100

percent duty cycle modes.

When the 33937 is connected per the typical application

using the charge pump (see Figure 22), the regulation path

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31

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

• Standby Mode - The RST input is high while one of the

RESET AND ENABLE

Enable inputs is low. The IC is fully biased up and

operating, all the external FETs are actively turned off

by both High Side and Low Side gate drives. The IC is

ready to enter the Enable mode.

The 33937 has three power modes of operation described

in Table 6. There are three global control inputs (RST, EN1,

EN2), which together with the status of the VDD and VLS,

control the behavior of the IC.

• Enable Mode - In order to enter the Enable mode

(normal mode of operation), and to operate the outputs,

the RST input must be high, and both Enable inputs

EN1 and EN2 must also be high.

The operating status of the IC can be described by the

following three modes:

Sleep Mode - When RST is low, the IC is in Sleep mode.

The current consumption of the IC is at minimum.

Table 6. Functions of RST, EN1 and EN2 Pins

RST

EN1, EN2

Mode of Operation (Driver Condition)

0

Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error

and SPI registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except

SO are clamped to VSS.

xx

1

Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external

FETs (after initialization). The SPI port is functional. Logic level outputs are driven with low impedance. SO is high

impedance unless CS is low. V_DD, Charge Pump and V_LSregulators are all operating. The IC is ready to move to Enable

Mode.

0x

x0

Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs

require a pulse on Px_LS before corresponding HS outputs will turn on in order to charge the bootstrap capacitor. All

error pin and register bits are active if detected.

11

•

After entry to Enable Mode, the IC requires a pulse on

Px_LS in order to charge the bootstrap capacitor before

allowing the Px_HS to turn on. This pulse should be

long enough to guarantee the bootstrap capacitor is

charged (typically less than 50 µs), but the IC does not

enforce this condition. If there is an alternate means of

pre-charging the bootstrap capacitor, i.e. an external

resistor from Px_HS_S to GND, then a very brief pulse

of 100 ns is sufficient to reset the logic.

Table 7. Functional Ratings

(T_J= -40°C to 150°C and supply voltage range V_SUP= V_PWR= 5.0 to 45 V, C = 0.47 µF)

Characteristic

Value

Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open ⁽⁵⁵⁾

(Driver output is switched off, high-impedance mode)

Low (<1.0 V)

Default State of input pin Px_HS, CS if left open ⁽⁵⁵⁾

(Driver output is switched off, high-impedance mode)

High (>2.0 V)

Notes

55. To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.

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32

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

in an SPI word can be considered to be the Command with

the trailing five bits being the data.

COMMAND DESCRIPTIONS

The IC contains internal registers to control the various

operating parameters, modes, and interrupt characteristics.

These commands are sent and status is read via 8-bit SPI

commands. The IC will use the last eight bits in an SPI

transfer, so devices can be daisy-chained. The first three bits

The SPI logic will generate a framing error and ignore the

SPI message if the number of received bits is not eight or if it

is not a multiple of eight.

After RST, the first SPI result returned is Status Register 0.

Table 8. Command List

Command

Name

Description

000x xxxx

These commands are used to read IC status. These commands do not change any internal IC status. Returns

Status Register 0-3, depending on sub command.

NULL

0010 xxxx

0011 xxxx

010x xxxx

0110 xxxx

Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation

for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.

MASK0

MASK1

MODE

Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation

for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.

Enables Desat/Phase Error Mode. Enables FULLON Mode. Locks further Mode changes. Returns Status

Register 0.

Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears

the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status

Register 0.

CLINT0

0111 xxxx

Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears

the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status

Register 0.

CLINT1

100x xxxx

Set deadtime with calibration technique. Returns Status Register 0.

DEADTIME

indicating any faults not cleared since the CLINTx command

was last written (rising edge of CS) and the beginning of the

current SPI command (falling edge of CS). The NULL

command causes no changes to the state of any of the fault

or mask bits.

FAULT REPORTING AND INTERRUPT

GENERATION

Different fault conditions described in the previous

chapters can generate an interrupt - INT pin output signal

asserted high. When an interrupt occurs, the source can be

read from Status Register 0, which is also the return word of

most SPI messages.

The logic clearing the fault latches occurs only when:

1. A valid command had been received(i.e. no framing

error);

Faults are latched on occurrence, and the interrupt and

faults are only cleared by sending the corresponding CLINTx

command. A fault that still exists will continue to assert an

interrupt.

2. A state change did not occur during the SPI message

(if the bit is being returned as a 0 and a fault change

occurs during the middle of the SPI message, the latch

will remain set). The latch is cleared on the trailing

(rising) edge of the CS pulse. Note, to prevent missing

any faults the CLINTx command should not generally

clear any faults without being observed; i.e. it should

only clear faults returned in the prior NULL response.

Note: If there are multiple pending interrupts, the INT line

will not toggle when one of the faults is cleared. Interrupt

processing circuitry on the host must be level sensitive to

correctly detect multiple simultaneous interrupt.

Thus, when an interrupt occurs, the host can query the IC

by sending a NULL command; the return word contains flags

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33

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

NULL COMMANDS

This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message

000x xx00 reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers.

Table 9. NULL Commands

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

x

0

Reset

NULL Commands are described in detail in the STATUS REGISTERS section of this document.

MASK Command

This is the mask for interrupts. A bit set to “1” enables the corresponding interrupt. Because of the number of MASK bits, this

register is in two portions:

1. MASK0

2. MASK1

Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure 20 illustrates how interrupts are enabled and

faults cleared.

CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch

and status register 0 bit corresponding to the lower nibble of the command.

Table 10. MASK0 Register

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

1

0

x

Reset

1

INTERRUPT HANDLING

To Status Register

From MASKx:N Register

net N

INT Source

INT Clear

Fault

Various Faults

S

INT

Latch

From Clint Command

R

net 0

Figure 20. Interrupt Handling

Table 11. MASK1 Register

SPI Data Bits

7

6

5

4

3

2

1

0

Write

0

1

x

Reset

1

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34

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 12. Setting Interrupt Masks

Mask:bit

Description

MASK0:0

MASK0:1

MASK0:2

MASK0:3

MASK1:0

Over-temperature on any gate drive output generates an interrupt if this bit is set.

Desaturation event on any output generates an interrupt if this bit is set.

VLS under-voltage generates an interrupt if this bit is set.

Over-current Error–if the over-current comparator threshold is exceeded, an interrupt is generated.

Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is

generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration

of the desaturation blanking interval.

In FULLON mode, this signal is blanked and cannot generate an error.

Framing Error–if a framing error occurs, an interrupt is generated.

Write Error after locking.

MASK1:1

MASK1:2

MASK1:3

Reset Event–If the IC is reset or disabled, an interrupt occurs. Since the IC will always start from a reset condition, this can

be used to test the interrupt mechanism because when the IC comes out of RESET, an interrupt will immediately occur.

MODE COMMAND

This command is sent by sending binary 010x xxxx data.

Table 13. MODE Command

SPI Data Bits

Write

7

0

6

1

5

0

4

0

3

2

0

1

0

Desaturation

Fault Mode

FULLON

Mode

Lock

Reset

0

• Bit 0–Mode Lock is used to enable or disable Mode Lock. If Bit 0 is set, changes to the internal registers are disallowed

to prevent inadvertent changes. This bit cannot be cleared once set. Since the mode Lock mode can only be set, this bit

prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. The only

way to clear this bit is to RESET the IC. If an attempt is made to write to a register when Mode Lock is enabled, a Write

Error fault is generated.

• Bit 1–FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high

and Low Side drivers in a phase on simultaneously. This could be useful in special applications such as alternator

regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals

directly control the output stages, synchronized with the internal clock.

This bit is a “0”, after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs

from being turned on simultaneously.

• Bit 3– Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to “0”, any

desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the

CLINT command. When 1, desaturation faults are completely ignored.

Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are:

— 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates

an Interrupt, if interrupts are enabled.

— 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.

Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further

changes.

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35

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

the deadtime register. Until the next deadtime calibration is

performed, 30 clock cycles will separate the turn off and turn

on gate signals in the same phase. The worst case error

immediately after calibration will be +0/-1 time base cycle, for

this example +0 ns/-50 ns. Note that if the internal time base

drifts, the effect on dead time will scale directly.

DEADTIME COMMAND

Deadtime prevents the turn-on of both transistors in the

same phase until the deadtime has expired. The deadtime

timer starts when a FET is commanded off (see Figure 6 and

Figure 16). The deadtime control is disabled by enabling the

FULLON mode.

Sending a ZERO DEADTIME command (100x xxx0) sets

the deadtime timer to 0. However, simultaneous turn-on of

High Side and Low Side FETs in the same phase is still

prevented unless the FULLON command has been

transmitted. There is no calibration pulse expected after

receiving the ZERO DEADTIME command.

The deadtime is set by sending the DEADTIME command

(100x xxx1), and then sending a calibration pulse of CS. This

pulse must be 16 times longer than the required deadtime

(see Figure 21). Deadtime is measured in cycle times of the

internal time base, f_TB. This measurement is divided by 16

and stored in an internal register to provide the reference for

timing the deadtime between high and low gate transactions

in the same phase.

After RESET, deadtime is set to the maximum value of 255

time base cycles (typically 15 µs).

The IC ignores any SPI data that is sent during the

calibration pulse. If there are any transitions on SI or SCLK

while the Deadtime CS pulse is low, a Framing Error will be

generated, however, the CS pulse will be used to calibrate

the deadtime

For example: the internal time base is running at 20 MHz

and a 1.5 µs deadtime is required. First a DEADTIME

command is sent (using the SPI), then a CS is sent. The CS

pulse is 16*1.5 = 24 µs wide. The IC measures this pulse as

24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in

Table 14. .DEADTIME Command

SPI Data Bits

Write

7

6

5

4

3

2

1

0

1

0

x

ZERO/

CALIBRATE

Reset

x

Deadtime Calibration Pulse

CS

SCLK

Deadtime

Command

DEADTIME

SI

SO

Figure 21. Deadtime Calibration

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Other commands return a general status word in the Status

Register 0.

STATUS REGISTERS

After any SPI command, the status of the IC is reported in

the return value from the SPI port. There are four variants of

the NULL command used to read various status in the IC.

There are four Status Registers in the IC. Status

Register 0 is most commonly used for general status.

Registers one through three are used to read or confirm

internal IC settings.

Status Register 0 (Status Latch Bits)

This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command

returns the following data:

Table 15. Status Register 0

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Register 0

RESET

Event

Write

Error

Framing

Error

Phase

Error

Over-current

Low

VLS

DESAT

Detected on Detected on

any Channel any Channel

TLIM

Read

Reset

1

0

All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits

set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1

respectively.

• Bit 0–is a flag for Over-temperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This

flag can generate an interrupt if the appropriate mask bit is set.

• Bit 1–is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal High Side

desaturation detectors and phase error logic. Faults are also detected on the Low Side as phase errors. A phase error is

generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR

of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which

will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the

deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the

Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the

appropriate mask bit is set.

• Bit 2– is a flag for Low Supply Voltage. This bit is latched, thus a prior low voltage event is returned once before being

cleared on read. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 3–is a flag for the output of the Over-current Comparator. This flag can generate an interrupt if the appropriate mask

bit is set.

• Bit 4–is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the

individual high or Low Side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output

with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an

interrupt if the appropriate mask bit is set.

• Bit 5–is a flag for a Framing Error. A framing error is an SPI message not containing a multiple of eight bits (a 0-length

message is also a framing error on 33937A). SCLK toggling while measuring the Deadtime calibration pulse is also a

framing error. This would typically be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This

flag can generate an interrupt if the appropriate mask bit is set.

• Bit 6–indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a

Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one

defined in the Table 8. This would typically be a software error. This flag can generate an interrupt if the appropriate mask

bit is set.

• Bit 7–is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets

reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.

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FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Status Register 1 (MODE Bits)

This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns

the following data:

Table 16. Status Register 1

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Register 1

0

Desaturation

Mode

Zero

Deadtime

Set

Calibration

Overflow

Deadtime

Calibration

0

FULLON

Mode

Lock

Bit

Read

Reset

0

• Bit 0–Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to

these registers is ignored and will set the Write Error flag.

• Bit 1– is the present status of FULLON Mode. If this bit is set to “0”, the FULLON mode is not allowed. A “1” indicates the

IC can operate in FULLON Mode (both High Side and Low Side FETs of one phase can be simultaneously turned on).

• Bit 3–indicates Deadtime Calibration occurred. It will be “0” until a successful Deadtime command is executed. This

includes the Zero Deadtime setting, as well as a Calibration Overflow.

• Bit 4–is a flag for a Deadtime Calibration Overflow.

• Bit 5–is set if Zero Deadtime is commanded.

• Bit 6–reflects the current state of the Desaturation/Phase Error turn-off mode.

Status Register 2 (MASK bits)

This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns

the following data:

Table 17. Status Register 2

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Mask1:3

Mask1:2

Mask1:1

Mask1:0

Mask0:3

Mask0:2

Mask0:1

Mask0:0

Register 2

Read

Reset

1

Status Register 3 (Deadtime)

This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns

the following data:

Table 18. Status Register 3

SPI Data Bits

7

6

5

4

3

2

1

0

Results

Dead7

Dead6

Dead5

Dead4

Dead3

Dead2

Dead1

Dead0

Register 3

Read

Reset

0

These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not

yet performed, all these bits return 0 even though the actual dead time is the maximum.

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38

Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

IC Initialization

Here is a possible flow to initialize the IC and its software environment.

1. Apply power (V_SYS) to module

1.1. With RST still low, V_SUPand V_SYScurrent will be low because it will only be leakage and the small hold off bias

current.

2. Remove RST (EN1 and EN2 are still low)

2.1. When RST rises above the threshold, the IC will power-up. The charge pump (if configured) will start, and V_PWRand

V_LSwill stabilize.

2.2. V_DDwill rise as the internal regulator charges the external reservoir capacitor and the IC will come out of reset.

2.3. Initialize interrupt handler for MCU

2.4. Interrupt will occur because of the RESET (Interrupt processing will occur here)

3. Initialize registers

3.1. Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts.

3.2. Set desired dead time either by commanding zero dead time or calibrating the dead time.

3.3. Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes.

4. Bring EN1 & EN2 high

5. Initialize the outputs

5.1. Command all Px_LS and Px_HS to logic 1 simultaneously (command ON Low Side, sequentially switching the phases

will reduce the transient with very large bootstrap capacitors and may prevent an unintended reset)

5.2. Command all Px_LS and Px_HS to logic 0 simultaneously (command ON High Side)

5.3. Command all Px_LS and Px_HS to logic 1 simultaneously (command ON Low Side)

5.4. The device is now ready for operation.

MAIN LOOP

1. While (forever)

1.1. Send SPI messages (except NULL1-3), read results

1.2. If sending NULL1-3 messages, use a semaphore to detect interrupts

1.2.1. Set Semaphore flag in RAM

1.2.2. Send NULL1-3

1.2.3. Send NULL0, read SR1-3

1.2.4. If Semaphore is still set, then result is good, else go to 1.2.1 (because an interrupt has gotten in the way)

1.2.5. Clear semaphore

2. END

Interrupt Handler

When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take

corrective action (if needed), clear the fault and return.

Because the return value from an SPI command is actually returned in the subsequent message, main-loop software that tries

to read SR1, SR2 or SR3, may experience an interrupt between sending the SPI command and the subsequent read. Thus if

these registers are to be read, special care must be taken in the software to ensure that the correct results are being interpreted.

1. Interrupt Service Routine:

1.1. Disable further interrupts from the 33937

1.2. Clear semaphore set in 1.2.1 of Main loop. This indicates to the main loop that an interrupt occurred and that the

return value it gets may not be as expected.

1.3. Send NULL0 Command. Ignore return value (the previous command is unknown)

1.4. Send NULL0 Command. The return value will be SR0 from the previous NULL0 command

2. Process Bits in SR0 and correct any faults

3. Send CLINT0 command to clear known (i.e. processed faults from SR0) faults 0:3

4. Send CLINT1 command to clear processed faults 4:7. Note, the return SR0 register from this command is actually read in

the main routine.

5. Re-enable interrupts from the 33937

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FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSIS FEATURES

6. Return

PROTECTION AND DIAGNOSIS FEATURES

Table 19. 33937 Fault Protection

No.

Fault

Cause

Detection

33937 Protective Action

•

Directly sensed by ADC as voltage

across R_SENSE

Over-current Comparator output

OC_OUT monitoring (Over-current

Error)

1

Phase Output

Shorted to VSUP battery

Wire harness shorted to

•

All external FETs turned off

Fault bit set in Status Register

INT pin set high

(High Side FET

Shorted)

Drain-to-Source short on the

High Side FET

OC_OUT pin set high

•

Low Side Phase Error

Direct PHASEx output monitoring

2

3

Phase Output

Shorted to

Ground (R_SENSE

Bypassed)

Wire harness shorted to

battery

•

Desaturation Error

High Side Phase Error

Direct PHASEx output monitoring

•

All external FETs turned off

Fault bit set in Status Register

INT pin set high

•

Directly sensed by the ADC as

voltage across R_SENSE

Over-current Comparator output

OC_OUT high (Over-current error)

Desaturation Error

Low Side FET

Shorted

Drain-to-Source short on the

Low Side FET

•

All external FETs turned off

Fault bit set in Status Register

INT pin set high

•

OC_OUT pin set high

High Side Phase Error

Direct PHASEx output monitoring

•

All external FETs turned off

Fault bit set in Status Register

INT pin set high

4

5

6

High Side FET

Opened

Module board assembly

issue

•

Desaturation Error

High Side Phase Error

•

Directly sensed by ADC as voltage

across R_SENSE

Low Side Phase Error

•

All external FETs turned off

Fault bit set in Status Register

INT pin set high

Low Side FET

Opened

Module board assembly

issue

Phase Output

Opened (No

Load)

Wire harness open

Directly sensed by ADC as voltage

across R_SENSE

NOTE: Other protective actions should be taken at the system level by the controlling microcontroller or DSP. It is possible to disable all

automatic shutdowns except for VLS undervoltage. Even when masked, faults will be registered by the status registers.

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40

TYPICAL APPLICATIONS

PROTECTION AND DIAGNOSIS FEATURES

TYPICAL APPLICATIONS

V

SYS

+12V Nom.

To Other

Two Phases

C6

D1

D2

C2

C1

PUMP

VPWR

VSUP

VPUMP

Main

Charge

Pump

Trickle

Charge

Pump

Hold

-Off

Circuit

PGND

5V

Reg.

VDD

VLS

Reg.

VLS

Oscillator

C3

VDD

C4

UV

Detect

3 x

T-Lim

Px_BOOT

Px_HS_G

Q

HS

C

RST

x_Boot

R

High

-Side

INT

EN1

EN2

g_HS

VSUP

(Optional)

Driver

Control

Logic

+

1.4V

-

Desat.

Comp.

3

Px_HS

Px_LS

Phase x

Output

To Motor

Px_HS_S

CS

SI

Q

SCLK

SO

LS

Low

-Side

R

g_LS

Phase

Comp.

VSUP

3

PHASE_x

Px_LS_G

Px_LS_S

(Optional)

Driver

Phase

Return

OC_OUT

GND

I-sense

Amp.

Over-Cur.

Comp.

R1

R2

R

Sense

AMP_OUT

AMP_P

R3

OC_TH

VLS_CAP

C5

AMP_N

+

-

+

-

R

fb

To ADC

Figure 22. Typical Application Diagram Using Charge Pump (+12 V Battery System)

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TYPICAL APPLICATIONS

PROTECTION AND DIAGNOSIS FEATURES

V

SYS

+42V Nom.

+14V Nom.

To Other

Two Phases

C6

C2

PUMP

VPWR

VSUP

VPUMP

Main

Charge

Pump

Trickle

Charge

Pump

Hold

-Off

Circuit

PGND

5V

Reg.

VDD

VLS

Reg.

VLS

Oscillator

C3

VDD

C4

UV

Detect

3 x

T-Lim

Px_BOOT

Px_HS_G

Q

HS

C

RST

x_Boot

R

High

-Side

INT

EN1

EN2

g_HS

VSUP

(Optional)

Driver

Control

Logic

+

1.4V

-

Desat.

Comp.

3

Px_HS

Px_LS

Phase x

Output

To Motor

Px_HS_S

CS

SI

Q

SCLK

SO

LS

Low

-Side

R

g_LS

Phase

Comp.

VSUP

3

PHASE_x

Px_LS_G

Px_LS_S

(Optional)

Driver

Phase

Return

OC_OUT

GND

I-sense

Amp.

Over-Cur.

Comp.

R1

R2

R

Sense

AMP_OUT

AMP_P

R3

OC_TH

VLS_CAP

C5

AMP_N

+

-

+

-

R

fb

To ADC

Figure 23. High Voltage Application Diagram (+42 V Battery System)

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

TYPICAL APPLICATIONS

PROTECTION AND DIAGNOSIS FEATURES

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

5

10

15

20

25

30

35

40

Supply Voltage (V)

Figure 24. Power Dissipation Profile of Application Using Charge Pump

Reference application with:

•

Pump capacitor: 1.0 μF MLC

Pump filter capacitor: 47 μF low ESR aluminum electrolytic

Pump diodes: MUR120

Output FET gate charge: 240 nC @ 10 V

PWM Frequency: 20 kHz

Switching Single Phase

Below approximately 17 V the charge pump is actively regulating V_PWR. The increased power dissipation is due to the charge

pump losses. Above this voltage the charge pump oscillator shuts down and V_SYSis passed through the pump diodes directly to

V_PWR

.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

PROTECTION AND DIAGNOSIS FEATURES

1.500

1.400

1.300

1.200

1.100

1.000

0.900

0.800

0.700

0.600

0.500

0.400

0.300

0.200

0.100

0.000

10

15

20

25

30

35

40

45

50

55

60

Supply Voltage (V)

Figure 25. Power Dissipation Profile of Application Not Using Charge Pump

Reference application with:

•

Output FET gate charge: 240 nC @ 10 V

PWM Frequency: 20 kHz

Switching Single Phase

No connections to PUMP or VPUMP

VPWR connected to V_SYS

If VPWR is supplied by a separate pre-regulator, the power dissipation profile will be nearly flat at the value of the pre-regulator

voltage for all V_SYSvoltages.

33937

Analog Integrated Circuit Device Data

44

Freescale Semiconductor

PACKAGING

PACKAGING DIMENSION

PACKAGING

PACKAGING DIMENSION

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EK SUFFIX (PB-FREE)

54-PIN

98ASA99334D

ISSUE C

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

45

PACKAGING

PACKAGING DIMENSION (CONTINUED)

EK SUFFIX (PB-FREE)

54-PIN

98ASA99334D

ISSUE C

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

46

REVISION HISTORY

REVISION

1.0

DATE

6/2008

7/2008

DESCRIPTION OF CHANGES

•

Initial Release

•

Updated specifications for current sense amplifier and overcurrent comparator

Added Gain/Phase curves for current sense amplifier

Added typical curves for load margin on Px_CBOOT

Added discussion about bootstrap capacitors and requirements for external bootstrap diodes

Updated application drawings

Added VSUP requirement for hold-off

2.0

•

Updated Freescale form and style

11/2008

12/2008

3.0

4.0

Added note to VLS Regulator Outputs (VLS, VLS_CAP)⁽²⁾

Changed Charge Device Model - CDM

Corrected title to No output loads on Gate Drive Pins, No PWM, Outputs initialized

Changed CAUTION for 33937 only (Use the 33937A to avoid this CAUTION) and associated

paragraphs

•

Added PCZ33937AEK/R2 Part number throughout.

Added Note and changed parameters for Desaturation Detector and Phase Comparator to

Dynamic Electrical Characteristics Table.

•

Replaced Typical Application Diagrams (Pages 40 and 41).

Page 10 remove V_DDThreshold (V_DDFalling) change note 23

4/2009

9/2009

•

Note 41 clarification.

5.0

6.0

Changed part number from PCZ33937A to MCZ33937A on page 1. Added Device Variation table

on page 2.

33937

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

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USA/Europe or Locations Not Listed:

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Information in this document is provided solely to enable system and

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are the property of their respective owners.

33937

Rev. 6.0

9/2009