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February 2007  
rev 1.4  
ASM3P2508A  
Peak EMI Reducing Solution  
Features  
The ASM3P2508A allows significant system cost savings  
by reducing the number of circuit board layers and  
shielding that are required to pass EMI regulations. The  
ASM3P2508A modulates the output of PLL in order to  
spread the bandwidth of a synthesized clock, thereby  
decreasing the peak amplitudes of its harmonics. This  
results in significantly lower system EMI compared to the  
typical narrow band signal produced by oscillators and  
most clock generators. Lowering EMI by increasing a  
signal’s bandwidth is called spread spectrum clock  
generation.  
•
Generates an EMI optimized clocking signal at  
output.  
•
•
Input frequency – 14.31818MHz.  
Frequency outputs:  
•
•
120MHz (modulated) - default.  
72MHz (modulated) or 48MHz (modulated)  
selectable via I2C  
•
•
•
•
•
•
± 1% Centre spread.  
Modulation rate: 40KHz.  
Byte Write via I2C  
Supply voltage range 3.3V ± 0.3V.  
Available in 8-pin SOIC Package.  
Available in Commercial and Industrial  
Temperature ranges.  
The ASM3P2508A has a feature to power down the  
72MHz/48MHz output by writing data into specific  
registers in the device via I2C. By writing a ‘0’ into bit 1 of  
Byte 0, the PLL block generating 72MHz / 48MHz can be  
powered down. Writing ‘0’ into bit ‘7’ of Byte 1 selects an  
output of 72 MHz on FOUT2CLK while a ‘1’ at the same  
location selects a 48 MHz clock output. However, the I2C  
block, crystal oscillator, and the PLL block generating  
120MHz would be always running.  
Product Description  
The ASM3P2508A is  
a versatile spread spectrum  
frequency modulator. The ASM3P2508A reduces  
electromagnetic interference (EMI) at the clock source.  
Block Diagram  
VDD  
XIN  
XOUT  
Crystal  
PLL 1  
Oscillator  
FOUT1CLK  
(120MHz)  
SCL  
SDA  
I2C  
PLL 2  
FOUT2CLK  
Interface  
(72 MHz / 48MHz)  
V
SS  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
Pin Configuration  
1
2
3
4
8
7
6
5
XIN  
V
SS  
SCL  
XOUT  
ASM3P2508A  
SDA  
V
DD  
FOUT2CLK  
FOUT1CLK  
Pin Description  
Pin Name  
XIN  
Type  
Description  
I
O
P
O
O
I/O  
I
Connection to crystal  
Connection to crystal  
XOUT  
VDD  
FOUT1CLK  
FOUT2CLK  
SDA  
Power supply for the analog and digital blocks  
Clock output-1 (120MHz) - default  
Clock output-2 ( 72MHz / 48MHz)  
I2C Data  
SCL  
I2C Clock  
VSS  
P
Ground to entire chip  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
-0.5 to +4.6  
-40 to +85  
0 to 70  
Unit  
V
°C  
°C  
°C  
°C  
VDD, VIN  
TSTG  
TA  
Voltage on any pin with respect to Ground  
Storage temperature  
Operating temperature  
Ts  
TJ  
Max. Soldering Temperature (10 sec)  
Junction Temperature  
260  
150  
Static Discharge Voltage  
TDV  
2
KV  
(As per JEDEC STD22- A114-B)  
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect  
device reliability.  
Operating Conditions  
Condition /  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Description  
VDD  
Supply Voltage  
3.3V ± 10%  
3
3.3  
3.6  
V
TA  
Ambient Operating Temperature Range  
Crystal Resonator Frequency  
Serial Data Transfer Rate  
-10  
+70  
°C  
MHz  
Kb/s  
pF  
FXIN  
14.31818  
Standard Mode  
10  
100  
15  
CL  
Output Driver Load Capacitance  
Peak EMI Reducing Solution  
2 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
DC Electrical Characteristics  
(Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated)  
Parameter  
Symbol  
Conditions / Description  
Min  
Typ  
Max  
Unit  
Overall  
Supply Current,  
VDD =3.3V, FCLK =14.31818MHz,  
CL=15pF  
Icc  
40  
27  
49  
35  
60  
43  
mA  
mA  
Dynamic  
Supply Current,  
Static  
IDD  
VDD = 3.3V, Software Power Down*  
All input pins  
High-Level Input  
VIH  
VIL  
IIH  
VDD=3.3V  
VDD=3.3V  
2.0  
VSS-0.3  
-1  
-
-
VDD+0.3  
0.8  
V
Voltage  
Low-Level Input  
Voltage  
V
High-Level Input  
Current  
µ A  
-
1
Low-Level Input  
µ A  
IIL  
-20  
-36  
-80  
Current (pull-up)  
Clock Outputs (FOUT1CLK, FOUT2CLK)  
High-Level Output  
VOH  
VOL  
VDD= 3.3V, IOH = 20mA  
2.5  
0
-
-
3.3  
0.4  
V
V
Voltage  
Low-Level Output  
Voltage  
VDD= 3.3V, IOL = 20mA  
ZOH  
ZOL  
VO=0.5VDD; output driving high  
Vo=0.5VDD; output driving low  
-
-
29  
27  
-
-
Output Impedance  
Ω
* FOUT1CLK (120MHz) is functional and not loaded  
AC Electrical Characteristics  
Parameter  
Rise Time  
Fall Time  
Symbol  
Conditions/ Description  
Min  
Typ  
Max  
Unit  
pS  
FOUT1CLK  
640  
440  
660  
460  
680  
480  
720  
520  
750  
600  
800  
570  
tr  
tf  
VO = 0.8V to 2.0V; CL = 15pF  
VO = 2.0V to 0.8V; CL = 15pF  
FOUT2CLK  
FOUT1CLK  
FOUT2CLK  
pS  
Clock Duty  
Cycle  
Ratio of pulse width (as measured from rising edge  
tD  
45  
-
55  
%
to next falling edge at 2.5V) to one clock period  
Output Frequency =120MHz  
Output Frequency =72MHz /48 MHz  
-
-
±2.73  
±1.78  
-
-
Frequency  
Deviation  
fD  
%
On rising edges 500 uS apart at 2.5 V relative to an  
-
-
-
-
45  
-
-
-
-
ideal clock, PLL B inactive *  
Jitter, Long  
Term  
Tj (LT)  
pS  
On rising edges 500 uS apart at 2.5 V relative to an  
ideal clock, PLL B active *  
165  
110  
390  
From rising edge to next rising edge at 2.5 V,  
PLL B inactive *  
Jitter, peak to  
peak  
Tj (∆T)  
pS  
µS  
From rising edge to next rising edge at 2.5 V,  
PLL B active *  
Clock  
Output active from power up, RUN Mode via  
Software Power Down  
Stabilization  
Time  
tSTB  
-
125  
-
* CL = 15 pF, Fxin = 14.31818MHz  
Peak EMI Reducing Solution  
3 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
Typical Crystal Oscillator Circuit  
R1 = 510Ω  
Crystal  
C1 = 27 pF  
C2 = 27 pF  
Typical Crystal Specifications  
Fundamental AT cut parallel resonant crystal  
Nominal Frequency  
14.31818MHz  
Frequency Tolerance  
Operating temperature range  
Storage Temperature  
Load Capacitance  
+/- 50 ppm or better at 25°C  
-20°C to +85°C  
-40°C to +85°C  
18pF  
Shunt capacitance  
ESR  
7 pF maximum  
25 Ω  
Peak EMI Reducing Solution  
4 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
I2C Serial Interface Information  
The information in this section assumes familiarity with I2C programming.  
How to program ASM3P2508A through I2C:  
How to Read from ASM3P2508A through I2C:  
•
•
•
•
Master (host) sends a start bit.  
•
•
•
•
Master (host) will send start bit.  
Master (host) sends the write address D4 (H).  
ASM3P2508A device will acknowledge.  
Master (host) sends the beginning byte location  
(N = 0, 1).  
Master (host) sends the write address D4 (H).  
ASM3P2508A device will acknowledge.  
Master (host) sends the beginning byte location  
(N = 0, 1).  
•
•
•
•
ASM3P2508A device will acknowledge.  
Master (host) sends a byte count (X = 1,2)  
ASM3P2508A device will acknowledge.  
Master (host) starts sending byte N through byte  
(N+X – 1)  
ASM3P2508A device will acknowledge each byte one  
at a time.  
Master (host) sends a Stop bit.  
•
•
•
•
•
ASM3P2508A device will acknowledge.  
Master (host) will send a separate start bit.  
Master (host) sends the read address D5 (H).  
ASM3P2508A device will acknowledge.  
ASM3P2508A device will send the byte count  
(X = 1, 2).  
Master (host) acknowledges.  
ASM3P2508A device sends byte N through byte  
(N+X – 1).  
•
•
•
•
•
•
Master (host) will need to acknowledge each byte.  
Master (host) will send a stop bit.  
ASM3P2508A  
Controller (Host)  
(slave/receiver)  
Start Bit  
Slave Address D4(H)  
Controller (Host)  
ASM3P2508A  
(slave/receiver)  
ACK  
Start Bit  
Beginning byte location (=N)  
Slave Address D4(H)  
ACK  
ACK  
Byte count (=X)  
Beginning Byte = N  
ACK  
ACK  
Beginning byte (Byte N)  
Repeat start  
ACK  
Slave address D5(H)  
Next Byte (Byte N+1)  
ACK  
ACK  
Byte Count (= X)  
-------  
ACK  
ACK  
ACK  
-------  
----  
Beginning byte N  
Next Byte N+1  
----  
Last Byte (Byte N+X-1)  
ACK  
Stop Bit  
Last Byte (Byte N+X-1)  
Not Acknowledge  
Stop Bit  
Peak EMI Reducing Solution  
5 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
57 (H). To put ASM3P2508A in ‘power down’ mode, the  
bit 1 of Byte 0 is to be changed to logic ‘0’. Hence writing a  
55 (H) via I2C into Byte 0 would put the device in partial  
‘power down’ mode where the PLL block generating  
72 MHz / 48 MHz would be powered down while I2C block,  
crystal oscillator, and the PLL block generating 120 MHz  
would still be active. The organization of the register bits is  
as below:  
An example of a Byte Write via I2C to partially ‘power  
down’ the device:  
ASM3P2508A can be partially ‘powered down’ using bit 1  
of Byte 0. The organization of the register bits for Byte ‘0’ is  
given with default values below:  
Bit  
Bit  
7
6
5
4
3
2
1
PLL2  
Enable Enable  
0
PLL1  
7
6
5
4
3
2
1
PLL2  
0
PLL1  
Resv Resv Resv  
Resv Resv Resv  
Resv Resv Resv  
Resv Resv Resv  
Enable Enable  
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
The function of partial power down of the device is of  
interest to us - that is bit 1 of Byte 0. In the default mode  
this bit is logic ‘1’. As such, the Byte 0 default value is  
Byte 0  
Byte 1  
3F(H)  
BF(H)  
3F(H)  
BF(H)  
FOUT1CLK (MHz)  
FOUT2CLK(MHz)  
Power up default  
48_MHz Mode  
Power down PLL with 72MHz  
Power down PLL with 48MHz  
6F(H)  
6F(H)  
6D(H)  
6D(H)  
120  
120  
120  
120  
72  
48  
-
-
Figure showing a complete data transfer:  
.
Peak EMI Reducing Solution  
6 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
Package Information  
8-lead (150-mil) SOIC Package  
H
E
D
A2  
A
C
θ
e
A1  
L
B
Dimensions  
Symbol  
Inches  
Millimeters  
Min  
Max  
0.010  
0.069  
0.059  
0.020  
0.010  
Min  
0.10  
1.35  
1.25  
0.31  
0.18  
Max  
0.25  
1.75  
1.50  
0.51  
0.25  
A1  
A
0.004  
0.053  
0.049  
0.012  
0.007  
A2  
B
C
D
E
0.193 BSC  
0.154 BSC  
0.050 BSC  
0.236 BSC  
4.90 BSC  
3.91 BSC  
1.27 BSC  
6.00 BSC  
e
H
L
0.016  
0°  
0.050  
8°  
0.41  
0°  
1.27  
8°  
θ
Peak EMI Reducing Solution  
7 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
Ordering Codes  
Part number  
Marking  
3P2508AG  
Package Configuration  
Temperature  
Commercial  
Commercial  
Industrial  
ASM3P2508AG-08ST  
ASM3P2508AG-08SR  
ASM3I2508AG-08ST  
ASM3I2508AG-08SR  
ASM3P2508AF-08ST  
ASM3P2508AF-08SR  
ASM3I2508AF-08ST  
ASM3I2508AF-08SR  
8-PIN SOIC, TUBE, Green  
3P2508AG  
3I2508AG  
3I2508AG  
3P2508AF  
3P2508AF  
3I2508AF  
3I2508AF  
8-PIN SOIC, TAPE AND REEL, Green  
8-PIN SOIC, TUBE, Green  
8-PIN SOIC, TAPE AND REEL, Green  
8-PIN SOIC, TUBE, Pb Free  
Industrial  
Commercial  
Commercial  
Industrial  
8-PIN SOIC, TAPE AND REEL, Pb Free  
8-PIN SOIC, TUBE, Pb Free  
8-PIN SOIC, TAPE AND REEL, Pb Free  
Industrial  
Device Ordering Information  
A S M 3 P 2 5 0 8 A F - 0 8 S R  
R = Tape & Reel, T = Tube or Tray  
O = SOT  
U = MSOP  
E = TQFP  
L = LQFP  
U = MSOP  
P = PDIP  
S = SOIC  
T = TSSOP  
A = SSOP  
V = TVSOP  
B = BGA  
D = QSOP  
X = SC-70  
Q = QFN  
DEVICE PIN COUNT  
F = LEAD FREE AND RoHS COMPLIANT PART  
G = GREEN PACKAGE, LEAD FREE, and RoHS  
PART NUMBER  
X= Automotive  
I= Industrial  
P or n/c = Commercial  
(0C to +70C)  
(-40C to +125C) (-40C to +85C)  
1 = Reserved  
6 = Power Management  
7 = Power Management  
8 = Power Management  
9 = Hi Performance  
0 = Reserved  
2 = Non PLL based  
3 = EMI Reduction  
4 = DDR support products  
5 = STD Zero Delay Buffer  
PulseCore Semiconductor Mixed Signal Product  
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.  
Peak EMI Reducing Solution  
8 of 9  
Notice: The information in this document is subject to change without notice.  
February 2007  
rev 1.4  
ASM3P2508A  
Copyright © PulseCore Semiconductor  
All Rights Reserved  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200  
Campbell, CA 95008  
Preliminary Information  
Part Number: ASM3P2508A  
Document Version: v1.3  
Tel: 408-879-9077  
Fax: 408-879-9018  
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003  
© Copyright 2007 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or  
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their  
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without  
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein  
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct  
this data at any time, without notice. If the product described herein is under development, significant changes to these  
specifications are possible. The information in this product data sheet is intended to be general descriptive information for  
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or  
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product  
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products  
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual  
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from  
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.  
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,  
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products  
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result  
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the  
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use  
Peak EMI Reducing Solution  
9 of 9  
Notice: The information in this document is subject to change without notice.