AT25DF021-MH-T--Datasheet/数据表在线中文翻译

Features

• Very Low-cost Configuration Memory

• Programmable 1,048,576 x 1, 2,097,152 x 1, 4,194,304 x 1 and 7,340,032 x 1-bit Serial

Memories Designed to Store Configuration Programs for Field Programmable Gate

Arrays (FPGAs)

• 1.8V, 2.5V, and 3.3V I/O

• 3.3V Supply Voltage

• Program Support using an Atmel Programmer or Industry-standard Third Party

Programmers

FPGA

• In-System Programmable (ISP) via JTAG Interface (IEEE 1532)

• IEEE 1149.1 Boundary-scan Testability

Configuration

Flash Memory

• Simple Interface to SRAM FPGAs

• Pin Compatible with Xilinx^®XCFxxS Series Platform Flash PROM to Configure Xilinx

Spartan^®and Virtex^®FPGAs

• Cascadable Read-back to Support Additional Configurations or Higher-density FPGAs

• Low-power CMOS FLASH Process

AT18F010

AT18F002

AT18F040

AT18F080

• Available in 20-lead TSSOP Package

• Low-power Standby Mode

• Fast Serial Download Speeds up to 33 MHz

• Endurance: 100,000 Write Cycles Typical

• Green (Pb/Halide-free/RoHS Compliant) Package

• Functionally-compatible with Existing AT17 Series Configuration Memories to

Configure Atmel AT40KAL Series FPGAs

AT18F Series Configuration Memory Offering

Preliminary

AT18F010

AT18F002

AT18F040

AT18F080

Density

1 Mbit

2 Mbit

4 Mbit

7 Mbit

JTAG Programming

VCCINT

Yes

3.3V

VCCO

1.8-3.3V

VCCJ

Configuration Clock

Package

33 MHz

20-lead TSSOP

Yes

Green Package

1. Description

The AT18F Series of JTAG In-System Programmable Configuration PROMs (Configu-

rators) provide an easy-to-use, cost-effective configuration memory for Field

Programmable Gate Arrays. The AT18F Series device is packaged in a 20-lead

TSSOP. The AT18F Series Configurator uses a simple serial-access procedure to

configure one or more FPGA devices.

The AT18F Series Configurators can be programmed with Atmel or industry-standard,

third-party, stand-alone programmers such as BP, Data I/O, Hi-Lo, etc.

3672A–CNFG–1/08

2. Pin Configuration

20-lead TSSOP

DATA

NC

1

2

3

4

5

6

7

8

9

10

20

VCCJ

VCCO

VCCINT

TDO

NC

19

18

17

16

15

14

13

12

11

CLK

TDI

TMS

TCK

NC

CF

NC

RESET/OE

NC

CEO

NC

CE

GND

3. Block Diagram

Power-on

Reset

TCK

TMS

TDI

JTAG

Interface

TDO

Internal

Oscillator

Controller

CF

CE

Download

Interface

RESET/OE

CEO

Flash

DATA

Memory

CLK

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AT18F010/002/040/080 [Preliminary]

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AT18F010/002/040/080 [Preliminary]

4. Device Description

The download interface of the configuration memory will directly communicate with the FPGA

through the interface-control signals (CLK, RESET/OE, CE) to initialize and terminate configura-

tion. All FPGA devices in the master serial mode can control the entire configuration process to

receive data from the configuration device without requiring an external intelligent controller.

When FPGA devices are used in slave serial mode, an external clock signal can be applied to

the CLK pin of an AT18F series device as a configuration loading clock. Multiple FPGAs that are

setup in Master Serial and Slave Serial modes can also be used to control the configuration pro-

cess to obtain data from a single configurator or cascaded configurators. Please contact Atmel

at configurator@atmel.com for detailed descriptions.

The CF pin is used as an optional input pin for the JTAG CONFIG instruction to initialize the

FPGA configuration without requiring powering down the device. The RESET/OE and CE pins

control the tri-state buffer on the DATA output pin and enable the address counter. When

RESET/OE is driven Low, the configuration device resets its address counter and tri-states its

DATA pin. The CE pin also controls the output of the AT18F Series Configurator. If CE is held

High after the RESET/OE reset pulse, the counter is reset and the DATA output pin is tri-stated.

When the configurator has driven out all of its data and CEO is driven Low, the device tri-states

the DATA pin to avoid contention with other configurators. Upon power-up, the address counter

is automatically reset.

3

3672A–CNFG–1/08

AT18F series devices are compatible with a portion of the Xilinx’s FGPA device families.

Table 4-1.

Atmel

AT18F Series Configurator Compatibility with Xilinx FPGAs

Xilinx Atmel

XC2V40

Xilinx

XC2VP4

Virtex-II Pro

Virtex-II

XC2V80

XC2V500

XCV50E

XCV100E

XCV50

XC2V1000

XCV400E

XCV405E

XCV600E

XCV400

Virtex-E

Virtex

XCV100

XCV150

AT18F040-30XU Virtex

Spartan-3E

Spartan-3

XC3S100E

XC3S50

XCV600

AT18F010-30XU

XC3S500E

XC3S1200E

XC3S1000L

XC3S1000

XC2S400E

XC2S600E

XC5VLX30

XC4VLX15

XC4VLX25

XC4VFX12

XC4VFX20

Spartan-3E

XC3S200

XC2S50E

XC2S100E

XC2S15

Spartan-3L

Spartan-3

Spartan-IIE

Virtex-5 LX

Virtex-4 LX

XC2S30

Spartan-II

XC2S50

XC2S100

XC2S150

XC2VP2

XC2V250

XCV200E

XCV300E

XCV200

Virtex-II Pro

Virtex-II

Virtex-4 FX

Virtex-II Pro X XC2VPX20

Virtex-E

Virtex

XC2VP7

Virtex-II Pro

XC2VP20

XCV300

XC2V1500

Virtex-II

AT18F002-30XU

Spartan-3E

Spartan-3

XC3S250E

XC3S400

XC2S150E

XC2S200E

XC2S300E

XC2S200

AT18F080-30XU

XC2V2000

XCV812E

Virtex-E

XCV1000E

XCV1600E

XCV800

Spartan-IIE

Spartan-II

Virtex

XCV1000

Spartan-3E

Spartan-3L

XC3S1600E

XC3S1500L

XC3S1500

XC3S2000

Spartan-3

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AT18F010/002/040/080 [Preliminary]

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AT18F010/002/040/080 [Preliminary]

5. Programming

AT18Fxx devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol.

This capability eliminates package handling normally required for programming and facilitates

rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow programming of the AT18Fxx via the PC.

ISP is performed by using either a download cable or a comparable board tester or a simple

microprocessor interface.

To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial

Vector Format (SVF) files can be created by the Atmel JCPS Software. Conversion to other ATE

tester format beside SVF is also possible

AT18Fxx devices can also be programmed using standard third-party programmers such as BP,

DataI/O, Hi-Lo, etc. Factory-preprogrammed devices, as required by customers, are also avail-

able for certain ordering quantities.

Contact your local Atmel representatives or Atmel PLD applications for details.

5.1

JTAG-BST Overview

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the

AT18F series. The boundary-scan technique involves the inclusion of a shift-register stage (con-

tained in a boundary-scan cell) adjacent to each component so that signals at component

boundaries can be controlled and observed using scan testing principles. Each input pin and I/O

pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The

AT18Fxx series does not currently include a Test Reset (TRST) input pin because the TAP con-

troller is automatically reset at power-up. The six JTAG BST modes supported include:

SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the AT18Fxx series is imple-

mented using the Boundary-scan Definition Language (BSDL) described in the JTAG

specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be

used to perform BST on the AT18Fxx series.

The AT18F series uses the four JTAG-standard I/O pins for In-System programming (ISP). The

AT18F series is programmable through the four JTAG pins using programming algorithm com-

patible with the IEEE JTAG Standard 1532. Programming is performed by using selectable

voltage levels of the programming signals from the JTAG ISP interface.

5.2

JTAG Boundary-scan Cell (BSC) Testing

The AT18F series has I/Os that contain boundary-scan cells (BSC) in order to support bound-

ary-scan testing as described in detail by IEEE Standard 1149.1. Input to the capture register

chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are

used to capture active device data signals, to shift data in and out of the device and to load data

into the update registers. Control signals are generated internally by the JTAG TAP controller.

5

3672A–CNFG–1/08

6. Pin Description

Table 6-1.

Pin Descriptions

Name

DATA

CLK

Type

20-lead TSSOP

I/O

1

I

3

RESET/OE

CE

I

8

I

10

CF

I

7

CEO

TMS

O

13

I

5

TCK

I

6

TDI

I

4

TDO

O

17

VCCINT

NC

I

18

-

2, 9, 12, 14, 15, 16

VCCO

GND

VCCJ

Power Supply

Ground

19

11

20

Power Supply

6.1

6.2

DATA (D0)

CLK

Open-collector bi-directional data pin. This pin has an internal 20 KΩ pull-up resistor.

Clock input. Used to increment the internal address and bit counter for reading and program-

ming. This pin has an internal 20 KΩ pull-up resistor.

6.3

6.4

RESET/OE

CE

Output Enable (active High) and RESET (active Low). A Low level on RESET/OE resets both

the address and bit counters. A High level (with CE Low) enables the data output driver. This pin

has an internal 20 KΩ pull-up resistor.

Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address

counter and enables the data output driver. A High level on CE disables both the address and bit

counters and forces the device into a low-power standby mode. This pin has an internal 20 KΩ

pull-up resistor.

6.5

CF

Configuration Pulse (open-drain output). Allows JTAG CONFIG instruction to initiate FPGA con-

figuration without powering down the FPGA. This is an open-drain output that is pulsed Low by

the JTAG CONFIG command.

6

AT18F010/002/040/080 [Preliminary]

3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

6.6

6.7

CEO

TMS

Chip Enable Output for configuration download. This output goes Low when the internal address

counter of the device has reached its maximum value which signals that all configuration data is

being clocked out of the device. In a daisy chain of AT18F Series devices, the CEO pin of one

device must be connected to the CE input of the next device in the chain. It will stay Low as long

as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay

High until the entire memory device is read again.

JTAG Mode Control Input. The state of TMS with the rising edge of TCK determines the state

transitions of the Test Access Port (TAP) controller. TMS has an internal 50 KΩ weak pull-up to

V

_CCJto provide a logic 1 to the device.

6.8

6.9

TCK

TDI

JTAG Clock Input. This pin is the JTAG clock input to the TAP controller of the device.

JTAG Serial Data Input. This pin is the serial input to all JTAG instructions and data registers. An

internal 50 KΩ weak pull-up to V_CCJprovides a logic 1 to the device.

6.10 TDO

JTAG Serial Data Output. This pin is the serial output to all JTAG instruction and data registers.

An internal 50 KΩ weak pull-up to V_CCJprovides a logic 1 to the device if the pin is not driven.

6.11 VCCINT

6.12 NC

+3.3V supply voltage for internal logic.

No Connect Pin. This pin is not connected to any internal logic of the device and can be left

floating.

6.13 VCCO

6.14 VCCJ

6.15 GND

Supply voltage for I/O drivers (1.8V, 3.3V, or 3.3V).

Supply voltage for JTAG I/O drivers (1.8V, 3.3V, or 3.3V).

Power supply ground.

7. Standby Mode

The AT18F Series Configurators enter a low-power standby mode whenever the JTAG mode is

inactive and CE is asserted High. In this mode, the AT18F Configurator consumes less than 1

mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of

the OE input.

7

3672A–CNFG–1/08

8. Configuration Memory to FPGA Device Interface Connection Diagrams

Figure 8-1. General Connection Diagram for Loading FPGA from Configurator and JTAG Signals

Notes: 1. Signals within parenthesis will be applied to Atmel AT40AK FPGA.

2. For details of the circuit connection, please contact factory.

8

AT18F010/002/040/080 [Preliminary]

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AT18F010/002/040/080 [Preliminary]

9. Absolute Maximum Ratings*

Operating Temperature................................. -55°C to +125° C

*NOTICE:

Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those listed under oper-

ating conditions is not implied. Exposure to Abso-

lute Maximum Rating conditions for extended

periods of time may affect device reliability.

Storage Temperature.................................... -65°C to +150° C

Voltage on Any Pin

with Respect to Ground..............................-0.1V to V_CC+0.5V

Supply Voltage (V_CC) .........................................-0.5V to +3.6V

Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260° C

ESD (R_ZAP= 1.5K, C_ZAP= 100 pF)................................. 2000V

10. Operating Conditions

T_AI= -40° C to +85° C for Industrial and 0°C to +70°C for Commercial

Symbol Description

Min

3.0

2.3

1.7

3.0

2.3

1.7

-0.3

2.0

1.7

Typ

3.3

2.5

1.8

3.3

2.5

1.8

Max

3.6

Units

V_CCINT

Supply Voltage for Internal Logic

Supply Voltage for I/O Drivers

V

3.3V Operation

2.5V Operation

1.8V Operation

3.3V Operation

2.5V Operation

1.8V Operation

3.3V Operation

2.5V Operation

1.8V Operation

3.3V Operation

2.5V Operation

3.6

V_CCO

2.7

V

1.9

3.6

Supply Voltage for JTAG I/O Drivers

Input Low Voltage

2.7

V_CCJ

1.9

0.8

0.7

V_IL

0.35 x V_CCO

3.9

Input High Voltage

3.9

V_IH

1.8V Operation 0.65 x V_CCO

3.9

9

3672A–CNFG–1/08

11. DC Characteristics

Symbol

I_CCINT

I_CCIO

Description

Condition

33 MHz

Min

Typ

Max

10

5

Units

mA

Internal Voltage Supply Current, Active Mode

I/O Drive Supply Current, Active Mode

JTAG Supply Current, Active Mode

33 MHz

mA

I_CCJ

mA

V

_CCINT= 3.6V,

I_CCINTS

I_CCIOS

I_CCJS

Internal Voltage Supply Current, Standby Mode

Output Drive Supply Current, Standby Mode

JTAG Supply Current, Standby Mode

1

mA

V_CIO= 3.6V

V_CCINT= 3.6V,

V_CIO= 3.6V

V_CCINT= 3.6V,

V_CIO= 3.6V

I_IL

Input or I/O Low Leakage

Input or I/O High Leakage

3.3V Operation

1

10

µA

I_IH

-10

10

0.4

0.45

V_OL

Output Low Voltage

2.5V Operation

1.8V Operation

3.3V Operation

2.5V Operation

1.8V Operation

V

V_CCO- 0.4

V_OH

Output High Voltage

V

_CCO- 0.4

V_CCO- 0.45

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AT18F010/002/040/080 [Preliminary]

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AT18F010/002/040/080 [Preliminary]

12. AC Characteristics

Figure 12-1. AT18Fxx as Configuration Slave with CLK Input Pin as Clock Source

CE

T_HCE

T_HOE

T_SCE

RESET/OE

T_CYC

T_HC

T_LC

CLK

DATA

CF

T_OE

T_OH

T_DF

T_CE

T_CAC

T_CF

T_OH

Table 12-1. AC Characteristics over Operating Conditions

Symbol Description

Min

Max

50

Units

µs

ns

µs

ns

µs

ns

s

T_CF

CF to Data Delay

20

T_OE

RESET/OE to Data Delay

CE to Data Delay

10

T_CE

20

T_CAC

T_OH

CLK to Data Delay

15

25

Data Hold from CE, RESET/OE, CLK, or CF

CE or RESET/OE to Data Float Delay

Clock Period

T_DF

T_CYC

T_LC

30

15

CLK Low Time

T_HC

CLK High Time

15

T_SCE

T_HCE

T_HOE

T_BLKE

CE Setup Time to CLK

CE Hold Time

20

250

0.7

RESET/OE Hold Time

Block Erase Time

1

3

Bulk Erase Time – 1M

Bulk Erase Time – 2M

Bulk Erase Time – 4M

Bulk Erase Time – 8M

TAP Clock Minimum Period

s

5

s

T_ERASE

9

s

15

s

T_{CK_J}

100

ns

11

3672A–CNFG–1/08

Figure 12-2. AC Characteristics when Cascading

RESET/OE

CE

CLK

T_CDF

DATA

CEO

LAST BIT

FIRST BIT

T_OCE

T_OOE

T_OCK

Table 12-2. AC Characteristics When Cascading

Symbol Description

Min

Max

Units

ns

T_CDF

T_OCK

T_OCE

T_OOE

CLK to Output Float Delay

CLK to CEO Delay

25

20

ns

CE to CEO Delay

ns

RESET/OE to CEO Delay

ns

12

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3672A–CNFG–1/08

AT18F010/002/040/080 [Preliminary]

13. Ordering Information

Memory Size

Ordering Code

Package

Operation Range

Industrial

1-Mbit

AT18F010-30XU

AT18F002-30XU

AT18F040-30XU

AT18F080-30XU

20A2 - 20 TSSOP

(-40°C to 85°C)

Industrial

2-Mbit

4-Mbit

7-Mbit

20A2 - 20 TSSOP

(-40°C to 85°C)

Industrial

(-40°C to 85°C)

Industrial

(-40°C to 85°C)

Package Type

20-lead, 0.65 mm Wide, Plastic Think-Shrink Small Outline (TSSOP)

20A2

13

3672A–CNFG–1/08

14. Packaging Information

14.1 20A2 – TSSOP

b

Marked Pin1 Indentifier

E

L

L1

E

E1

A

D

A1

Top View

End View

Side View

e

Pin1 Corner

L1

COMMON DIMENSIONS

(Unit of Measure = mm)

0.10 mm

TYP

Top View

8

1

MIN

MAX

NOM

NOTE

SYMBOL

e

D

E

6.40

6.50

6.60

2, 5

COMMON DIMENSIONS

(Unit of Measure = mm)

D

7

2

3

6.40 BSC

A

A2

E1

SYMBOL

4.30

MIN

4.40

NOM

4.50

MAX

3, 5

NOTE

A

–

0.94

–

1.04

1.20

1.14

6

5

A2

A1

0.80

0.30

1.00

0.34

1.05

0.38

b

e

L

0.19

0.45

–

0.50

0.30

0.55

4

1

b

0.65 BSC

5.99

4

D

E

5.89

6.09

0.45

0.60

5.99

0.75

6.09

4.89

Side View

L1

1.00 REF

1.27 BSC

e1

L

e

e1

1.10 REF

Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional

Bottom View

information.

L

0.95

1.00

1.05

1.35

1

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall

L1 1.25 1.30

not exceed 0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed

0.25 mm (0.010 in) per side.

Note: 1. Metal Pad Dimensions.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess

of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.

Minimum space between protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

6/3/02

11/14/01

TITLE

DRAWING NO.

REV.

A

C

2325 Orchard Parkway

San Jose, CA 95131

20A2, 20-lead (4.4 x 6.5 mm Body), 0.65 pitch,

8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,

2

8

0

C

A

N

2

4

R

Thin Shrink Small Outline Package (TSSOP)

Leadless Array Package (LAP)

14

AT18F010/002/040/080 [Preliminary]

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AT18F010/002/040/080 [Preliminary]

15. Revision History

Revision Level – Release Date History

A – January 2008 Initial release.

15

3672A–CNFG–1/08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

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77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

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Le Krebs

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

configurator@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

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3672A–CNFG–1/08