34825_10--Datasheet/数据表在线中文翻译

Document Number: MC34825

Rev 2.0, 3/2010

Freescale Semiconductor

Advance Information

Micro-USB Interface IC

Supporting Universal Charging

Solution and Wired Accessories

34825

The 34825 is designed to support the Universal Charging Solution

(UCS) recommended by the OMTP (Open Mobile Terminal Platform),

as well as to use the same 5-pin micro or mini-USB connector for other

wired accessories. The 34825 supports various types of external power

supplies, such as a dedicated ac/dc adapter or a USB port, to charge

the battery. It has functions built in to identify the type of the power

supply, and sets low or high charging current, based on the current

capability of the power supply. The 34825 monitors the power supply,

and offers an up to 28 V of over-voltage protection (OVP) to the cell

phone against failed power supplies. The 34825 also contains analog

switches to multiplex the 5 pins, to support UART and high speed USB

data communication, mono or stereo audio headset with or without a

microphone and a cord remote controller, manufacturing or research-

and-development (R/D) test cables, and other accessories.

INTERFACE IC

(PB-FREE)

98ASA00037D

20-PIN QFN

ORDERING INFORMATION

The 34825 monitors both the VBUS status and the resistance

between the ID pin and the ground to identify the accessory being

plugged into the mini or micro-USB connector. A high-accuracy 5-bit

ADC is offered to distinguish 32 levels of ID resistance that are

assigned to buttons in a cord remote controller or to identification (ID)

resistors of accessories. After identifying the attached accessory, the

34825 sends an interrupt signal to a host IC and the host IC can

configure the analog switches via an I²C serial bus for further actions.

When the accessory is detached from the cell phone, an interrupt signal

is also sent to inform the host.

Temperature

Package

Device

Range (T )

A

3mm X 3mm

MC34825EP/R2

-40°C to 85°C

UTQFN

Features

• Identifies various types of power supplies to set low or high

battery-charging-current levels

• Supports 32 ID resistance values with a high accuracy 5-

bit ADC

• Internal power switch to offer OVP against up to 28 V

failed power supply input

• Supports stereo/mono headset with or without microphone

and remote controller with pure passive components

• Supports USB or UART R/D test cables

• High speed (480 Mbps) USB 2.0 compliant

• Accessory attachment and detachment detection with an

interrupt signal to the host IC

• I²C interface

• 10 μA quiescent current in Standby mode

• Pb-free packaging designated by suffix code EP

Baseband

GPIO

34825

VDDIO

INT

I2C_SDA

I2C_SCL

RXD

VDD

Charger

LI+

I2C

UART

ISET

TXD

OUT

D+

D-

V

VBUS

BUS

USB XCVR

SPK_L

SPK_R

MIC

ID

DP

ID

AUDIO

D+

D-

DM

GND

USB Connector

Figure 1. 34825 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

VDD

Internal

Supplies

OSC

VDDIO

Reset

VBUS

Detect

VBUS

Gate

Drive &

OCP

I²C_SDA

I²C_SCL

I²C

Interface

Registers

and

OUT

ISET

State

Machine

Interrupt

INT

DP

RXD

TXD

UART

Switches

DM

ID

D+

D-

USB

Switches

ID ADC

SPK_R

SPK_L

MIC

ID

Detect

Audio

Switches

VBUS

GND

Figure 2. 34825 Simplified Internal Block Diagram

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Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

20

19

18

17

16

TRANSPARENT

TOP VIEW

SPK_R

SPK_L

MIC

1

2

3

4

15 OUT

I²C_SCL

I²C_SDA

14

13

21

GND

12 INT

D+

5

11 VDD

D-

6

7

8

9

10

Figure 3. 34825 Pin Connections

Table 1. 34825 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section on page 13.

Pin Number Pin Name

Pin Function

Formal Name

Definition

Right channel input for speaker signals

Left channel input for speaker signals

1

2

3

4

SPK_R

SPK_L

MIC

Input

Output

IO

Speaker right channel

Speaker left channel

Microphone output

Microphone output to the baseband of the cell phone system

D+ line of the USB transceiver

D+

D+ of the USB

transceiver

5

D-

D- line of the USB transceiver

IO

D- of the USB

transceiver

6

7

8

9

RXD

TXD

Receive line of the UART

Transmit line of the UART

No Connection

Output

Input

UART receiver

UART transmitter

No Connection

IO power supply

NC

No Connection

Input

VDDIO

IO supply voltage. The VDDIO voltage is used as the reference voltage

for the I²C bus signals. This pin also functions as a hardware reset to

the IC.

10

11

12

13

14

15

16

17

NC

VDD

INT

No Connection

Input

No Connection

Power supply

IC power supply input

Open-drain interrupt output

Output

IO

Interrupt output

I²C data

Data line of the I²C interface

I²C_SDA

Clock line of the I²C interface

Input

I²C clock

I²C_SCL

OUT

The output of the power MOSFET pass switch

Open-drain output to set the charger current

VBUS line of the Mini or micro-USB connector

Output

Input

Power output

ISET

Charge current setting

VBUS power supply

VBUS

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Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Table 1. 34825 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section on page 13.

Pin Number Pin Name

Pin Function

Formal Name

Definition

18

19

20

21

DM

D- line of the mini or micro-USB connector

IO

D- of the USB

connector

DP

D+ line of the mini or micro-USB connector

ID pin of the mini or micro-USB connector

Ground

IO

D+ of the USB

connector

ID

Input

ID of the USB

connector

GND

Ground

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Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

Exceeding these ratings may cause a malfunction or permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Input Voltage Range

VBUS Pin

V

V_BUS

V_OUT

-0.3 to 28

-0.3 to 8.0

OUT Pin

SPK_L, SPK_R, DP, and DM Pins

All Other Pins

-2.0 to V_DD+0.3

-0.3 to 5.5

ESD Voltage ⁽¹⁾

V

V_ESD

Human Body Model (HBM) for VBUS, DP, DM, ID Pins

Human Body Model (HBM) for all other pins

Machine Model (MM)

8000

2000

200

THERMAL RATINGS

Operating Temperature

Ambient

°C

T_A

T_J

-40 to +85

150

Junction

Storage Temperature

°C

T_STG

-65 to +150

Thermal Resistance ⁽²⁾

Junction-to-Case

°C/W

R_θJC

R_θJA

6.0

45

Junction-to-Ambient

(4)

Peak Package Reflow Temperature During Reflow ⁽³⁾

,

Note 4

°C

T_PPRT

Notes

1. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω), and the Machine Model

(MM) (C_ZAP= 200 pF, R_ZAP= 0 Ω).

2. Device mounted on the Freescale EVB test board per JEDEC DESD51-2.

3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

4. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and

enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx)], and review parametrics.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions V_DD= 3.6 V, V_BUS= 5.0 V, V_DDIO= 3.0 V, -40°C ≤ T_A≤ 85°C (see Figure 1), unless

otherwise noted. Typical values noted reflect the approximate parameter means at V_DD= 3.6 V and T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT

VDD Supply Voltage

V_DD

2.7

-

5.5

V

VDD Power-On-Reset Threshold

Rising edge

V_VDDPOR

-

2.5

2.65

-

V

Hysteresis

100

mV

VDD Quiescent Current

In Standby mode

I_VDD

μA

-

9.0

16

12

22

In Power Save mode

In Active mode (V

< V

> V

)

DD

BUS

550

850

650

1000

VBUS Supply Voltage

V_BUS

2.8

5.0

28

V

VBUS Detection Threshold Voltage

Rising edge

V_{BUS_DET}

-

2.65

150

2.80

-

V

Hysteresis

mV

VBUS Supply Quiescent Current

In VBUS Power mode

I_VBUS

-

1.2

0.5

mA

μA

In Active mode - Dedicated Charger

In Active mode - power MOSFET is off (V_BUS< V_DD

)

VBUS Over-voltage Protection Threshold

V_{BUS_OVP}

Rising edge

Hysteresis

6.8

-

7.0

7.2

-

V

150

mV

VBUS Over-current Protection Threshold

I_{BUS_OCP}

Triggering threshold (at onset of OTP shutoff)

1.2

1.8

2.2

A

Over-temperature Protection Threshold

Rising threshold

T_OTP

°C

115

-

130

95

145

-

Falling threshold

VDDIO Supply Voltage

V_DDIO

1.65

-

3.6

V

SWITCH

ISET Open-Drain Output MOSFET

On resistance (loaded by 3.0 mA current)

R_ISETB

-

100

0.5

Ω

Leakage current (when the MOSFET is off at 5.0 V bias voltage)

I_{ISET_OFF}

μA

OUT Pin Discharge MOSFET⁽¹⁾

On resistance (loaded by 3.0 mA current)

R_{OUT_DISC}

I_{OUT_OFF}

-

100

-

Ω

Leakage current (when the MOSFET is off at 5.0 V bias voltage)

0.5

μA

Power MOSFET

R_PSW

mΩ

On resistance (when V_BUS= 5.0 V, T_A< 50°C)

-

200

250

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions V_DD= 3.6 V, V_BUS= 5.0 V, V_DDIO= 3.0 V, -40°C ≤ T_A≤ 85°C (see Figure 1), unless

otherwise noted. Typical values noted reflect the approximate parameter means at V_DD= 3.6 V and T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

SPK_L and SPK_R Switches

Symbol

Min

Typ

Max

Unit

Ω

On resistance (20 Hz to 470 kHz)

Matching between channels

R_{SPK_ON}

R_{SPK_ONMCT}

R_{SPK_ONFLT}

-

1.6

3.0

0.05

0.01

0.15

0.05

On resistance flatness (from -1.2 to 1.2 V)

D+ and D- Switches

Ω

On resistance (0.1 Hz to 240 MHz)

Matching between channels

R_{USB_ON}

R_{USB_ONMCT}

R_{USB_ONFLT}

-

5.0

0.5

0.1

0.02

On resistance flatness (from 0.0 to 3.3 V)

RXD and TXD Switches

On resistance

Ω

R_{UART_ON}

-

60

On resistance flatness (from 0.0 to 3.3V)

R_{UART_ONFLT}

5.0

MIC Switch

On resistance (at below 2.5 V MIC bias voltage)

On resistance flatness (from 1.8 to 2.3 V)

R_{MIC_ON}

-

100

5.0

R_{MIC_ONFLT}

Pull-down Resistors between SPK_L or SPK_R Pins to GND

R_{PD_AUDIO}

-

100

-

kΩ

Signal Voltage Range

SPK_L, SPK_R,

V

-1.5

-0.3

-

1.5

3.6

D+, D-, RXD, TXD, MIC

PSRR - From VDD (100 mVrms) to DP/DM Pins⁽⁴⁾

V_{A_PSRR}

dB

%

20 Hz to 20 kHz with 32/16 Ω load.

-

-60

Total Harmonic Distortion⁽⁴⁾

THD

20 Hz to 20 kHz with 32/16 Ω load.

-

0.05

Crosstalk between Two Channels

less than 1.0MHz

V_{A_CT}

dB

-60

-80

-

Off-Channel Isolation

Less than 1.0 MHz

V_{A_ISO}

POWER SUPPLY TYPE IDENTIFICATION

Data Source Voltage

V_{DAT_SRC}

V

Loaded by 0~200 μA

0.5

0

0.6

-

0.7

Data Source Current

I_{DAT_SRC}

V_{DAT_REF}

200

μA

Data Detect Voltage

Low threshold

V

0.3

0.8

0.35

0.9

0.4

1.0

High threshold

Data Sink Current

I_{DAT_SINK}

μA

DM pin is biased between 0.15 to 3.6 V

65

-

100

8

135

-

DP, DM Pin Capacitance

C_DP/DM

R_DP/DM

pF

DP, DM Pin Impedance

All switches are off

MΩ

-

50

-

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Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions V_DD= 3.6 V, V_BUS= 5.0 V, V_DDIO= 3.0 V, -40°C ≤ T_A≤ 85°C (see Figure 1), unless

otherwise noted. Typical values noted reflect the approximate parameter means at V_DD= 3.6 V and T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

ID DETECTION

ID_Float Threshold

Detection threshold

V_FLOAT

V

-

2.3

-

Pull-up Current Source

I_ID

μA

When ADC result is 1xxxx

When ADC result is 0xxxx

1.9

2.0

32

2.1

30.4

33.6

ID Shorted to Ground Detection

Detection current

I_VCBL

1.0

-

1.2

50

1.4

-

mA

mV

Detection voltage threshold

V_{VCBL_L}

LOGIC INPUT AND OUTPUT

VDDIO Logic Input Level

Input LOW level

V_{DDIO_IL}

V_{DDIO_IH}

-

0.5

-

V

Input HIGH level

1.5

Push-pull Logic Output

V

Output HIGH level (loaded by 1.0 mA current)

Output LOW level (loaded by 4.0 mA current)

V_OH

V_OL

0.7V_DDIO

-

0.4

Open-Drain Logic Output (INT)

V_ODOL

V

Output LOW level (loaded by 4.0 mA current)

-

0.4

I²C INTERFACE⁽⁴⁾

Low Voltage on I²C_SDA, I²C_SCL Inputs

High Voltage on I²C_SDA, I²C_SCL Inputs

Low Voltage on I²C_SDA Output

V_{I2C_IL}

V_{I2C_IH}

V_{I2C_OL}

I_{I2C_OL}

I_{I2C_LEAK}

C_I2CIN

-0.2

-

0.3V_DDIO

V_DDIO

0.4

V

0.7V_DDIO

-

0

V

Current Load when I²C_SDA Outputs Low Voltage

Leakage Current on I²C_SDA, I²C_SCL Outputs

Input Capacitance of the I²C_SDA, I²C_SCL Pins

Notes

4.0

mA

μA

pF

-1.0

-

1.0

8.0

1. The OUT pin discharge MOSFET is shown in Figure 15. This MOSFET will be turned on when the power MOSFET is off.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions V_DD= 3.6 V, V_BUS= 5.0 V, V_DDIO= 3.0 V, -40°C ≤ T_A≤ 85°C (see Figure 1), unless

otherwise noted. Typical values noted reflect the approximate parameter means at V_DD= 3.6 V and T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER ON AND OFF DELAY

VDD Power-On-Reset Timing

VDD rising deglitch time

VDD falling deglitch time

ms

t_D2

7.0

1.7

8.5

2.5

10.2

3.5

t_{VDDDGT_F}

VBUS Detection Deglitch Time (for Both Rising and Falling Edges)⁽⁴⁾

t_{VBUS_DET}

3.5

4.5

5.7

ms

VBUS Over-voltage Protection

Protection delay⁽²⁾⁽⁴⁾

μs

t_OVPD

-

2.0

-

Falling-edge deglitch time⁽³⁾

t_{OVPDGT_F}

25

VBUS Over-temperature Protection

MOSFET turning off speed when OTP occurs⁽⁴⁾

Deglitch time

A/μs

μs

t_{OTP_TO}

-

0.5

-

t_{OTP_DGT}

15

OSCILLATOR

Oscillation Frequency

SWITCHING DELAY

f_OSC

85

100

112

kHz

ms

ID Detection Delay Time after VBUS Applied (Default Value is TD = 0100)

t_D

TD = 0000

TD = 0001

TD = 0010

TD = 0011

TD = 0100

......

-

100

200

300

400

500

......

1600

-

......

-

......

-

TD = 1111

ID DETECTION

ID Float Detection Deglitch Time

t_{ID_FLOAT}

t_VCBL

-

20

-

ms

ID Shorted to Ground Detection Time (The Detection Current Source On Time)

ADC

ADC Conversion Time

REMOTE CONTROL

Key Press Comparator Debounce Time

RESET TIMING

t_CONV

t_{RMTCON_DG}

t_RSTDVC

-

1.0

20

10

-

ms

Device Reset Time

μs

VDDIO Logic Input Timing

Rising edge deglitch time

Falling edge deglitch time

t_{VDDIODGT_R}

t_{VDDIODGT_F}

660

105

875

125

1130

150

VDDIO Reset Timing

μs

VDDIO reset pulse width

t_RSTVDDIO

150

-

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Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions V_DD= 3.6 V, V_BUS= 5.0 V, V_DDIO= 3.0 V, -40°C ≤ T_A≤ 85°C (see Figure 1), unless

otherwise noted. Typical values noted reflect the approximate parameter means at V_DD= 3.6 V and T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

I²C Reset Timing

ms

I²C reset pulse width

t_RSTI2C

13.5

-

I²C_SDA/I²C_SCL concurrent low time without causing a reset

t_NRSTI2C

8.8

I²C INTERFACE⁽⁴⁾

SCL Clock Frequency

f_SCL

t_BUF

t_HD:STA

t_LOW

-

1.3

-

400

kHz

μs

ns

Bus Free Time between a STOP and START Condition

Hold Time Repeated START Condition

Low Period of SCL Clock

-

0.6

-

1.3

-

High Period of SCL Clock

t_HIGH

t_SU:STA

t_HD:DAT

t_SU:DAT

t_R

0.6

-

Setup Time for a Repeated START condition

Data Hold Time

0.6

-

0

-

Data Setup Time

100

-

Rising Time of Both SDA and SCL Signals

Falling Time of Both SDA and SCL Signals

Setup Time for STOP Condition

Input Deglitch Time (for Both Rising and Falling Edges)

Notes

20+0.1C_B

0.6

-

ns

t_F

-

ns

t_SU:STO

t_DGT

μs

ns

55

300

2. The protection delay is defined as the interval between VBUS voltage rising above the OVP rising threshold, and the OUT pin voltage

dropping below the OVP rising threshold voltage for a VBUS ramp rate of >1.0 V/μs.

3. The OVP deglitch timer is only for the falling edge threshold.

4. These parameters are not tested. They are guaranteed by design.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

90

2.2

2.0

1.8

1.6

1.4

Temperature = 85°C

Temperature = 25°C

Temperature = -40°C

Temperature =85°C

80

70

60

50

40

Temperature =25°C

Temperature = -40°C

1.8

1.9

2.0

2.1

2.2

2.3

-1.5 -1.0 -0.5 0.0

0.5

1.0

1.5

Input Voltage ( V)

Figure 7. MIC Switch On Resistance vs Input Voltage

Figure 4. SPK Switch On Resistance vs Input Voltage

9.6

9.4

9.2

9.0

8.8

4.5

Temperature = 85°C

4.0

3.5

Temperature = 25°C

3.0

Temperature = -40°C

2.5

8.6

2.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VDD Voltage ( V)

Input Voltage ( V)

Figure 8. VDD Supply Current vs Supply Voltage in

Standby Mode

Figure 5. USB Switch On Resistance vs Input Voltage

45

11

10

9

Temperature = 85°C

40

35

Temperature = 25°C

30

8

25

Temperature = -40°C

7

20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

-40 -20

0

20

40

60

80

Input Voltage ( V)

Figure 6. UART Switch On Resistance vs Input Voltage

Temperature ( °C)

Figure 9. VDD Supply Current vs Temperature In

Standby Mode

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ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

900

880

860

840

820

800

780

760

9.0

7.5

6.0

4.5

3.0

1.5

0.0

-40 -20

0

20

40

60

80

0.0

1.5

3.0

VBUS Voltage ( V)

Figure 11. OUT Voltage vs VBUS Voltage

4.5

6.0

7.5

9.0

Temperature ( °C)

Figure 10. VBUS Supply Current vs Temperature In

VBUS Power Mode

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 34825 is designed to support cell phones that adopt

the micro or mini-USB connector as the sole wired interface

between the cell phone and external accessories. Using the

micro-USB connector for charging and USB data

communication is required by the OMTP standard for the

UCS. The 34825 further extends the micro-USB connector to

support other accessories to eliminate all other mechanical

connectors in a cell phone. The supported accessories

include various audio headsets, UART connection, R/D test

cables for firmware downloading, and other user defined

accessories, in addition to the chargers defined in the Battery

Charging Specification, Revision 1.0, from the USB

in the ID pin floating status. Detaching the accessory from the

micro or mini-USB connector causes the VBUS voltage or/

and the ID resistance to change. The identification flow will be

initiated to confirm if an accessory is still connected. The host

can also initiate the identification flow by resetting an ACTIVE

bit in the register from 1 to 0.

Upon the completion of the identification flow, an interrupt

signal is sent to the host IC, so the host IC can take further

actions. The 34825 contains switches that the host IC can

control via an I²C interface. Based on the accessory, the host

IC can configure the switch connections in the 34825, so that

the signal paths for the USB communication, or the UART

communication, or audio accessories can be established

between the micro or mini-USB connector pins and the

system ICs. If the accessory is a power supply, the supplied

voltage is switched to the Li-ion battery charging function in

the cell phone via an internal power MOSFET.

Implementer’s Forum and the CEA-936-A USB Carkit

Specification, from the Consumer Electronics Association

(CEA). The supported chargers are listed in Table 7.

The 34825 offers two mechanisms to assist the

identification of the accessory. The ID detection mechanism

allows the cell phone to measure the ID resistor value

between the ID pin and the ground with a 5-bit ADC. The

VBUS detection mechanism allows the cell phone to find out

the connection status between the D+ and D- pins. Together,

the exact accessory can be determined. A detection flow is

initiated by a change in the VBUS pin voltage or by a change

The host IC controls the 34825 via the I²C serial bus. The

register map in the 34825 contains status information of the

device and the control bits that the host IC can access to

control the 34825.

FUNCTIONAL PIN DESCRIPTION

SPEAKER RIGHT CHANNEL (SPK_R)

IO POWER SUPPLY (VDDIO)

Right channel of the baseband speaker output.

Power supply input for the logic IO interface. Generally the

IO power supply voltage should be the same as the IO

voltage used in the cell phone system. VDDIO is also one of

the hardware reset input sources. A falling edge at this pin will

reset the 34825. See Reset for more information.

SPEAKER LEFT CHANNEL (SPK_L)

Left channel of the baseband speaker output.

MICROPHONE OUTPUT (MIC)

POWER SUPPLY (VDD)

Microphone output to the baseband.

Power supply input. Bypass to ground with a 1.0 μF

capacitor.

D+ OF THE USB TRANSCEIVER (D+)

D+ line of the USB transceiver.

INTERRUPT OUTPUT (INT)

Active low open-drain output. The INT pin sends an

interrupt signal to the host IC when an interrupt event

happens. The INT output returns to high voltage once all

interrupt bits are read.

D- OF THE USB TRANSCEIVER (D-)

D- line of the USB transceiver.

UART RECEIVER (RXD)

DATA LINE OF THE I²C INTERFACE (I²C_SDA)

Receiver line of the UART.

Data line of the I²C interface.

UART TRANSMITTER (TXD)

I²C CLOCK (I²C_SCL)

Transmitter line of the UART.

Clock line of the I²C interface. The I²C_SCL input together

with the I²C_SDA input forms one of the hardware reset input

sources.

NO CONNECT (NC)

These pins are not used in application. Freescale

recommends that these pins be floated

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

POWER OUTPUT (OUT)

D- OF THE USB CONNECTOR (DM)

Output of the power MOSFET in the 34825. This pin is

connected to a charger input. Bypass to ground with a 1.0 μF

capacitor.

D- line of the mini or micro-USB connector.

D+ OF THE USB CONNECTOR (DP)

D+ line of the mini or micro-USB connector.

CHARGE CURRENT SETTING (ISET)

Open-drain output to set the charge current according to

the power supply current capability.

ID OF THE USB CONNECTOR (ID)

ID pin of the mini or micro-USB connector.

VBUS POWER SUPPLY (VBUS)

GROUND (GND)

USB VBUS input. Bypass this pin to ground with a less

than 10 nF capacitor. When the accessory is an audio kit, this

pin is the microphone input to the 34825.

Ground.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Internal

Power

Supplies

Logic &

State

Machine

I²C

Interface

VBUS

Detection

Switch

Array

ID

Logic

Output

ID ADC

Detection

Figure 12. 34825 Functional Internal Block Diagram

SWITCH ARRAY

INTERNAL POWER SUPPLIES

This block contains the bias power supplies to the internal

circuits. The inputs to this block include VBUS, VDD and

VDDIO.

The switch array consists of analog switches for UART,

USB, audio signal switching and one high-voltage power

MOSFET for power switching.

LOGIC AND STATE MACHINE

VBUS DETECTION

This block includes the state machine for accessory

detection and identification, the register map, and other logic

circuits.

This block detects whether the power supply at VBUS pin

is present or removed.

ID DETECTION

I²C INTERFACE

The I²C interface block has the circuit for the I²C

communication that a master device can use to access the

registers in the 34825. The 34825 is a slave device.

This block contains a circuit to detect whether an ID resistor

is connected to the ID pin or not.

ID ADC

LOGIC OUTPUT

An internal 5-bit ADC measures the resistance at the ID

pin. The result is stored in the ADC Result register and sent

to the Logic and State Machine block to determine what

accessory is attached.

The logic output includes two open-drain logic output

signals, INT and ISET.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The 34825 has five operational modes: Power Down

mode, VBUS Power mode, Standby mode, Active mode, and

Power Save mode. The mode transition diagram is given in

Figure 13.

VBUS power down

VBUS power up

VBUS

Power

Down

V_DD> V_VDDPOR

V_DD< V_VDDPOR

I²C resets ACTIVE bit or

detachment of accessory

Standby

Active

ID det or VBUS det

I²C or detection

of no activity

I²C or detection

of the activity

Detachment

of accessory

Power

Save

Figure 13. Mode Transition Diagram

ACTIVE MODE

POWER DOWN MODE

The Power Down mode is when neither the VDD pin nor

the VBUS pin is powered. In this mode, the IC does not

respond to any accessory attachment except for a power

supply. When an external power supply is plugged into the

mini or micro-USB connector, the 34825 enters the VBUS

Power mode.

The Active mode starts when an accessory is plugged into

the mini or micro-USB connector while the VDD pin is

powered. The 34825 identifies the accessory and interrupts

the host IC for further actions. Different functions will be

enabled according to the identification result, so the

quiescent current in Active mode is dependent on the type of

accessories.

VBUS POWER MODE

The operational mode can be changed from Active to

Standby either by an accessory detachment or by resetting

the ACTIVE bit to 0 through an I²C programming operation.

The 34825 enters the VBUS Power mode when the VBUS

pin is powered but the VDD pin is not. In the VBUS Power

mode, the internal power MOSFET is turned on to power the

charging function in the cell phone. The ISET pin outputs

high-impedance in this mode.

POWER SAVE MODE

The Power Save mode can be enabled only for

accessories with a remote controller (refer to Table 21). The

34825 enters into the Power Save mode to minimize the

operating current while such an accessory is attached, but

not in operation. For example, if the cell phone is not in an

audio playback mode when a headset is attached, the host IC

can force the 34825 to the Power Save mode via the I²C

programming. The 34825 can also automatically enter into

the Power Save mode when no activity is detected on the

SPK_R or SPK_L pins in 10 seconds. The VDD current in the

Power Save mode is slightly higher than the current in the

Standby mode.

STANDBY MODE

The Standby mode is when the VDD voltage is higher than

the POR (Power-On-Reset) threshold and no accessory is

attached. In this mode, only the ID detection circuit, the I²C

interface, and the internal registers are powered in order to

minimize the quiescent current from the VDD pin. The ID

detection circuit samples the status of the ID line every

50 ms.

If detecting an attachment of an accessory, the 34825

moves to the Active mode for further accessory identification.

The 34825 can exit the Power Save mode by an I²C

programming or will exit the mode automatically when

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

POWER-UP

detecting audio signal activities or an accessory detachment.

If the transition is caused by an accessory detachment, the

34825 moves from the Power Save mode to the Standby

mode directly. Otherwise, it moves to the Active mode, and

the configuration of the IC resumes to the same configuration

before entering the Power Save mode.

accessory identification flow shown in Figure 14 will be re-

started.

The PSAVE bit is also a R/W bit. When the 34825 is

configured to the Auto Power-save mode (AutoPSAVE bit is

set to 1), the PSAVE bit indicates whether the 34825 is in the

Power Save mode or not. When the 34825 is configured to

the Manual Power-save mode (AutoPSAVE bit set to 0), the

host IC can writes ‘1’ to the PSAVE bit to force the 34825 into

the Power Save mode when an Audio R/C accessory is

attached. For all other accessories attachment, the 34825

does not enter the Power Save mode even the PSAVE bit is

set to 1.

DEVICE MODE REGISTER

The PSAVE bit, ACTIVE bit and RST bit in the Device

Mode register (refer to Table 9) hold the information of the

device operational mode. The RST bit, which is of R/C (read

and clear) type, indicates whether a reset has occurred. The

RST bit is set when a reset occurs (refer to Reset for more

information). The RST bit is cleared when read by an I²C

access. The ACTIVE bit and the PSAVE bit together indicate

the device mode by the relationship shown in Table 5. When

the device is in the VBUS Power mode, the registers are not

powered up.

Table 5. The Device Modes vs. the Register Bits

PSAVE

ACTIVE

MODE

0

1

0

1

0

Standby

Active

The ACTIVE bit is a R/W (read and write) bit, it can be

written by an I²C operation. When the host IC writes ‘0’ to the

ACTIVE bit, the device will be forced to the Standby mode. If

an accessory is attached when the ACITVE is set to 0, the

Power Save

Undefined

POWER-UP

The 34825 has four possible power-up scenarios

depending on which of the VDD pin and the VBUS pin is

powered up first. The four scenarios correspond to the

following four mode transitions.

SCENARIO 2: VBUS = HIGH AND VDD IS

POWERED UP (VBUS POWER MODE TO STANDBY

MODE TRANSITION)

If the VBUS pin is already powered when the VDD pin is

powered up, the device moves from the VBUS Power mode

to the Standby mode and then quickly moves to the

identification flow of the Active mode to identify the

accessory, as shown in Figure 14.

1. From Power Down to VBUS Power: the VBUS pin is

powered up when V_DD< V_VDDPOR(VDD POR

threshold)

2. From VBUS Power to Standby: VBUS is already

powered when the VDD voltage rises above its POR

threshold

After the VDD pin is powered up, the 34825 starts up the

internal supplies. The POR resets all register bits. The power

MOSFET remains on during the reset process.

3. From Power Down to Standby: the VDD pin is

powered up when V_BUS< V_VBUSPOR(VBUS POR

SCENARIO 3: VBUS = 0 V AND VDD IS POWERED

UP (POWER DOWN MODE TO STANDBY MODE

TRANSITION)

threshold)

4. From Standby to Active: the VDD pin is already

powered when the VBUS voltage rises above its POR

threshold

If no accessory is plugged into the micro or mini-USB

connector when VDD is powered up, the 34825 moves from

the Power Down mode to the Standby mode. The internal

supplies are started up first, and then the whole chip is reset

and is ready to accept accessories. Then when an accessory

is attached, the 34825 enters the Active mode. The power

MOSFET is off in this case since VBUS = 0 V.

SCENARIO 1: VDD = 0 V AND VBUS IS POWERED

UP (POWER DOWN MODE TO VBUS POWER

MODE TRANSITION)

If the VDD pin is not powered but the VBUS is powered up

within a voltage range between the POR threshold and the

OVP (over-voltage protection) threshold, the internal power

MOSFET is softly turned on. The IC is in the VBUS Power

mode.

SCENARIO 4: VDD = HIGH AND VBUS IS

POWERED UP (STANDBY TO ACTIVE MODE

TRANSITION)

In this VBUS Power mode, the ISET outputs high-

impedance and all registers are in the reset state. The power

MOSFET remains on unless it is disabled by the over-voltage

protection or the over-temperature protection block.

This is a normal VBUS detection case as shown in

Figure 14. More description can be found in Power Supply

Type Identification.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DEVICE OPERATION

ACCESSORY IDENTIFICATION

Accessories are categorized into two groups. Powered

accessories are accessories that supply power to the VBUS

pin while non-powered accessories do not. When the

accessory is a powered one, the VBUS-detection mechanism

will check the connection between the D+ and the D- pins as

part of the power supply type identification (PSTI). A powered

accessory may or may not have an ID resistor. A non-

powered accessory must have an ID resistor for the

identification purpose.

resistor values are 619 kΩ and 1.0 MΩ respectively, as

given in Table 21. Such accessories are non-powered

accessories. The 34825 monitors the ID pin

continuously for key pressing when such an accessory

is connected. 13 ID resistors are assigned to the

remote control keys, as listed in Table 21.

3. Other accessories. The remaining ID resistor values

are reserved for users to assign to their own

accessories.

Accessories that have an ID resistor are grouped into

three types, as listed in Table 21.

The identification flow chart is shown in Figure 14. In the

Standby mode, the 34825 monitors both the ID pin and the

VBUS pin simultaneously. If an accessory is detected, the

identification state machine will find out in parallel the ID

resistor value and the type of the power supply (if a powered

accessory is attached). When the 34825 is in the Active mode

with the ACTIVE bit = 1, the host IC can force the ACTIVE bit

to 0 via the I²C bus to initiate the identification state machine.

1. Test Accessories. Such accessories include two USB

test cables that are powered accessories, and two

UART test cables that are non-powered accessories. A

test accessory has an ID resistor and four ID resistor

values are reserved for them (see Table 21 for the ID

resistor assignment). The USB or the UART switches

in the IC will be turned on automatically when a test

accessory is attached.

The details on the identification flow for the VBUS-

detection mechanism and the ID detection mechanism are

described as following.

2. Accessories with a remote controller. Two accessories

are offered to support remote control (RC) keys. The ID

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

ACCESSORY IDENTIFICATION

VBUS=0V

ACTIVE = 0

ID Float

VBUS

Applied?

Set

DETACH bit

No

Yes

ID Float?

Yes

No

Set

Clear

Set

VBUS_DET bit

ID_FLOAT bit

Yes

No

Set

ID Float?

ADC RESULT

Set

ID_GND bit

ID shorted

to GND?

ADC =

00000?

Yes

No

Yes

No

Delay

TD time

Key

VBUS_DET

=1?

Released?

No

Yes

No

DP->DM

SHORT?

ADC =

Key Value?

Key Released

within 1.5s?

Set

ATTACH bit

No

Yes

No

ID_FLOAT

=1?

ADC =

1000x?

ADC =

0111x?

Yes

No

Yes

Turn on

UART

switches

DM->DP

SHORT?

Turn on

USB switches

Yes

No

Set DP/DM

_SHORT bit

Set

USB_CHG bit

Set

ATTACH bit

Set

ACTIVE bit

Figure 14. Detailed Accessory Identification Flow Diagram

ID DETECTION

The ID detection relies on the resistance between the ID

pin and the ground (R_ID) inside the accessory for the

accessory detection and recognition. The nominal ID

resistance that the 34825 supports is listed in Table 6 as well

as in Table 21. The 34825 offers a 5-bit ADC for the

resistance recognition and the corresponding ADC results vs.

the R_IDare also listed in Table 6. The resistors are required

to have 1% or better accuracy for the ADC to recognize

successfully.

Table 6. A rising edge of the ID_FLOAT bit represents the

detachment of the accessory.

The ADC results are broken into two groups. The values

between ‘00001’ to ‘01101’ are assigned to 13 remote-control

keys for the two accessories that support remote controllers,

as listed in Table 21. The rest of the ADC results are

assigned to various accessories. If the ADC result is one of

the remote control key values in the identification flow, it is

possible that the remote control key is stuck when the

accessory is attached.

A comparator monitors the ID pin for attachment and

detachment detection. When no accessory is attached, the ID

pin is floating. An ID_FLOAT bit in the Status register stays in

the value of 1. When a resistor less than or equal to 1.0 MΩ

is connected between the ID line and the ground, the

ID_FLOAT bit changes to 0. When the resistor is removed,

ID_FLOAT bit returns to 1. A falling-edge of the ID_FLOAT bit

represents the attachment of the accessory and the ADC is

enabled to measure the ID resistance. The ADC Result

register has the identification result of the R_ID, as given in

A special Stuck Key Identification flow is designed to

resolve such an issue. As shown in the Figure 14, if the stuck

key is recognized but is released within 1.5s, the identification

flow will return to re-detect the ID line; Otherwise, the

ATTACH bit will be set and the ADC Result register has the

key result. After the key is released, the 34825 will detect the

ID resistance value again. If the accessory is still connected,

the ATTACH bit is set again and the ADC result has the ID

resistor value of the accessory.

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DEVICE OPERATION

ACCESSORY IDENTIFICATION

When the ADC result is 00000, the resistance between the

ID pin and the ground is less than 1.90 kΩ. The ID_GND bit

in the Status register indicates whether the ID pin is shorted

to ground or not. If the ID pin is shorted to ground with less

than 30 Ω of resistance, the ID_GND pin is set to “1”.

Table 6. ADC Output vs. Resistor Values (Unit: kΩ)

ADC Result

00000

R_ID(kΩ)

ADC Result

R_ID(kΩ)

ADC Result

R_ID(kΩ)

ADC Result

R_ID(kΩ)

(1)

01000

01001

01010

01011

01100

01101

01110

01111

10.03

12.03

14.46

17.26

20.5

10000

10001

10010

10011

10100

10101

10110

10111

40.2

49.9

64.9

80.6

102

121

150

200

11000

11001

11010

11011

11100

11101

11110

11111

255

301

365

442

523

619

00001

2.00

2.604

3.208

4.014

4.820

6.03

00010

00011

00100

00101

24.07

28.7

00110

1000

(2)

00111

8.03

34.0

Notes

1. If the ID resistance is below 1.90 kΩ (nominal value), the ADC result is set to 00000.

2. If the ID line is floating, the ADC result is set to 11111

POWER SUPPLY TYPE IDENTIFICATION

The 34825 supports various standard power supplies for

charging the battery. The power supplies supported include

those that are user defined, and the ones defined in the

Battery Charging Specification, Revision 1.0, from the USB

Implementer’s Forum and the CEA-936-A USB Carkit

Specification, from the Consumer Electronics Association.

The five types of power supplies specified in the afore

mentioned two specification documents are listed in Table 7.

between the DP and the DM pins. The state machine starts

when the VBUS pin voltage rises above the VBUS detection

threshold, which is indicated with an VBUS_DET bit in the

status register. The state machine will find out if the DP and

DM pins are shorted, indicated with the DP/DM_SHORT bit,

or the connection has the characteristics of a USB charger,

indicated with the USB_CHG bit. Together with the ID

detection result, the power supply type can be determined.

The conditions for reaching the conclusion of the five

supported power supplies are listed in Table 7.

The Power Supply Type Identification (PSTI) function is

offered to assist the identification of the power supply type.

The PSTI state machine checks the connection status

Table 7. Power Supply Type vs. Detection Result

Item #

VBUS_DET

DP/DM_SHORT

USB_CHG

ID_FLOAT

ADC Result

Accessory Type

1

2

3

4

5

1

0

1

0

1

0

1

0

11111

10111

11011

Standard USB Port

USB Charger

Dedicated Charger

Carkit Charger Type 1

Carkit Charger Type 2

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

OPERATION AFTER IDENTIFICATION

The operation after the identification is dependent on the

VDDIO voltage. The VDD voltage has to be higher than its

POR threshold for the 34825 to perform the identification

state machine. Once completed, the identification results are

stored in the Status and the ADC Result registers and the

ATTACH bit is set. If the VDDIO is not powered, the interrupt

signal from the INT pin cannot be sent because the INT pin is

normally pulled up to the VDDIO. The host cannot access the

34825 either via the I²C bus. Hence, no communication will

occur between the 34825 and the host IC when the VDDIO is

not powered. The INT signal will send an interrupt signal if the

VDDIO is powered and the ATTACH bit is not masked by the

ATTACH_m bit (refer to Interrupt on page 25 for more

details). If the ATTACH bit is masked while the VDDIO is

powered, the interrupt signal will not be sent but the host IC

can still access the register map via the I²C bus. Once the

host IC accesses the 34825 register map and determines the

accessory type, it can manage the analog switches and other

signals in the 34825 by programming the S/W Control 1 and

S/W Control 2 registers.

The switches are open by default except if the attached

accessory is one of the four test cables listed in Table 21.

More descriptions on the analog switches and the operation

of the 34825 are given in the following sections.

ANALOG SWITCHES

signals of +/-1.5 V, referencing to the GND pin voltage. The

SPK_L and the SPK_R pins are pulled down to ground via a

100 kΩ resistor respectively, as shown in Figure 15. A

microphone switch connects the MIC pin to the VBUS pin.

SIGNAL SWITCH ARRAY

The 34825 offers an array of analog switches for signal

switching, as shown in Figure 15. Two pairs of switches (USB

and UART) are for switching the UART and USB signals to

the micro or mini-USB connector. Stereo audio signals can

be switched from the SPK_L and the SPK_R inputs to the DP

and the DM pins that are wired to the USB connector. Both

the SPK_L and the SPK_R inputs are capable of passing

All switches are controlled by bits in the S/W Control 1 and

2 registers except when the accessory attached is a test

cable.

DP

RXD

SW1

TXD

DM

SW2

SW3

D+

SW6

SW7

D-

SW4

SPK_R

SPK_L

SW5

MIC

VBUS

Gate

Drive

SW8

ISET

SW9

OUT

SW10

Figure 15. Analog and Digital Switches

the power flow from the VBUS input to the OUT pin. The

power MOSFET serves two purposes. For the Audio

accessory with microphone, the power MOSFET isolates the

POWER MOSFET

The SW8 in Figure 15 is a power MOSFET that controls

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

OPERATION AFTER IDENTIFICATION

VBUS pin from both the input decoupling capacitor and the

input quiescent current of the charger IC connected to the

OUT pin, so that the microphone signal can be connected to

the VBUS pin without any interference from the OUT pin. The

power MOSFET is also used as the input Over-voltage

Protection (OVP) or Over-current Protection (OCP) switch for

other components in the cell phone, such as the charger IC,

to allow a low voltage rated charger IC to be used for cost

reduction.

The power MOSFET is guaranteed to be turned on in

VBUS power mode even when the VDD voltage is below

V_VDDPORthreshold, to ensure that the cell phone battery can

be charged when the battery is fully discharged.

PROTECTION

(Constant Current) mode, regulating the output current at the

OCP limit. If the OCP condition persists, the IC temperature

will rise, eventually reaching the Over-Temperature-

Protection (OTP) limit. The 34825 then turns off the power

MOSFET and sets the OTP_EN interrupt bit in the Interrupt

register to inform the host IC. The power MOSFET is turned

on again when the IC temperature falls below the OTP falling

temperature threshold, and the OVP_OTP_DIS bit is set. If

the above case happens repeatedly 7 times, the power

MOSFET will be permanently turned off until the accessory is

detached or the IC is reset.

OVER-VOLTAGE PROTECTION (OVP)

The VBUS line is capable of withstanding a 28 V voltage.

The 34825 protects the cell phone by turning off the internal

power MOSFET when the VBUS voltage is higher than the

OVP threshold. In this case, the 34825 turns off the power

MOSFET within 1.0 μs after the input voltage exceeds the

OVP threshold, and the OVP_EN bit in the Interrupt register

is set to interrupt the host IC. When the OVP event is cleared,

the OVP_OTP_DIS bit in the Interrupt register is set to inform

the host IC.

The power MOSFET is turned off with a limited speed

under the OTP case to prevent a high overshoot voltage at

the VBUS pin.

OVER-CURRENT PROTECTION (OCP) AND OVER-

TEMPERATURE PROTECTION (OTP)

If the current flowing through the power MOSFET exceeds

the specified OCP limit, the 34825 will operate in CC

OPERATION WITH ACCESSORIES

low impedance when the key is released and returns to

a high impedance, due to the clearance of the KP bit

when the interrupt register is read.

AUDIO ACCESSORY SUPPORTING REMOTE

CONTROLLER (R/C ACCESSORY)

Two ID resistors are designated for accessories with a

remote controller, as listed in Table 21. A typical accessory

with a remote controller is an audio headset that has a stereo

speaker, a micro phone, and a remote controller, as shown in

Figure 16. The five pins in the mini or micro-USB connector

are assigned in Figure 16. If some components are not

included in the accessory, the corresponding pins should be

left floating. For example, if the microphone is not included in

the stereo headset, VBUS pin should be left floating in the

headset.

3. Long key press: if the key pressing time is longer than

T_LKP, the long key press bit LKP in the Interrupt register

is set to inform the host IC. The host IC needs to

respond to the key press immediately. The ADC result

holds the key value. When the key is released, the long

key release bit LKR in the Interrupt register is set to

interrupt the host IC again. The ADC Result register

still has the key value.

When such a accessory is attached, the 34825 can either

be forced into the Power Save mode or automatically enter

into the Power Save mode. This is controlled by the

AutoPSAVE bit in the Control register.

The timing of the key pressing is shown in Figure 17. If a

key is pressed for a time less than 20 ms, the 34825 ignores

this key press. If the key is still pressed after 20 ms, 34825

starts a timer to count the time during which the key is

pressed. There are three kinds of key press conditions

according to the pressing time: error key press, short key

press, and long key press.

When AutoPSAVE = 1, if no activity is detected at the

SPK_L and SPK_R pins in 10 seconds, the 34825 enters the

Power Save mode automatically to minimize the quiescent

current. Upon detecting the activity in audio signal switches,

the 34825 returns to the Active mode. When AutoPSAVE = 0,

the host IC can control the mode of 34825 manually by

setting the PSAVE bit in the Device Mode register via I²C.

1. Error key press: if the key pressing time is less than

T_KP, The 34825 ignores this key press.

2. Short key press: if the key pressing time is between

T_KPand T_LKP, the KP bit is set to inform the host IC.

In the Power Save mode, the key pressing is monitored as

well.

The ADC result holds the key value. The INT outputs

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

OPERATION AFTER IDENTIFICATION

VBUS

AUDIO

ACCESSORY

D+

D-

MIC

Audio_R

Audio_L

R₂

ID

R₁

R_N-1

R₃

…...

SEND/END

HOLD

/

R_N

GND

Figure 16. Audio Accessory with Remote Control and Microphone

T_KP

T_LKP

20 ms

Key Press

20 ms

KP

INT

Interrupt Register read

LKP

LKR

INT

Interrupt Register read

ADC Time

Interrupt Register read

Figure 17. The Remote Control Key Pressing Timing

UART cable. The test accessory has four ID resistance

TEST ACCESSORY

values to distinguish the test cable type. The detection result

turns on or off the USB switches, UART switches, and the

power MOSFET automatically, as shown in the Table 8.

The Test Accessories listed in Table 21 are special USB

cables and UART cables for test and R/D purpose. It has an

ID resistance to differentiate it from a regular USB cable or

Table 8. Switch Status vs. Test Cables

Accessory Type

UART test cable type 1

UART test cable type 2

USB test cable type 1

USB test cable type 2

Other accessories

ADC Result

Auto-ON Switches

Power MOSFET

01110

01111

10000

10001

others

UART Switches

USB Switches

OFF

ON

No auto-on Switches No auto-on Switches

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

LOGIC CONTROL FEATURES

of either 200kΩ or 440kΩ to distinguish the current capability

of the charger. Refer to the CEA-936-A USB Carkit

Specification for more information.

USB HOST (PC OR HUB)

When the attached accessory is a USB host or hub, the ID

pin is floating. The power MOSFET is turned on to allow the

charger to charge the battery. The ISET outputs default high

impedance to limit the charging current to a lower level. The

host IC can turn on the D+ and D- switches and then pull the

D+ signal to high to start the USB attaching sequence.

When the attached accessory is a 5-wire carkit charger,

the 34825 turns on the power MOSFET to allow the Li-ion

battery charging function to start. The host can set the ISET

outputting high impedance or low impedance to choose the

charge current.

USB CHARGER OR DEDICATED CHARGER

RESERVED ACCESSORY

When the attached accessory is a USB Charger or a

Dedicated Charger, the 34825 turns on the power MOSFET

to allow the charger to start. The host IC can set the ISET

outputs low impedance to allow a higher charge current.

The users can assign the reserved ID resistor values listed

in Table 21 to their user specific accessories. When a user

specific accessory is attached, the identification flow will

identify the ID resistance and as well as the power supply

type in case of a powered accessory. The ADC Result

register and the Status register contain the information of the

R_IDvalue and the power supply type. The baseband can read

these registers to distinguish the type of the accessory for

further actions.

5-WIRE CARKIT CHARGER (TYPE 1 OR TYPE 2)

A 5-wire carkit charger is a charger specified in the CEA-

936-A USB Carkit Specification. The 5-wire carkit charger

outputs 5V to the VBUS pin, has the D+ and D- pins shorted

internally, and has an ID resistor. The ID resistor has a value

DETACHING DETECTION

When either the VBUS voltage drops below the VBUS

power detection threshold or the ID resistor is removed, a

detaching detection flow starts. Figure 18 shows the detailed

detection flow. When the DETACH bit is set, the INT outputs

low voltage to inform the host IC. At the end of the detaching

detection flow, the ACTIVE bit is cleared and the 34825

enters the Standby mode. A new identification flow will start

if either the VBUS voltage is above its POR threshold or the

ID resistor is connected.

RID

Connected

VBUS=5V

VBUS

Removed

No

ID Float

Yes

Clear

Set

VBUS_DET bit

ID_FLOAT bit

Clear

ATTACH bit

Set

DETACH bit

Clear

ACTIVE bit

Figure 18. The Detachment Detection Flow

LOGIC CONTROL FEATURES

RESET

On-Reset caused by the rising VDD, a hardware reset

HARDWARE RESET

caused by the VDDIO input and a hardware reset using the

The 34825 has three sources for hardware resetting the

IC. As the Figure 19 shows, the sources include the Power-

I²C bus lines. The Power-On-Reset is described earlier. The

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

LOGIC CONTROL FEATURES

reset caused by the VDDIO input or by the I²C bus lines

belongs to system resets.

The hardware reset condition using the I²C signals is

shown in Figure 20. When both the I²C_SCL and the

I²C_SDA have a negative pulse with time of t_RSTI2C, a

hardware reset is generated. The result of the reset is same

as a Power-On-Reset.

To effectively reset the 34825, the reset pulse from the

VDDIO needs be longer than the 150 μs minimum reset

pulse width given in the Dynamic Electrical Characteristics

table.

SOFTWARE RESET

In addition to the two hardware reset types, the system

reset has another reset source, the software reset by writing

‘1’ to the RESET bit in the Control register. The Reset bit will

be cleared to ‘0’ at once since it is of W/C type. The

consequence of the software reset is the same as the

hardware reset. All registers will be reset.

The operating waveforms of the hardware reset using the

VDDIO pin are shown in Figure 21. The VDDIO detection has

a deglitch-time t_{VDDIODGT_F}. A glitch on the VDDIO with

duration less than the deglitch time will be ignored. If the

pulse on the VDDIO lasts longer than the deglitch time, a

reset from the VDDIO is detected to generate a reset signal.

I²C_SDA

I²C-Bus

Reset

I²C_SCL

Detection

VDD

+

reset

Delay

Time

-

V_VDDPOR

VDDIO

Reset

VDDIO

Detection

Figure 19. Sources of Reset in 34825

8.8~13.5ms

Reset

I2C_SDA

I2C_SCL

Reset

Start

Stop

Condition

Figure 20. Hardware Reset Using the I²C Bus

t_{VDDIODGT_F}

Reset

VDDIO

Figure 21. Hardware Reset Using the VDDIO Input

INTERRUPT

There are eight interrupt sources in the 34825 causing an

interrupt at the INT pin to the host IC. They are accessory

attachment, accessory detachment, short-key press, long

key press, long-pressed key release, VBUS voltage OVP, the

IC temperature OTP, and either the OVP or the OTP

condition is removed. The 34825 detects each event and sets

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

I2C SERIAL BUS INTERFACE

the corresponding bit in the Interrupt register. As long as the

Interrupt register is set, the INT pin outputs low voltage. The

Interrupt register is not writable. When the Interrupt register is

read, the Interrupt register is cleared automatically. Once the

Interrupt register is cleared, the INT pin returns to high

voltage.

An interrupt mask register is provided to mask unwanted

interrupt source. When the bit of the Interrupt Mask register

is set to 1, the corresponding interrupt source is blocked. The

INT does not output low voltage even though this interrupt bit

is set in the Interrupt register.

LOGIC OUTPUT

There are two open-drain logic output pins, INT and ISET.

The INT pin is related to the interrupt sources as described in

the Interrupt section. The ISET pin is controlled by the

register bit with the same name in the Control register.

The ISET generally is used to control the charge current

level. A typical charger IC uses one external resistor to set

the charge current. By using ISET output, the charger IC can

use two external resistors in parallel to set two charge current

levels, as shown in Figure 27.

2

I C SERIAL BUS INTERFACE

The I²C bus is enabled in the Standby, the Power Save,

and the Active modes. The serial clock (SCL) and the serial

data (SDA) lines must be connected to a positive supply

using pull-up resistors. Internally the I²C bus voltage is

referenced to the VDDIO input. The 34825 is a slave device.

Maximum data rate is 400 kbps.

1

0

1

0

1

R/W

Figure 22. I²C Slave Address

The following three figures show three I²C-bus transaction

protocols. The Word Address is an 8-bit register address in

the 34825.

ADDRESSING AND PROTOCOL

The 7-bit address for the 34825 is 0100101, as shown in

Figure 22.

Figure 23. Master Transmits to Slave (Write Mode)

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Figure 24. Master Reads After Setting Word Address (Write Word Address and then Read Data)

Figure 25. Master Reads Slave Immediately after First Byte (Read Mode)

REGISTER MAP

Table 9. Register Map

Addr Register Type

Reset

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

83H

85H

87H

88H

93H

94H

A0H

A1H

A2H

A3H

Interrupt

R/C 00000000

OVP_OTP_DIS

OTP_EN

OTP_EN_m

Reserved

OVP_EN

OVP_EN_m

Reserved

LKR

LKP

KP

KP_m

DETACH

ATTACH

Interrupt Mask R/W 00000000 OVP_OTP_DIS_m

LKR_m

LKP_m

DETACH_m

ATTACH_m

ADC Result

Timing Set

R

00011111

Reserved

ADC Value

R/W 00000000

Key Press

Long Key Press

S/W Control 1 R/W 00000001

S/W Control 2 R/W 00000100

Reserved

FET_STATUS

Reserved

DP/DM Switching

Reserved

VBUS Switching

Reserved

USB_CHG

AutoPSAVE

Reserved

ISETB

DP/DM_SHORT

Reserved

ID_FLOAT

RESET

Status

Control

R

0x000xxx

ID_GND

VBUS_DET

ADC_STATUS

Reserved

R/W 011000x0

R/W 10010100

R/W 00000001

Reserved

Time Delay

Device Mode

TD

Reserved

PSAVE

ACTIVE

RST

Table 10. Interrupt Register

Bit

Mode

Symbol

Reset

Description

Notes

0

1: accessory attached

R/C

ATTACH

0

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Table 10. Interrupt Register

Bit

Mode

Symbol

Reset

Description

Notes

1

2

3

4

5

6

7

1: accessory detached

R/C

DETACH

KP

0

1: remote controller short key is pressed

1: remote controller long key is pressed

1: remote controller long key is released

1: VBUS voltage higher than the OVP threshold

1: The temperature of 34825 is above the OTP threshold

1: OVP or OTP event is removed

LKP

LKR

OVP_EN

OTP_EN

OVP_OTP_DIS

Table 11. Interrupt Mask Register

Bit

Mode

Symbol

Reset

Description

1: interrupt disabled

Notes

0

1

2

3

4

5

6

7

R/W

ATTACH_m

DETACH_m

KP_m

0

1: interrupt disabled

LKP_m

1: interrupt disabled

LKR_m

1: interrupt disabled

OVP_EN_m

OTP_EN_m

OVP_OTP_DIS_m

1: interrupt disabled

Table 12. ADC Result Register

Bit

4-0

7-5

Mode

Symbol

Reset

Description

Notes

ADC Result of the ID resistor

R

ADC Result

Reserved

11111

000

Table 13. Timing Set Register

Bit

3-0

Mode

Symbol

Reset

Description

Long key press duration

0000: 300 ms

0001: 400 ms

0010: 500 ms

......

R/W

Long Key Press

0000

7-4

Normal key press duration

0000: 100 ms

0001: 200 ms

0010: 300 ms

......

R/W

Key Press

0000

Table 14. Timing Table

Setting Value

Key Press

Long Key Press

0000

0001

0010

100 ms

200 ms

300 ms

400 ms

500 ms

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Table 14. Timing Table

Setting Value

Key Press

Long Key Press

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

400 ms

600 ms

700 ms

800 ms

900 ms

1000 ms

1100 ms

1200 ms

1300 ms

1400 ms

1500 ms

-

500 ms

600 ms

700 ms

800 ms

900 ms

1000 ms

-

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Table 15. S/W Control Register 1

Bit

1-0

Mode

Symbol

Reset

Description

VBUS line switching configuration

Notes

R/W

VBUS Switching

01

00: open all switches connected to the VBUS line.

01: internal power MOSFET on

10: VBUS connected to MIC

11: open all switches connected to the VBUS line.

4-2

DP/DM line switching configuration

R/W

DP/DM Switching

000

000: open all switches

001: DP connected to D+, DM connected to D-

010: DP connected to SPK_R, DM connected to SPK_L

011: DP connected to RxD, DM connected to TXD

Others: open all switches connected to the DP pin and DM pin

7-5

R

Reserved

000

Table 16. S/W Control Register 2

Bit

3-0

Mode

Symbol

Reset

Description

Notes

R/W

Reserved

ISETB

0100

0

4

ISET output

0: high-impedance

1: low-impedance

7-5

R/W

Reserved

000

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Table 17. Status Register

Bit

Mode

Symbol

Reset

Description

Notes

0

1

2

3

4

5

6

7

ADC conversion status

1: ADC conversion completed

0: ADC in progress

R

ADC_Status

x

VBUS voltage is higher than the POR

R

VBUS_DET

ID_FLOAT

x

0

x

0: no

1: yes

ID line is floating

0: no

1: yes

ID pin is shorted to ground

ID_GND

0: no

1: yes

DP/DM shorted

0: no

DP/DM_SHORT

USB_CHG

1: yes

A USB charger is connected

0: no

1: yes

The on/off status of the power MOSFET

FET_STATUS

Reserved

0: off

1: on

0

Table 18. Control Register

Bit

1-0

Mode

Symbol

Reset

Description

Notes

R/W

W/C

Reserved

RESET

x0

0

2

Soft reset. When written to 1, the IC is reset. Once the reset is complete,

the RST bit is set and the RESET bit is cleared automatically.

1: to soft reset the IC

4-3

5

R/W

Reserved

00

1

Automatic Power Save mode detection control

AutoPSAVE

0: disable automatic Power Save mode detection. Device can enter

Power Save mode via the I²C

1: enable automatic Power Save mode detection.

7-6

R/W

Reserved

01

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

REGISTER MAP

Table 19. Time Delay Register

Bit

3-0

Mode

Symbol

Reset

Description

Notes

Time delay to start the powered accessory identification flow after

detecting the VBUS voltage

R/W

TD

0100

0000: 100 ms

0001: 200 ms

0010: 300 ms

0011: 400 ms

0100: 500 ms

......

1111:1600 ms

7-4

R/W

Reserved

1001

Table 20. Device Mode Register

Bit

Mode

Symbol

Reset

Description

Notes

0

This bit indicates if a chip reset has occurred. This bit will be cleared once

being read.

R/C

RST

1

0: no.

1: Yes.

1

2

Indicate either the device is in Active mode

R/W

ACTIVE

PSAVE

0

0: Standby

1: Active

To indicate either the device is in Power Save mode

0: no

1: yes

7-3

Reserved

00000

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

TYPICAL APPLICATIONS

APPLICATION INFORMATION

TYPICAL APPLICATIONS

APPLICATION INFORMATION

Table 21. ID Resistance Assignment (Unit: kΩ)

ID RESISTANCE VALUE ASSIGNMENT

The ID resistors used with the 34825 are standard 1%

resistors. Table 21 lists the complete 32 ID resistor

assignment. The ones with the Assigned Functions filled are

the ones that are already used with special functions. The

ones reserved can be assigned to other functions.

Item#

29

ADC Result

ID Resistance

Assignment

11101

11110

11111

619

1000

-

R/C Accessory 1

R/C Accessory 2

ID float

30

31

Table 21. ID Resistance Assignment (Unit: kΩ)

The remote control architecture is illustrated in Figure 26.

The recommended resistors for the remote control resistor

network are given in Table 22.

Item#

0

ADC Result

ID Resistance

Assignment

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

<1.9

2.0

Reserved

Table 22. Remote Control Resistor Values (Unit: kΩ)

1

S0

Resistor

Standard Value

ID Resistance

2

2.604

3.208

4.014

4.820

6.03

8.03

10.03

12.03

14.46

17.26

20.5

24.07

28.7

34.0

40.2

49.9

64.9

80.6

102

S1

R1

2.0

0.604

0.806

1.21

2.0

2.604

3.208

4.014

4.82

3

S2

R2

4

S3

R3

5

S4

R4

6

S5

R5

7

S6

S7

R6

6.03

8

R7

8.03

9

S8

R8

2.0

10.03

12.03

14.46

17.26

20.5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

S9

R9

2.0

S10

R10

R11

R12

R13

R14

2.43

2.8

S11

S12

3.24

3.57

590/976

UART Test Cable 1

UART Test Cable 2

USB Test Cable 1

USB Test Cable 2

Reserved

24.07

614/1000

ID

R₁

R₂

R₁₃

R₃

…...

S0

HOLD

S1

S2

S12

R₁₄

GND

121

150

Figure 26. Remote Control Architecture

200

Carkit Charger

Type 1

DECOUPLING CAPACITOR

24

25

26

27

11000

11001

11010

11011

255

301

365

442

Reserved

Decoupling capacitors are required at all power supply

input and output pins. For the VDD pin, a X5R capacitor of

1.0 μF is recommended. For VBUS pin, because it also acts

as the microphone input, the decoupling capacitance at

VBUS pin must be carefully considered. Assuming the voice

band is 3.4 kHz and the pull-up resistance for the microphone

is 2kΩ, the decoupling capacitance at the VBUS pin should

Carkit Charger

Type 2

28

11100

523

Reserved

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

TYPICAL APPLICATIONS

be less than 22 nF. A 4.7 nF X5R capacitor is recommended

decoupling capacitor; a 0.01 μF capacitance is enough for

for the typical application. The OUT pin requires a 1.0 μF

the VDDIO pin.

TYPICAL APPLICATIONS

of the cell phone baseband or application processor are

direct drive signals, the audio signals can be connected to the

corresponding pins of 34825 directly. Otherwise these

signals need DC-blocking capacitors to remove the DC level.

INTERFACE CIRCUIT IN A CELL PHONE

When the 34825 is used in a cell phone. The typical circuit

is shown in the Figure 27. The I²C bus need two pull-up

resistors. Typically they are 4.7 kΩ. When the audio outputs

V_DDIO

2x4.7 k

Baseband

VDD

1.0 µF

MC34673

I²C_SDA

Li+

1.0 µF

I²C

I²C_SCL

INT

VDDIO

GPIO

12 k

9.1 k

RxD

ISET

UART

TxD

OUT

D+

VBUS

USB Xcvr

D-

4.7 nF

V_AIO

2 k

0.1 µF

ID

DP

DM

ID

D+

D-

MIC

*

Audio

SPK_L

*

GND

SHLD

SPK_R

* : For direct-drive audio output, these DC

blocking capacitors are not needed

Figure 27. Interface Circuit in a Cell Phone System

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

TYPICAL APPLICATIONS

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EP SUFFIX

20 LD. QFN

98ASA00037D

REVISION O

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

TYPICAL APPLICATIONS

PACKAGE DIMENSIONS

EP SUFFIX

20 LD. QFN

98ASA00037D

REVISION O

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

PACKAGE DIMENSIONS

EP SUFFIX

20 LD. QFN

98ASA00037D

REVISION O

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

• Initial Release

3/2010

2.0

34825

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

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MC34825

Rev 2.0

3/2010