35XS3400_11--Datasheet/数据表在线中文翻译

Document Number: MC35XS3400

Rev. 8.0, 1/2011

Freescale Semiconductor

Advance Information

Quad High Side Switch

(Quad 35 mOhm)

35XS3400

The 35XS3400 is one in a family of devices designed for low-voltage

automotive lighting applications. Its four low R_DS(ON)MOSFETs (quad

35 mOhm) can control four separate 28 W bulbs, and/or LEDs.

HIGH SIDE SWITCH

Programming, control and diagnostics are accomplished using a

16-bit SPI interface. Its output with selectable slew-rate improves

electromagnetic compatibility (EMC) behavior. Additionally, each

output has its own parallel input or SPI control for pulse-width

modulation (PWM) control if desired. The 35XS3400 allows the user to

program via the SPI the fault current trip levels and duration of

acceptable lamp inrush. The device has Fail-safe mode to provide fail-

safe functionality of the outputs in case of MCU damaged.

Features

• Four protected 35 mΩ high side switches (at 25°C)

• Operating voltage range of 6.0 V to 20 V with standby current <

5.0 μA, extended mode from 4.0 V to 28 V

PNA SUFFIX (PB-FREE)

98ARL10596D

24-PIN PQFN

• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting

with daisy chain capability

ORDERING INFORMATION

Temperature

• PWM module using external clock or calibratable internal

oscillator with programmable outputs delay management

• Smart over-current shutdown, severe short-circuit, over-

temperature protections with time limited autoretry, and Fail-safe

mode in case of MCU damage

• Output OFF or ON open-load detection compliant to bulbs or

LEDs and short to battery detection. Analog current feedback

with selectable ratio and board temperature feedback.

• Pb-free packaging designated by suffix code DPNA

Device

Package

Range (T )

A

MC35XS3400CPNA

MC35XS3400DPNA

-40°C to 125°C

24 PQFN

V

PWR

DD

PWR

DD

35XS3400

VDD

VPWR

HS0

WAKE

FS

LOAD

I/O

SCLK

CS

SCLK

CS

SO

RST

SI

IN0

IN1

IN2

IN3

CSNS

FSI

HS1

HS2

HS3

SI

LOAD

I/O

SO

I/O

MCU

I/O

A/D

GND

Figure 1. 35XS3400 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

DEVICE VARIATIONS

Table 1. Device Variations

Characteristic

Symbol

Min

Typ

Max

Unit

Wake Input Clamp Voltage, I

35XS3400C

< 2.5 mA

V

CL(WAKE)

18

20

25

27

32

35

35XS3400D

Fault Detection Blanking Time

35XS3400C

t_FAULT

μs

°C

-

5.0

20

10

35XS3400D

Output Shutdown Delay Time

35XS3400C

t_DETECT

-

7.0

30

20

35XS3400D

Peak Package Reflow Temperature During Reflow⁽¹⁾

,

T_PPRT

Note 2

(2)

1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits

may cause malfunction or permanent damage to the device.

2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

INTERNAL BLOCK DIAGRAM

VDD

VPWR

Voltage Clamp

Internal

Regulator

Over/Under-voltage

Protections

V_DDFailure

Detection

Charge

Pump

POR

I

UP

V_REG

CS

SCLK

Selectable Slew Rate

Gate Driver

I

DWN

Selectable Over-current

Detection

HS0

SO

SI

RST

WAKE

FS

Severe Short-circuit

Detection

Logic

Short to VPWR

Detection

IN0

Over-temperature

Detection

IN1

IN2

IN3

Open-load

Detections

HS0

R

I

DWN

HS1

HS2

HS3

PWM

Module

Calibratable

Oscillator

HS2

HS3

V_REG

Programmable

Watchdog

FSI

Selectable Output

Current Recopy

Temperature

Feedback

Over-temperature

Prewarning

Analog MUX

V_DD

GND

Figure 2. 35XS3400 Simplified Internal Block Diagram

CSNS

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Transparent Top View of Package

13 12 11 10

9

8

7

6

5

4

3

2

1

SO

16

17

24

FSI

GND

23

GND

14

GND

HS3

18

22

HS2

15

VPWR

19

20

21

HS1

NC

HS0

Figure 3. 35XS3400 Pin Connections

Table 2. 35XS3400 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.

Number

Function

Pin Name

Formal Name

Definition

This pin reports an analog value proportional to the designated HS[0:3] output

current or the temperature of the GND flag (pin 14). It is used externally to

generate a ground-referenced voltage for the microcontroller (MCU) . Current

recopy and temperature feedback is SPI programmable.

1

CSNS

Output

Input

Output Current

Monitoring

Each direct input controls the device mode. The IN[0:3] high side input pins

are used to directly control HS0:HS3 high side output pins.

2

3

5

6

IN0

IN1

IN2

IN3

Direct Inputs

The PWM frequency can be generated from IN0 pin to PWM module in case

the external clock is set.

This pin is an open drain configured output requiring an external pull-up

resistor to V_DDfor fault reporting.

7

FS

Output

Fault Status

(Active Low)

This input pin controls the device mode.

8

9

WAKE

RST

Input

Wake

Reset

This input pin is used to initialize the device configuration and fault registers,

as well as place the device in a low-current Sleep mode.

This input pin is connected to a chip select output of a master microcontroller

(MCU).

10

11

12

CS

SCLK

SI

Input

Chip Select

(Active Low)

This input pin is connected to the MCU providing the required bit shift clock for

SPI communication.

Serial Clock

This pin is a command data input pin connected to the SPI serial data output

of the MCU or to the SO pin of the previous device of a daisy-chain of devices.

Serial Input

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

PIN CONNECTIONS

Table 2. 35XS3400 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.

Number

Function

Pin Name

Formal Name

Definition

This pin is an external voltage input pin used to supply power interfaces to the

SPI bus.

13

14, 17, 23

15

VDD

Power

Ground

Power

Output

Digital Drain Voltage

These pins, internally shorted, are the ground for the logic and analog circuitry

of the device. These ground pins must be also shorted in the board.

GND

VPWR

SO

Ground

This pin connects to the positive power supply and is the source of operational

power for the device.

Positive Power Supply

Serial Output

This output pin is connected to the SPI serial data input pin of the MCU or to

the SI pin of the next device of a daisy-chain of devices.

16

Protected 35 mΩ high side power output pins to the load.

18

19

21

22

HS3

HS1

HS0

HS2

High Side Outputs

These pins may not be connected.

4, 20

24

NC

FSI

N/A

No Connect

This input enables the watchdog timeout feature.

Input

Fail-safe Input

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage Range

V

PWR

PWR(SS)

Load Dump at 25°C (400 ms)

Maximum Operating Voltage

Reverse Battery at 25°C (2.0 min.)

41

28

-18

V_DDSupply Voltage Range

Input/Output Voltage

V_DD

(6)

-0.3 to 5.5

V

-0.3 to V +0.3

DD

WAKE Input Clamp Current

CSNS Input Clamp Current

HS [0:3] Voltage

I

2.5

mA

V

CL(WAKE)

I

CL(CSNS)

V

HS[0:3]

Positive

Negative

41

-16

Output Current⁽³⁾

Output Clamp Energy using single-pulse method⁽⁴⁾

ESD Voltage⁽⁵⁾

I

6

A

mJ

V

HS[0:3]

E

35

CL[0:3]

Human Body Model (HBM) for HS[0:3], VPWR and GND

Human Body Model (HBM) for other pins

Charge Device Model (CDM)

V

±8000

±2000

ESD1

ESD2

V

±750

±500

ESD3

ESD4

Corner Pins (1, 13, 19, 21)

All Other Pins (2-12, 14-18, 20, 22-24)

THERMAL RATINGS

Operating Temperature

°C

Ambient

Junction

T_A

T_J

-40 to 125

-40 to 150

Storage Temperature

THERMAL RESISTANCE

Thermal Resistance⁽⁷⁾

T_STG

-55 to 150

°C

°C/W

R

Junction to Case

Junction to Ambient

θJC

<1.0

30

θJA

(9)

Peak Package Reflow Temperature During Reflow⁽⁸⁾

,

T_PPRT

Note 9

°C

Notes

3. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

4. Active clamp energy using single-pulse method (L = 2.0 mH, R = 0 Ω, V

= 14 V, T = 150°C initial).

J

L

PWR

5. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 Ω), the Machine Model (MM)

(C_ZAP= 200 pF, R_ZAP= 0 Ω), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0 pF).

6. Input / Output pins are: IN[0:3], RST, FSI, CSNS, SI, SCLK, CS, SO, FS

7. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of R_θJAcan be reached in a real application case (4 layers board).

8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS

Battery Supply Voltage Range

Fully Operational

V

PWR

6.0

4.0

–

20

28

Extended mode⁽¹⁰⁾

Battery Clamp Voltage⁽¹¹⁾

V

41

47

53

V

PWR(CLAMP)

V

Operating Supply Current

I

mA

PWR

PWR(ON)

Outputs commanded ON, HS[0:3] open, IN[0:3] > V

–

6.5

20

IH

V

Supply Current

PWR

I

mA

PWR(SBY)

Outputs commanded OFF, OFF Open-load Detection Disabled,

HS[0:3] shorted to the ground with V = 5.5 V

–

6.0

8.0

DD

WAKE > V or RST > V and IN[0:3] < V

IL

IH

Sleep State Supply Current

I

μA

PWR(SLEEP)

V_PWR= 12 V, RST = WAKE = IN[0:3] < V , HS[0:3] shorted to the

IL

ground

T_A= 25°C

T_A= 85°C

–

1.0

–

5.0

30

V

Supply Voltage

V

3.0

–

5.5

V

DD

DD(ON)

Supply Current at V = 5.5 V

I

mA

DD

DD(ON)

No SPI Communication

–

1.6

5.0

2.2

–

8.0 MHz SPI Communication⁽¹²⁾

V

Sleep State Current at V = 5.5 V

I

–

5.0

36

μA

V

DD

DD(SLEEP)

Over-voltage Shutdown Threshold

Over-voltage Shutdown Hysteresis

Under-voltage Shutdown Threshold⁽¹³⁾

V

28

32

0.8

3.9

–

PWR(OV)

V

0.2

3.3

0.5

2.2

3.4

1.5

4.3

0.9

2.8

4.5

V

PWR(OVHYS)

V

PWR(UV)

V

and V_DDPower on Reset Threshold

V

PWR

SUPPLY(POR)

PWR(UV)

V

Supply Failure Threshold ( for V_PWR> V_PWR(UV)

)

V

2.5

4.1

DD

DD(FAIL)

Recovery Under-voltage Threshold

V

PWR(UV)_UP

OUTPUTS HS0 TO HS3

Output Drain-to-Source ON Resistance (I = 2.0 A, T = 25°C)

R

mΩ

HS

A

DS(ON)_25

V

= 4.0 V

= 6.0 V

= 10 V

= 13 V

–

100

55

PWR

35

Notes

10. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 V to 6.0 V voltage range, the device is only

protected with the thermal shutdown detection.

11. Measured with the outputs open.

12. Typical value guaranteed per design.

13. Output will automatically recover with time limited autoretry to instructed state when V_PWRvoltage is restored to normal as long as the

V_PWRdegradation level did not go below the under-voltage power-ON reset threshold. This applies to all internal device logic that is

supplied by V_PWRand assumes that the external V_DDsupply is within specification.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

OUTPUTS HS0 TO HS3 (Continued)

Symbol

Min

Typ

Max

Unit

Output Drain-to-Source ON Resistance (I = 2.0 A, T = 150°C)

R

mΩ

HS

A

DS(ON)_150

V

= 4.5 V

= 6.0 V

= 10 V

= 13 V

–

170

94

PWR

66

Output Source-to-Drain ON Resistance (I = -2.0 A, V

= -18 V )⁽¹⁴⁾

R

mΩ

HS

PWR

SD(ON)

T

= 25°C

–

52.5

70

A

= 150°C

A

Maximum Severe Short-circuit Impedance Detection⁽¹⁵⁾

R

70

160

200

mΩ

SHORT

Output Over-current Detection Levels (6.0 V < V

HS[0:3]

< 20 V)

A

39.5

25.2

22

47

30

54.5

34.8

30.4

26.1

21.7

17.4

13.0

8.7

OCHI1_0

OCHI2_0

OC1_0

26.2

22.5

18.7

15

18.9

15.7

12.6

9.4

OC2_0

OC3_0

OC4_0

11.2

7.5

OCLO4_0

OCLO3_0

OCLO2_0

OCLO1_0

6.3

5.0

6.0

7.0

3.2

4.0

4.8

C

V

Current Recopy Accuracy with one calibration point (6.0 V <

C

%

SR0

SR0_0_ACC(CAL)

< 20 V)⁽¹⁷⁾

HS[0:3]

Output Current

2.0 A

-5.0

–

5.0

Current Sense Ratio (6.0 V <

CSNS_ratio bit = 0

< 20 V, CSNS < 5.0 V)⁽¹⁶⁾

–

HS[0:3]

C

–

1/4300

–

SR0_0

SR1_0

CSNS_ratio bit = 1

1/25800

Current Sense Ratio (C

) Accuracy (6.0 V < V

< 20 V)

HS[0:3]

C

%

SR0

SR0_0_ACC

Output Current

6.75 A

-12

-13

-16

-20

–

12

13

16

20

2.5 A

1.5 A

0.75 A

Notes

14. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

15. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design.

.

PWR

16. Current sense ratio = I_CSNS/ I_HS[0:3]

.

17. Based on statistical analysis, it is not production tested.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

OUTPUTS HS0 TO HS3 (continued)

Current Recopy Temperature Drift (6.0 V < V

Symbol

Min

Typ

Max

Unit

C

< 20 V)⁽¹⁸⁾

HS[0:3]

Δ(C

)/Δ(T)

%/°C

SR0

SR0_0

Output Current

2.0 A

0.04

Current Sense Ratio (C

Output Current

6.25 A

) Accuracy (6.0 V < V

< 20 V)

HS[0:3]

C

%

SR1

SR1_0_ACC

-17

-12

–

+17

+12

39.5 A

Current Sense Clamp Voltage

CSNS Open; I = 2.0 A with C

V

CL(CSNS)

ratio

SR0

V_DD+0.25

–

V_DD+1.0

HS[0:3]

OFF Open-load Detection Source Current⁽¹⁹⁾

I

30

2.0

100

–

100

4.0

μA

V

OLD(OFF)

OFF Open-load Fault Detection Voltage Threshold

ON Open-load Fault Detection Current Threshold

V

3.0

300

OLD(THRES)

I

600

mA

OLD(ON)

ON Open-load Fault Detection Current Threshold with LED

I

OLD(ON_LED)

V

= V

- 0.75 V

PWR

2.5

5.0

10

HS[0:3]

Output Short to V

Detection Voltage Threshold

V

PWR

OSD(THRES)

V_CL

Output programmed OFF

V

-1.2

V

-0.8

V

-0.4

PWR

Output Negative Clamp Voltage

0.5 A < I

< 5.0 A, Output programmed OFF

-22

155

–

-16

HS[0:3]

Output Over-temperature Shutdown for 4.5 V < VPWR < 28 V

Notes

T

175

195

°C

SD

18. Based on statistical data: delta(C

production tested.

)/delta(T)={(measured I_CSNSat T₁- measured I_CSNSat T₂) / measured I_CSNSat room} / {T₁-T₂}. No

SR0

19. Output OFF Open-load Detection Current is the current required to flow through the load for the purpose of detecting the existence of

an open-load condition when the specific output is commanded OFF. Pull-up current is measured for V_HS=V_OLD(THRES)

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CONTROL INTERFACE

Input Logic High Voltage⁽²⁰⁾

Input Logic Low Voltage⁽²⁰⁾

Input Logic Pull-down Current (SCLK, SI)⁽²³⁾

Input Logic Pull-up Current (CS)⁽²⁴⁾

SO, FS Tri-state Capacitance⁽²¹⁾

V

2.0

-0.3

5.0

–

V_DD+0.3

0.8

V

IH

V

IL

I

–

20

μA

pF

kΩ

pF

V

DWN

I

–

20

UP

C

–

20

SO

Input Logic Pull-down Resistor (RST, WAKE and IN[0:3])

Input Capacitance⁽²¹⁾

R

125

–

250

4.0

500

12

DWN

C

IN

Wake Input Clamp Voltage⁽²²⁾, I

< 2.5 mA

V

CL(WAKE)

35XS3400C

35XS3400D

18

20

25

27

32

35

Wake Input Forward Voltage

V

F(WAKE)

I

= -2.5 mA

-2.0

–

0

-0.3

–

CL(WAKE)

SO High State Output Voltage

= 1.0 mA

V

SOH

I

V

-0.4

OH

DD

SO and FS Low-state Output Voltage

= -1.0 mA

V

SOL

I

–

0.4

2.0

OL

SO, CSNS and FS Tri-state Leakage Current

I

μA

kΩ

SO(LEAK)

RFS

CS = V_IHand 0 V < V_SO< V_DD, or FS = 5.5 V, or CSNS=0.0 V

-2.0

FSI External Pull-down Resistance⁽²⁵⁾

Watchdog Disabled

–

0

1.0

–

Watchdog Enabled

10

Infinite

Notes

20. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST

signals may be supplied by a derived voltage referenced to V

.

PWR

21. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production

tested.

22. The current must be limited by a series resistance when using voltages > 7.0 V.

23. Pull-down current is with V_SI> 1.0 V and V_SCLK> 1.0 V.

24. Pull-up current is with V_CS< 2.0 V. CS has an active internal pull-up to V

.

DD

25. In Fail-Safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to V

~ 3.0 V.

REG

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

POWER OUTPUT TIMING HS0 TO HS3

Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0]=00)⁽²⁶⁾

= 14 V

Symbol

Min

Typ

Max

Unit

SR

V/μs

μs

R_00

R_01

R_10

F_00

F_01

F_10

V

0.2

0.1

0.4

0.2

0.1

0.4

35

0.4

0.2

0.8

0.4

0.2

0.8

60

0.8

0.4

1.6

0.8

0.4

1.6

85

PWR

Output Rising Slow Slew Rate (low speed slew rate / SR[1:0]=01)⁽²⁶⁾

= 14 V

V

PWR

Output Falling Fast Slew Rate (high speed slew rate / SR[1:0]=10)⁽²⁶⁾

= 14 V

V

PWR

Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0]=00)⁽²⁶⁾

= 14 V

V

PWR

Output Falling Slow Slew Rate (low speed slew rate / SR[1:0]=01)⁽²⁶⁾

= 14 V

V

PWR

Output Rising Fast Slew Rate (high speed slew rate / SR[1:0]=10)⁽²⁶⁾

= 14 V

V

PWR

Output Turn-ON Delay Time⁽²⁷⁾

= 14 V for medium speed slew rate (SR[1:0]=00)

t

DLY(ON)

V

PWR

Output Turn-OFF Delay Time⁽²⁸⁾

= 14 V for medium speed slew rate (SR[1:0]=00)

t_DLY(OFF)

μs

V

35

60

85

PWR

Driver Output Matching Slew Rate (SR /SR )

ΔSR

Δt_RF

R

F

0.8

1.0

1.2

V

= 14 V @ 25°C and for medium speed slew rate (SR[1:0]=00)

PWR

Driver Output Matching Time (t_DLY(ON)- t_DLY(OFF)

)

μs

V

= 14 V, f = 240Hz, PWM duty cycle = 50%, @ 25°C for medium

-25

0

25

PWR

PWM

speed slew rate (SR[1:0]=00)

Notes

26. Rise and Fall Slew Rates measured across a 5.0 Ω resistive load at high side output = 30% to 70% (see Figure 4, page 16).

27. Turn-ON delay time measured from rising edge of any signal (IN[0:3] and CS) that would turn the output ON to V

= V

/ 2 with

PWR

HS[0:3]

R = 5.0 Ω resistive load.

L

28. Turn-OFF delay time measured from falling edge of any signal (IN[0:3] and CS) that would turn the output OFF to V

=V

/ 2

PWR

HS[0:3]

with R = 5.0 Ω resistive load.

L

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED)

Fault Detection Blanking Time⁽²⁹⁾

t_FAULT

μs

35XS3400C

35XS3400D

-

5.0

20

10

Output Shutdown Delay Time⁽³⁰⁾

t_DETECT

μs

35XS3400C

35XS3400D

-

7.0

30

20

-

–

CS to CSNS Valid Time⁽³¹⁾

Watchdog Time-out⁽³²⁾

t_CNSVAL

t_WDTO

70

100

400

-

μs

ms

217

-

310

ON Open-load Fault Cyclic Detection Time with LED

f_IN0/ 128

Notes

29. Time necessary to report the fault to FS pin.

30. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage =

50% of V_PWR

31. Time necessary for the CSNS to be with ±5% of the targeted value.

32. For FSI open, the watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding

input command.

35XS3400

Analog Integrated Circuit Device Data

12

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Output Over-current Time Step

OC[1:0]=00 (slow by default)

Symbol

Min

Typ

Max

Unit

ms

t_{OC1_00}

t_{OC2_00}

t_{OC3_00}

t_{OC4_00}

t_{OC5_00}

t_{OC6_00}

t_{OC7_00}

3.4

1.0

1.4

2.0

3.4

8.4

31.2

5.0

1.72

2.0

6.6

2.0

2.6

4.0

6.74

16

3.0

5.0

12.2

44.6

48

OC[1:0]=01 (fast)

t_{OC1_01}

t_{OC2_01}

t_{OC3_01}

t_{OC4_01}

t_{OC5_01}

t_{OC6_01}

t_{OC7_01}

1.72

0.56

0.72

1.02

1.56

4.28

15.4

2.48

0.8

3.22

1.04

1.36

1.92

2.92

7.96

29

1.04

1.58

2.24

6.12

22.2

OC[1:0]=10 (medium)

t_{OC1_10}

t_{OC2_10}

t_{OC3_10}

t_{OC4_10}

t_{OC5_10}

t_{OC6_10}

t_{OC7_10}

6.8

2.2

2.8

4.0

6.8

17

9.8

3.2

12.8

4.2

5.6

5.8

7.6

9.8

12.8

31.8

116

24.4

89.2

6.24

OC[1:0]=11 (very slow)

t_{OC1_11}

t_{OC2_11}

t_{OC3_11}

t_{OC4_11}

t_{OC5_11}

t_{OC6_11}

t_{OC7_11}

13.7

4.5

19.6

6.4

25.5

8.3

5.9

8.4

10.9

15.1

25.5

63.4

231.9

8.1

11.6

19.6

48.8

178.4

13.7

34.2

124.9

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Bulb Cooling Time Step

CB[1:0]=00 or 11 (medium)

ms

t_{BC1_00}

t_{BC2_00}

t_{BC3_00}

t_{BC4_00}

t_{BC5_00}

t_{BC6_00}

582

312

356

416

502

628

834

448

510

596

718

898

1084

584

664

776

934

1168

CB[1:0]=01 (fast)

t_{BC1_01}

t_{BC2_01}

t_{BC3_01}

t_{BC4_01}

t_{BC5_01}

t_{BC6_01}

296

156

176

202

256

452

418

224

254

290

360

648

544

292

332

378

468

884

CB[1:0]=10 (slow)

t_{BC1_10}

t_{BC2_10}

t_B

1166

624

1668

894

2170

1164

1310

1552

1866

2340

714

1022

1192

1434

1796

C3_10

t_{BC4_10}

t_{BC5_10}

834

1002

1256

t_B

C6_10

PWM MODULE TIMING

Input PWM Clock Range on IN0

f_IN0

7.68

1.0

100

–

2.0

200

–

30.72

4.0

400

1.0

+10

156

26

kHz

%

Input PWM Clock Low Frequency Detection Range on IN0⁽³³⁾

Input PWM Clock High Frequency Detection Range on IN0⁽³³⁾

Output PWM Frequency Range

f_IN0(LOW)

f_IN0(HIGH)

f_PWM

Output PWM Frequency Accuracy using Calibrated Oscillator

Default Output PWM Frequency using Internal Oscillator

CS Calibration Low Minimum Time Detection Range

CS Calibration Low Maximum Tine Detection Range

Output PWM Duty-cycle Range for f_PWM= 400 Hz⁽³⁴⁾

Output PWM Duty-cycle Range for f_PWM= 200 Hz⁽³⁴⁾

Output PWM Duty-cycle Range for f_PWM= 1.0 kHz for high speed slew rate⁽³⁴⁾

INPUT TIMING

A_FPWM(CAL)

f_PWM(0)

-10

84

–

120

20

200

–

Hz

μs

t_CSB(MIN)

t_CSB(MAX)

R_PWM_400

R_PWM_200

R_PWM_1k

14

140

10

260

98

μs

%

5.0

6.0

–

98

%

–

94

%

Direct Input Toggle Timeout

t_IN

175

105

250

150

325

195

ms

AUTORETRY TIMING

Autoretry Period

t_AUTO

Notes

33. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].

34. The PWM ratio is measured at V_HS= 50% of V_PWRand for the default SR value. It is possible to put the device fully-on (PWM duty-cycle

100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming

and the PWM on the output with R = 5.0 Ω resistive load.

L

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_PWR≤ 20 V, 3.0 V ≤ V_DD≤ 5.5 V, -40°C ≤ T_A≤ 125°C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TEMPERATURE ON THE GND FLAG

Thermal Prewarning Detection⁽³⁵⁾

T_OTWAR

110

1.15

-3.5

125

1.20

-3.7

140

1.25

-3.9

°C

V

Analog Temperature Feedback at T_A= 25°C with R_CSNS=2.5 kΩ

Analog Temperature Feedback Derating with R_CSNS=2.5 kΩ⁽³⁶⁾

SPI INTERFACE CHARACTERISTICS⁽³⁵⁾

T_FEED

DT_FEED

mV/°C

Maximum Frequency of SPI Operation

f_SPI

t_WRST

t_CS

–

10

–

8.0

–

MHz

μs

ns

(37)

Required Low State Duration for RST

Rising Edge of CS to Falling Edge of CS (Required Setup Time)⁽³⁸⁾

Rising Edge of RST to Falling Edge of CS (Required Setup Time)⁽³⁸⁾

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)⁽³⁸⁾

Required High State Duration of SCLK (Required Setup Time)⁽³⁸⁾

Required Low State Duration of SCLK (Required Setup Time)⁽³⁸⁾

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)⁽³⁸⁾

SI to Falling Edge of SCLK (Required Setup Time)⁽³⁹⁾

Falling Edge of SCLK to SI (Required Setup Time)⁽³⁹⁾

SO Rise Time

1.0

5.0

500

50

60

37

49

t_ENBL

–

t_LEAD

t_WSCLKh

t_WSCLKl

t_LAG

–

t_SI(SU)

t_SI(HOLD)

t_RSO

–

C = 80 pF

L

–

13

SO Fall Time

t_FSO

ns

C = 80 pF

L

–

13

SI, CS, SCLK, Incoming Signal Rise Time⁽³⁹⁾

SI, CS, SCLK, Incoming Signal Fall Time⁽³⁹⁾

Time from Rising Edge of SCLK to SO Low Logic Level⁽⁴⁰⁾

Time from Rising Edge of SCLK to SO High Logic Level⁽⁴¹⁾

t_RSI

t_FSI

t_SO(EN)

t_SO(DIS)

–

13

60

ns

Notes

35. Parameters guaranteed by design.

36. Value guaranteed per statistical analysis

37. RST low duration measured with outputs enabled and going to OFF or disabled condition.

38. Maximum setup time required for the 35XS3400 is the minimum guaranteed time needed from the microcontroller.

39. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

40. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.

41. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

IN[0:3]

high logic level

low logic level

Time

or

CS

high logic level

low logic level

V_HS[0:3]

V

PWR

R

PWM

50%V

PWR

t_DLY(OFF)

t_DLY(ON)

V_HS[0:3]

70% V

PWR

SR_F

SR_R

30% V

PWR

Time

Figure 4. Output Slew Rate and Time Delays

I

OCH1

I

OCH2

OC1

OC2

Load

Current

I

OC3

OC4

I

OCLO4

OCLO3

OCLO2

I

OCLO1

Time

t

OC7

OC3

OC1

t

OC5

t

OC6

t

OC4

OC2

Figure 5. Over-current Shutdown Protection

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

I

OCH1

OCH2

I

OC1

OC2

I

OC3

OC4

OCLO4

OCLO3

I

OCLO2

OCLO1

Previous OFF duration

(toff)

t

B

C5

B

C3

C1

t

B

C6

t

B

C4

t

B

C2

Figure 6. Bulb Cooling Management

VIH

V

IH

RSTB

RST

10% V_DD

0.2 VDD

VIL

V_IL

TwRSTB

TCSB

t_CS

t

ENBL

t

WRST

TENBL

VIH

90% V

0.7VDD

DD

V

IH

CCSSB

10.07%VDVD

DD

VIL

V

IL

t

RSI

TrSI

TtwSCLKh

WSCLKh

tTlead

LEAD

t

Tlag

LAG

VIH

90% V_DD

0.7VDD

V

IH

SCLK

10% V_DD

0.2VDD

VIL

V

IL

tTSIsu

SI(SU)

t

TwSCLKl

WSCLKl

TfSI

t

FSI

t

TSI(hold)

SI(HOLD)

VIH

V

IH

900.7%VVDD

DD

Don’t Care

Valid

SI

10.02%VDVD

DD

V

VIL

IH

Figure 7. Input Timing Switching Characteristics

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

t

FSI

RSI

TrSI

TfSI

VOH

V_OH

90% V

3.5V_DD

50%

SCLK

1.0V

10% V_DD

VOL

V_OL

t_SO(EN)

TdlyLH

0.210V%DDV_DD

VOH

V_OH

90% V

0.7 VD_DD_D

SO

VOL

V_OL

Low-to-High

Low to High

TrSO

t_RSO

T

t_V^V_A^A_L^LI_I^D_D

TfSO

t_FSO

SO

V_OH

VOH

90% V

0.7 VDD_DD

High to Low

High-to-Low

0.2VDD

10% V_DD

VOL

V_OL

TdlyHL

t_SO(DIS)

Figure 8. SCLK Waveform and Valid SO Data Delay Time

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 35XS3400 is one in a family of devices designed for

low-voltage automotive lighting applications. Its four low

R_DS(ON)MOSFETs (quad 35 mΩ) can control four separate

28 W bulbs.

Additionally, each output has its own parallel input or SPI

control for pulse-width modulation (PWM) control if desired.

The 35XS3400 allows the user to program via the SPI the

fault current trip levels and duration of acceptable lamp

inrush. The device has Fail-safe mode to provide fail-safe

functionality of the outputs in case of MCU damaged.

Programming, control and diagnostics are accomplished

using a 16-bit SPI interface. Its output with selectable slew-

rate improves electromagnetic compatibility (EMC) behavior.

FUNCTIONAL PIN DESCRIPTION

the device is capable of transferring information to, and

receiving information from, the MCU. The 35XS3400 latches

in data from the input shift registers to the addressed

registers on the rising edge of CS. The device transfers status

information from the power output to the Shift register on the

falling edge of CS. The SO output driver is enabled when CS

is logic [0]. CS should transition from a logic [1] to a logic [0]

state only when SCLK is a logic [0]. CS has an active internal

OUTPUT CURRENT MONITORING (CSNS)

The Current Sense pin provides a current proportional to

the designated HS0:HS3 output or a voltage proportional to

the temperature on the GND flag. That current is fed into a

ground-referenced resistor (4.7 kΩ typical) and its voltage is

monitored by an MCU's A/D. The output type is selected via

the SPI. This pin can be tri-stated through the SPI.

pull-up from V_DD, I_UP

.

DIRECT INPUTS (IN0, IN1, IN2, IN3)

SERIAL CLOCK (SCLK)

Each IN input wakes the device. The IN0:IN3 high side

input pins are also used to directly control HS0:HS3 high side

output pins. If the outputs are controlled by the PWM module,

the external PWM clock is applied to IN0 pin. These pins are

to be driven with CMOS levels, and they have a passive

The SCLK pin clocks the internal shift registers of the

35XS3400 device. The serial input (SI) pin accepts data into

the input shift register on the falling edge of the SCLK signal

while the serial output (SO) pin shifts data information out of

the SO line driver on the rising edge of the SCLK signal. It is

important the SCLK pin be in a logic low state whenever CS

makes any transition. For this reason, it is recommended the

SCLK pin be in a logic [0] whenever the device is not

accessed (CS logic [1] state). SCLK has an active internal

pull-down. When CS is logic [1], signals at the SCLK and SI

pins are ignored and SO is tri-stated (high-impedance) (see

Figure 9, page 22). SCLK input has an active internal pull-

internal pull-down, R_DWN

.

FAULT STATUS (FS)

This pin is an open drain configured output requiring an

external pull-up resistor to V_DDfor fault reporting. If a device

fault condition is detected, this pin is active LOW. Specific

device diagnostics and faults are reported via the SPI SO pin.

down, I_DWN

.

WAKE

The wake input wakes the device. An internal clamp

protects this pin from high damaging voltages with a series

resistor (10kΩ typ). This input has a passive internal pull-

SERIAL INPUT (SI)

This is a serial interface (SI) command data input pin.

Each SI bit is read on the falling edge of SCLK. A 16-bit

stream of serial data is required on the SI pin, starting with

D15 (MSB) to D0 (LSB). The internal registers of the

35XS3400 are configured and controlled using a 5-bit

addressing scheme described in Table 10, page 30. Register

addressing and configuration are described in Table 11,

down, R_DWN

.

RESET (RST)

The reset input wakes the device. This is used to initialize

the device configuration and fault registers, as well as place

the device in a low-current Sleep mode. The pin also starts

the watchdog timer when transitioning from logic [0] to

page 30. SI input has an active internal pull-down, I_DWN

.

DIGITAL DRAIN VOLTAGE (VDD)

logic [1]. This pin has a passive internal pull-down, R_DWN

.

This pin is an external voltage input pin used to supply

power to the SPI circuit. In the event V_DDis lost (V_DDFailure),

the device goes to Fail-safe mode.

CHIP SELECT (CS)

The CS pin enables communication with the master

microcontroller (MCU). When this pin is in a logic [0] state,

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

SCLK. SO reporting descriptions are provided in Table 23,

page 35.

GROUND (GND)

These pins are the ground for the device.

HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)

POSITIVE POWER SUPPLY (VPWR)

Protected 35 mΩ high side power outputs to the load.

This pin connects to the positive power supply and is the

source of operational power for the device. The VPWR

contact is the backside surface mount tab of the package.

FAIL-SAFE INPUT (FSI)

This pin incorporates an active internal pull-up current

source from internal supply (V_REG). This enables the

SERIAL OUTPUT (SO)

watchdog timeout feature.

The SO data pin is a tri-stateable output from the shift

register. The SO pin remains in a high-impedance state until

the CS pin is put into a logic [0] state. The SO data is capable

of reporting the status of the output, the device configuration,

the state of the key inputs, etc. The SO pin changes state on

the rising edge of SCLK and reads out on the falling edge of

When the FSI pin is opened, the watchdog circuit is

enabled. After a watchdog timeout occurs, the output states

depends on IN[0:3].

When the FSI pin is connected to GND, the watchdog

circuit is disabled. The output states depends on IN[0:3] in

case of V_DDfailure condition, in case V_DDfailure detection is

activated (VDD_FAIL_en bit sets to logic [1]).

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

SELF-

POWER SUPPLY

PROTECTED

HIGH SIDE

SWITCHES

MCU INTERFACE and

OUTPUT CONTROL

HS0-HS3

SPI INTERFACE

PARALLEL CONTROL

INPUTS

MCU

INTERFACE

PWM CONTROLLER

28 W bulbs and LED modules. 55 W/65 W lamps can be

driven for two outputs shorted together. Those N-channel

MOSFETs with 35 mΩ R_DS(ON)are self-protected and

present extended diagnostics in order to detect bulb outage

and short-circuit fault condition. The HS output is actively

clamped during turn off of inductive loads and inductive

battery line.

POWER SUPPLY

The 35XS3400 is designed to operate from 4.0 V to 28 V

on the VPWR pin. Characteristics are provided from 6.0 V to

20 V for the device. The VPWR pin supplies power to internal

regulator, analog, and logic circuit blocks. The VDD supply is

used for Serial Peripheral Interface (SPI) communication in

order to configure and diagnose the device. This IC

When driving DC motor or solenoid loads demanding

multiple switching, an external recirculation device must be

used to maintain the device in its Safe Operating Area.

architecture provides a low quiescent current Sleep mode.

Applying V_PWRand V_DDto the device will place the device in

the Normal mode. The device will transit to Fail-safe mode in

case of failures on the SPI or/and on VDD voltage.

MCU INTERFACE AND OUTPUT CONTROL

HIGH SIDE SWITCHES: HS0 – HS3

In Normal mode, each bulb is controlled directly from the

MCU through SPI. A pulse width modulation control module

allows improvement of lamp lifetime with bulb power

These pins are the high side outputs controlling

automotive lamps located for the rear of vehicle, such as

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

regulation (PWM frequency range from 100 to 400 Hz) and

addressing the dimming application (day running light). An

analog feedback output provides a current proportional to the

load current or the temperature of the board. The SPI is used

to configure and to read the diagnostic status (faults) of high

side outputs. The reported fault conditions are: open load,

short-circuit to battery, short-circuit to ground (over-current

and severe short-circuit), thermal shutdown, and under/over-

voltage. Thanks to accurate and configurable over-current

detection circuitry and wire-harness optimization, the vehicle

is lighter.

In Fail-safe mode, each lamp is controlled with dedicated

parallel input pins. The device is configured in default mode.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

FUNCTIONAL DEVICE OPERATION

The SI/SO pins of the 35XS3400 follow a first-in first-out

(D15 to D0) protocol, with both input and output words

transferring the most significant bit (MSB) first. All inputs are

compatible with 5.0 V or 3.3 V CMOS logic levels.

SPI PROTOCOL DESCRIPTION

The SPI interface has a full duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),

and Chip Select (CS).

CS

CSB

CS

SCLK

SI

D15

D14

D13

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SO

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

Notes 1. RST is a logic [1] state during the above operation.

2. D15 D0 relate to the most recent ordered entry of data into the device.

:

NOTES: 1. RSTB is in a logic H state during the above operation.

3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

device.

2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

Figure 9. Single 16-Bit Word SPI Communication

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The 35XS3400 has four operating modes: Sleep, Normal,

Fail-safe and Fault. Table 6 and Figure 11 summarize details

contained in succeeding paragraphs.

Table 6. 35XS3400 Operating Modes

Mode wake-up fail fault

Comments

The Figure 10 describes an internal signal called IN_ON[x]

depending on IN[x] input.

Sleep

0

x

Device is in Sleep mode. All

outputs are OFF.

Normal

1

0

Device is currently in Normal

mode. Watchdog is active if

enabled.

t_IN

IN[x]

Fail-safe

1

0

1

Device is currently in Fail-safe

mode due to watchdog timeout

or V_DDFailure conditions. The

output states depend on the

corresponding input in case

FSI is open.

IN_ON[x]

Figure 10. IN_ON[x] internal signal

The 35XS3400 transits to operating modes according to

the following signals:

Fault

X

Device is currently in Fault

mode. The faulted output(s) is

(are) OFF. The safe autoretry

circuitry is active to turn-on

again the output(s).

• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or

IN_ON[2] or IN_ON[3],

• fail = (V_DDFailure and VDD_FAIL_en) or ( Watchdog

time-out and FSI input not shorted to ground ),

• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV

( UV ) or ( OV and OV_dis ).

x = Don’t care.

(fail=0) and (wake-up=1) and (fault=0)

(wake-up=0)

Sleep

(wake-up=0)

(wake-up=1) and

(fail=1)

and (fault=0)

(wake-up=1)

and (fault=1)

(wake-up=0)

(fail=1) and

(wake-up=1)

and (fault=1)

(fail=0) and

(wake-up=1)

and (fault=1)

Fault

Normal

(fail=0) and

(wake-up=1)

and (fault=0)

(fail=1) and

(wake-up=1)

and (fault=0)

Fail-Safe

(fail=0) and (wake-up=1) and (fault=0)

(fail=1) and (wake-up=1) and (fault=0)

Figure 11. Operating Modes

This is the Default mode of the device after first applying

battery voltage (VPWR) prior to any I/O transitions. This is

also the state of the device when the WAKE and RST and

IN_ON[0:3] are logic [0]. In the Sleep mode, the output and

all unused internal circuitry, such as the internal regulator, are

off to minimize draw current. In addition, all SPI-configurable

features of the device are as if set to logic [0].

SLEEP MODE

The 35XS3400 is in Sleep mode when:

• V_PWRand V_DDare within the normal voltage range,

• wake-up = 0,

• fail = X,

• fault = X.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

NORMAL MODE

The 35XS3400 is in Normal mode when:

• V_PWRand V_DDare within the normal voltage range,

Table 8. Output PWM Switching Delay

Delay bits

Output delay

• wake-up = 1,

• fail = 0,

• fault = 0.

000

001

010

011

100

101

110

111

no delay

16 PWM clock periods

32 PWM clock periods

48 PWM clock periods

64 PWM clock periods

80 PWM clock periods

96 PWM clock periods

112 PWM clock periods

In this mode, the NM bit is set to lfault_contrologic [1] and

the outputs HS[0:3] are under control, as defined by hson

signal:

hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en

) or (On bit [x] and Duty_cycle[x] and PWM_en).

In this mode and also in Fail-safe, the fault condition reset

depends on fault_control signal, as defined below:

fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en )

or (On bit [x]).

The clock frequency from IN0 is permanently monitored in

order to report a clock failure in case of the frequency is out

a specified frequency range (from f_IN0(LOW)to f_IN0(HIGH)). In

Programmable PWM module

case of clock failure, no PWM feature is provided, the On bit

defines the outputs state and the CLOCK_fail bit reports [1].

The outputs HS[0:3] are controlled by the programmable

PWM module if PWM_en and On bits are set to logic [1].

Calibratable internal clock

The clock frequency from IN0 input pin or from internal

clock is the factor 2⁷(128) of the output PWM frequency

(CLOCK_sel bit). The outputs HS[0:3] can be controlled in

the range of 5% to 98% with a resolution of 7 bits of duty cycle

(Table 7). The state of other IN pin is ignored.

The internal clock can vary as much as +/-30 percent

corresponding to typical f_PWM(0)output switching period.

Using the existing SPI inputs and the precision timing

reference already available to the MCU, the 35XS3400

allows clock period setting within ±10 percent of accuracy.

Calibrating the internal clock is initiated by defined word to

CALR register. The calibration pulse is provided by the MCU.

The pulse is sent on the CS pin after the SPI word is

launched. At the moment, the CS pin transitions from logic [1]

to [0] until from logic [0] to [1] determine the period of internal

clock with a multiplicative factor of 128.

Table 7. Output PWM Resolution

On bit

Duty cycle

X

Output state

OFF

0

1

0000000

0000001

0000010

n

PWM (1/128 duty cycle)

PWM (2/128 duty cycle)

PWM (3/128 duty cycle)

PWM ((n+1)/128 duty cycle)

fully ON

CS

SI

1111111

The timing includes seven programmable PWM switching

delay (number of PWM clock rising edges) to improve overall

EMC behavior of the light module (Table 8).

SI command

ignored

CALR

Internal

clock duration

In case of negative CS pulse is outside a predefined time

range (from t_CSB(MIN)to t_CSB(MAX)), the calibration event will

be ignored and the internal clock will be unaltered or reset to

default value (f_PWM(0)) if this was not calibrated before.

The calibratable clock is used, instead of the clock from

IN0 input, when CLOCK_sel is set to [1].

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Transition Normal to Fail-safe Mode

FAIL-SAFE MODE

To leave the Normal mode, a fail-safe condition must

occurred (fail=1). The previous latched faults are reset by the

transition into Fail-safe mode (autoretry included).

The 35XS3400 is in Fail-safe mode when:

• V_PWRis within the normal voltage range,

• wake-up = 1,

• fail = 1,

• fault = 0.

FAULT MODE

The 35XS3400 is in Fault mode when:

• V_PWRand V_DDare within the normal voltage range,

Watchdog

• wake-up = 1,

• fail = X,

• fault=1.

If the FSI input is not grounded, the watchdog timeout

detection is active when either the WAKE or IN_ON[0:3] or

RST input pin transitions from logic [0] to logic [1]. The WAKE

input is capable of being pulled up to VPWR with a series of

limiting resistance limiting the internal clamp current

according to the specification.

This device indicates the faults below as they occur by

driving the FS pin to logic [0] for RST input is pulled up:

•Over-temperature fault,

•Over-current fault,

•Severe short-circuit fault,

•Output(s) shorted to VPWR fault in OFF state,

The watchdog timeout is a multiple of an internal oscillator.

As long as the WD bit (D15) of an incoming SPI message is

toggled within the minimum watchdog timeout period

(WDTO), the device will operate normally.

•Open load fault in OFF state,

•Over-voltage fault (enabled by default),

•Under-voltage fault.

Fail-safe Conditions

If an internal watchdog time-out occurs before the WD bit

for FSI open (Table 9) or in case of V_DDfailure condition

(V_DD< V_DD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the

device will revert to a Fail-safe mode until the WD bit is written

to logic [1] (see fail-safe to normal mode transition paragraph)

and V_DDis within the normal voltage range.

The FS pin will automatically return to logic [1] when the

fault condition is removed, except for over-current, severe

short-circuit, over-temperature and under-voltage which will

be reset by a new turn-on command (each fault_control

signal to be toggled).

Table 9. SPI Watchdog Activation

Fault information is retained in the SPI fault register and is

available (and reset) via the SO pin during the first valid SPI

communication.

Typical RFSI (Ω)

Watchdog

0 (shorted to ground)

(open)

Disabled

Enable

The Open load fault in ON state is only reported through

SPI register without effect on the corresponding output state

(HS[x]) and the FS pin.

During the Fail-safe mode, the outputs will depend on the

corresponding input. The SPI register content is reset to their

default value (except POR bit) and fault protections are fully

operational.

START-UP SEQUENCE

The 35XS3400 enters in Normal mode after start-up if

following sequence is provided:

The Fail-safe mode can be detected by monitoring the NM

bit is set to [0].

•VPWR and VDD power supplies must be above their

under-voltage thresholds,

NORMAL & FAIL-SAFE MODE TRANSITIONS

Transition Fail-Safe to Normal mode

•generate wake-up event (wake-up=1) from 0 to 1 on

RSTB. The device switches to Normal mode with SPI

register content is reset (as defined in Table 11 and

Table 23). All features of 35XS3400 will be available

after 50μs typical and all SPI registers are set to default

values (set to logic [0]). The UV fault is reported in the

SPI status registers.

To leave the Fail-safe mode, V_DDmust be in nominal

voltage and the microcontroller has to send a SPI command

with WDIN bit set to logic [1]; the other bits are not

considered. The previous latched faults are reset by the

transition into Normal mode (autoretry included).

And, in case of the PWM module is used (PWM_en bit is

set to logic [1]) with an external reference clock:

Moreover, the device can be brought out of the Fail-safe

mode due to watchdog timeout issue by forcing the FSI pin to

logic [0].

•apply PWM clock on IN0 input pin after maximum 200 μs

(min. 50 μs).

If the correct start-up sequence is not provided, the PWM

function is not guaranteed.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

If the load current level ever reaches the over-current

detection level, the corresponding output will latch the output

OFF and FS will be also latched to logic [0]. To delatch the

fault and be able to turn ON again the corresponding output,

the failure condition must disappear and the autoretry

circuitry must be active or the corresponding output must be

commanded OFF and then ON (toggling fault_control signal

of corresponding output) or V_SUPPLY(POR)condition if

PROTECTIONS

Over-temperature Fault

The 35XS3400 incorporates over-temperature detection

and shutdown circuitry for each output structure.

Two cases need to be considered when the output

temperature is higher than T_SD

:

•If the output command is ON: the corresponding output is

latched OFF. FS will be also latched to logic [0]. To

delatch the fault and be able to turn ON again the

outputs, the failure condition must disappear and the

autoretry circuitry must be active or the corresponding

output must be commanded OFF and then ON (toggling

fault_control signal of corresponding output) or

V_SUPPLY(POR)condition if V_DD= 0.

V_DD= 0.

The SPI fault report (OC[0:3] bits) is removed after a read

operation.

In Normal mode using the internal PWM module, the

35XS3400 also incorporates a cooling bulb filament

management, if the OC_mode is set to logic [1]. In this case,

the 1^ststep of multi-step over-current protection will depend

to the previous OFF duration, as illustrated in Figure 6. The

following figure illustrates the current level will be used in

function to the duration of previous OFF state (toff). The slope

of cooling bulb emulator is configurable with OCOFFCB[1:0]

bits.

•If the output command is OFF: FS will go to logic [0] until

the corresponding output temperature will be below

T_SD

.

For both cases, the fault register OT[0:3] bit into the status

register will be set to [1]. The fault bits will be cleared in the

status register after a SPI read command.

Over-current Fault

Depending on toff

depending to toff

The 35XS3400 incorporates output shutdown in order to

protect each output structure against resistive short-circuit

condition. This protection is composed by eight predefined

current levels (time dependent) to fit 28 W bulb profiles.

Over-current thresholds

Cooling

In the first turn-on, the lamp filament is cold and the current

will be huge. fault_control signal transition from logic [0] to [1]

or an autoretry define this event. In this case, the over-current

protection will be fitted to inrush current, as shown in

Figure 5. This over-current protection is programmable:

OC[1:0] bits select over-current slope speed and OCHI1

current step can be removed in case the OCHI bit is set to [1].

toff

fault_control

hson signal

hson

PWM

Severe Short-Circuit Fault

Over-current thresholds

The 35XS3400 provides output shutdown in order to

protect each output in case of severe short-circuit during of

the output switching.

If the short-circuit impedance is below R

, the device

SHORT

fault_control

will latch the output OFF, FS will go to logic [0] and the fault

register SC[0:3] bit will be set to [1]. To delatch the fault and

be able to turn ON again the outputs, the failure condition

must disappear and the corresponding output must be

commanded OFF, and then ON (toggling fault_control signal

of corresponding output) or V_SUPPLY(POR)condition, if

hson signal

hson

PWM

V_DD= 0.

In steady state, the wire harness will be protected by

OCLO2 current level by default. Three other DC over-current

levels are available: OCLO1 or OCLO3 or OCLO4 based on

the state of the OCLO[1,0] bits.

The SPI fault report (SC[0:3] bits) is removed after a read

operation.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

Over-voltage Fault (Enabled by default)

FS will go to logic [0], and the fault register UV bit will be set

to [1].

By default, the over-voltage protection is enabled. The

35XS3400 shuts down all outputs and FS will go to logic [0]

during an over-voltage fault condition on the VPWR pin

(V_PWR> V_PWR(OV)). The outputs remain in the OFF state until

Two cases need to be considered when the battery level

recovers (V_PWR> V_{PWR(UV)_UP}):

•If the output command is OFF, FS will go to logic [1], but

the UV bit will remain set to 1 until the next read

operation (warning report).

•If the output command is ON, FS will remain at logic [0].

To delatch the fault and be able to turn ON again the

outputs, the failure condition must disappear and the

autoretry circuitry must be active or the corresponding

output must be commanded OFF and then ON (toggling

fault_control signal of corresponding output) or

V_SUPPLY(POR)condition if V_DD= 0.

the over-voltage condition is removed (V_PWR< V_PWR(OV)

-

V_PWR(OVHYS)). When experiencing this fault, the OVF fault bit

is set to logic [1] and cleared after either a valid SPI read.

The over-voltage protection can be disabled through SPI

(OV_dis bit is disabled set to logic [1]). The fault register

reflects any over-voltage condition (V_PWR> V_PWR(OV)). This

over-voltage diagnosis, as a warning, is removed after a read

operation, if the fault condition disappears. The HS[0:3]

outputs are not commanded in R_DS(ON)above the OV

In extended mode, the output is protected by over-

temperature shutdown circuitry. All previous latched faults,

occurred when VPWR was within the normal voltage range,

are guaranteed if VDD is within the operational voltage range

or until V_SUPPLY(POR)if VDD = 0. Any new OT fault is

detected (VDD failure included) and reported through SPI

above VPWR_(UV). The output state is not changed as long as

the VPWR voltage does not drop any lower than 3.5 V typical.

threshold.

In Fail-safe mode, the over-voltage activation depends on

the RST logic state; enable for RST = 1 and disable for

RST = 0. The device is still protected with over-temperature

protection in case the over-voltage feature is disabled.

Under-voltage Fault

All latched faults (over-temperature, over-current, severe

short-circuit, over and under-voltage) are reset if:

• V_DD< V_DD(FAIL)with V_PWRin nominal voltage range,

•V_DDand V_PWRsupplies is below V_SUPPLY(POR)voltage

value.

The output(s) will latch off at some battery voltage below

VPWR_(UV). As long as the V_DDlevel stays within the normal

specified range, the internal logic states within the device will

remain (configuration and reporting).

In the case where battery voltage drops below the under-

voltage threshold (V_PWR< V_PWR(UV)), the outputs will turn off,

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

(fault_control=0)

(OpenloadON=1)

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(fault_control=1 and OV=0)

OFF

if hson=0

(SC=1)

ON

Latched

if hson=1

(fault_control=0 or OV=1)

(fault_control=0)

OFF

(count=16)

(Retry=1)

(SC=1)

(OpenloadON=1)

(after Retry Period and OV=0)

(OV=1)

Autoretry

OFF

Autoretry

ON

if hson=1

(Retry=1)

=> count=count+1

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(fault_control=0)

Figure 12. Auto-retry State Machine

status register after the internal gate voltage is pulled low

enough to turn OFF the output. The OS[0:3] and

OL_OFF[0:3] fault bits are set in the status register and FS

pin reports in real time the fault. If the output shorted to

VPWR fault is removed, the status register will be cleared

after reading the register.

AUTO-RETRY

The auto-retry circuitry is used to reactivate the output(s)

automatically in case of over-current or over-temperature or

under-voltage failure conditions to provide a high availability

of the load.

Auto-retry feature is available in Fault mode. It is activated

in case of internal retry signal is set to logic [1]:

The open output shorted to VPWR protection can be

disabled through SPI (OS_DIS[0:3] bit).

retry[x] = OC[x] or OT[x] or UV.

Open-Load Faults

The feature retries to switch-on the output(s) after one

auto-retry period (t_AUTO) with a limitation in term of number of

The 35XS3400 incorporates three dedicated open-load

detection circuitries on the output to detect in OFF and in ON

state.

occurrence (16 for each output). The counter of retry

occurrences is reset in case of Fail-safe to Normal or Normal

to Fail-safe mode transitions. At each auto-retry, the over-

current detection will be set to default values in order to

sustain the inrush current.

Open-load Detection In Off State

The OFF output open-load fault is detected when the

output voltage is higher than V_OLD(THRES)pulled up with

The Figure 12 describes the auto-retry state machine.

internal current source (I_OLD(OFF)) and reported as a fault

condition when the output is disabled (OFF). The OFF Output

open-load fault is latched into the status register or when the

internal gate voltage is pulled low enough to turn OFF the

output. The OL_OFF[0:3] fault bit is set in the status register.

If the open load fault is removed (FS output pin goes to high),

the status register will be cleared after reading the register.

DIAGNOSTIC

Output Shorted to VPWR Fault

The 35XS3400 incorporates output shorted to VPWR

detection circuitry in OFF state. Output shorted to VPWR fault

is detected if output voltage is higher than V

and

OSD(THRES)

The OFF output open-load protection can be disabled

through SPI (OLOFF_DIS[0:3] bit).

reported as a fault condition when the output is disabled

(OFF). The output shorted to VPWR fault is latched into the

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

Open-load Detection In On State

REVERSE BATTERY ON VPWR

The ON output open-load current thresholds can be

chosen by SPI to detect a standard bulbs or LEDs

(OLLED[0:3] bit set to logic [1]). In cases where the load

current drops below the defined current threshold, the OLON

bit will be set to a logic [1], the output will stay ON and FS will

not be disturbed.

The output survives the application of reverse voltage as

low as -18 V. Under these conditions, the ON resistance of

the output is 2 times higher than typical ohmic value in

forward mode. No additional passive components are

required except on V_DDcurrent path.

GROUND DISCONNECT PROTECTION

Open-load Detection In On State For Led

In the event the 35XS3400 ground is disconnected from

load ground, the device protects itself and safely turns OFF

the output regardless of the state of the output at the time of

disconnection (maximum VPWR=16 V). A 10 kΩ resistor

needs to be added between the MCU and each digital input

pin in order to ensure that the device turns off in case of

ground disconnect and to prevent this pin from exceeding

maximum ratings.

Open load for LEDs only (OLLED[0:3] set to logic [1]) is

detected periodically each t_OLLED(fully-on, D[6:0]=7F). To

detect OLLED in fully-on state, the output must be ON at least

t_OLLED.

To delatch the diagnosis, the condition should be removed

and SPI read operation is needed (OL_ON[0:3] bit). The ON

output open-load protection can be disabled through SPI

(OLON_DIS[0:3] bit).

LOSS OF SUPPLY LINES

Loss of VDD

Analog Current Recopy and Temperature Feedbacks

The CSNS pin is an analog output reporting a current

proportional to the designed output current or a voltage

proportional to the temperature of the GND flag (pin #14).

The routing is SPI programmable (TEMP_en, CSNS_en,

CSNS_s[1,0] and CSNS_ratio_s bits).

If the external V_DDsupply is disconnected (or not within

specification: V_DD<V_DD(FAIL))with VDD_FAIL_en bit is set to

logic [1]), all SPI register content is reset.

The outputs can still be driven by the direct inputs IN[0:3]

if V_PWRis within specified voltage range. The 35XS3400

In case the current recopy is active, the CSNS output

delivers current only during ON time of the output switch

without overshoot. The maximum current is 2.0 mA typical.

The typical value of external CSNS resistor connected to the

ground is 4.7 kΩ.

uses the battery input to power the output MOSFET-related

current sense circuitry and any other internal logic providing

Fail-safe device operation with no V_DDsupplied. In this state,

the over-temperature, over-current, severe short-circuit,

short to VPWR and OFF open-load circuitry are fully

operational with default values corresponding to all SPI bits

are set to logic [0]. No current is conducted from VPWR to

The current recopy is not active in Fail-safe mode.

Temperature Prewarning Detection

In Normal mode, the 35XS3400 provides a temperature

prewarning reported via SPI in case of the temperature of the

GND flag is higher than T_OTWAR. This diagnosis (OTW bit set

to [1]) is latched in the SPI DIAGR0 register. To delatch, a

read SPI command is needed.

V_DD

.

Loss of VPWR

If the external VPWR supply is disconnected (or not within

specification), the SPI configuration, reporting, and daisy

chain features are provided for RST is set to logic [1] under

V_DDin nominal conditions. This fault condition can be

ACTIVE CLAMP ON VPWR

diagnosed with a UV fault in the SPI STATS_s registers. The

SPI pull-up and pull-down current sources are not

operational. The previous device configuration is maintained.

No current is conducted from VDD to VPWR.

The device provides an active gate clamp circuit in order

to limit the maximum transient VPWR voltage at

VPWR_(CLAMP). In case of overload on an output the

corresponding output is turned off which leads to high-

voltage at VPWR with an inductive VPWR line. When VPWR

voltage exceeds VPWR_(CLAMP)threshold, the turn-off on the

corresponding output is deactivated and all HS[0:3] outputs

are switched ON automatically to demagnetize the inductive

Battery line.

Loss of VPWR and VDD

If the external VPWR and VDD supplies are disconnected

(or not within specification: (VDD and VPWR) <

V_SUPPLY(POR)), all SPI register contents are reset with default

For a long battery line between the battery and the device

(> 20 meters), the smart high side switch output may exceed

the energy capability in case of a short-circuit. It is

recommended to implement a voltage transient suppressor

to drain the battery line energy.

values corresponding to all SPI bits are set to logic [0] and all

latched faults are also reset.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

The device is protected in case of positive and negative

transients on the VPWR line (per ISO 7637-2).

EMC PERFORMANCES

All following tests are performed on Freescale evaluation

board in accordance with the typical application schematic.

The 35XS3400 successfully meets the Class 5 of the

CISPR25 emission standard and 200 V/m or BCI 200 mA

injection level for immunity tests.

LOGIC COMMANDS AND REGISTERS

remaining nine bits, D8:D0, are used to configure and control

the outputs and their protection features.

SERIAL INPUT COMMUNICATION

SPI communication is accomplished using 16-bit

messages. A message is transmitted by the MCU starting

with the MSB D15 and ending with the LSB, D0 (Table 10).

Each incoming command message on the SI pin can be

interpreted using the following bit assignments: the MSB,

D15, is the watchdog bit (WDIN). In some cases, output

selection is done with bits D14:D13. The next three bits,

D12:D10, are used to select the command register. The

Multiple messages can be transmitted in succession to

accommodate those applications where daisy-chaining is

desirable, or to confirm transmitted data, as long as the

messages are all multiples of 16 bits. Any attempt made to

latch in a message that is not 16 bits will be ignored.

The 35XS3400 has defined registers, which are used to

configure the device and to control the state of the outputs.

Table 11 summarizes the SI registers.

Table 10. SI Message Bit Assignment

Bit Sig

SI Msg Bit

Message Bit Description

MSB

D15

D14:D13

D12:D10

D9

Watchdog in: toggled to satisfy watchdog requirements.

Register address bits used in some cases for output selection (Table 12).

Register address bits.

Not used (set to logic [0]).

LSB

D8:D0

Used to configure the inputs, outputs, and the device protection features and SO status content.

Table 11. Serial Input Address and Configuration Bit Map

SI Data

SI

D1 D1 D1 D1 D1

Register

D15

D9 D8

D7

D6

D5

0

D4

D3

D2

D1

D0

4

3

2

1

0

STATR_s WDI

N

X

0

ON_s

0

PWM6_s

0

SOA4

SOA3

SOA2

SOA1

SOA0

PWMR_s WDI

N

A

0

1

X

0

1

0

1

X

1

0

1

0

1

X

PWM5_s

DIR_dis_s

PWM4_s

SR1_s

PWM3_s

SR0_s

PWM2_s

PWM1_s

PWM0_s

1

0

CONFR0_s WDI

N

A

DELAY2_s DELAY1_s DELAY0_s

CONFR1_s WDI

N

0

Retry_

unlimited_s

Retry_dis_s OS_dis_s OLON_dis_s OLOFF_dis_ OLLED_en CSNS_ratio

_s _s

s

OCR_s

GCR

WDI

N

BC1_s

BC0_s

OC1_s

OC0_s

OCHI_s

OCLO1_s OCLCO0_s OC_mode_

s

1

0

WDI

N

0

VDD_F PWM_en CLOCK_sel TEMP_en CSNS_en

AIL_en

CSNS1

CSNS0

X

1

0

OV_dis

CALR

WDI

N

0

1

0

1

0

1

0

Register

state after

RST=0 or

0

V

or

DD(FAIL)

V

SUPPLY(PO

R)

condition

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 11. Serial Input Address and Configuration Bit Map

x=Don’t care.

s=Output selection with the bits A₁A₀as defined in Table 12.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DEVICE REGISTER ADDRESSING

Table 13. Slew Rate Speed Selection

The following section describes the possible register

addresses (D[14:10]) and their impact on device operation.

SR1_s (D4)

SR0_s (D3)

Slew Rate Speed

0

1

0

1

0

1

medium (default)

low

ADDRESS XX000—STATUS REGISTER

(STATR_S)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D[4:0] determine the content of the first sixteen bits of SO

data. In addition to the device status, this feature provides the

ability to read the content of the PWMR_s, CONFR0_s,

CONFR1_s, OCR_s, GCR and CALR registers (Refer to the

section entitled Serial Output Communication (Device Status

Return Data) on page 34.

high

Not used

Incoming message bits D2:D0 reflect the desired output

that will be delayed of predefined PWM clock rising edges

number, as shown Table 8, page 24 (only available for

PWM_en bit is set to logic [1]).

ADDRESS A A 011—OUTPUT CONFIGURATION

1

0

REGISTER (CONFR1_S)

ADDRESS A A 001—OUTPUT PWM CONTROL

1

0

The CONFR1_s register allows the MCU to configure

corresponding output fault management through the SPI.

Each output “s” is independently selected for configuration

based on the state of the D14:D13 bits (Table 12).

REGISTER (PWMR_S)

The PWMR_s register allows the MCU to control the state

of corresponding output through the SPI. Each output “s” is

independently selected for configuration based on the state

A logic [1] on bit D6 (RETRY_unlimited_s) disables the

autoretry counter for the selected output, the default value [0]

corresponds to enable auto-retry feature without time

limitation.

of the D14:D13 bits (Table 12).

Table 12. Output Selection

A₁(D14)

A₀(D13)

HS Selection

A logic [1] on bit D5 (RETRY_dis_s) disables the auto-

retry for the selected output, the default value [0] corresponds

to enable this feature.

0

1

0

1

0

1

HS0 (default)

HS1

A logic [1] on bit D4 (OS_dis_s) disables the output hard

shorted to VPWR protection for the selected output, the

default value [0] corresponds to enable this feature.

HS2

HS3

Bit D7 sets the output state. A logic [1] enables the

corresponding output switch and a logic [0] turns it OFF (if IN

input is also pulled down). Bits D6:D0 set the output PWM

duty-cycle to one of 128 levels for PWM_en is set to logic [1],

as shown Table 7, page 24.

A logic [1] on bit D3 (OLON_dis_s) disables the ON output

open-load detection for the selected output, the default value

[0] corresponds to enable this feature (Table 14).

A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF

output open-load detection for the selected output, the

default value [0] corresponds to enable this feature.

ADDRESS A A 010—OUTPUT CONFIGURATION

1

0

A logic [1] on bit D1 (OLLED_en_s) enables the ON output

open-load detection for LEDs for the selected output, the

default value [0] corresponds to ON output open-load

detection is set for bulbs (Table 14).

REGISTER (CONFR0_S)

The CONFR0_s register allows the MCU to configure

corresponding output switching through the SPI. Each output

“s” is independently selected for configuration based on the

state of the D14:D13 bits (Table 12).

Table 14. ON Open-load Selection

For the selected output, a logic [0] on bit D5 (DIR_DIS_s)

will enable the output for direct control. A logic [1] on bit D5

will disable the output from direct control (in this case, the

output is only controlled by On bit).

OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection

0

enable with bulb threshold

(default)

D4:D3 bits (SR1_s and SR0_s) are used to select the high

or medium or low speed slew rate for the selected output, the

default value [00] corresponds to the medium speed slew rate

(Table 13).

0

1

enable with LED threshold

disable

X

A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio

on the CSNS pin for the corresponding output. The default

value [0] is the low ratio (Table 15).

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 15. Current Sense Ratio Selection

I

OCH1

OCH2

CSNS_high_s (D0)

Current Sense Ratio

I

0

1

CRS0 (default)

CRS1

OC1

OC2

OC3

OC4

OCLO4

OCLO3

OCLO2

OCLO1

ADDRESS A A 100—OUTPUT OVER-CURRENT

1

0

REGISTER (OCR)

Time

The OCR_s register allows the MCU to configure

corresponding output over-current protection through the

SPI. Each output “s” is independently selected for

configuration based on the state of the D14:D13 bits

(Table 12).

t

OC7

t

OC3

OC1

t

OC5

OC6

OC4

OC2

Figure 13. Over-current profile with OCHI bit set to ‘1’

The wire harness is protected by one of four possible

current levels in steady state, as defined in Table 18.

D[7:6] bits allow to MCU to programmable bulb cooling

curve and D[5:4] bits inrush curve for selected output, as

shown Table 16 and Table 17.

Table 18. Output Steady State Selection

OCLO1 (D2) OCLO0 (D1)

Steady State Current

.

0

1

0

1

0

1

OCLO2 (default)

OCLO3

Table 16. Cooling and Inrush Curve Selection

BC1_s (D7)

BC0_s (D6)

Profile Curves Speed

OCLO4

OCLO1

0

1

0

1

0

1

medium (default)

slow

Bit D0 (OC_mode_sel) allows to select the over-current

mode, as described Table 19.

fast

medium

Table 19. Over-current Mode Selection

Table 17. Inrush Curve Selection

OC_mode_s (D0)

Over-current Mode

OC1_s (D5)

OC0_s (D4)

Profile Curves Speed

slow (default)

fast

0

1

only inrush current management (default)

inrush current and bulb cooling management

0

1

0

1

0

1

ADDRESS 00101—GLOBAL CONFIGURATION

REGISTER (GCR)

medium

very slow

The GCR register allows the MCU to configure the device

through the SPI.

A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is

replaced by OCHI2 during t_OC1, as shown Figure 13.

Bit D8 allows the MCU to enable or disable the V_DDfailure

detector. A logic [1] on VDD_FAIL_en bit allows transitioning

to Fail-safe mode for V_DD< V_DD(FAIL).

Bit D7 allows the MCU to enable or disable the PWM

module. A logic [1] on PWM_en bit allows control of the

outputs HS[0:3] with PWMR register (the direct input states

are ignored).

Bit D6 (CLOCK_sel) allows to select the clock used as

reference by PWM module, as described in the following

Table 20.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

a CS transition, is dependent upon the previously written SPI

word.

Table 20. PWM Module Selection

PWM_en (D7) CLOCK_sel (D6)

Any bits clocked out of the Serial Output (SO) pin after the

first 16 bits will be representative of the initial message bits

clocked into the SI pin since the CS pin first transitioned to a

logic [0]. This feature is useful for daisy-chaining devices as

well as message verification.

PWM module

0

1

X

0

1

PWM module disabled

(default)

PWM module enabled with

external clock from IN0

A valid message length is determined following a CS

transition of [0] to [1]. If there is a valid message length, the

data is latched into the appropriate registers. A valid

message length is a multiple of 16 bits. At this time, the SO

pin is tri-stated and the fault status register is now able to

accept new fault status information.

PWM module enabled with

internal calibrated clock

Bits D5:D4 allow the MCU to select one of two analog

feedback on CSNS output pin, as shown in Table 21.

SO data will represent information ranging from fault

status to register contents, user selected by writing to the

STATR bits OD4, OD3, OD2, OD1, and OD0. The value of

the previous bits SOA4 and SOA3 will determine which

output the SO information applies to for the registers which

are output specific; viz., Fault, PWMR, CONFR0, CONFR1

and OCR registers.

Table 21. CSNS Reporting Selection

TEMP_en CSNS_en

CSNS reporting

(D5)

(D4)

0

X

1

0

1

0

CSNS tri-stated (default)

current recopy of selected output (D3:2] bits)

temperature on GND flag

Note that the SO data will continue to reflect the

information for each output (depending on the previous

SOA4, SOA3 state) that was selected during the most recent

STATR write until changed with an updated STATR write.

Table 22. Output Current Recopy Selection

CSNS1 (D3) CSNS0 (D2)

CSNS reporting

The output status register correctly reflects the status of

the STATR-selected register data at the time that the CS is

pulled to a logic [0] during SPI communication, and/or for the

period of time since the last valid SPI communication, with

the following exception:

0

1

0

1

0

1

HS0 (default)

HS1

HS2

•The previous SPI communication was determined to be

invalid. In this case, the status will be reported as

though the invalid SPI communication never occurred.

•The VPWR voltage is below 4.0 V, the status must be

ignored by the MCU.

HS3

The GCR register disables the over-voltage protection

(D0). When this bits is [0], the over-voltage is enabled (default

value).

SERIAL OUTPUT BIT ASSIGNMENT

ADDRESS 00111—CALIBRATION REGISTER

(CALR)

The 16 bits of serial output data depend on the previous

serial input message, as explained in the following

paragraphs. Table 23, summarizes SO returned data for bits

OD15:OD0.

The CALR register allows the MCU to calibrate internal

clock, as explained in Figure 12.

• Bit OD15 is the MSB; it reflects the state of the

Watchdog bit from the previously clocked-in message.

• Bits OD14:OD10 reflect the state of the bits

SOA4:SOA0 from the previously clocked in message.

• Bit OD9 is set to logic [1] in Normal mode (NM).

• The contents of bits OD8:OD0 depend on bits D4:D0

from the most recent STATR command SOA4:SOA0

as explained in the paragraphs following Table 23.

SERIAL OUTPUT COMMUNICATION (DEVICE

STATUS RETURN DATA)

When the CS pin is pulled low, the output register is

loaded. Meanwhile, the data is clocked out MSB- (OD15-)

first as the new message data is clocked into the SI pin. The

first sixteen bits of data clocking out of the SO, and following

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 23. Serial Output Bit Map Description

SO Returned Data

S

O

S

O

S

O

S

O

S

O

OD OD OD OD OD OD OD

OD8 OD7 OD6 OD5 OD4

OD3

OD2

OD1

OD0

15 14 13 12 11 10

9

A4 A3 A2 A1 A0

STATR

_s

WDI SOA SOA SOA SOA SOA

OLON_ OLOFF

A

0

1

0

1

0

NM POR UV

OV

OS_s

OT_s

SC_s

OC_s

1

0

N

4

3

2

1

0

s

_s

ON_s PWM6_ PWM5_ PWM4_ PWM3_s

PWM2_s

PWM1_s PWM0_s

PWMR_

s

WDI SOA SOA SOA SOA SOA

NM

0

s

N

4

3

2

1

0

DIR_dis SR1_s

_s

SR0_s

DELAY2_s DELAY1_s DELAY0_s

CONFR

0_s

WDI SOA SOA SOA SOA SOA

X

N

4

3

2

1

0

Retry_ Retry_d OS_dis OLON_dis_s OLOFF_dis_s OLLED_en CSNS_rati

CONFR

1_s

WDI SOA SOA SOA SOA SOA

A

0

1

0

1

0

1

NM

X

is_s

_s

o_s

unlimite

d_s

1

0

N

4

3

2

1

0

BC0_s OC1_s OC0_s

OCHI_s

CSNS1

OCLO1_s

CSNS0

OCLO0_s OC_mode

_s

WDI SOA SOA SOA SOA SOA

BC1_

s

OCR_s

GCR

N

4

3

2

1

0

VDD_ PWM CLOCK TEMP_ CSNS_

X

OV_dis

WDI SOA SOA SOA SOA SOA

0

FAIL_ _en

en

_sel

en

N

4

3

2

1

0

X

CLOCK_fail

IN1

WDI SOA SOA SOA SOA SOA

DIAGR0

DIAGR1

DIAGR2

0

1

0

1

0

1

NM

X

CAL_fail

IN0

OTW

N

4

3

2

1

0

IN2

WDI SOA SOA SOA SOA SOA

IN3

WD_en

N

4

3

2

1

0

WDI SOA SOA SOA SOA SOA

NM

0

X

0

X

0

X

0

X

0

X

0

X

0

x

1

0

N

4

3

2

1

0

Registe

r state

after

0

N/ N/ N/ N/ N/

A

0

A

RST=0

or

V

DD(FAI

or

L)

SUPPL

V

Y(POR)

conditi

on

s=Output selection with the bits A₁A₀as defined in Table 12

• OS_s: output shorted to VPWR fault detection for a

selected output,

PREVIOUS ADDRESS SOA4:SOA0=A A 000

(STATR_S)

1

0

• OLOFF_s: openload in OFF state fault detection for a

selected output,

• OLON_s: openload in ON state fault detection (depending

on current level threshold: bulb or LED) for a selected

output,

• OV: over-voltage fault detection,

• UV: under-voltage fault detection

• POR: power on reset detection.

The returned data OD8 reports logic [1] in case of previous

Power ON Reset condition (V_SUPPLY(POR)). This bit is only

reset by a read operation.

Bits OD7:OD0 reflect the current state of the Fault register

(FLTR) corresponding to the output previously selected with

the bits SOA4:SOA3 = A₁A₀(Table 23).

• OC_s: over-current fault detection for a selected output,

• SC_s: severe short-circuit fault detection for a selected

output,

The FS pin reports all faults. For latched faults, this pin is

reset by a new Switch OFF command (toggling fault_control

signal).

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

PREVIOUS ADDRESS SOA4:SOA0=A A 001

(PWMR_S)

PREVIOUS ADDRESS SOA4:SOA0=01111

(DIAGR1)

1

0

The returned data contains the programmed values in the

PWMR register for the output selected with A₁A₀.

The returned data OD4: OD1 report in real time the state

of the direct input IN[3:0].

The OD0 indicates if the watchdog is enabled (set to logic

[1]) or not (set to logic [0]). OD4:OD1 report the output state

in case of Fail-safe state due to watchdog time-out as

explained in the following Table 24.

PREVIOUS ADDRESS SOA4:SOA0=A A 010

(CONFR0_S)

1

0

The returned data contains the programmed values in the

CONFR0 register for the output selected with A₁A₀.

Table 24. Watchdog activation report

WD_en (OD0)

PREVIOUS ADDRESS SOA4:SOA0=A A 011

1

0

(CONFR1_S)

0

1

disabled

enabled

The returned data contains the programmed values in the

CONFR1 register for the output selected with A₁A₀.

PREVIOUS ADDRESS SOA4:SOA0=10111

(DIAGR2)

PREVIOUS ADDRESS SOA4:SOA0=A A 100

(OCR_S)

1

0

The returned data is the product ID. Bits OD2:OD0 are set

to 1XX for Protected Quad 35 mΩ High Side Switches.

The returned data contains the programmed values in the

OCR register for the output selected with A₁A₀.

DEFAULT DEVICE CONFIGURATION

PREVIOUS ADDRESS SOA4:SOA0=00101 (GCR)

The default device configuration is explained below:

• HS output is commanded by corresponding IN input or On

bit through SPI. The medium slew-rate is used,

• HS output is fully protected by the severe short-circuit

protection, the under-voltage, and the over-temperature

protection. The auto-retry feature is enabled,

• Open-load in ON and OFF state and HS shorted to VPWR

detections are available,

The returned data contains the programmed values in the

GCR register.

PREVIOUS ADDRESS SOA4:SOA0=00111

(DIAGR0)

The returned data OD2 reports logic [1] in case of PWM

clock on IN0 pin is out of specified frequency range.

• No current recopy and no analog temperature feedback

active,

• Over-voltage protection is enabled,

The returned data OD1 reports logic [1] in case of

calibration failure.

• SO reporting fault status from HS0,

• VDD failure detection is disabled.

The returned data OD0 reports logic [1] in case of over-

temperature prewarning (temperature of GND flag is above

T_OTWAR).

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

TYPICAL APPLICATIONS

The following figure shows a typical automotive lighting

implemented to substitute light control (from MCU to

application (only one vehicle corner) using an external PWM

clock from the main MCU. A redundancy circuitry has been

watchdog) in case of a Fail-safe condition.

It is recommended to locate a 22 nF decoupling capacitor

to the module connector.

V_PWR

V_DD

Voltage regulator

10µF

100nF

10µF

100nF

V_PWR

V_DD

V_PWR

ignition

switch

V_DD

VPWR

VDD

100nF

10k

100nF

V_DD

WAKE

HS0

HS1

HS2

22nF

I/O

FS

LOAD 0

LOAD 1

IN0

IN1

IN2

IN3

MCU

35XS3400

10k

SCLK

10k

SCLK

CS

RST

CS

10k

I/O

SO

SI

22nF

SI

LOAD 2

LOAD 3

SO

HS3

A/D

CSNS

FSI

10k

GND

22nF

4.7k

10k

VPWR

Watchdog

direct light commands (pedal, comodo,...)

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

PACKAGING

SOLDERING INFORMATION

PACKAGING

SOLDERING INFORMATION

The 35XS3400 is packaged in a surface mount power

package intended to be soldered directly on the printed circuit

board.

The DPNA code was qualified in accordance with JEDEC

standards J-STD-020C Pb-free reflow profile. The maximum

peak temperature during the soldering process should not

exceed 260 for 40 seconds maximum duration.

The CPNA code was qualified in accordance with JEDEC

standards J-STD-020C Sn-Pb reflow profile. The maximum

peak temperature during the soldering process should not

exceed 245 for 10 seconds maximum duration.

The AN2469 provides guidelines for Printed Circuit Board

design and assembly.

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below.

PNA SUFFIX

24-PIN PQFN

NONLEADED PACKAGE

98ARL10596D

ISSUE D

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

PACKAGING

PACKAGE DIMENSIONS

PNA SUFFIX

24-PIN PQFN

NONLEADED PACKAGE

98ARL10596D

ISSUE D

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

40

PACKAGING

PACKAGE DIMENSIONS

PNA SUFFIX

24-PIN PQFN

NONLEADED PACKAGE

98ARL10596D

ISSUE D

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

PACKAGING

PACKAGE DIMENSIONS

PNA SUFFIX

24-PIN PQFN

NONLEADED PACKAGE

98ARL10596D

ISSUE D

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 1.0)

ADDITIONAL DOCUMENTATION

35XS3400PNA

THERMAL ADDENDUM (REV 1.0)

Introduction

This thermal addendum is provided as a supplement to the 35XS3400

technical data sheet. The addendum provides thermal performance

information that may be critical in the design and development of system

applications. All electrical, application and packaging information is

provided in the data sheet.

24-PIN

PQFN

Package and Thermal Considerations

This 35XS3400 is a dual die package. There are two heat sources in the

package independently heating with P₁and P₂. This results in two junction

temperatures, T_J1and T_J2, and a thermal resistance matrix with R_θJAmn

.

For m, n = 1, R_θJA11is the thermal resistance from Junction 1 to the

reference temperature while only heat source 1 is heating with P₁.

PNA SUFFIX (PB-FREE)

98ARL10596D

24-PIN PQFN (12 x 12)

For m = 1, n = 2, R_θJA12is the thermal resistance from Junction 1 to the

reference temperature while heat source 2 is heating with P₂. This applies

to R_θJ21and R_θJ22, respectively.

Note For package dimensions, refer to

the 35XS3400 data sheet.

R_θJA11R_θJA12

R_θJA21R_θJA22

T_J1

T_J2

P₁

P₂

.

=

The stated values are solely for a thermal performance comparison of

one package to another in a standardized environment. This methodology is not meant to and will not predict the performance

of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to

the standards listed below.

Standards

Table 25. Thermal Performance Comparison

1 = Power Chip, 2 = Logic Chip [°C/W]

Thermal

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

Resistance

(1)(2)

R_θJAmn

R_θJBmn

R_θJAmn

R_θJCmn

27.35

14.53

47.63

1.48

18.40

6.64

35.25

23.69

53.61

0.95

(2)(3)

(1)(4)

(5)

0.2mm

37.21

0.00

Notes:

0.2mm

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

0.5mm dia.

2. 2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Figure 14. Detail of Copper Traces Under Device with

Thermal Vias

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 1.0)

76.2mm

Figure 15. 1s JEDEC Thermal Test Board Layout

Figure 16. 2s2p JEDEC Thermal Test Board

(Red - Top Layer, Yellow - Two Buried Layers)

Transparent Top View

13 12 11 10

9

8

7

6

5

4

3

2

1

SO

16

17

24

FSI

GND

23

GND

14

GND

HS3

18

22

HS2

15

VPWR

MC35XS3400 Pin Connections

24 Pin PQFN (12 x 12)

0.9mm Pitch

12.0mm x 12.0mm Body

19

20

21

HS1

NC

HS0

Figure 17. Pin Connections

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

44

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 1.0)

Device on Thermal Test Board

Table 26. Thermal Resistance Performance

Material:

Single layer printed circuit board

1 = Power Chip, 2 = Logic Chip (°C/W)

FR4, 1.6 mm thickness

Area A

(mm²)

Thermal

Resistance

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

Cu traces, 0.07 mm thickness

Cu buried traces thickness

0.035 mm

0

47.63

42.82

41.23

40.07

39.24

37.21

33.14

31.84

30.90

30.14

53.61

51.06

50.36

49.26

48.57

150

300

450

600

Outline:

76.2 mm x 114.3 mm board area,

including edge connector for thermal

testing, 74 mm x 74 mm buried

layers area

R_θJAmn

Area A:

Cu heat-spreading areas on board

surface

R_θJAis the thermal resistance between die junction and

ambient air.

This device is a dual die package. Index m indicates the

die that is heated. Index n refers to the number of the die

where the junction temperature is sensed.

Ambient Conditions: Natural convection, still air

65.00

60.00

55.00

50.00

45.00

40.00

35.00

30.00

25.00

0

100

200

300

400

500

600

Heat spreading area [sqmm]

RJA11

RJA12=RJA21

RJA22

Figure 18. Steady State Thermal Resistance in Dependence on Heat Spreading Area;

1s JEDEC Thermal Test Board with Spreading Areas

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

45

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 1.0)

100

10

1

0.1

0.000001

0.0001

0.01

1

100

10000

Time[s]

RJA11

RJA12

RJA22

Figure 19. Transient Thermal 1W Step Response; Device on

1s JEDEC Standard Thermal Test Board with Heat Spreading Areas 600 Sq. mm

100

10

1

0.1

0.000001

0.0001

0.01

1

100

10000

Time [s]

RJA11

RJA12

RJA22

Figure 20. Transient Thermal 1W Step Response;

Device on 2s2p JEDEC Standard Thermal Test Board

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

46

REVISION HISTORY

REVISION DATE

DESCRIPTION OF CHANGES

9/2008

•

Initial release

4.0

5.0

Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics

Table on page 7.

10/2008

•

Added explanation for recovering to Sleep Mode on page 22.

7/2009

Added MC35XS3400DPNA part number. The “D” version has different soldering limits.

6.0

7.0

•

Corrected minor formatting

Separated definitions for the 35XS3400C and 35XS3400D in the Static and Dynamic Tables

10/2009

•

Table 23, Serial Output Bit Map Description: (DIAGR2 register): OD1=X (instead of 0) and OD0=X

(instead of 0)

1/2011

8.0

•

Previous Address SOA4:SOA0=10111 (diagr2) on page 36: bits OD2:OD0 are set to 1XX (instead of

100) for protected..

35XS3400

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

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MC35XS3400

Rev. 8.0

1/2011