S-1003NB21I-M5T1U_技术文档

S-1003 Series

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

HIGH-ACCURACY VOLTAGE DETECTOR

www.ablic.com

www.ablicinc.com

Rev.1.0_03

The S-1003 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed

internally with an accuracy of 1.0% (V_DET2.2 V). It operates with current consumption of 500 nA typ.

The release signal can be delayed by setting a capacitor externally. Delay time accuracy is 15%.

Moreover, since the S-1003 Series includes the manual reset function, the reset signal can be also output forcibly.

Two output forms Nch open-drain output and CMOS output are available.

 Features

 Detection voltage:

 Detection voltage accuracy:

1.2 V to 5.0 V (0.1 V step)

1.0% (2.2 V  V_DET 5.0 V)

22 mV (1.2 V  V_DET 2.2 V)

500 nA typ.

 Current consumption:

 Operation voltage range:

 Hysteresis width:

0.95 V to 10.0 V

5%  2%

 Manual reset function:

 Delay time accuracy:

 Output form:

MR pin logic active "L", active "H"

15% (C_D= 4.7 nF)

Nch open-drain output (Active "L")

CMOS output (Active "L")

Ta = 40°C to 85°C

 Operation temperature range:

 Lead-free (Sn 100%), halogen-free

 Applications

 Power supply monitor for microcomputer and reset for CPU

 Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance

 Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone

 Packages

 SOT-23-5

 SNT-6A

1

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Block Diagrams

1. Nch open-drain output product (S-1003NAxxI)

Function

Status

VDD

Output logic Active "L"

MR pin logic Active "L"

*1



Delay

OUT

circuit

*1



*1

V_REF

MR

*1

circuit

*1

VSS

MR

CD

*1. Parasitic diode

Figure 1

2. Nch open-drain output product (S-1003NBxxI)

Function

Status

VDD

Output logic Active "L"

MR pin logic Active "H"

*1



Delay

OUT

circuit

*1



*1

V_REF

MR

*1

circuit

*1

VSS

MR

CD

*1. Parasitic diode

Figure 2

2

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

3. CMOS output product (S-1003CAxxI)

Function

Status

Output logic Active "L"

MR pin logic Active "L"

VDD

*1



Delay

circuit

*1



OUT

*1

V_REF

MR

circuit

*1

VSS

MR

CD

*1. Parasitic diode

Figure 3

4. CMOS output product (S-1003CBxxI)

Function

Status

VDD

Output logic Active "L"

MR pin logic Active "H"

*1



Delay

circuit

*1



OUT

*1

V_REF

MR

circuit

*1

VSS

MR

CD

*1. Parasitic diode

Figure 4

3

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Product Name Structure

Users can select the output form, MR pin logic, detection voltage value, and package type for the S-1003 Series. Refer

to "1. Product name" regarding the contents of product name, "2. Product type list" regarding the product types,

"3. Packages" regarding the package drawings and "4. Product name list" regarding details of product name.

1. Product name

S-1003

x

xx

I

-

xxxx

U

Environmental code

U:

Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specifications^*1

M5T1: SOT-23-5, Tape

I6T1: SNT-6A, Tape

Operation temperature

I:

Ta = 40C to 85C

Detection voltage value

12 to 50

(e.g., when the detection voltage is 1.2 V, it is expressed as 12.)

MR pin logic^*2

A:

B:

Active "L"

Active "H"

Output form^*2

N:

C:

Nch open-drain output (Active "L")^*3

CMOS output (Active "L")^*3

*1. Refer to the tape drawing.

*2. Refer to "2. Product type list".

*3. If you request the product with output logic active "H", contact our sales office.

2. Product type list

Table 1

Product Type

Output Form

MR Pin Logic

Active "L"

Output Logic

Active "L"

NA

NB

CA

CB

Nch open-drain output

Active "H"

Active "L"

Active "H"

Active "L"

CMOS output

3. Packages

Table 2 Package Drawing Codes

Package Name

SOT-23-5

Dimension

Tape

Reel

Land

MP005-A-P-SD

PG006-A-P-SD

MP005-A-C-SD

PG006-A-C-SD

MP005-A-R-SD

PG006-A-R-SD



SNT-6A

PG006-A-L-SD

4

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

4. Product name list

4. 1 S-1003 Series NA type

Output form: Nch open-drain output (Active "L")

MR pin logic: Active "L"

Table 3

Detection Voltage

SOT-23-5

SNT-6A

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

S-1003NA12I-M5T1U

S-1003NA13I-M5T1U

S-1003NA14I-M5T1U

S-1003NA15I-M5T1U

S-1003NA16I-M5T1U

S-1003NA17I-M5T1U

S-1003NA18I-M5T1U

S-1003NA19I-M5T1U

S-1003NA20I-M5T1U

S-1003NA21I-M5T1U

S-1003NA22I-M5T1U

S-1003NA23I-M5T1U

S-1003NA24I-M5T1U

S-1003NA25I-M5T1U

S-1003NA26I-M5T1U

S-1003NA27I-M5T1U

S-1003NA28I-M5T1U

S-1003NA29I-M5T1U

S-1003NA30I-M5T1U

S-1003NA31I-M5T1U

S-1003NA32I-M5T1U

S-1003NA33I-M5T1U

S-1003NA34I-M5T1U

S-1003NA35I-M5T1U

S-1003NA36I-M5T1U

S-1003NA37I-M5T1U

S-1003NA38I-M5T1U

S-1003NA39I-M5T1U

S-1003NA40I-M5T1U

S-1003NA41I-M5T1U

S-1003NA42I-M5T1U

S-1003NA43I-M5T1U

S-1003NA44I-M5T1U

S-1003NA45I-M5T1U

S-1003NA46I-M5T1U

S-1003NA47I-M5T1U

S-1003NA48I-M5T1U

S-1003NA49I-M5T1U

S-1003NA50I-M5T1U

S-1003NA12I-I6T1U

S-1003NA13I-I6T1U

S-1003NA14I-I6T1U

S-1003NA15I-I6T1U

S-1003NA16I-I6T1U

S-1003NA17I-I6T1U

S-1003NA18I-I6T1U

S-1003NA19I-I6T1U

S-1003NA20I-I6T1U

S-1003NA21I-I6T1U

S-1003NA22I-I6T1U

S-1003NA23I-I6T1U

S-1003NA24I-I6T1U

S-1003NA25I-I6T1U

S-1003NA26I-I6T1U

S-1003NA27I-I6T1U

S-1003NA28I-I6T1U

S-1003NA29I-I6T1U

S-1003NA30I-I6T1U

S-1003NA31I-I6T1U

S-1003NA32I-I6T1U

S-1003NA33I-I6T1U

S-1003NA34I-I6T1U

S-1003NA35I-I6T1U

S-1003NA36I-I6T1U

S-1003NA37I-I6T1U

S-1003NA38I-I6T1U

S-1003NA39I-I6T1U

S-1003NA40I-I6T1U

S-1003NA41I-I6T1U

S-1003NA42I-I6T1U

S-1003NA43I-I6T1U

S-1003NA44I-I6T1U

S-1003NA45I-I6T1U

S-1003NA46I-I6T1U

S-1003NA47I-I6T1U

S-1003NA48I-I6T1U

S-1003NA49I-I6T1U

S-1003NA50I-I6T1U

5

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

4. 2 S-1003 Series NB type

Output form: Nch open-drain output (Active "L")

MR pin logic: Active "H"

Table 4

Detection Voltage

SOT-23-5

SNT-6A

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

S-1003NB12I-M5T1U

S-1003NB13I-M5T1U

S-1003NB14I-M5T1U

S-1003NB15I-M5T1U

S-1003NB16I-M5T1U

S-1003NB17I-M5T1U

S-1003NB18I-M5T1U

S-1003NB19I-M5T1U

S-1003NB20I-M5T1U

S-1003NB21I-M5T1U

S-1003NB22I-M5T1U

S-1003NB23I-M5T1U

S-1003NB24I-M5T1U

S-1003NB25I-M5T1U

S-1003NB26I-M5T1U

S-1003NB27I-M5T1U

S-1003NB28I-M5T1U

S-1003NB29I-M5T1U

S-1003NB30I-M5T1U

S-1003NB31I-M5T1U

S-1003NB32I-M5T1U

S-1003NB33I-M5T1U

S-1003NB34I-M5T1U

S-1003NB35I-M5T1U

S-1003NB36I-M5T1U

S-1003NB37I-M5T1U

S-1003NB38I-M5T1U

S-1003NB39I-M5T1U

S-1003NB40I-M5T1U

S-1003NB41I-M5T1U

S-1003NB42I-M5T1U

S-1003NB43I-M5T1U

S-1003NB44I-M5T1U

S-1003NB45I-M5T1U

S-1003NB46I-M5T1U

S-1003NB47I-M5T1U

S-1003NB48I-M5T1U

S-1003NB49I-M5T1U

S-1003NB50I-M5T1U

S-1003NB12I-I6T1U

S-1003NB13I-I6T1U

S-1003NB14I-I6T1U

S-1003NB15I-I6T1U

S-1003NB16I-I6T1U

S-1003NB17I-I6T1U

S-1003NB18I-I6T1U

S-1003NB19I-I6T1U

S-1003NB20I-I6T1U

S-1003NB21I-I6T1U

S-1003NB22I-I6T1U

S-1003NB23I-I6T1U

S-1003NB24I-I6T1U

S-1003NB25I-I6T1U

S-1003NB26I-I6T1U

S-1003NB27I-I6T1U

S-1003NB28I-I6T1U

S-1003NB29I-I6T1U

S-1003NB30I-I6T1U

S-1003NB31I-I6T1U

S-1003NB32I-I6T1U

S-1003NB33I-I6T1U

S-1003NB34I-I6T1U

S-1003NB35I-I6T1U

S-1003NB36I-I6T1U

S-1003NB37I-I6T1U

S-1003NB38I-I6T1U

S-1003NB39I-I6T1U

S-1003NB40I-I6T1U

S-1003NB41I-I6T1U

S-1003NB42I-I6T1U

S-1003NB43I-I6T1U

S-1003NB44I-I6T1U

S-1003NB45I-I6T1U

S-1003NB46I-I6T1U

S-1003NB47I-I6T1U

S-1003NB48I-I6T1U

S-1003NB49I-I6T1U

S-1003NB50I-I6T1U

6

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

4. 3 S-1003 Series CA type

Output form: CMOS output (Active "L")

MR pin logic: Active "L"

Table 5

Detection Voltage

SOT-23-5

SNT-6A

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

S-1003CA12I-M5T1U

S-1003CA13I-M5T1U

S-1003CA14I-M5T1U

S-1003CA15I-M5T1U

S-1003CA16I-M5T1U

S-1003CA17I-M5T1U

S-1003CA18I-M5T1U

S-1003CA19I-M5T1U

S-1003CA20I-M5T1U

S-1003CA21I-M5T1U

S-1003CA22I-M5T1U

S-1003CA23I-M5T1U

S-1003CA24I-M5T1U

S-1003CA25I-M5T1U

S-1003CA26I-M5T1U

S-1003CA27I-M5T1U

S-1003CA28I-M5T1U

S-1003CA29I-M5T1U

S-1003CA30I-M5T1U

S-1003CA31I-M5T1U

S-1003CA32I-M5T1U

S-1003CA33I-M5T1U

S-1003CA34I-M5T1U

S-1003CA35I-M5T1U

S-1003CA36I-M5T1U

S-1003CA37I-M5T1U

S-1003CA38I-M5T1U

S-1003CA39I-M5T1U

S-1003CA40I-M5T1U

S-1003CA41I-M5T1U

S-1003CA42I-M5T1U

S-1003CA43I-M5T1U

S-1003CA44I-M5T1U

S-1003CA45I-M5T1U

S-1003CA46I-M5T1U

S-1003CA47I-M5T1U

S-1003CA48I-M5T1U

S-1003CA49I-M5T1U

S-1003CA50I-M5T1U

S-1003CA12I-I6T1U

S-1003CA13I-I6T1U

S-1003CA14I-I6T1U

S-1003CA15I-I6T1U

S-1003CA16I-I6T1U

S-1003CA17I-I6T1U

S-1003CA18I-I6T1U

S-1003CA19I-I6T1U

S-1003CA20I-I6T1U

S-1003CA21I-I6T1U

S-1003CA22I-I6T1U

S-1003CA23I-I6T1U

S-1003CA24I-I6T1U

S-1003CA25I-I6T1U

S-1003CA26I-I6T1U

S-1003CA27I-I6T1U

S-1003CA28I-I6T1U

S-1003CA29I-I6T1U

S-1003CA30I-I6T1U

S-1003CA31I-I6T1U

S-1003CA32I-I6T1U

S-1003CA33I-I6T1U

S-1003CA34I-I6T1U

S-1003CA35I-I6T1U

S-1003CA36I-I6T1U

S-1003CA37I-I6T1U

S-1003CA38I-I6T1U

S-1003CA39I-I6T1U

S-1003CA40I-I6T1U

S-1003CA41I-I6T1U

S-1003CA42I-I6T1U

S-1003CA43I-I6T1U

S-1003CA44I-I6T1U

S-1003CA45I-I6T1U

S-1003CA46I-I6T1U

S-1003CA47I-I6T1U

S-1003CA48I-I6T1U

S-1003CA49I-I6T1U

S-1003CA50I-I6T1U

7

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

4. 4 S-1003 Series CB type

Output form: CMOS output (Active "L")

MR pin logic: Active "H"

Table 6

Detection Voltage

SOT-23-5

SNT-6A

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

S-1003CB12I-M5T1U

S-1003CB13I-M5T1U

S-1003CB14I-M5T1U

S-1003CB15I-M5T1U

S-1003CB16I-M5T1U

S-1003CB17I-M5T1U

S-1003CB18I-M5T1U

S-1003CB19I-M5T1U

S-1003CB20I-M5T1U

S-1003CB21I-M5T1U

S-1003CB22I-M5T1U

S-1003CB23I-M5T1U

S-1003CB24I-M5T1U

S-1003CB25I-M5T1U

S-1003CB26I-M5T1U

S-1003CB27I-M5T1U

S-1003CB28I-M5T1U

S-1003CB29I-M5T1U

S-1003CB30I-M5T1U

S-1003CB31I-M5T1U

S-1003CB32I-M5T1U

S-1003CB33I-M5T1U

S-1003CB34I-M5T1U

S-1003CB35I-M5T1U

S-1003CB36I-M5T1U

S-1003CB37I-M5T1U

S-1003CB38I-M5T1U

S-1003CB39I-M5T1U

S-1003CB40I-M5T1U

S-1003CB41I-M5T1U

S-1003CB42I-M5T1U

S-1003CB43I-M5T1U

S-1003CB44I-M5T1U

S-1003CB45I-M5T1U

S-1003CB46I-M5T1U

S-1003CB47I-M5T1U

S-1003CB48I-M5T1U

S-1003CB49I-M5T1U

S-1003CB50I-M5T1U

S-1003CB12I-I6T1U

S-1003CB13I-I6T1U

S-1003CB14I-I6T1U

S-1003CB15I-I6T1U

S-1003CB16I-I6T1U

S-1003CB17I-I6T1U

S-1003CB18I-I6T1U

S-1003CB19I-I6T1U

S-1003CB20I-I6T1U

S-1003CB21I-I6T1U

S-1003CB22I-I6T1U

S-1003CB23I-I6T1U

S-1003CB24I-I6T1U

S-1003CB25I-I6T1U

S-1003CB26I-I6T1U

S-1003CB27I-I6T1U

S-1003CB28I-I6T1U

S-1003CB29I-I6T1U

S-1003CB30I-I6T1U

S-1003CB31I-I6T1U

S-1003CB32I-I6T1U

S-1003CB33I-I6T1U

S-1003CB34I-I6T1U

S-1003CB35I-I6T1U

S-1003CB36I-I6T1U

S-1003CB37I-I6T1U

S-1003CB38I-I6T1U

S-1003CB39I-I6T1U

S-1003CB40I-I6T1U

S-1003CB41I-I6T1U

S-1003CB42I-I6T1U

S-1003CB43I-I6T1U

S-1003CB44I-I6T1U

S-1003CB45I-I6T1U

S-1003CB46I-I6T1U

S-1003CB47I-I6T1U

S-1003CB48I-I6T1U

S-1003CB49I-I6T1U

S-1003CB50I-I6T1U

8

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Pin Configurations

1. SOT-23-5

Table 7

Top view

Pin No.

Symbol

Description

5

4

1

2

3

4

5

CD

Connection pin for delay capacitor

GND pin

VSS

MR

Manual reset pin

OUT

VDD

Voltage detection output pin

Voltage input pin

1

2

3

Figure 5

2. SNT-6A

Table 8

Top view

Pin No.

Symbol

Description

Connection pin for delay capacitor

Voltage input pin

1

2

3

6

5

4

1

2

3

4

5

6

CD

VDD

OUT

MR

NC^*1

VSS

Voltage detection output pin

Manual reset pin

Figure 6

No connection

GND pin

*1. The NC pin is electrically open.

The NC pin can be connected to the VDD pin or the VSS pin.

9

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Absolute Maximum Ratings

Table 9

(Ta = 25°C unless otherwise specified)

Item

Power supply voltage

CD pin input voltage

Symbol

Absolute Maximum Rating

12.0

Unit

V

V_DDV_SS

V_CD

V_SS0.3 to V_DD 0.3

V_SS0.3 to 12.0

V_SS0.3 to V_DD 0.3

50

V

MR pin input voltage

V_MR

V

Nch open-drain output product

V

Output voltage

Output current

Power dissipation

V_OUT

I_OUT

P_D

CMOS output product

V

mA

mW

°C

SOT-23-5

SNT-6A

600^*1

400^*1

Operation ambient temperature

Storage temperature

T_opr

T_stg

40 to 85

40 to 125

*1. When mounted on board

[Mounted board]

(1) Board size: 114.3 mm  76.2 mm  t1.6 mm

(2) Name: JEDEC STANDARD51-7

Caution The absolute maximum ratings are rated values exceeding which the product could suffer

physical damage. These values must therefore not be exceeded under any conditions.

700

600

500

SOT-23-5

400

300

SNT-6A

200

100

0

100

150

50

0

Ambient Temperature (Ta) [C]

Figure 7 Power Dissipation of Package (When Mounted on Board)

10

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Electrical Characteristics

1. Nch open-drain output product

Table 10

(Ta = 25°C unless otherwise specified)

Test

Circuit

Item

Symbol

Condition

1.2 V  V_DET 2.2 V

Min.

Typ.

Max.

Unit

V

V_DET(S)

 0.022

V_DET(S)

 0.99

V_DET

 0.03



V_DET(S)

 0.022

V_DET(S)

 1.01

V_DET

 0.07

0.90

10.0



V_DET(S)

1

Detection voltage^*1

Hysteresis width

V_DET

2.2 V  V_DET 5.0 V

V

1

V_DET

 0.05

0.50



1.00

1.33

2.39

2.50

V_HYS



V

Current consumption I_SS

V_DD= V_DET(S) 1.0 V

A

V

2

1

3

Operation voltage

Output current

V_DD



0.95

V

_DD= 0.95 V

0.59

mA

Output transistor

Nch

V_DD= 1.2 V

V_DD= 2.4 V

V_DD= 4.8 V

0.73



I_OUT

V_DS^*2= 0.5 V

MR pin active

1.47

1.86

Output transistor

Nch

Leakage current

I_LEAK



0.08

11.5

A

3

V

_DD= 10.0 V, V_OUT= 10.0 V

MR pin non-active

C_D= 4.7 nF

Delay time^*3

t_D

8.5

10.0

ms

4

1

Detection voltage

temperature

coefficient^*4

V_DET

Ta  V_DET

Ta = 40°C to 85°C



100

350 ppm/°C

NA type

(MR pin logic active "L")

NB type

(MR pin logic active "H")

NA type

(MR pin logic active "L")

NB type

V_DD

 0.3



V

6

MR pin

input voltage "H"

V_MRH

1.2



V_DD

 1.2



V

MR pin

input voltage "L"

V_MRL



0.3

1.6

V

(MR pin logic active "H")

MR pin

input resistance

R_MR



0.5

1.0

M

*1. V_DET: Actual detection voltage value, V_DET(S): Set detection voltage value (the center value of the detection voltage

range in Table 3 or Table 4.)

*2.

V_DS: Drain-to-source voltage of the output transistor

*3. The time period from when the pulse voltage of 0.95 V  V_DET(S)1.0 V is applied to the VDD pin to when V_OUT

reaches V_DD 0.9, after the output pin is pulled up to V_DDby the resistance of 100 k

*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.

  V_DET

Ta

  V_DET

Ta  V_DET

mV/°C ^*1= V_DET(S)(typ.) V ^*2

ppm/°C ^*3 1000

]

[

]

[ ]

[

*1. Temperature change of the detection voltage

*2. Set detection voltage

*3. Detection voltage temperature coefficient

11

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

2. CMOS output product

Table 11

(Ta = 25°C unless otherwise specified)

Test

Circuit

Item

Symbol

Condition

1.2 V  V_DET 2.2 V

Min.

Typ.

Max.

Unit

V

V_DET(S)

 0.022

V_DET(S)

 0.99

V_DET

 0.03



V_DET(S)

 0.022

V_DET(S)

 1.01

V_DET

 0.07

0.90

10.0



V_DET(S)

1

Detection voltage^*1

Hysteresis width

V_DET

2.2 V  V_DET 5.0 V

V

1

V_DET

 0.05

0.50



1.00

1.33

2.39

2.50

V_HYS



V

Current consumption I_SS

V_DD= V_DET(S) 1.0 V

A

V

2

1

3

Operation voltage

V_DD



0.95

V

_DD= 0.95 V

0.59

mA

Output transistor

Nch

V_DD= 1.2 V

0.73



V_DS^*2= 0.5 V

MR pin active

V_DD= 2.4 V

1.47

V_DD= 4.8 V

1.86

Output current

I_OUT

V_DD= 4.8 V

S-1003Cx12 to 43

Output transistor

Pch

1.62

2.60



mA

5

V_DS^*2= 0.5 V

V_DD= 6.0 V

1.78

8.5

2.86

10.0



mA

ms

5

4

Delay time^*3

t_D

C_D= 4.7 nF

11.5

Detection voltage

temperature

coefficient^*4

V_DET

Ta  V_DET

Ta = 40°C to 85°C

CA type

(MR pin logic active "L")

CB type

(MR pin logic active "H")

CA type

(MR pin logic active "L")

CB type



100

350 ppm/°C

1

V_DD

 0.3



V

6

MR pin

input voltage "H"

V_MRH

1.2



V_DD

 1.2



V

MR pin

input voltage "L"

V_MRL



0.3

1.6

V

(MR pin logic active "H")

MR pin

input resistance

R_MR



0.5

1.0

M

*1. V_DET: Actual detection voltage value, V_DET(S): Set detection voltage value (the center value of the detection voltage

range in Table 5 or Table 6.)

*2.

V_DS: Drain-to-source voltage of the output transistor

*3. The time period from when the pulse voltage of 0.95 V  V_DET(S)1.0 V is applied to the VDD pin to when V_OUT

reaches V_DD 0.9.

*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.

  V_DET

Ta

  V_DET

Ta  V_DET

mV/°C ^*1= V_DET(S)(typ.) V ^*2

ppm/°C ^*3 1000

]

[

]

[ ]

[

*1. Temperature change of the detection voltage

*2. Set detection voltage

*3. Detection voltage temperature coefficient

12

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Test Circuits



A

R^*1

100 k

VDD

V_DD



VDD

V_DD

OUT

CD

V

MR

VSS



OUT

CD

MR

*2

V

*1

VSS

*1. R is unnecessary for CMOS output product.

*2. Set to V_DDor GND (MR pin non-active).

*1. Set to V_DDor GND (MR pin non-active).

Figure 8 Test Circuit 1

Figure 9 Test Circuit 2

Oscilloscope

R^*1

100 k

VDD

V_DD





MR

OUT

CD

P.G.

OUT

CD

MR

V

A

V_DS



*2

V_OUT

VSS

*1

V

C_D

*1. Set to V_DDor GND.

*1. R is unnecessary for CMOS output product.

*2. Set to V_DDor GND (MR pin non-active).

Figure 10 Test Circuit 3

Figure 11 Test Circuit 4

V_DS





R^*1

V

VDD

MR

VSS

100 k

VDD

V_DD





V

OUT

CD

A

OUT

CD

A

MR

V_MR



VSS



*1

V

*1. Set to V_DDor GND (MR pin non-active).

*1. R is unnecessary for CMOS output product.

Figure 12 Test Circuit 5

Figure 13 Test Circuit 6

13

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Timing Charts

1. Nch open-drain output product

V_DD

Release voltage (V_DET

)

Hysteresis width

Detection voltage (V_DET

)

(V_HYS

)

Minimum operation voltage

V_SS

R

VDD

MR

100 k

V_DD

OUT

^*1VSS CD

V_DD



V

Output from OUT pin

V_SS

*1. Set to V_DDor GND (MR pin non-active).

t_D

Figure 14

2. CMOS output product

V_DD

Release voltage (V_DET

Detection voltage (V_DET

)

Hysteresis width

)

(V_HYS

)

Minimum operation voltage

V_SS

VDD

MR

V_DD

OUT

VSS CD

*1



V

V_DD

Output from OUT pin

*1. Set to V_DDor GND (MR pin non-active).

V_SS

t_D

Remark When V_DDis the minimum operation voltage or less, the output voltage from the OUT pin is indefinite

in the shaded area.

Figure 15

14

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Operation

1. Basic operation: CMOS output (active "L") product

(1)

When the power supply voltage (V_DD) is the release voltage (V_DET) or more, the Nch transistor is OFF and

the Pch transistor is ON to output V_DD("H"). Since the Nch transistor N1 in Figure 16 is OFF, the comparator

(R_B R_C)  V_DD

R_A R_B R_C

input voltage is

.

(2)

Although V_DDdecreases to V_DETor less, V_DDis output when V_DDis higher than the detection voltage (V_DET).

When V_DDdecreases to V_DETor less (point A in Figure 17), the Nch transistor is ON and the Pch transistor

is OFF so that V_SS("L") is output. At this time, the Nch transistor N1 in Figure 16 is turned on, and the input

R_B V_DD

voltage to the comparator is

.

R_A R_B

The output is indefinite by decreasing V_DDto the IC's minimum operation voltage or less. If the output is

pulled up, it will be V_DD

V_SSis output by increasing V_DDto the minimum operation voltage or more. Although V_DDexceeds V_DETand

V_DDis less than V_DET, the output is V_SS

(3)

(4)

(5)

.

When increasing V_DDto V_DETor more (point B in Figure 17), the Nch transistor is OFF and the Pch

transistor is ON so that V_DDis output. At this time, V_DDis output from the OUT pin after the passage of the

delay time (t_D).

VDD

*1

Pch

R_A





Delay

circuit

OUT

*1

R_B

R_C

Nch

V_REF

MR

circuit

*1

N1

VSS

MR

CD

C_D

*1. Parasitic diode

Figure 16 Operation 1

(2) (3)

(4)

B

(5)

V_DD

Release voltage (V_DET

Detection voltage (V_DET

(1)

)

A

Hysteresis width

(V_HYS

)

Minimum operation voltage

V_SS

V_DD

Output from OUT pin

V_SS

t_D

Remark When V_DDis the minimum operation voltage or less, the output voltage from the OUT pin is indefinite

in the shaded area.

Figure 17 Operation 2

15

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

2. Manual reset function

The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (V_MR).

When not using the manual reset function, set V_MR= V_DDin the S-1003 Series xA type, and V_MR= V_SSin the

S-1003 Series xB type.

Caution Perform thorough evaluation in the actual application when using the MR pin in open. Due to the

parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply

fluctuates.

2. 1 S-1003 Series xA type (MR pin logic active "L")

(1) MR pin = "L"

When the VDD pin voltage is the release voltage (V_DET) or more, the OUT pin changes to the detection status

from the release status immediately if a voltage of the MR pin input voltage "L" (V_MRL) or less is applied to the

MR pin.

(2) MR pin = "H"

If a voltage of the MR pin input voltage "H" (V_MRH) or more is applied to the MR pin, output from the OUT pin is

determined to be "H" or "L" depending on the VDD pin voltage.

After the passage of the delay time (t_D), the OUT pin changes to the release status from the detection status.

(1)

(2)

Input from VDD pin

Input from MR pin

V_DD(V_DET)

MR pin input voltage "H" (V_MRH

)

MR pin input voltage "L" (V_MRL

)

V_DD

Output from OUT pin

V_SS

t_D

Figure 18 Timing Chart of MR Pin Logic Active "L"

Remark Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in

the floating status depending on the VDD pin voltage (Refer to Figure 19).

VDD

*1

R_MR

MR

*1

VSS

*1. Parasitic diode

Figure 19

16

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

2. 2 S-1003 Series xB type (MR pin logic active "H")

(1) MR pin = "H"

When the VDD pin voltage is the release voltage (V_DET) or more, the OUT pin changes to the detection status

from the release status immediately if a voltage of the MR pin input voltage "H" (V_MRH) or more is applied to the

MR pin.

(2) MR pin = "L"

If a voltage of the MR pin input voltage "L" (V_MRL) or less is applied to the MR pin, output from the OUT pin is

determined to be "H" or "L" depending on the VDD pin voltage.

After the passage of the delay time (t_D), the OUT pin changes to the release status from the detection status.

(1)

(2)

Input from VDD pin

Input from MR pin

V_DD(V_DET)

MR pin input voltage "H" (V_MRH

)

MR pin input voltage "L" (V_MRL

)

V_DD

Output from OUT pin

V_SS

t_D

Figure 20 Timing Chart of MR Pin Logic Active "H"

Remark Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or

"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).

VDD

*1

MR

*1

R_MR

VSS

*1. Parasitic diode

Figure 21

17

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

2. 3 Cautions of manual reset function

2. 3. 1 Slew rate when switching manual reset function

Although there is a hysteresis width between the MR pin input voltage "L" (V_MRL) and the MR pin input voltage "H"

(V_MRH), note that the IC may malfunction if the slew rate (Refer to Figure 22, Figure 23) is low when the MR pin

voltage is changed.

The slew rate is calculated by using the following equation.

V_MRH V_MRL

Slew rate =

t

(1) When MR pin logic is active "L"

The OUT pin voltage may oscillate if the parasitic resistance (R_P) between the power supply and the VDD pin is

high.

・In case of R_P 8 k



Connect a capacitor of 1 nF or more between the VDD pin and the VSS pin.

・In case of 5 k  R_P 8 kCapacitors are unnecessary if the slew rate is 100 V/s or higher.

・In case of R_P 5 k



Capacitors are unnecessary if the slew rate is 1 V/s or higher.

V_MR

V_MRH

V_MRL

Time

t

Figure 22

(2) When MR pin logic is active "H"

Connect a capacitor of 100 pF or more to the CD pin, and set the slew rate 20 V/s or higher.

V_MR

V_MRH

V_MRL

Time

t

Figure 23

18

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

2. 4 When connecting resistance (R_A) between power supply voltage (V_DD) and VDD pin

When the MR pin voltage (V_MR) is an intermediate voltage (especially V_MRLV_MRV_MRH), the current consumption

increases by 25 A max. A voltage drop occurs since this current flows through R_A. If the VDD pin voltage (V_IN)

becomes the detection voltage (V_DET) or less for that reason, the OUT pin changes to the detection status, and the

detection status or the release status are not controlled by V_MR. The OUT pin may not be able to change to the

release status unless V_DDis raised (Refer to Figure 24).

(1) When MR pin logic is active "L"

In case of V_IN V_MR, a current also flows through the MR pin input resistance (R_MR). For example, when V_IN

=

10 V, V_MR= 1 V, R_MR= 0.5 M (min.), a current of 18 A flows from the VDD pin to the MR pin. Therefore, set

R_Aso as to satisfy the following equation.

R_A (V_DD (V_DET)) / (25 AMR pin current)

(2) When MR pin logic is active "H"

Set R_Aso as to satisfy the following equation.

R_A (V_DD (V_DET)) / 25 A

V_DD

R_A

V_IN

VDD

OUT

MR

VSS

CD

V_MR

(Nch open-drain output product)

GND

Figure 24

19

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

3. Delay circuit

The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (V_DD

)

exceeds the release voltage (V_DET) when V_DDis turned on. The output signal is not delayed when V_DDdecreases

to the detection voltage (V_DET) or less (refer to "Figure 17 Operation 2").

The delay time (t_D) is determined by the time constant of the built-in constant current (approx. 100 nA) and the

attached delay capacitor (C_D), or the delay time (t_D0) when the CD pin is open, and calculated from the following

equation. When the C_Dvalue is sufficiently large, the t_D0value can be disregarded.

t_D[ms] = Delay coefficient  C_D[nF]  t_D0[ms]

Table 12 Delay Coefficient

Delay Coefficient

Operation

Temperature

Min.

1.60

1.78

2.01

Typ.

1.89

2.05

2.31

Max.

2.13

2.30

2.71

Ta = 85°C

Ta = 25°C

Ta = 40°C

Table 13 Delay Time

Delay Time (t_D0)

Typ.

0.044 ms

Operation Temperature

Min.

Max.

0.147 ms

Ta = 40°C to 85°C

0.021 ms

Caution 1. When the CD pin is open, a double pulse shown in Figure 25 may appear at release.

To avoid the double pulse, attach a 100 pF or larger capacitor to the CD pin. Do not apply

voltage to the CD pin from the exterior.

V_OUT

Time

Figure 25

2. Mounted board layout should be made in such a way that no current flows into or flows from

the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be

provided.

3. There is no limit for the capacitance of C_Das long as the leakage current of the capacitor can

be ignored against the built-in constant current value. Leakage current causes deviation in

delay time. When the leakage current is larger than the built-in constant current, no release

takes place.

20

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

4. Other characteristics

4. 1 Temperature characteristics of detection voltage

The shaded area in Figure 26 shows the temperature characteristics of detection voltage in the operation

temperature range.

V_DET[V]

0.945 mV/°C

*1

V_DET25

0.945 mV/°C

40

25

85

Ta [°C]

*1. V_DET25is an actual detection voltage value at Ta = 25°C.

Figure 26 Temperature Characteristics of Detection Voltage (Example for V_DET= 2.7 V)

4. 2 Temperature characteristics of release voltage

  V_DET

Ta

The temperature change

of the release voltage is calculated by using the temperature change

  V_DET

Ta

of the detection voltage as follows:

  V_DET

Ta

V_DET

V_DET

  V_DET

Ta

=



The temperature change of the release voltage and the detection voltage has the same sign consequently.

4. 3 Temperature characteristics of hysteresis voltage

  V_DET

Ta

  V_DET

Ta

The temperature change of the hysteresis voltage is expressed as

follows:



and is calculated as

  V_DET

Ta

  V_DET

Ta

V_HYS

V_DET

  V_DET

Ta



=



21

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Standard Circuit

R^*1

100 k

VDD

MR

OUT

CD

VSS

*2

C_D

*1. R is unnecessary for CMOS output product.

*2. The delay capacitor (C_D) should be connected directly to the CD pin and the VSS pin.

Figure 27

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

22

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Explanation of Terms

1. Detection voltage (V_DET

)

The detection voltage is a voltage at which the output in Figure 30 turns to "L". The detection voltage varies slightly

among products of the same specification. The variation of detection voltage between the specified minimum

(V_DETmin.) and the maximum (V_DETmax.) is called the detection voltage range (Refer to Figure 28).

Example: In the S-1003Cx15, the detection voltage is either one in the range of 1.478 V  V_DET 1.522 V.

This means that some S-1003Cx15 have V_DET= 1.478 V and some have V_DET= 1.522 V.

2. Release voltage (V_DET

)

The release voltage is a voltage at which the output in Figure 30 turns to "H". The release voltage varies slightly

among products of the same specification. The variation of release voltage between the specified minimum (V_DET

min.) and the maximum (V_DETmax.) is called the release voltage range (Refer to Figure 29). The range is

calculated from the actual detection voltage (V_DET) of a product and is in the range of V_DET 1.03  V_DET V_DET

 1.07.

Example: For the S-1003Cx15, the release voltage is either one in the range of 1.522 V  V_DET 1.629 V.

This means that some S-1003Cx15 have V_DET= 1.522 V and some have V_DET= 1.629 V.

V_DD

Release voltage

Detection voltage

V_DETmax.

V_DETmin.

V_DETmax.

V_DETmin.

Release voltage

range

Detection voltage

range

OUT

t_D

Figure 28 Detection Voltage

Figure 29 Release Voltage

R^*1

100 k

VDD

V_DD



OUT

CD

V

MR

VSS



*2

V

*1. R is unnecessary for CMOS output product.

*2. Set to V_DDor GND (MR pin non-active).

Figure 30 Test Circuit of Detection Voltage and Release Voltage

23

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

3. Hysteresis width (V_HYS

)

The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at

point B  the voltage at point A = V_HYSin "Figure 17 Operation 2"). Setting the hysteresis width between the

detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.

4. Delay time (t_D)

The delay time in the S-1003 Series is a period from the input voltage to the VDD pin exceeding the release voltage

(V_DET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (C_D).

V_DD

V_DET

OUT

t_D

Figure 31 Delay Time

5. Feed-through current

Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage

detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.

6. Oscillation

In applications where a resistor is connected to the voltage detector input (Figure 32), taking a CMOS active "L"

product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)

causes a voltage drop equal to [feed-through current]  [input resistance] across the resistor. When the input

voltage drops below the detection voltage (V_DET) as a result, the output voltage goes to "L". In this status, the

feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The

feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces

oscillation.

V_DD

R_A

V_IN

VDD

OUT

MR

CD

VSS

R_B

(CMOS output product)

GND

Figure 32 Example for Bad Implementation Due to Detection Voltage Change

24

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Precautions

 Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic

protection circuit.

 In CMOS output product of the S-1003 Series, the feed-through current flows at the detection and the release. If the

input impedance is high, oscillation may occur due to the voltage drop by the feed-through current when releasing.

 In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power

supply voltage (V_DD) is slow near the detection voltage.

 When designing for mass production using an application circuit described herein, the product deviation and

temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any

responsibility for patent infringements related to products using the circuits described herein.

 ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by

products including this IC of patents owned by a third party.

 As seen in Figure 33, when connecting an input resistance (R_A) in Nch open-drain output product of the S-1003

Series, R_Ashould be 100 k or less to prevent oscillation. Moreover, note that the hysteresis width may be larger

as the following equation.

Maximum hysteresis width = V_HYSR_A 20 A

 When using the manual reset function, refer to "2. 4 When connecting resistance (R_A) between power supply

voltage (V_DD) and VDD pin" in " Operation" to set the constant.

V_DD

R_A

(R_A 100 k)

V_IN

VDD

MR

VSS

OUT

CD

(Nch open-drain output product)

Set to V_INor GND (MR pin non-active)

GND

Figure 33

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

25

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

 Characteristics (Typical Data)

1. Detection voltage (V_DET) vs. Temperature (Ta)

S-1003CA12

S-1003CA24

1.40

2.60

+VDET

−VDET

1.30

1.20

1.10

1.00

2.50

2.40

2.30

2.20

+VDET

−VDET

−

40

−

25

0

25

Ta [C]

50

75 85

−

40

−

25

0

25

50

75 85

Ta [C]

S-1003CA50

5.40

+VDET

5.20

5.00

4.80

4.60

−VDET

−

40

−

25

0

25

Ta [C]

50

75 85

2. Hysteresis width (V_HYS) vs. Temperature (Ta)

S-1003CA12

S-1003CA24

7

6

5

4

3

6

5

4

3

−

40

−

25

0

25

50

75 85

−

40

−

25

0

25

50

75 85

Ta [C]

S-1003CA50

7

6

5

4

3

−

40

−

25

0

25

50

75 85

Ta [C]

26

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

3. Current consumption (I_SS) vs. Input voltage (V_DD)

S-1003CA12

Ta = 25°C

S-1003CA24

Ta = 25°C

1.50

1.25

1.00

0.75

0.50

0.25

1.25

1.00

0.75

0.50

0.25

0

2

4

6

8

10

2

4

6

8

10

VDD [V]

S-1003CA50

Ta = 25°C

1.50

1.25

1.00

0.75

0.50

0.25

0

2

4

6

8

10

VDD [V]

4. Current consumption (I_SS) vs. Temperature (Ta)

S-1003NA12

V

_DD= V_DET(S) 1.0 V

S-1003NA24

V_DD= V_DET(S) 1.0 V

1.00

0.75

0.50

0.25

0

0.75

0.50

0.25

0

−

40

−

25

0

25

Ta [C]

50

75 85

−

40

−

25

0

25

Ta [C]

50

75 85

S-1003NA50

V_DD= V_DET(S) 1.0 V

1.00

0.75

0.50

0.25

0

−

40

−

25

0

25

Ta [C]

50

75 85

27

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

5. Nch transistor output current (I_OUT

)

vs. V_DS

6. Pch transistor output current (I_OUT

)

vs. V_DS

S-1003NA12

Ta = 25°C, MR pin active

S-1003CA12

Ta = 25°C

20.0

17.5

15.0

12.5

10.0

7.5

5.0

2.5

0

40.0

V

DD = 6.00 V

V

DD = 8.4 V

30.0

20.0

10.0

V

DD = 4.80 V

V

DD = 7.2 V

DD = 6.0 V

DD = 4.8 V

DD = 3.6 V

V

DD = 3.60 V

V

DD = 2.40 V

V

DD = 1.20 V

V

DD = 2.4 V

DD = 0.95 V

0

1.0 2.0 3.0 4.0 5.0 6.0 7.0

2.0

4.0

6.0

8.0

10.0

V

DS [V]

VDS [V]

7. Nch transistor output current (I_OUT

Input voltage (V_DD)

)

vs.

8. Pch transistor output current (I_OUT

Input voltage (V_DD)

) vs.

S-1003NA12

V_DS= 0.5 V, MR pin active

S-1003CA12

V_DS= 0.5 V

4.0

5.0

Ta = −40°C

4.0

3.0

2.0

1.0

3.0

2.0

1.0

Ta = +25°C

Ta = +85°C

Ta = +25°C

Ta = +85°C

0

2.0

4.0

6.0

8.0

10.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

VDD [V]

Remark V_DS: Drain-to-source voltage of the output transistor

28

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

9. Minimum operation voltage (V_OUT) vs. Input voltage (V_DD)

S-1003NA12

Pull-up to V_DD

S-1003NA24

Pull-up to V_DD

Pull-up resistance: 100 k

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3.0

2.5

2.0

1.5

1.0

0.5

Ta = −40°C

Ta = +25°C

Ta = −40°C

Ta = +25°C

Ta = +85°C

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

0.4 0.8 1.2 1.6 2.0 2.4 2.8

V

DD [V]

VDD [V]

S-1003NA50

Pull-up to V_DD

Pull-up resistance: 100 k

6.0

5.0

4.0

3.0

2.0

1.0

Ta = −40°C

Ta = +25°C

Ta = +85°C

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD [V]

S-1003NA12

Pull-up to 10 V

Pull-up resistance: 100 k

S-1003NA24

Pull-up to 10 V

Pull-up resistance: 100 k

12.0

10.0

8.0

12.0

10.0

8.0

Ta = −40°C

Ta = +25°C

Ta = +85°C

Ta = +25°C

Ta = +85°C

6.0

4.0

2.0

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

0.4 0.8 1.2 1.6 2.0 2.4 2.8

V

DD [V]

VDD [V]

S-1003NA50

Pull-up to 10 V

Pull-up resistance: 100 k

12.0

10.0

8.0

Ta = −40°C

Ta = +25°C

Ta = +85°C

6.0

4.0

2.0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD [V]

29

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

10. Dynamic response vs. Output pin capacitance (C_OUT) (CD pin; open)

S-1003CA12

S-1003CA24

1

t

PLH

0.1

0.01

t

PLH

0.1

0.01

t

PHL

t

PHL

0.001

0.00001 0.0001

0.001

0.01

0.1

0.00001 0.0001

0.001

0.01

0.1

Output pin capacitance [μF]

S-1003CA50

1

t

PLH

0.1

0.01

t

PHL

0.001

0.00001 0.0001

0.001

0.01

Output pin capacitance [μF]

S-1003NA12

S-1003NA24

100

10

1

10

1

t

PLH

PHL

t

PLH

PHL

0.1

0.01

t

0.001

0.00001 0.0001

0.001

0.01

0.00001 0.0001

0.001

0.01

0.1

Output pin capacitance [μF]

S-1003NA50

100

10

1

t

PLH

PHL

0.1

0.01

t

0.001

0.00001 0.0001

0.001

0.01

Output pin capacitance [μF]

30

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

1 s

*1

V_IH

R^*1

Input voltage

V_DD

100 k

VDD

MR

VSS

*2



OUT

CD

V_IL

t_PHL

t_PLH

*1

V

V_DD1

V_DD^*3 90%

*3

C_OUT



*2

V_DD

V

Output voltage

V_DD^*3 10%

*1. R and V_DD1are unnecessary for CMOS output

product.

*1. V_IH= 10 V

*2. Set to V_DDor GND (MR pin non-active).

*2. V_IL= 0.95 V

*3. CMOS output product: V_DD

Nch open-drain product: V_DD1

Figure 34 Test Condition of Response Time

Figure 35 Test Circuit of Response Time

Caution 1. The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

2. When the CD pin is open, a double pulse may appear at release.

To avoid the double pulse, attach a 100 pF or more capacitor to the CD pin.

Response time when detecting (t_PHL) is not affected by CD pin capacitance. Besides, response

time when releasing (t_PLH) can set the delay time by attaching the CD pin.

Refer to "11. Delay time (t_D) vs. CD pin capacitance (C_D) (Without output pin capacitance)" for

details.

11. Delay time (t_D) vs. CD pin capacitance (C_D) (Without output pin capacitance)

S-1003NA12

Ta = 25°C

S-1003NA24

Ta = 25°C

10000

1000

100

10

1000

100

10

1

0.1

0.01

0.1

1

10

[nF]

100

1000

0.1

1

10

[nF]

100

1000

C

D

C

D

S-1003NA50

Ta = 25°C

10000

1000

100

10

1

0.1

0.01

0.1

1

10

[nF]

100

1000

C

D

31

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

12. Delay time (t_D) vs. Temperature (Ta)

S-1003NA12

S-1003NA24

C_D= 4.7 nF, V_DD= 0.95 V  V_DET(S) 1.0 V

12

11

10

9

12

11

10

9

8

−

40

−

25

0

25

50

75 85

−

40

−

25

0

25

50

75 85

Ta [C]

S-1003NA50

C_D= 4.7 nF, V_DD= 0.95 V  V_DET(S) 1.0 V

12

11

10

9

8

−

40

−

25

0

25

50

75 85

Ta [C]

1 s

*1

V_IH

R^*1

V_DD

100 k

VDD

MR

VSS

*2

Input voltage

OUT

CD



V

*2

V_IL

t_D



V

C_D

V_DD 90%

Output voltage

V_SS

*1. R is unnecessary for CMOS output product.

*2. Set to V_DDor GND (MR pin non-active).

*1.

V_IH= V_DET(S)1.0 V

*2. V_IL= 0.95 V

Figure 36 Test Condition for Delay Time

Figure 37 Test Circuit for Delay Time

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

32

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_03

S-1003 Series

 Application Circuit Examples

1. Microcomputer reset circuits

In microcomputers, when the power supply voltage is lower than the guaranteed operation voltage, an unspecified

operation may be performed or the contents of the memory register may be lost. When power supply voltage

returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may

malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched

off or lowered.

Using the S-1003 Series which has the low operation voltage, a high accuracy detection voltage and hysteresis,

reset circuits can be easily constructed as seen in Figure 38 and Figure 39.

V_DD

V_DD1

V_DD

VDD

MR

VSS CD

VDD

OUT

Microcomputer

OUT

CD

MR

*1

Microcomputer

*1

VSS

GND

*1. Set to V_DDor GND (MR pin non-active).

Figure 38 Example of Reset Circuit

(CMOS Output Product)

Figure 39 Example of Reset Circuit

(Nch Open-drain Output Product)

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

33

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_03

2. Change of detection voltage (Nch open-drain output product only)

If there is not a product with a specified detection voltage value in the S-1003N Series, the detection voltage can be

changed by using a resistance divider or a diode, as seen in Figure 40 and Figure 41.

In Figure 40, hysteresis width also changes.

V_DD

V_f1

R

*1

R_A

100 k

V_IN

(R_A 100 k)

VDD

MR

VSS

VDD

MR

VSS

OUT

CD

OUT

CD

*1

(Nch open-drain

output product)

R_B

(Nch open-drain

output product)

*2

GND

R_A R_B

Detection voltage = V_f1 (V_DET

)

Detection voltage =

Hysteresis width =

 V_DET

 V_HYS

R_B

*1. Set to V_INor GND (MR pin non-active).

R_A R_B

R_B

*1. R_Ashould be 100 k or less to prevent oscillation.

*2. Set to V_INor GND (MR pin non-active).

Caution If R_Aand R_Bare large, the hysteresis width

may also be larger than the value given by

the above equation due to the feed-through

current.

Figure 40

Figure 41

Caution 1. The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

2. Note that the hysteresis width may be larger as the following equation shows when using the

above connections. Perform thorough evaluation using the actual application to set the

constant.

R_A R_B

Maximum hysteresis width =

 V_HYSR_A 20 A

R_B

3. When using the manual reset function, refer to "2. 4 When connecting resistance (R_A)

between power supply voltage (V_DD) and VDD pin" in " Operation" to set the constant.

34

2.9±0.2

1.9±0.2

4

5

+0.1

-0.06

1

2

3

0.16

0.95±0.1

0.4±0.1

No. MP005-A-P-SD-1.3

TITLE

SOT235-A-PKG Dimensions

MP005-A-P-SD-1.3

No.

ANGLE

UNIT

mm

ABLIC Inc.

4.0±0.1(10 pitches:40.0±0.2)

+0.1

-0

2.0±0.05

0.25±0.1

ø1.5

+0.2

-0

4.0±0.1

ø1.0

1.4±0.2

3.2±0.2

3

4

2 1

5

Feed direction

No. MP005-A-C-SD-2.1

TITLE

SOT235-A-Carrier Tape

MP005-A-C-SD-2.1

No.

ANGLE

UNIT

mm

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

No. MP005-A-R-SD-1.1

TITLE

SOT235-A-Reel

MP005-A-R-SD-1.1

No.

ANGLE

UNIT

QTY.

3,000

mm

ABLIC Inc.

1.57±0.03

6

5

4

+0.05

-0.02

0.08

1

2

3

0.5

0.48±0.02

0.2±0.05

No. PG006-A-P-SD-2.1

SNT-6A-A-PKG Dimensions

PG006-A-P-SD-2.1

TITLE

No.

ANGLE

UNIT

mm

ABLIC Inc.

+0.1

-0

ø1.5

4.0±0.1

2.0±0.05

0.25±0.05

+0.1

ø0.5

-0

4.0±0.1

0.65±0.05

1.85±0.05

3

2

5

1

6

4

Feed direction

No. PG006-A-C-SD-2.0

TITLE

SNT-6A-A-Carrier Tape

PG006-A-C-SD-2.0

No.

ANGLE

UNIT

mm

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

No. PG006-A-R-SD-1.0

SNT-6A-A-Reel

TITLE

No.

PG006-A-R-SD-1.0

ANGLE

UNIT

5,000

QTY.

mm

ABLIC Inc.

0.52

2

1.36

0.52

1

0.3

0.2

1.

2.

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

0.03 mm

SNT

1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).

2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).

Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.

2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm

or less from the land pattern surface.

3. Match the mask aperture size and aperture position with the land pattern.

4. Refer to "SNT Package User's Guide" for details.

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

1.

2.

SNT-6A-A

-Land Recommendation

TITLE

No. PG006-A-L-SD-4.1

No.

PG006-A-L-SD-4.1

ANGLE

UNIT

mm

ABLIC Inc.

Disclaimers (Handling Precautions)

1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application

circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.

2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of

any specific mass-production design.

ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein

(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use

of the information described herein.

3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.

4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,

operation voltage range and electrical characteristics, etc.

ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the

products outside their specified ranges.

5. When using the products, confirm their applications, and the laws and regulations of the region or country where they

are used and verify suitability, safety and other factors for the intended use.

6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related

laws, and follow the required procedures.

7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass

destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to

develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.

8. The products are not designed to be used as part of any device or equipment that may affect the human body, human

life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control

systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,

aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do

not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.

Especially, the products cannot be used for life support devices, devices implanted in the human body and devices

that directly affect human life, etc.

Prior consultation with our sales office is required when considering the above uses.

ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.

9. Semiconductor products may fail or malfunction with some probability.

The user of the products should therefore take responsibility to give thorough consideration to safety design including

redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or

death, fires and social damage, etc. that may ensue from the products' failure or malfunction.

The entire system must be sufficiently evaluated and applied on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the

product design by the customer depending on the intended use.

11. The products do not affect human health under normal use. However, they contain chemical substances and heavy

metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be

careful when handling these with the bare hands to prevent injuries, etc.

12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.

13. The information described herein contains copyright information and know-how of ABLIC Inc.

The information described herein does not convey any license under any intellectual property rights or any other

rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any

part of this document described herein for the purpose of disclosing it to a third-party without the express permission

of ABLIC Inc. is strictly prohibited.

14. For more details on the information described herein, contact our sales office.

2.2-2018.06

www.ablic.com


型号：	S-1003NB21I-M5T1U
厂家：	ABLIC
描述：	MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
文件：	总42页 (文件大小：660K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S-1003NB21I-M5T1U [ABLIC]

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