S-1004CA29I-I6T1U_技术文档

S-1004 Series

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

VOLTAGE DETECTOR WITH SENSE PIN

www.ablic.com

www.ablicinc.com

Rev.2.1_02

The S-1004 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed

internally with an accuracy of 1.0% (V_DET(S) 2.2 V). It operates with current consumption of 500 nA typ.

Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even

if the SENSE pin falls to 0 V.

The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy at Ta = 25C is

15%.

Two output forms Nch open-drain output and CMOS output are available.

 Features

 Detection voltage:

 Detection voltage accuracy:

1.0 V to 5.0 V (0.1 V step)

1.0% (2.2 V  V_DET(S) 5.0 V)

22 mV (1.0 V  V_DET(S) 2.2 V)

500 nA typ.

0.95 V to 10.0 V

5%  2%

 Current consumption:

 Operation voltage range:

 Hysteresis width:

 Release delay time accuracy:

 Output form:

15% (C_D= 4.7 nF, Ta = 25°C)

Nch open-drain output (Active "L")

CMOS output (Active "L")

Ta = 40°C to 85°C

 Operation temperature range:

 Lead-free (Sn 100%), halogen-free

 Applications

 Power supply monitor for microcomputer and reset for CPU

 Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance

 Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone

 Packages

 SOT-23-5

 SNT-6A

1

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Block Diagrams

1. S-1004 Series NA / NB type (Nch open-drain output)

SENSE

Function

Status

Output logic Active "L"

VDD



Delay

*1

circuit

*1

OUT



*1

V_REF

*1

VSS

CD

*1. Parasitic diode

Figure 1

2. S-1004 Series CA / CB type (CMOS output)

SENSE

Function

Status

Output logic Active "L"

VDD

*1



Delay

*1

circuit

*1



OUT

*1

V_REF

*1

VSS

CD

*1. Parasitic diode

Figure 2

2

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

 Product Name Structure

Users can select the output form and detection voltage value for the S-1004 Series.

Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding

the product types, "3. Packages" regarding the package drawings and "4. Product name list" regarding details of

product name.

1. Product name

S-1004

x

xx

I

-

xxxx

U

Environmental code

U:

Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specifications^*1

M5T1: SOT-23-5, Tape

I6T1: SNT-6A, Tape

Operation temperature

I:

Ta = 40C to 85C

Detection voltage value

10 to 50

(e.g., when the detection voltage is 1.0 V, it is expressed as 10.)

Pin configuration^*2

A, B

Output form^*3

N:

C:

Nch open-drain output (Active "L")^*4

CMOS output (Active "L")^*4

*1. Refer to the tape drawing.

*2. Refer to " Pin Configurations".

*3. Refer to "2. Function list of product types".

*4. If you request the product with output logic active "H", contact our sales office.

2. Function list of product types

Table 1

Product Type

Output Form

Output Logic

Active "L"

Pin Configuration

Package

SOT-23-5, SNT-6A

SOT-23-5

NA

NB

CA

CB

A

B

A

B

Nch open-drain output

Active "L"

SOT-23-5, SNT-6A

SOT-23-5

CMOS output

3. Packages

Table 2 Package Drawing Codes

Package Name

Dimension

Tape

Reel

Land

SOT-23-5

SNT-6A

MP005-A-P-SD

PG006-A-P-SD

MP005-A-C-SD

PG006-A-C-SD

MP005-A-R-SD

PG006-A-R-SD



PG006-A-L-SD

3

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

4. Product name list

4. 1 S-1004 Series NA type

Output form: Nch open-drain output (Active "L")

Table 3

Detection Voltage

1.0 V  22 mV

1.1 V  22 mV

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

SOT-23-5

SNT-6A

S-1004NA10I-M5T1U

S-1004NA11I-M5T1U

S-1004NA12I-M5T1U

S-1004NA13I-M5T1U

S-1004NA14I-M5T1U

S-1004NA15I-M5T1U

S-1004NA16I-M5T1U

S-1004NA17I-M5T1U

S-1004NA18I-M5T1U

S-1004NA19I-M5T1U

S-1004NA20I-M5T1U

S-1004NA21I-M5T1U

S-1004NA22I-M5T1U

S-1004NA23I-M5T1U

S-1004NA24I-M5T1U

S-1004NA25I-M5T1U

S-1004NA26I-M5T1U

S-1004NA27I-M5T1U

S-1004NA28I-M5T1U

S-1004NA29I-M5T1U

S-1004NA30I-M5T1U

S-1004NA31I-M5T1U

S-1004NA32I-M5T1U

S-1004NA33I-M5T1U

S-1004NA34I-M5T1U

S-1004NA35I-M5T1U

S-1004NA36I-M5T1U

S-1004NA37I-M5T1U

S-1004NA38I-M5T1U

S-1004NA39I-M5T1U

S-1004NA40I-M5T1U

S-1004NA41I-M5T1U

S-1004NA42I-M5T1U

S-1004NA43I-M5T1U

S-1004NA44I-M5T1U

S-1004NA45I-M5T1U

S-1004NA46I-M5T1U

S-1004NA47I-M5T1U

S-1004NA48I-M5T1U

S-1004NA49I-M5T1U

S-1004NA50I-M5T1U

S-1004NA10I-I6T1U

S-1004NA11I-I6T1U

S-1004NA12I-I6T1U

S-1004NA13I-I6T1U

S-1004NA14I-I6T1U

S-1004NA15I-I6T1U

S-1004NA16I-I6T1U

S-1004NA17I-I6T1U

S-1004NA18I-I6T1U

S-1004NA19I-I6T1U

S-1004NA20I-I6T1U

S-1004NA21I-I6T1U

S-1004NA22I-I6T1U

S-1004NA23I-I6T1U

S-1004NA24I-I6T1U

S-1004NA25I-I6T1U

S-1004NA26I-I6T1U

S-1004NA27I-I6T1U

S-1004NA28I-I6T1U

S-1004NA29I-I6T1U

S-1004NA30I-I6T1U

S-1004NA31I-I6T1U

S-1004NA32I-I6T1U

S-1004NA33I-I6T1U

S-1004NA34I-I6T1U

S-1004NA35I-I6T1U

S-1004NA36I-I6T1U

S-1004NA37I-I6T1U

S-1004NA38I-I6T1U

S-1004NA39I-I6T1U

S-1004NA40I-I6T1U

S-1004NA41I-I6T1U

S-1004NA42I-I6T1U

S-1004NA43I-I6T1U

S-1004NA44I-I6T1U

S-1004NA45I-I6T1U

S-1004NA46I-I6T1U

S-1004NA47I-I6T1U

S-1004NA48I-I6T1U

S-1004NA49I-I6T1U

S-1004NA50I-I6T1U

4

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

4. 2 S-1004 Series NB type

Output form: Nch open-drain output (Active "L")

Table 4

Detection Voltage

1.0 V  22 mV

1.1 V  22 mV

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

SOT-23-5

S-1004NB10I-M5T1U

S-1004NB11I-M5T1U

S-1004NB12I-M5T1U

S-1004NB13I-M5T1U

S-1004NB14I-M5T1U

S-1004NB15I-M5T1U

S-1004NB16I-M5T1U

S-1004NB17I-M5T1U

S-1004NB18I-M5T1U

S-1004NB19I-M5T1U

S-1004NB20I-M5T1U

S-1004NB21I-M5T1U

S-1004NB22I-M5T1U

S-1004NB23I-M5T1U

S-1004NB24I-M5T1U

S-1004NB25I-M5T1U

S-1004NB26I-M5T1U

S-1004NB27I-M5T1U

S-1004NB28I-M5T1U

S-1004NB29I-M5T1U

S-1004NB30I-M5T1U

S-1004NB31I-M5T1U

S-1004NB32I-M5T1U

S-1004NB33I-M5T1U

S-1004NB34I-M5T1U

S-1004NB35I-M5T1U

S-1004NB36I-M5T1U

S-1004NB37I-M5T1U

S-1004NB38I-M5T1U

S-1004NB39I-M5T1U

S-1004NB40I-M5T1U

S-1004NB41I-M5T1U

S-1004NB42I-M5T1U

S-1004NB43I-M5T1U

S-1004NB44I-M5T1U

S-1004NB45I-M5T1U

S-1004NB46I-M5T1U

S-1004NB47I-M5T1U

S-1004NB48I-M5T1U

S-1004NB49I-M5T1U

S-1004NB50I-M5T1U

5

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

4. 3 S-1004 Series CA type

Output form: CMOS output (Active "L")

Table 5

Detection Voltage

1.0 V  22 mV

1.1 V  22 mV

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

SOT-23-5

SNT-6A

S-1004CA10I-M5T1U

S-1004CA11I-M5T1U

S-1004CA12I-M5T1U

S-1004CA13I-M5T1U

S-1004CA14I-M5T1U

S-1004CA15I-M5T1U

S-1004CA16I-M5T1U

S-1004CA17I-M5T1U

S-1004CA18I-M5T1U

S-1004CA19I-M5T1U

S-1004CA20I-M5T1U

S-1004CA21I-M5T1U

S-1004CA22I-M5T1U

S-1004CA23I-M5T1U

S-1004CA24I-M5T1U

S-1004CA25I-M5T1U

S-1004CA26I-M5T1U

S-1004CA27I-M5T1U

S-1004CA28I-M5T1U

S-1004CA29I-M5T1U

S-1004CA30I-M5T1U

S-1004CA31I-M5T1U

S-1004CA32I-M5T1U

S-1004CA33I-M5T1U

S-1004CA34I-M5T1U

S-1004CA35I-M5T1U

S-1004CA36I-M5T1U

S-1004CA37I-M5T1U

S-1004CA38I-M5T1U

S-1004CA39I-M5T1U

S-1004CA40I-M5T1U

S-1004CA41I-M5T1U

S-1004CA42I-M5T1U

S-1004CA43I-M5T1U

S-1004CA44I-M5T1U

S-1004CA45I-M5T1U

S-1004CA46I-M5T1U

S-1004CA47I-M5T1U

S-1004CA48I-M5T1U

S-1004CA49I-M5T1U

S-1004CA50I-M5T1U

S-1004CA10I-I6T1U

S-1004CA11I-I6T1U

S-1004CA12I-I6T1U

S-1004CA13I-I6T1U

S-1004CA14I-I6T1U

S-1004CA15I-I6T1U

S-1004CA16I-I6T1U

S-1004CA17I-I6T1U

S-1004CA18I-I6T1U

S-1004CA19I-I6T1U

S-1004CA20I-I6T1U

S-1004CA21I-I6T1U

S-1004CA22I-I6T1U

S-1004CA23I-I6T1U

S-1004CA24I-I6T1U

S-1004CA25I-I6T1U

S-1004CA26I-I6T1U

S-1004CA27I-I6T1U

S-1004CA28I-I6T1U

S-1004CA29I-I6T1U

S-1004CA30I-I6T1U

S-1004CA31I-I6T1U

S-1004CA32I-I6T1U

S-1004CA33I-I6T1U

S-1004CA34I-I6T1U

S-1004CA35I-I6T1U

S-1004CA36I-I6T1U

S-1004CA37I-I6T1U

S-1004CA38I-I6T1U

S-1004CA39I-I6T1U

S-1004CA40I-I6T1U

S-1004CA41I-I6T1U

S-1004CA42I-I6T1U

S-1004CA43I-I6T1U

S-1004CA44I-I6T1U

S-1004CA45I-I6T1U

S-1004CA46I-I6T1U

S-1004CA47I-I6T1U

S-1004CA48I-I6T1U

S-1004CA49I-I6T1U

S-1004CA50I-I6T1U

6

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

4. 4 S-1004 Series CB type

Output form: CMOS output (Active "L")

Table 6

Detection Voltage

SOT-23-5

1.0 V  22 mV

1.1 V  22 mV

1.2 V  22 mV

1.3 V  22 mV

1.4 V  22 mV

1.5 V  22 mV

1.6 V  22 mV

1.7 V  22 mV

1.8 V  22 mV

1.9 V  22 mV

2.0 V  22 mV

2.1 V  22 mV

2.2 V  1.0%

2.3 V  1.0%

2.4 V  1.0%

2.5 V  1.0%

2.6 V  1.0%

2.7 V  1.0%

2.8 V  1.0%

2.9 V  1.0%

3.0 V  1.0%

3.1 V  1.0%

3.2 V  1.0%

3.3 V  1.0%

3.4 V  1.0%

3.5 V  1.0%

3.6 V  1.0%

3.7 V  1.0%

3.8 V  1.0%

3.9 V  1.0%

4.0 V  1.0%

4.1 V  1.0%

4.2 V  1.0%

4.3 V  1.0%

4.4 V  1.0%

4.5 V  1.0%

4.6 V  1.0%

4.7 V  1.0%

4.8 V  1.0%

4.9 V  1.0%

5.0 V  1.0%

S-1004CB10I-M5T1U

S-1004CB11I-M5T1U

S-1004CB12I-M5T1U

S-1004CB13I-M5T1U

S-1004CB14I-M5T1U

S-1004CB15I-M5T1U

S-1004CB16I-M5T1U

S-1004CB17I-M5T1U

S-1004CB18I-M5T1U

S-1004CB19I-M5T1U

S-1004CB20I-M5T1U

S-1004CB21I-M5T1U

S-1004CB22I-M5T1U

S-1004CB23I-M5T1U

S-1004CB24I-M5T1U

S-1004CB25I-M5T1U

S-1004CB26I-M5T1U

S-1004CB27I-M5T1U

S-1004CB28I-M5T1U

S-1004CB29I-M5T1U

S-1004CB30I-M5T1U

S-1004CB31I-M5T1U

S-1004CB32I-M5T1U

S-1004CB33I-M5T1U

S-1004CB34I-M5T1U

S-1004CB35I-M5T1U

S-1004CB36I-M5T1U

S-1004CB37I-M5T1U

S-1004CB38I-M5T1U

S-1004CB39I-M5T1U

S-1004CB40I-M5T1U

S-1004CB41I-M5T1U

S-1004CB42I-M5T1U

S-1004CB43I-M5T1U

S-1004CB44I-M5T1U

S-1004CB45I-M5T1U

S-1004CB46I-M5T1U

S-1004CB47I-M5T1U

S-1004CB48I-M5T1U

S-1004CB49I-M5T1U

S-1004CB50I-M5T1U

7

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Pin Configurations

1. S-1004 Series NA / CA type

1. 1 SOT-23-5

Top view

Table 7 Pin Configuration A

Symbol Description

5

4

Pin No.

1

2

3

4

5

OUT

VDD

VSS

Voltage detection output pin

Power supply pin

GND pin

1

2

3

CD

Connection pin for delay capacitor

Detection voltage input pin

SENSE

Figure 3

1. 2 SNT-6A

Table 8 Pin Configuration A

Top view

Pin No.

Symbol

Description

Voltage detection output pin

Power supply pin

1

2

3

6

5

4

1

2

3

4

5

6

OUT

VDD

SENSE

CD

NC^*1

VSS

Detection voltage input pin

Connection pin for delay capacitor

No connection

Figure 4

GND pin

*1. The NC pin is electrically open.

The NC pin can be connected to the VDD pin or the VSS pin.

2. S-1004 Series NB / CB type

2. 1 SOT-23-5

Top view

Table 9 Pin Configuration B

5

4

Pin No.

Symbol

OUT

Description

Voltage detection output pin

GND pin

1

2

3

4

5

VSS

VDD

SENSE

CD

Power supply pin

1

2

3

Detection voltage input pin

Connection pin for delay capacitor

Figure 5

8

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

 Absolute Maximum Ratings

Table 10

(Ta = 25°C unless otherwise specified)

Item

Power supply voltage

CD pin input voltage

Symbol

Absolute Maximum Rating

12.0

Unit

V

V_DDV_SS

V_CD

V_SS 0.3 to V_DD 0.3

V_SS 0.3 to 12.0

V_SS 0.3 to V_DD 0.3

50

V

SENSE pin input voltage

V_SENSE

V

Nch open-drain output product

V

Output voltage

Output current

Power dissipation

V_OUT

I_OUT

P_D

CMOS output product

V

mA

mW

°C

SOT-23-5

SNT-6A

600^*1

400^*1

Operation ambient temperature

Storage temperature

T_opr

T_stg

40 to 85

40 to 125

*1. When mounted on board

[Mounted board]

(1) Board size: 114.3 mm  76.2 mm  t1.6 mm

(2) Name: JEDEC STANDARD51-7

Caution The absolute maximum ratings are rated values exceeding which the product could suffer

physical damage. These values must therefore not be exceeded under any conditions.

700

600

SOT-23-5

500

400

300

200

100

0

SNT-6A

100

150

50

0

Ambient Temperature (Ta) [C]

Figure 6 Power Dissipation of Package (When Mounted on Board)

9

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Electrical Characteristics

1. Nch open-drain output product

Table 11

(Ta = 25°C unless otherwise specified)

Test

Circuit

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

V

V_DET(S)

 0.022

V_DET(S)

 0.99

V_DET(S)

 0.022

V_DET(S)

 1.01

1.0 V  V_DET(S) 2.2 V

V_DET(S)

1

Detection voltage^*1V_DET

0.95 V  V_DD 10.0 V

2.2 V  V_DET(S) 5.0 V

V_DET(S)

V_DET

V

1

2

V_DET

Hysteresis width

V_HYS

I_SS



V

 0.03  0.05  0.07

Current

V_DD= 10.0 V, V_SENSE= V_DET(S) 1.0 V



0.50

0.90

A

consumption^*2

Operation voltage V_DD



V

0.95

0.59

0.73

1.47

1.86



10.0

V

1

3

_DD= 0.95 V

1.00

1.33

2.39

2.50



mA

Output transistor

Nch

V_DD= 1.2 V

V_DD= 2.4 V

V_DD= 4.8 V

Output current

I_OUT

V_DS^*3= 0.5 V

V_SENSE= 0.0 V

Output transistor

Nch

Leakage current

I_LEAK



0.08

A

3

1

V_DD= 10.0 V, V_DS^*3= 10.0 V, V_SENSE= 10.0 V

Detection voltage

temperature

coefficient^*4

Detection

V_DET

Ta V_DET

ppm/C

Ta = 40°C to 85°C

100

350

t_DET

V_DD= 5.0 V



40



s

4

delay time^*5

Release

t_RESET

R_SENSE

V_DD= V_DET(S) 1.0 V, C_D= 4.7 nF

10.79

12.69

14.59

ms

delay time^*6

SENSE pin

resistance

1.0 V  V_DET(S) 1.2 V

1.2 V  V_DET(S) 5.0 V

5.0

6.0

19.0

30.0

42.0

98.0

M

2

*1. V_DET: Actual detection voltage value, V_DET(S): Set detection voltage value (the center value of the detection voltage

range in Table 3 or Table 4)

*2. The current flowing through the SENSE pin resistance is not included.

*3.

V_DS: Drain-to-source voltage of the output transistor

*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.

V_DET

Ta

V_DET

Ta  V_DET

mV/°C ^*1= V_DET(S)(typ.) V ^*2

ppm/°C ^*3 1000

]

[

]

[ ]

[

*1. Temperature change of the detection voltage

*2. Set detection voltage

*3. Detection voltage temperature coefficient

*5. The time period from when the pulse voltage of 6.0 V  V_DET(S) 2.0 V or 0 V is applied to the SENSE pin to when

V_OUTreaches V_DD/ 2, after the output pin is pulled up to 5.0 V by the resistance of 470 k.

*6. The time period from when the pulse voltage of 0.95 V  10.0 V is applied to the SENSE pin to when V_OUTreaches

V_DD 90%, after the output pin is pulled up to V_DDby the resistance of 100 k.

10

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

2. CMOS output product

Table 12

(Ta = 25°C unless otherwise specified)

Test

Circuit

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

V

V_DET(S)

 0.022

V_DET(S)

 0.99

V_DET(S)

 0.022

V_DET(S)

 1.01

1.0 V  V_DET(S) 2.2 V

V_DET(S)

1

Detection voltage^*1V_DET

0.95 V  V_DD 10.0 V

2.2 V  V_DET(S) 5.0 V

V_DET(S)

V_DET

V

1

2

V_DET

Hysteresis width

V_HYS

I_SS



V

 0.03  0.05  0.07

Current

V_DD= 10.0 V, V_SENSE= V_DET(S) 1.0 V



0.50

0.90

A

consumption^*2

Operation voltage V_DD



0.95

0.59

0.73

1.47

1.86



10.0

V

1

3

V_DD= 0.95 V

V_DD= 1.2 V

V_DD= 2.4 V

V_DD= 4.8 V

1.00

1.33

2.39

2.50



mA

Output transistor

Nch

V_DS^*3= 0.5 V

V_SENSE= 0.0 V

Output current

I_OUT

Output transistor

Pch

V_DS^*3= 0.5 V

V_SENSE= 10.0 V

V

_DD= 4.8 V

_DD= 6.0 V

1.62

1.78

2.60

2.86



mA

5



Detection voltage

temperature

coefficient^*4

Detection

V_DET

Ta V_DET

1

ppm/C

Ta = 40°C to 85°C



100

350

t_DET

V_DD= 5.0 V



40



s

4

delay time^*5

Release

t_RESET

R_SENSE

V_DD= V_DET(S) 1.0 V, C_D= 4.7 nF

10.79

12.69

14.59

ms

delay time^*6

SENSE pin

resistance

1.0 V  V_DET(S) 1.2 V

1.2 V  V_DET(S) 5.0 V

5.0

6.0

19.0

30.0

42.0

98.0

M

2

*1. V_DET: Actual detection voltage value, V_DET(S): Set detection voltage value (the center value of the detection voltage

range in Table 5 or Table 6)

*2. The current flowing through the SENSE pin resistance is not included.

*3.

V_DS: Drain-to-source voltage of the output transistor

*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.

V_DET

Ta

V_DET

Ta  V_DET

mV/°C ^*1= V_DET(S)(typ.) V ^*2

ppm/°C ^*3 1000

]

[

]

[ ]

[

*1. Temperature change of the detection voltage

*2. Set detection voltage

*3. Detection voltage temperature coefficient

*5. The time period from when the pulse voltage of 6.0 V  V_DET(S) 2.0 V or 0 V is applied to the SENSE pin to when

_OUTreaches V_DD/ 2.

V

*6. The time period from when the pulse voltage of 0.95 V  10.0 V is applied to the SENSE pin to when V_OUTreaches

V_DD 90%.

11

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Test Circuits

R

VDD

100 k

V_DD

OUT

CD

OUT

CD

SENSE

VSS

SENSE

VSS





V

Figure 7 Test Circuit 1

(Nch open-drain output product)

Figure 8 Test Circuit 1

(CMOS output product)



A

VDD

V_DD



VDD

SENSE

VSS

V_DD

OUT

CD

V

A



V_DS

A

OUT

CD

SENSE

VSS



V

Figure 9 Test Circuit 2

Figure 10 Test Circuit 3

R

470 k or 100 k

VDD

V_DD

Oscilloscope

OUT

CD

OUT

CD

SENSE

VSS

SENSE

VSS

P.G.

Figure 11 Test Circuit 4

(Nch open-drain output product)

Figure 12 Test Circuit 4

(CMOS output product)

V_DS



V

VDD

V_DD





SENSE

VSS

V

OUT

CD

A

Figure 13 Test Circuit 5

12

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

 Standard Circuits

1. Nch open-drain output product

R

100 k

VDD

SENSE

OUT

CD

VSS

*1

C_D

*1. The delay capacitor (C_D) should be connected directly to the CD pin and the VSS pin.

Figure 14

2. CMOS output product

VDD

SENSE

OUT

CD

VSS

*1

C_D

*1. The delay capacitor (C_D) should be connected directly to the CD pin and the VSS pin.

Figure 15

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

13

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Explanation of Terms

1. Detection voltage (V_DET

)

The detection voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "L". The detection voltage

varies slightly among products of the same specification. The variation of detection voltage between the specified

minimum (V_DETmin.) and the maximum (V_DETmax.) is called the detection voltage range (Refer to Figure 16).

Example: In the S-1004Cx18, the detection voltage is either one in the range of 1.778 V  V_DET 1.822 V.

This means that some S-1004Cx18 have V_DET= 1.778 V and some have V_DET= 1.822 V.

2. Release voltage (V_DET

)

The release voltage is a voltage at which the output in Figure 18 or Figure 19 turns to "H". The release voltage

varies slightly among products of the same specification. The variation of release voltage between the specified

minimum (V_DETmin.) and the maximum (V_DETmax.) is called the release voltage range (Refer to Figure 17). The

range is calculated from the actual detection voltage (V_DET) of a product and is in the range of V_DET 1.03 

V_DET V_DET 1.07.

Example: For the S-1004Cx18, the release voltage is either one in the range of 1.832 V  V_DET 1.949 V.

This means that some S-1004Cx18 have V_DET= 1.832 V and some have V_DET= 1.949 V.

V_SENSE

Detection voltage

Release voltage

V_DETmax.

V_DETmax.

V_DETmin.

Release voltage

range

Detection voltage

range

V_DETmin.

V_SENSE

V_OUT

t_RESET

t_DET

Figure 16 Detection Voltage

Figure 17 Release Voltage

R

VDD

100 k

V_DD

OUT

CD

OUT

CD

SENSE

VSS

SENSE

VSS





V

Figure 18 Test Circuit of Detection Voltage

and Release Voltage

Figure 19 Test Circuit of Detection Voltage

and Release Voltage

(Nch open-drain output product)

(CMOS output product)

14

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

3. Hysteresis width (V_HYS

)

The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at

point B  the voltage at point A = V_HYSin "Figure 23 Timing Chart of S-1004 Series NA / NB Type" and "Figure

25 Timing Chart of S-1004 Series CA / CB Type"). Setting the hysteresis width between the detection voltage

and the release voltage, prevents malfunction caused by noise on the input voltage.

4. Release delay time (t_RESET

)

The release delay time is the time period from when the input voltage to the SENSE pin exceeds the release

voltage (V_DET) to when the output from the OUT pin inverts. The release delay time changes according to the

delay capacitor (C_D).

V_SENSE

V_DET

OUT

t_RESET

Figure 20 Release Delay Time

5. Feed-through current

The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release

of a voltage detector. The feed-through current is large in CMOS output product, small in Nch open-drain output

product.

6. Oscillation

In applications where an input resistor is connected (Figure 21), taking a CMOS output (active "L") product for

example, the feed-through current which is generated when the output goes from "L" to "H" (at the time of release)

causes a voltage drop equal to [feed-through current]  [input resistance]. Since the VDD pin and the SENSE pin

are shorted as in Figure 21, the SENSE pin voltage drops at the time of release. Then the SENSE pin voltage

drops below the detection voltage and the output goes from "H" to "L". In this status, the feed-through current stops

and its resultant voltage drop disappears, and the output goes from "L" to "H". The feed-through current is then

generated again, a voltage drop appears, and repeating the process finally induces oscillation.

V_DD

R_A

V_IN

VDD

OUT

SENSE

VSS

CD

R_B

(CMOS output product)

GND

Figure 21 Example for Bad Implementation Due to Detection Voltage Change

15

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Operation

1. Basic operation

1. 1 S-1004 Series NA / NB type

(1) When the power supply voltage (V_DD) is the minimum operation voltage or higher, and the SENSE pin voltage

(V_SENSE) is the release voltage (V_DET) or higher, the Nch transistor is turned off to output V_DD("H") when the

output is pulled up. Since the Nch transistor (N1) is turned off, the input voltage to the comparator is

(R_B R_C)  V_SENSE

.

R_A R_B R_C

(2) Even if V_SENSEdecreases to V_DETor lower, V_DDis output when V_SENSEis higher than the detection voltage

(V_DET).

When V_SENSEdecreases to V_DETor lower (point A in Figure 23), the Nch transistor is turned on. And then V_SS

("L") is output from the OUT pin after the elapse of the detection delay time (t_DET).

R_B V_SENSE

At this time, N1 is turned on, and the input voltage to the comparator is

.

R_A R_B

(3) Even if V_SENSEfurther decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is

stable when V_DDis minimum operation voltage or higher.

(4) Even if V_SENSEexceeds V_DET, V_SSis output when V_SENSEis lower than V_DET

.

(5) When V_SENSEincreases to V_DETor higher (point B in Figure 23), the Nch transistor is turned off. And then V_DD

is output from the OUT pin after the elapse of the release delay time (t_RESET) when the output is pulled up.

SENSE

VDD

R

100 k

R_A

V_DD

OUT





Delay

circuit

*1

V_SENSE

R_B

*1

V_REF



N1

Nch

V

*1

R_C

VSS

CD

C_D

*1. Parasitic diode

Figure 22 Operation of S-1004 Series NA / NB Type

(2) (3) (4) (5)

(1)

B

Hysteresis width

(V_HYS

Release voltage (V_DET

)

A

)

Detection voltage (V_DET

)

V_SENSE

Minimum operation voltage

V_SS

V_DD

V_SS

Output from OUT pin

t_DET

t_RESET

Figure 23 Timing Chart of S-1004 Series NA / NB Type

16

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

1. 2 S-1004 Series CA / CB type

(1) When the power supply voltage (V_DD) is the minimum operation voltage or higher, and the SENSE pin voltage

(V_SENSE) is the release voltage (V_DET) or higher, the Nch transistor is turned off and the Pch transistor is turned

on to output V_DD("H"). Since the Nch transistor (N1) is turned off, the input voltage to the comparator is

(R_B R_C)  V_SENSE

.

R_A R_B R_C

(2) Even if V_SENSEdecreases to V_DETor lower, V_DDis output when V_SENSEis higher than the detection voltage

(V_DET).

When V_SENSEdecreases to V_DETor lower (point A in Figure 25), the Nch transistor is turned on and the Pch

transistor is turned off. And then V_SS("L") is output from the OUT pin after the elapse of the detection delay time

(t_DET).

R_B V_SENSE

R_A R_B

At this time, N1 is turned on, and the input voltage to the comparator is

.

(3) Even if V_SENSEfurther decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is

stable when V_DDis minimum operation voltage or higher.

(4) Even if V_SENSEexceeds V_DET, V_SSis output when V_SENSEis lower than V_DET

.

(5) When V_SENSEincreases to V_DETor higher (point B in Figure 25), the Nch transistor is turned off and the Pch

transistor is turned on. And then V_DDis output from the OUT pin after the elapse of the release delay time

(t_RESET).

SENSE

VDD

Pch

*1

R_A

V_DD





OUT

Delay

circuit

*1

V_SENSE

R_B

*1

V_REF



N1

Nch

V

*1

R_C

VSS

CD

C_D

*1. Parasitic diode

Figure 24 Operation of S-1004 Series CA / CB Type

(2) (3) (4) (5)

(1)

B

Hysteresis width

(V_HYS

Release voltage (V_DET

)

A

)

Detection voltage (V_DET

)

V_SENSE

Minimum operation voltage

V_SS

V_DD

V_SS

Output from OUT pin

t_DET

t_RESET

Figure 25 Timing Chart of S-1004 Series CA / CB Type

17

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

2. SENSE pin

2. 1 Error when detection voltage is set externally

By connecting a node that was resistance-divided by the resistor (R_A) and the resistor (R_B) to the SENSE pin as

seen in Figure 26, the detection voltage can be set externally.

For conventional products without the SENSE pin, R_Acannot be too large since the resistance-divided node must

be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin when it goes

from detection to release, and if R_Ais large, problems such as oscillation or larger error in the hysteresis width may

occur.

In the S-1004 Series, R_Aand R_Bare easily made larger since the resistance-divided node can be connected to the

SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing through

the internal resistance (R_SENSE) that will occur.

Although R_SENSEin the S-1004 Series is large (5 M min.) to make the error small, R_Aand R_Bshould be selected

such that the error is within the allowable limits.

2. 2 Selection of R_Aand R_B

In Figure 26, the relation between the external setting detection voltage (V_DX) and the actual detection voltage

(V_DET) is ideally calculated by the equation below.

R_A

R_B

V_DX= V_DET



1 

··· (1)

(

)

However, in reality there is an error in the current flowing through R_SENSE

.

When considering this error, the relation between V_DXand V_DETis calculated as follows.

R_A

V_DX= V_DET

= V_DET



1 

(

)

R_B|| R_SENSE

R_A

_{1 }







R_B R_SENSE

R_B R_SENSE





R_A

R_B

R_A

= V_DET



1 



 V_DET

··· (2)

(

)

R_SENSE

R_A

R_SENSE

By using equations (1) and (2), the error is calculated as V_DET



.

The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).

R_A R_B

R_SENSE (R_A R_B)

R_A|| R_B

R_SENSE

 100 [%] =

 100 [%]

··· (3)

As seen in equation (3), the smaller the resistance values of R_Aand R_Bcompared to R_SENSE, the smaller the error

rate becomes.

Also, the relation between the external setting hysteresis width (V_HX) and the hysteresis width (V_HYS) is calculated

by equation below. Error due to R_SENSEalso occurs to the relation in a similar way to the detection voltage.

R_A

R_B

V_HX= V_HYS



1 

··· (4)

(

)

R_A

VDD

SENSE

R_SENSE

OUT

CD

V_DX

V_DET

R_B

VSS

Figure 26 Detection Voltage External Setting Circuit

Caution If R_Aand R_Bare large, the SENSE pin input impedance becomes higher and may cause a

malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS

pin.

18

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

2. 3 Power on sequence

Apply power in the order, the VDD pin then the SENSE pin.

As seen in Figure 27, when V_SENSE V_DET, the OUT pin output (V_OUT) rises and the S-1004 Series becomes the

release status (normal operation).

V_DD

V_DET

V_SENSE

t_RESET

V_OUT

Figure 27

Caution If power is applied in the order the SENSE pin then the VDD pin, an erroneous release may occur

even if V_SENSE V_DET

.

2. 4 Precautions when shorting between the VDD pin and the SENSE pin

2. 4. 1 Input resistor

Do not connect the input resistor (R_A) when shorting between the VDD pin and the SENSE pin.

A feed-through current flows through the VDD pin at the time of release. When connecting the circuit shown as

Figure 28, the feed-through current of the VDD pin flowing through R_Awill cause a drop in V_SENSEat the time of

release.

At that time, oscillation may occur if V_SENSE V_DET

.

R_A

VDD

VSS

OUT

CD

SENSE

V_DD

Figure 28

2. 4. 2 Parasitic resistance and parasitic capacitance

Due to the difference in parasitic resistance and parasitic capacitance of the VDD pin and the SENSE pin,

power may be applied to the SENSE pin first.

Note that an erroneous release may occur if this happens (refer to "2. 3 Power on sequence").

Caution In CMOS output product, make sure that the VDD pin input impedance does not become too

high, regardless of the above. Since a feed-through current is large, a malfunction may occur if

the VDD pin voltage changes greatly at the time of release.

19

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

2. 5 Malfunction when V_DDfalls

As seen in Figure 29, note that if the VDD pin voltage (V_DD) drops steeply below 1.2 V when V_DET V_SENSE

V_DET, erroneous detection may occur.



When V_{DD_Low} 1.2 V, erroneous detection does not occur.

When V_{DD_Low} 1.2 V, the more the V_DDfalling amplitude increases or the shorter the falling time becomes, the

easier the erroneous detection.

Perform thorough evaluation in actual application.

V_{DD_High}

V_DD

V_{DD_Low}(Voltage drops below 1.2 V.)

V_DET

V_SENSE

V_DET

V_OUTfalling influenced by V_DDfalling

(erroneous detection)

V_OUT

Figure 29

The S-1004Cx50 example in Figure 30 shows an example of erroneous detection boundary conditions.

12

10

8

6

4

2

0

Danger of erroneous

detection

0.1

1

10

100

1000

t

F

[s]

Figure 30

Remark Test conditions

Product name: S-1004Cx50

V_SENSEV_DET(S) 0.1 V

V_{DD_High}

V_{DD_Low}

:

VDD pin voltage before falling

VDD pin voltage after falling (0.95 V)

V_{DD_High} V_{DD_Low}

V_DD

:

t_F:

Falling time of V_DDfrom V_{DD_High} V_DD 10% to V_{DD_Low} V_DD 10%

V

DD_High

DD_High  VDD  10%

VDD

VDD_Low  VDD  10%

V

DD_Low

t

F

Figure 31

20

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

3. Delay circuit

The delay circuit has the function that adjusts the release delay time (t_RESET) from when the SENSE pin voltage

(V_SENSE) reaches release voltage (V_DET) to when the output from OUT pin inverts.

t_RESETis determined by the delay coefficient, the delay capacitor (C_D), and the release delay time when the CD pin

is open (t_RESET0), and calculated by the equation below.

t_RESET[ms] = Delay coefficient  C_D[nF]  t_RESET0[ms]

Table 13

Delay Coefficient

Operation

Temperature

Min.

1.78

2.30

2.68

Typ.

2.29

2.66

3.09

Max.

3.13

3.07

3.57

Ta = 85°C

Ta = 25°C

Ta = 40°C

Table 14

Release Delay Time when CD Pin is Open (t_RESET0

)

Operation

Temperature

Min.

Typ.

Max.

Ta = 85°C

Ta = 25°C

Ta = 40°C

0.020 ms

0.021 ms

0.024 ms

0.049 ms

0.059 ms

0.074 ms

0.130 ms

0.164 ms

0.202 ms

Caution 1. Mounted board layout should be made in such a way that no current flows into or flows from

the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be

provided.

2. There is no limit for the capacitance of C_Das long as the leakage current of the capacitor can

be ignored against the built-in constant current value (30 nA to 200 nA).

3. The detection delay time (t_DET) cannot be adjusted by C_D.

21

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

4. Other characteristics

4. 1 Temperature characteristics of detection voltage

The shaded area in Figure 32 shows the temperature characteristics of detection voltage in the operation

temperature range.

V_DET[V]

0.945 mV/°C

*1

V_DET25

0.945 mV/°C



40

25

85

Ta [°C]

*1. V_DET25is a detection voltage value at Ta = 25°C.

Figure 32 Temperature Characteristics of Detection Voltage (Example for V_DET= 2.7 V)

4. 2 Temperature characteristics of release voltage

V_DET

Ta

The temperature change

of the release voltage is calculated by using the temperature change

V_DET

Ta

of the detection voltage as follows:

V_DET

Ta

V_DET

V_DET

V_DET

Ta

=



The temperature change of the release voltage and the detection voltage has the same sign consequently.

4. 3 Temperature characteristics of hysteresis voltage

V_DET

Ta

V_DET

Ta

The temperature change of the hysteresis voltage is expressed as

follows:



and is calculated as

V_DET

Ta

V_DET

Ta

V_HYS

V_DET

V_DET

Ta



=



22

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

 Precautions

 Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic

protection circuit.

 In CMOS output product of the S-1004 Series, the feed-through current flows at the time of detection and release. If

the VDD pin input impedance is high, malfunction may occur due to the voltage drop by the feed-through current

when releasing.

 In CMOS output product, oscillation may occur if a pull-down resistor is connected and falling speed of the SENSE

pin voltage (V_SENSE) is slow near the detection voltage when the VDD pin and the SENSE pin are shorted.

 When designing for mass production using an application circuit described herein, the product deviation and

temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any

responsibility for patent infringements related to products using the circuits described herein.

 ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by

products including this IC of patents owned by a third party.

23

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

 Characteristics (Typical Data)

1. Detection voltage (V_DET), Release voltage (V_DET) vs. Temperature (Ta)

S-1004Cx10

V_DD= 5.0 V

S-1004Cx24

V_DD= 5.0 V

1.2

2.6

VDET

VDET

1.1

1.0

0.9

0.8

2.5

2.4

2.3

2.2

VDET

VDET

40



25

0

25

Ta [C]

50

75 85

40



25

0

25

50

75 85

Ta [C]

S-1004Cx50

V_DD= 5.0 V

5.4

VDET

5.2

5.0

4.8

4.6

VDET

40



25

0

25

Ta [C]

50

75 85

2. Hysteresis width (V_HYS) vs. Temperature (Ta)

S-1004Cx10

V

_DD= 5.0 V

S-1004Cx24

V_DD= 5.0 V

7.0

6.0

5.0

4.0

3.0

6.0

5.0

4.0

3.0

40

25

0

25

50

75 85

40



25

0

25

50

75 85

Ta [C]

S-1004Cx50

V

_DD= 5.0 V

7.0

6.0

5.0

4.0

3.0

40

25

0

25

50

75 85

Ta [C]

24

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

3. Detection voltage (V_DET) vs. Power supply voltage (V_DD)

S-1004Cx10

S-1004Cx24

1.030

2.430

2.420

2.410

2.400

2.390

2.380

2.370

1.020

1.010

1.000

0.990

0.980

Ta = 25C

40C

Ta = 85C

Ta =



Ta = 25C

40C

Ta = 85C

Ta =



0.970

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

VDD [V]

S-1004Cx50

5.050

5.025

Ta = 25C

Ta =



40C

Ta = 85C

5.000

4.975

4.950

0.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

4. Hysteresis width (V_HYS) vs. Power supply voltage (V_DD)

S-1004Cx10

S-1004Cx24

7.0

Ta = 25C

Ta =



40C

Ta = 25C

6.0

5.0

4.0

6.0

5.0

4.0

Ta = 85C

Ta =

2.0



40C

Ta = 85C

2.0 4.0

3.0

0.0

3.0

0.0

6.0

8.0

10.0

4.0

6.0

8.0

10.0

VDD [V]

S-1004Cx50

7.0

6.0

5.0

4.0

Ta = 85C

Ta =



40C

Ta = 25C

3.0

0.0

2.0

4.0

6.0

8.0

10.0

V^DD[V]

25

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

5. Current consumption (I_SS) vs. Power supply voltage (V_DD)

S-1004Cx10

V_SENSE= V_DET(S) 0.1 V (during detection)

1.00

Ta = 25°C,

S-1004Cx10

Ta = 25°C,

V

_SENSE= V_DET(S) 1.0 V (during release)

1.00

0.80

0.60

0.40

0.20

0.00

0.80

0.60

0.40

0.20

0.00

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

VDD [V]

S-1004Cx24

Ta = 25°C,

S-1004Cx24

Ta = 25°C,

V

_SENSE= V_DET(S) 0.1 V (during detection)

V

_SENSE= V_DET(S) 1.0 V (during release)

1.00

0.80

0.60

0.40

0.20

0.00

0.80

0.60

0.40

0.20

0.00

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

VDD [V]

S-1004Cx50

Ta = 25°C,

S-1004Cx50

Ta = 25°C,

V

_SENSE= V_DET(S) 0.1 V (during detection)

V

_SENSE= V_DET(S) 1.0 V (during release)

1.00

0.80

0.60

0.40

0.20

0.00

0.80

0.60

0.40

0.20

0.00

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

V

DD [V]

VDD [V]

26

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

6. Current consumption (I_SS) vs. SENSE pin input voltage (V_SENSE

)

S-1004Cx10

Ta = 25°C,

S-1004Cx24

Ta = 25°C,

V_DD= V_DET(S) 1.0 V, V_SENSE= 0.0 V  10.0 V

1.00

0.80

0.60

0.40

0.20

0.00

0.80

0.60

0.40

0.20

0.00

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

V

SENSE [V]

VSENSE [V]

S-1004Cx50

Ta = 25°C,

V

_DD= V_DET(S) 1.0 V, V_SENSE= 0.0 V  10.0 V

1.00

0.80

0.60

0.40

0.20

0.00

0.0

2.0

4.0

6.0

8.0

10.0

V

SENSE [V]

7. Current consumption (I_SS) vs. Temperature (Ta)

S-1004Cx10

V_DD= V_DET(S) 1.0 V,

S-1004Cx24

V_DD= V_DET(S) 1.0 V,

V

_SENSE= V_DET(S) 1.0 V (during release)

V

_SENSE= V_DET(S) 1.0 V (during release)

0.30

0.25

0.20

0.15

0.10

0.05

0.00

0.30

0.25

0.20

0.15

0.10

0.05

0.00

40



25

0

25

50

75 85

40

25

0

25

50

75 85

Ta [C]

S-1004Cx50

V_DD= V_DET(S) 1.0 V,

V

_SENSE= V_DET(S) 1.0 V (during release)

0.30

0.25

0.20

0.15

0.10

0.05

0.00

40



25

0

25

50

75 85

Ta [C]

27

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

8. Nch transistor output current (I_OUT) vs. V_DS

9. Pch transistor output current (I_OUT) vs. V_DS

S-1004Nx12

Ta = 25°C,

S-1004Cx12

Ta = 25°C,

V

_SENSE= 0.0 V (during detection)

V_SENSE= V_DET(S) 1.0 V (during release)

20.0

40.0

30.0

20.0

10.0

0.0

V

DD = 6.0 V

V

DD = 8.4 V

V

DD = 4.8 V

V

DD = 0.95 V

15.0

V

DD = 1.2 V

V

DD = 7.2 V

V

DD = 3.6 V

10.0

V

DD = 6.0 V

DD = 4.8 V

VDD = 2.4 V

V

5.0

V

DD = 3.6 V

V

DD = 1.2 V

V

DD = 2.4 V

V

DD = 0.95 V

0.0

1.0

2.0 3.0

4.0

5.0

6.0

0.0

2.0

4.0

6.0

8.0

10.0

V

DS [V]

V

DS [V]

10.

Nch transistor output current (I_OUT) vs. Power supply voltage (V_DD)

11.

Pch transistor output current (I_OUT) vs.



Power supply voltage (V_DD)

S-1004Nx12

V_DS= 0.5 V,

S-1004Cx12

V_DS= 0.5 V,

V_SENSE= 0.0 V (during detection)

V_SENSE= V_DET(S) 1.0 V (during release)

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

Ta = 40C

Ta = 25C

Ta = 85C

Ta = 25C

Ta = 85C

0.0

2.0

4.0

6.0

8.0

10.0

0.0

2.0

4.0

6.0

8.0

10.0

VDD [V]

V

DD [V]

12. Minimum operation voltage (V_OUT) vs. Power supply voltage (V_DD)

S-1004Nx10

V_SENSE= V_DD

,

S-1004Nx10

Pull-up to 10 V, Pull-up resistance: 100 k

12.0

V_SENSE= V_DD,

Pull-up to V_DD, Pull-up resistance: 100 k

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

10.0

8.0

6.0

4.0

2.0

0.0

Ta = 40C

Ta = 25C

Ta = 40C

Ta = 25C

Ta = 85C

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

V

DD [V]

VDD [V]

13. Minimum operation voltage (V_OUT) vs. SENSE pin input voltage (V_SENSE

)

S-1004Nx10

V

_DD= 0.95 V,

S-1004Nx10

V_DD= 0.95 V,

Pull-up to V_DD, Pull-up resistance: 100 k

Pull-up to 10 V, Pull-up resistance: 100 k

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

12.0

10.0

8.0

Ta = 40C

6.0

Ta = 40C

Ta = 25C

Ta = 85C

Ta = 25C

4.0

2.0

0.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

V

SENSE [V]

VSENSE [V]

Remark V_DS: Drain-to-source voltage of the output transistor

28

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

14. Dynamic response vs. Output pin capacitance (C_OUT) (CD pin; open)

S-1004Cx10

Ta = 25°C,

S-1004Cx24

Ta = 25°C,

V

_DD= V_DET(S) 1.0 V

V_DD= V_DET(S) 1.0 V

1

t

PLH

t

PLH

0.1

0.01

0.1

0.01

tPHL

t

PHL

0.001

0.00001 0.0001

0.001

0.01

0.1

0.00001 0.0001

0.001

0.01

0.1

Output pin capacitance [F]

S-1004Cx50

Ta = 25°C,

_DD= V_DET(S) 1.0 V

V

1

t

PLH

0.1

0.01

t

PHL

0.001

0.00001 0.0001

0.001

0.01

0.1

Output pin capacitance [F]

S-1004Nx10

Ta = 25°C,

_DD= V_DET(S) 1.0 V

S-1004Nx24

Ta = 25°C,

V_DD= V_DET(S) 1.0 V

V

100

10

100

10

tPLH

1

t

PHL

t

PHL

0.1

0.01

0.00001 0.0001

0.001

0.01

0.00001 0.0001

0.001

0.01

0.1

Output pin capacitance [F]

S-1004Nx50

Ta = 25°C,

_DD= V_DET(S) 1.0 V

V

100

10

tPLH

1

t

PHL

0.1

0.01

0.00001 0.0001

0.001

0.01

Output pin capacitance [F]

29

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

1 s

*1

IH

V

SENSE pin voltage

*2

VIL

tPHL

tPLH

V

DD

V

DD  90%

Output voltage

DD  10%

V

*1. V_IH= 10 V

*2. V_IL= 0.95 V

Figure 33 Test Condition of Response Time

R

VDD

100 k

V_DD

Oscilloscope

OUT

SENSE

P.G.

VSS CD

Figure 34 Test Circuit of Response Time

(Nch open-drain output product)

Figure 35 Test Circuit of Response Time

(CMOS output product)

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

30

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

15. Release delay time (t_RESET) vs. CD pin capacitance (C_D) (Without output pin capacitance)

S-1004Cx10

Ta = 25°C,

_DD= V_DET(S) 1.0 V

S-1004Cx24

Ta = 25°C,

_DD= V_DET(S) 1.0 V

V

10000

1000

100

10

10000

1000

100

10

1

0.1

0.01

0.1

1

10

100

1000

0.1

1

10

100

1000

CD [nF]

S-1004Cx50

Ta = 25°C,

_DD= V_DET(S) 1.0 V

V

10000

1000

100

10

1

0.1

0.01

0.1

1

10

100

1000

CD [nF]

16. Release delay time (t_RESET) vs. Temperature (Ta)

S-1004Cx10

S-1004Cx24

C_D= 4.7 nF, V_DD= V_DET(S) 1.0 V

16

15

14

13

12

11

16

15

14

13

12

11

40



25

0

25

50

75 85

40

25

0

25

50

75 85

Ta [C]

S-1004Cx50

C_D= 4.7 nF, V_DD= V_DET(S) 1.0 V

16

15

14

13

12

11

40

25

0

25

50

75 85

Ta [C]

31

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

17. Release delay time (t_RESET

)

vs. Power supply voltage (V_DD)

S-1004Cx10

Ta = 25°C,

C_D= 4.7 nF

16

15

14

13

12

11

0.0

2.0

4.0

6.0

8.0

10.0

VDD [V]

1 s

*1

IH

V

SENSE pin voltage

*2

V

IL

tRESET

V

DD

V

DD  90%

Output voltage

V

SS

*1. V_IH= 10 V

*2. V_IL= 0.95 V

Figure 36 Test Condition of Release Delay Time

R

VDD

100 k

V_DD

Oscilloscope

OUT

SENSE

P.G.

VSS CD

C_D

Figure 37 Test Circuit of Release Delay Time

(Nch open-drain output product)

Figure 38 Test Circuit of Release Delay Time

(CMOS output product)

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

32

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_02

S-1004 Series

 Application Circuit Examples

1. Microcomputer reset circuits

In microcomputers, when the power supply voltage is lower than the minimum operation voltage, an unspecified

operation may be performed or the contents of the memory register may be lost. When power supply voltage

returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may

malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched

off or lowered.

Using the S-1004 Series which has the low minimum operation voltage, the high-accuracy detection voltage and

the hysteresis width, reset circuits can be easily constructed as seen in Figure 39 and Figure 40.

V_DD

V_DD1

VDD

SENSE

Microcomputer

OUT

VSS

CD

GND

Figure 39 Example of Reset Circuit

(Nch open-drain output product)

Figure 40 Example of Reset Circuit

(CMOS output product)

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

33

BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_02

2. Change of detection voltage

If there is not a product with a specified detection voltage value in the S-1004 Series, the detection voltage can be

changed by using a resistance divider or a diode, as seen in Figure 41 to Figure 44.

In Figure 41 and Figure 42, hysteresis width also changes.

V_DD

R

R_A

100 k

VDD

SENSE

VSS

VDD

SENSE

VSS

V_IN

OUT

CD

OUT

CD

R_B

GND

Figure 41 Detection voltage change

when using a resistance divider

(Nch open-drain output product)

Figure 42 Detection voltage change

when using a resistance divider

(CMOS output product)

R_A R_B

Remark Detection voltage =

 V_DET

 V_HYS

R_B

R_A R_B

Hysteresis width =

R_B

V_DD

V_f1

R

100 k

V_IN

VDD

SENSE

VSS

VDD

SENSE

VSS

OUT

CD

OUT

CD

GND

Figure 43 Detection voltage change

when using a diode

Figure 44 Detection voltage change

when using a diode

(Nch open-drain output product)

(CMOS output product)

Remark Detection voltage = V_f1 (V_DET

)

Caution 1. The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

2. Set the constants referring to "2. 1 Error when detection voltage is set externally" in

" Operation".

34

2.9±0.2

1.9±0.2

4

5

+0.1

-0.06

1

2

3

0.16

0.95±0.1

0.4±0.1

No. MP005-A-P-SD-1.3

TITLE

SOT235-A-PKG Dimensions

MP005-A-P-SD-1.3

No.

ANGLE

UNIT

mm

ABLIC Inc.

4.0±0.1(10 pitches:40.0±0.2)

+0.1

-0

2.0±0.05

0.25±0.1

ø1.5

+0.2

-0

4.0±0.1

ø1.0

1.4±0.2

3.2±0.2

3

4

2 1

5

Feed direction

No. MP005-A-C-SD-2.1

TITLE

SOT235-A-Carrier Tape

MP005-A-C-SD-2.1

No.

ANGLE

UNIT

mm

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

No. MP005-A-R-SD-1.1

TITLE

SOT235-A-Reel

MP005-A-R-SD-1.1

No.

ANGLE

UNIT

QTY.

3,000

mm

ABLIC Inc.

1.57±0.03

6

5

4

+0.05

-0.02

0.08

1

2

3

0.5

0.48±0.02

0.2±0.05

No. PG006-A-P-SD-2.1

SNT-6A-A-PKG Dimensions

PG006-A-P-SD-2.1

TITLE

No.

ANGLE

UNIT

mm

ABLIC Inc.

+0.1

-0

ø1.5

4.0±0.1

2.0±0.05

0.25±0.05

+0.1

ø0.5

-0

4.0±0.1

0.65±0.05

1.85±0.05

3

2

5

1

6

4

Feed direction

No. PG006-A-C-SD-2.0

TITLE

SNT-6A-A-Carrier Tape

PG006-A-C-SD-2.0

No.

ANGLE

UNIT

mm

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

No. PG006-A-R-SD-1.0

SNT-6A-A-Reel

TITLE

No.

PG006-A-R-SD-1.0

ANGLE

UNIT

5,000

QTY.

mm

ABLIC Inc.

0.52

2

1.36

0.52

1

0.3

0.2

1.

2.

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

0.03 mm

SNT

1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).

2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).

Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.

2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm

or less from the land pattern surface.

3. Match the mask aperture size and aperture position with the land pattern.

4. Refer to "SNT Package User's Guide" for details.

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

1.

2.

SNT-6A-A

-Land Recommendation

TITLE

No. PG006-A-L-SD-4.1

No.

PG006-A-L-SD-4.1

ANGLE

UNIT

mm

ABLIC Inc.

Disclaimers (Handling Precautions)

1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application

circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.

2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of

any specific mass-production design.

ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein

(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use

of the information described herein.

3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.

4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,

operation voltage range and electrical characteristics, etc.

ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the

products outside their specified ranges.

5. When using the products, confirm their applications, and the laws and regulations of the region or country where they

are used and verify suitability, safety and other factors for the intended use.

6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related

laws, and follow the required procedures.

7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass

destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to

develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.

8. The products are not designed to be used as part of any device or equipment that may affect the human body, human

life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control

systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,

aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do

not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.

Especially, the products cannot be used for life support devices, devices implanted in the human body and devices

that directly affect human life, etc.

Prior consultation with our sales office is required when considering the above uses.

ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.

9. Semiconductor products may fail or malfunction with some probability.

The user of the products should therefore take responsibility to give thorough consideration to safety design including

redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or

death, fires and social damage, etc. that may ensue from the products' failure or malfunction.

The entire system must be sufficiently evaluated and applied on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the

product design by the customer depending on the intended use.

11. The products do not affect human health under normal use. However, they contain chemical substances and heavy

metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be

careful when handling these with the bare hands to prevent injuries, etc.

12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.

13. The information described herein contains copyright information and know-how of ABLIC Inc.

The information described herein does not convey any license under any intellectual property rights or any other

rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any

part of this document described herein for the purpose of disclosing it to a third-party without the express permission

of ABLIC Inc. is strictly prohibited.

14. For more details on the information described herein, contact our sales office.

2.2-2018.06

www.ablic.com


型号：	S-1004CA29I-I6T1U
厂家：	ABLIC
描述：	BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
文件：	总42页 (文件大小：2595K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S-1004CA29I-I6T1U [ABLIC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E