S-1011G80-M6T1U4 [ABLIC]
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR;
| 型号： | S-1011G80-M6T1U4 |
| 厂家： | 
ABLIC |
| 描述： | HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR |
| 文件： | 总43页 (文件大小：2363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-1011 Series
HIGH-WITHSTAND VOLTAGE
www.ablic.com
© ABLIC Inc., 2014-2015
Rev.1.2_02
The S-1011 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally, and the accuracy of the S-1011 Series A / C / E / G type is 1.5%. It operates with current consumption of
600 nA typ.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared in the SENSE detection
product, so the output is stable even if the SENSE pin falls to 0 V.
The detection signal and release signal can be delayed by setting a capacitor externally, and the detection delay time
accuracy is 20% (CN = 3.3 nF, Ta = 25°C), the release delay time accuracy is 20% (CP = 3.3 nF, Ta = 25°C).
Output form is Nch open-drain output.
Features
Detection voltage:
3.0 V to 10.0 V (0.05 V step) (SENSE detection product)
3.6 V to 10.0 V (0.05 V step) (VDD detection product)
1.5% (A / C / E / G type)
20% (CN = 3.3 nF)
20% (CP = 3.3 nF)
Detection voltage accuracy:
Detection delay time accuracy:
Release delay time accuracy:
Current consumption:
600 nA typ.
Operation voltage range:
Hysteresis width:
Output form:
1.8 V to 36.0 V
"Available" (5.0% typ.) / "unavailable" is selectable.
Nch open-drain output
Operation temperature range:
Lead-free (Sn 100%), halogen-free
Ta = 40°C to 85°C
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV and home appliance etc.
Power supply monitor for Blu-ray recorder, notebook PC and digital still camera
Industrial equipment, housing equipment
Package
SOT-23-6
1
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Block Diagrams
1. S-1011 Series A / J type (VDD detection product)
CP
Function
Status
Voltage detection VDD detection
Available
Hysteresis width
VDD
(5.0% typ.)
Delay
OUT
circuit
*1
*1
VREF
*1
*1
VSS
CN
*1. Parasitic diode
Figure 1
2. S-1011 Series C / L type (VDD detection product)
CP
Function
Status
Voltage detection VDD detection
Hysteresis width Unavailable
VDD
Delay
OUT
circuit
*1
*1
VREF
*1
*1
VSS
CN
*1. Parasitic diode
Figure 2
2
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
3. S-1011 Series E / N type (SENSE detection product)
CP
SENSE
Function
Status
Voltage detection SENSE detection
Available
Hysteresis width
VDD
(5.0% typ.)
Delay
circuit
*1
*1
OUT
*1
VREF
*1
*1
VSS
CN
*1. Parasitic diode
Figure 3
4. S-1011 Series G / Q type (SENSE detection product)
CP
SENSE
Function
Status
Voltage detection SENSE detection
Hysteresis width Unavailable
VDD
Delay
circuit
*1
*1
OUT
*1
VREF
*1
*1
VSS
CN
*1. Parasitic diode
Figure 4
3
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Product Name Structure
Users can select the product type and detection voltage value for the S-1011 Series.
Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding
the product types, "3. Package" regarding the package drawings and "4. Product name lists" regarding details of
the product name.
1. Product name
S-1011
x
xx
-
M6T1
U
4
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M6T1: SOT-23-6, Tape
Detection voltage value
30 to A0
(e.g., when the output voltage is 3.0 V, it is expressed as 30.
when the output voltage is 10.0 V, it is expressed as A0.)
Product type*2
A, C, E, G, J, L, N, Q
*1. Refer to the tape drawing.
*2. Refer to "2. Function list of product types".
Remark
Although the detection voltage in the S-1011 Series is 10.0 V max., the detection voltage exceeding
10.0 V with an external resistor can be set.
Refer to "2. SENSE pin" in " Operation" for details.
2. Function list of product types
Table 1
Product Type
Voltage Detection
VDD detection
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Hysteresis Width
Available (5.0% typ.)
Unavailable
Detection Voltage
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
3.6 V to 4.95 V
3.6 V to 4.95 V
3.0 V to 4.95 V
3.0 V to 4.95 V
A
C
E
G
J
VDD detection
SENSE detection
SENSE detection
VDD detection
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
L
VDD detection
N
Q
SENSE detection
SENSE detection
Available (5.0% typ.)
Unavailable
3. Package
Table 2 Package Drawing Codes
Package Name
SOT-23-6
Dimension
MP006-A-P-SD
Tape
Reel
MP006-A-C-SD
MP006-A-R-SD
4
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
4. Product name lists
4. 1 S-1011 Series A type
Voltage detection: VDD detection
Output logic: Active "L"
Hysteresis width: Available (5.0% typ.)
Detection voltage: 5.0 V to 10.0 V
Table 3
Detection Voltage
5.0 V 1.5%
6.0 V 1.5%
7.0 V 1.5%
8.0 V 1.5%
9.0 V 1.5%
10.0 V 1.5%
SOT-23-6
S-1011A50-M6T1U4
S-1011A60-M6T1U4
S-1011A70-M6T1U4
S-1011A80-M6T1U4
S-1011A90-M6T1U4
S-1011AA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 2 S-1011 Series C type
Voltage detection: VDD detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 4
Detection Voltage
SOT-23-6
S-1011C50-M6T1U4
S-1011C60-M6T1U4
S-1011C70-M6T1U4
S-1011C80-M6T1U4
S-1011C90-M6T1U4
S-1011CA0-M6T1U4
5.0 V 1.5%
6.0 V 1.5%
7.0 V 1.5%
8.0 V 1.5%
9.0 V 1.5%
10.0 V 1.5%
Remark Please contact our sales office for products with specifications other than the above.
4. 3 S-1011 Series E type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 5
Detection Voltage
5.0 V 1.5%
6.0 V 1.5%
7.0 V 1.5%
8.0 V 1.5%
9.0 V 1.5%
10.0 V 1.5%
SOT-23-6
S-1011E50-M6T1U4
S-1011E60-M6T1U4
S-1011E70-M6T1U4
S-1011E80-M6T1U4
S-1011E90-M6T1U4
S-1011EA0-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 4 S-1011 Series G type
Voltage detection: SENSE detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 6
Detection Voltage
SOT-23-6
S-1011G50-M6T1U4
S-1011G60-M6T1U4
S-1011G70-M6T1U4
S-1011G80-M6T1U4
S-1011G90-M6T1U4
S-1011GA0-M6T1U4
5.0 V 1.5%
6.0 V 1.5%
7.0 V 1.5%
8.0 V 1.5%
9.0 V 1.5%
10.0 V 1.5%
Remark Please contact our sales office for products with specifications other than the above.
5
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
4. 5 S-1011 Series J type
Voltage detection: VDD detection
Output logic: Active "L"
Hysteresis width: Available (5.0% typ.)
Detection voltage: 3.6 V to 4.95 V
Table 7
Detection Voltage
3.6 V 3.0%
4.2 V 2.5%
SOT-23-6
S-1011J36-M6T1U4
S-1011J42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 6 S-1011 Series L type
Voltage detection: VDD detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 3.6 V to 4.95 V
Table 8
Detection Voltage
SOT-23-6
S-1011L36-M6T1U4
S-1011L42-M6T1U4
3.6 V 3.0%
4.2 V 2.5%
Remark Please contact our sales office for products with specifications other than the above.
4. 7 S-1011 Series N type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)
Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 9
Detection Voltage
3.0 V 3.0%
3.3 V 3.0%
3.6 V 3.0%
4.2 V 2.5%
SOT-23-6
S-1011N30-M6T1U4
S-1011N33-M6T1U4
S-1011N36-M6T1U4
S-1011N42-M6T1U4
Remark Please contact our sales office for products with specifications other than the above.
4. 8 S-1011 Series Q type
Voltage detection: SENSE detection
Hysteresis width: Unavailable
Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 10
Detection Voltage
SOT-23-6
S-1011Q30-M6T1U4
S-1011Q33-M6T1U4
S-1011Q36-M6T1U4
S-1011Q42-M6T1U4
3.0 V 3.0%
3.3 V 3.0%
3.6 V 3.0%
4.2 V 2.5%
Remark Please contact our sales office for products with specifications other than the above.
6
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Pin Configurations
1. S-1011 Series A / C / J / L type (VDD detection product)
1. 1 SOT-23-6
Top view
Table 11
6
5
4
Pin No.
Symbol
VDD
Description
1
2
3
4
5
6
Voltage input pin
No connection
NC*1
OUT
CP*2
VSS
CN*3
Voltage detection output pin
Connection pin for release delay capacitor
GND pin
1
2
3
Figure 5
Connection pin for detection delay capacitor
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
*2. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*3. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.
2. S-1011 Series E / G / N / Q type (SENSE detection product)
2. 1 SOT-23-6
Top view
Table 12
6
5
4
Pin No.
Symbol
VDD
Description
1
2
3
4
5
6
Voltage input pin
SENSE
OUT
CP*1
Detection voltage input pin
Voltage detection output pin
Connection pin for release delay capacitor
GND pin
1
2
3
VSS
CN*2
Figure 6
Connection pin for detection delay capacitor
*1. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*2. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.
7
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Absolute Maximum Ratings
Table 13
(Ta = 25°C unless otherwise specified)
Item
Power supply voltage
SENSE pin input voltage
CP pin input voltage
CN pin input voltage
Output voltage
Symbol
Absolute Maximum Rating
VSS 0.3 to VSS 45
VSS 0.3 to VSS 45
VSS 0.3 to VDD 0.3 VSS 7.0
VSS 0.3 to VDD 0.3 VSS 7.0
VSS 0.3 to VSS 45
25
Unit
V
VDD VSS
VSENSE
VCP
V
V
VCN
V
VOUT
IOUT
V
Output current
mA
°C
°C
Operation ambient temperature
Storage temperature
Topr
40 to 85
40 to 125
Tstg
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 14
Item
Symbol
ja
Condition
Board 1
Board 2
Min.
Typ.
159
Max.
Unit
°C/W
°C/W
Junction-to-ambient thermal resistance*1
SOT-23-6
124
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Thermal Characteristics" for details of power dissipation and test board.
8
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Electrical Characteristics
1. VDD detection product
1. 1 S-1011 Series J / L type
Table 15
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
3.6 V VDET(S) 4.15 V
4.2 V VDET(S) 4.95 V
Min.
Typ.
Max.
Unit
V
VDET(S)
0.970
VDET(S)
0.975
VDET
0.010 0.050 0.100
VDET VDET VDET
0.020 0.050 0.090
VDET(S)
1.030
VDET(S)
1.025
VDET
VDET(S)
1
Detection voltage*1
VDET
VDET(S)
VDET
V
1
1
1
3.6 V VDET(S) 4.15 V
V
J type
Hysteresis width
VHYS
4.2 V VDET(S) 4.95 V
3.6 V VDET(S) 4.95 V
V
L type*2
1.8
0
0.60
1.60
36.0
V
A
V
1
2
1
Current consumption ISS
VDD = VDET 0.1 V, 3.6 V VDET 4.95 V
Operation voltage
VDD
Output transistor
Output current
IOUT
Nch
V
DD = 2.9 V
0.33
mA
3
VDS*3 = 0.05 V
Output transistor
Nch
Leakage current
ILEAK
VDD = 30.0 V, VOUT = 30.0 V
2.0
A
3
Detection delay time*4 tRESET
Release delay time*5 tDELAY
CN = 3.3 nF
CP = 3.3 nF
8.0
8.0
10.0
10.0
12.0
12.0
ms
ms
4
4
CP pin discharge
RCP
VDD = 6.9 V, VCP = 0.5 V
VDD = 2.9 V, VCN = 0.5 V
0.52
1.0
2.2
5.0
k
k
ON resistance
CN pin discharge
RCN
ON resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of VDET(S) 0.5 V VDET(S) 0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S) 0.5 V VDET(S) 0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2.
9
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
1. 2 S-1011 Series A / C type
Table 16
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
5.0 V VDET(S) 10.0 V
Min.
Typ.
Max.
Unit
V
VDET(S)
0.985
VDET
VDET(S)
1.015
VDET
Detection voltage*1
VDET
VDET(S)
VDET
1
A type
V
1
0.030 0.050 0.080
Hysteresis width
VHYS
C type*2
1.8
0
0.60
1.60
36.0
V
A
V
1
2
1
Current consumption ISS
VDD = VDET 0.1 V, 5.0 V VDET 10.0 V
Operation voltage
VDD
Output transistor
Output current
IOUT
Nch
V
DD = 4.5 V
0.5
mA
3
VDS*3 = 0.05 V
Output transistor
Nch
Leakage current
ILEAK
VDD = 30.0 V, VOUT = 30.0 V
2.0
A
3
Detection delay time*4 tRESET
Release delay time*5 tDELAY
CN = 3.3 nF
CP = 3.3 nF
8.0
8.0
10.0
10.0
12.0
12.0
ms
ms
4
4
CP pin discharge
RCP
VDD = 14.0 V, VCP = 0.5 V
VDD = 4.5 V, VCN = 0.5 V
0.30
0.63
2.60
2.60
k
k
ON resistance
CN pin discharge
RCN
ON resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor
*4. The time period from when the pulse voltage of VDET(S) 1.0 V VDET(S) 1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S) 1.0 V VDET(S) 1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2.
10
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
2. SENSE detection product
2. 1 S-1011 Series N / Q type
Table 17
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max. Unit
VDET(S)
0.970
VDET(S)
0.975
VDET
0.010 0.050 0.100
VDET VDET VDET
0.020 0.050 0.090
VDET(S)
V
3.0 V VDET(S) 4.15 V
4.2 V VDET(S) 4.95 V
VDET(S)
1
1.030
Detection voltage*1
VDET
VDD = 16.0 V
VDET(S)
1.025
VDET(S)
VDET
V
1
1
VDET
3.0 V VDET(S) 4.15 V
V
N type
Hysteresis width
VHYS
VDD = 16.0 V
4.2 V VDET(S) 4.95 V
Q type*2 3.0 V VDET(S) 4.95 V
VDD = 16.0 V, VSENSE = VDET 0.1 V,
V
V
1
1
0
Current
ISS
0.55
1.55
36.0
A
2
1
consumption*3
Operation voltage
3.0 V VDET 4.95 V
VDD
3.0
V
Output transistor
Output current
IOUT
Nch
VDD = 5.0 V, VSENSE = 2.9 V
0.5
mA
3
VDS*4 = 0.05 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Leakage current
ILEAK
2.0
A
3
Nch
VSENSE = 30.0 V
Detection delay time*5 tRESET
Release delay time*6 tDELAY
SENSE pin resistance RSENSE
CN = 3.3 nF
CP = 3.3 nF
8.0
8.0
6.8
10.0
10.0
12.0
12.0
ms
ms
4
4
2
275 M
CP pin discharge
RCP
VDD = 3.0 V, VSENSE = 6.9 V, VCP = 0.5 V
VDD = 3.0 V, VSENSE = 2.9 V, VCN = 0.5 V
0.72
0.72
4.29 k
ON resistance
CN pin discharge
RCN
4.29 k
ON resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4.
VDS: Drain-to-source voltage of the output transistor
*5. The time period from when the pulse voltage of VDET(S) 0.5 V VDET(S) 0.5 V is applied to the SENSE pin to
when VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE
reaches the release voltage once.
)
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S) 0.5 V
VDET(S) 0.5 V is applied to the SENSE pin to when VOUT reaches VDD / 2.
11
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
2. 2 S-1011 Series E / G type
Table 18
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
V
VDET(S)
0.985
VDET
VDET(S)
1.015
VDET
Detection voltage*1
VDET
VDD = 16.0 V, 5.0 V VDET(S) 10.0 V
VDET(S)
VDET
1
E type
V
V
1
1
0.030 0.050 0.080
Hysteresis width
VHYS
VDD = 16.0 V
G type*2
0
Current
VDD = 16.0 V, VSENSE = VDET 0.1 V,
5.0 V VDET 10.0 V
ISS
0.55
1.55
36.0
A
2
1
consumption*3
Operation voltage
VDD
DD = 5.0 V, VSENSE = 4.5 V
3.0
V
Output transistor
Output current
IOUT
Nch
V
0.5
mA
3
VDS*4 = 0.05 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Leakage current
ILEAK
2.0
A
3
Nch
VSENSE = 30.0 V
Detection delay time*5 tRESET
Release delay time*6 tDELAY
SENSE pin resistance RSENSE
CN = 3.3 nF
CP = 3.3 nF
8.0
8.0
10.0
10.0
12.0
12.0
400
ms
ms
4
4
2
26.0
M
CP pin discharge
RCP
VDD = 4.5 V, VSENSE = 14.0 V, VCP = 0.5 V
VDD = 4.5 V, VSENSE = 4.5 V, VCN = 0.5 V
0.30
0.63
2.60
2.60
k
k
ON resistance
CN pin discharge
RCN
ON resistance
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value
*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4.
VDS: Drain-to-source voltage of the output transistor
*5. The time period from when the pulse voltage of VDET(S) 1.0 V VDET(S) 1.0 V is applied to the SENSE pin to
when VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE
reaches the release voltage once.
)
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S) 1.0 V
VDET(S) 1.0 V is applied to the SENSE pin to when VOUT reaches VDD / 2.
12
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Test Circuits
R
R
VDD
VDD
100 k
100 k
OUT
VSS CP CN
SENSE
OUT
VDD
VDD
VSENSE
VSS CP CN
V
V
V
V
Figure 7 Test Circuit 1
Figure 8 Test Circuit 1
(SENSE detection product)
(VDD detection product)
A
A
VDD
VDD
OUT
SENSE
OUT
A
VDD
VDD
VSENSE
VSS CP CN
VSS CP CN
Figure 9 Test Circuit 2
Figure 10 Test Circuit 2
(SENSE detection product)
(VDD detection product)
VDD
VDD
OUT
VSS CP CN
SENSE
OUT
A
A
VDD
VDD
VDS
VDS
VSENSE
VSS CP CN
V
V
V
V
Figure 11 Test Circuit 3
Figure 12 Test Circuit 3
(VDD detection product)
(SENSE detection product)
R
R
VDD
VDD
100 k
100 k
Oscilloscope
Oscilloscope
OUT
VSS CP CN
SENSE
OUT
P.G.
P.G.
VDD
VSS CP CN
Figure 13 Test Circuit 4
(VDD detection product)
Figure 14 Test Circuit 4
(SENSE detection product)
13
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Standard Circuits
1. VDD detection product
R
100 k
VDD
VSS
OUT
CP
CN
*1
*2
CP
CN
*1. The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
*2. The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 15
2. SENSE detection product
R
100 k
VDD
SENSE
OUT
VSS
CP
CN
*1
*2
CP
CN
*1. The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
*2. The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 16
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
14
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Explanation of Terms
1. Detection voltage (VDET
)
The detection voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "L" (VDD detection
product: VDD, SENSE detection product: VSENSE). The detection voltage varies slightly among products of the same
specification. The variation of detection voltage between the specified minimum (VDET min.) and the maximum
(VDET max.) is called the detection voltage range (Refer to Figure 17, Figure 19).
Example: In VDET = 5.0 V product, the detection voltage is either one in the range of 4.925 V VDET 5.075 V.
This means that some VDET = 5.0 V product have VDET = 4.925 V and some have VDET = 5.075 V.
2. Release voltage (VDET
)
The release voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "H" (VDD detection product:
VDD, SENSE detection product: VSENSE).
The difference of detection voltage and release voltage is 5.0% typ.
The release voltage varies slightly among products of the same specification. The variation of release voltage
between the specified minimum (VDET min.) and the maximum (VDET max.) is called the release voltage range
(Refer to Figure 18, Figure 20). The range is calculated from the actual detection voltage (VDET) of a product.
In the S-1011 Series C / G / L / Q type, the release voltage (VDET) is the same value as the actual detection
voltage (VDET) of a product.
Example: In VDET = 6.0 V product, the release voltage is either one in the range of 6.0873 V VDET 6.5772 V.
This means that some VDET = 6.0 V product have VDET = 6.0873 V and some have VDET = 6.5772 V.
15
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
VDD
Detection voltage Release voltage
VDET max.
VDET min.
VDET max.
Detection voltage
Release voltage
range
range
VDET min.
VDD
VOUT
VOUT
tRESET
tDELAY
Figure 17 Detection Voltage (VDD detection product)
Figure 18 Release Voltage (VDD detection product)
VSENSE
Detection voltage Release voltage
VDET max.
VDET min.
VDET max.
Detection voltage
range
Release voltage
range
VDET min.
VSENSE
VOUT
VOUT
tRESET
tDELAY
Figure 19 Detection Voltage
(SENSE detection product)
Figure 20 Release Voltage
(SENSE detection product)
R
R
VDD
VDD
100 k
100 k
OUT
VSS CP CN
SENSE
OUT
VDD
VDD
VSENSE
VSS CP CN
V
V
V
V
Figure 21 Test Circuit of Detection Voltage
and Release Voltage
Figure 22 Test Circuit of Detection Voltage
and Release Voltage
(VDD detection product)
(SENSE detection product)
3. Hysteresis width (VHYS
)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in Figure 24 and Figure 28). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release
of a voltage detector.
16
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Operation
1. Basic operation
1. 1 S-1011 Series A / J type
(1) When the power supply voltage (VDD) is the release voltage (VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
(RB RC ) VDD
RA RB RC
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
.
(2) Even if VDD decreases to VDET or lower, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or lower (point A in Figure 24), the Nch transistor is turned on. And then VSS ("L")
is output from the OUT pin after the elapse of the detection delay time (tRESET).
RB VDD
At this time, N1 is turned on, and the input voltage to the comparator is
.
RA RB
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher. Even if VDD exceeds VDET, VSS is
output when VDD is lower than VDET
.
(5) When VDD increases to VDET or higher (point B in Figure 24), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
R
100 k
RA
VDD
OUT
Delay
circuit
*1
RB
RC
*1
VREF
N1
Nch
V
*1
*1
VSS
CP
CP
CN
CN
*1. Parasitic diode
Figure 23 Operation of S-1011 Series A / J Type
(2) (3) (4) (5)
(1)
Hysteresis width
(VHYS
B
Release voltage (VDET
)
A
)
Detection voltage (VDET
)
VDD
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
tRESET
tDELAY
Remark When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable in
the shaded area.
Figure 24 Timing Chart of S-1011 Series A / J Type
17
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
1. 2 S-1011 Series C / L type
(1) When the power supply voltage (VDD) is the release voltage (VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
(RB RC ) VDD
RA RB RC
At this time, the input voltage to the comparator is
.
(2) When VDD decreases to the detection voltage (VDET) or lower (point A in Figure 26), the Nch transistor is
turned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher.
(5) When VDD increases to VDET or higher (point B in Figure 26), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
VDD
R
100 k
RA
VDD
OUT
Delay
circuit
*1
RB
RC
*1
VREF
Nch
V
*1
*1
VSS
CP
CP
CN
CN
*1. Parasitic diode
Figure 25 Operation of S-1011 Series C / L Type
(2) (3) (4) (5)
(1)
A
B
Detection voltage (VDET
)
Release voltage (VDET
)
VDD
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
tRESET
tDELAY
Remark 1. When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable
in the shaded area.
2. The release voltage is set to the same value as the detection voltage, since there is no hysteresis
width.
Figure 26 Timing Chart of S-1011 Series C / L Type
18
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
1. 3 S-1011 Series E / N type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
(RB RC ) VSENSE
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is
.
RA RB RC
(2) Even if VSENSE decreases to VDET or lower, VDD is output when VSENSE is higher than the detection voltage
(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 28), the Nch transistor is turned on. And then VSS
("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
RB VSENSE
At this time, N1 is turned on, and the input voltage to the comparator is
.
RA RB
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VDET
.
(5) When VSENSE increases to VDET or higher (point B in Figure 28), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
SENSE
VDD
R
100 k
RA
VDD
OUT
Delay
circuit
*1
*1
VSENSE
RB
*1
VREF
N1
Nch
V
*1
*1
RC
VSS
CP
CP
CN
CN
*1. Parasitic diode
Figure 27 Operation of S-1011 Series E / N Type
(2) (3) (4)
(5)
(1)
B
Hysteresis width
(VHYS
Release voltage (VDET
)
A
)
Detection voltage (VDET
)
VSENSE
Minimum operation voltage
VSS
VDD
VSS
Output from OUT pin
tRESET
tDELAY
Figure 28 Timing Chart of S-1011 Series E / N Type
19
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
1. 4 S-1011 Series G / Q type
(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage
(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
(RB RC ) VSENSE
At this time, the input voltage to the comparator is
.
RA RB RC
(2) When VSENSE decreases to the detection voltage (VDET) or lower (point A in Figure 30), the Nch transistor is
turned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is
stable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE increases, VSS is output when VSENSE is lower than VDET
.
(5) When VSENSE increases to VDET or higher (point B in Figure 30), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
SENSE
VDD
R
100 k
RA
VDD
OUT
Delay
circuit
*1
*1
VSENSE
RB
*1
VREF
Nch
V
*1
*1
RC
VSS
CP
CP
CN
CN
*1. Parasitic diode
Figure 29 Operation of S-1011 Series G / Q Type
(2) (3) (4) (5)
(1)
A
B
Detection voltage (VDET
)
Release voltage (VDET
)
VSENSE
Minimum operation voltage
VSS
VDD
VSS
Output from OUT pin
tRESET
tDELAY
Remark The release voltage is set to the same value as the detection voltage, since there is no hysteresis width.
Figure 30 Timing Chart of S-1011 Series G / Q Type
20
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
2. SENSE pin
2. 1 Error when detection voltage is set externally
The detection voltage for the S-1011 Series is 10.0 V max., however, in the SENSE detection product with VDET
=
10.0 V, the detection voltage can be set externally by connecting a node that was resistance-divided by the resistor
(RA) and the resistor (RB) to the SENSE pin as shown in Figure 31.
For conventional products without the SENSE pin, external resistor cannot be too large since the resistance-divided
node must be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin
when it goes from detection to release, and if external resistor is large, problems such as oscillation or larger error
in the hysteresis width may occur.
In the S-1011 Series, RA and RB in Figure 31 are easily made larger since the resistance-divided node can be
connected to the SENSE pin through which no feed-through current flows. However, be careful of error in the
current flowing through the internal resistance (RSENSE) that will occur.
Although RSENSE in the S-1011 Series is large (the S-1011 Series E / G type: 26 M min., the S-1011 Series N / Q
type: 6.8 M min.) to make the error small, RA and RB should be selected such that the error is within the allowable
limits.
2. 2 Selection of RA and RB
In Figure 31, the relation between the external setting detection voltage (VDX) and the actual detection voltage
(VDET) is ideally calculated by the equation below.
RA
RB
VDX = VDET
1
··· (1)
(
)
However, in reality there is an error in the current flowing through RSENSE
.
When considering this error, the relation between VDX and VDET is calculated as follows.
RA
VDX = VDET
= VDET
1
(
)
RB || RSENSE
RA
1
RB RSENSE
RB RSENSE
RA
RB
RA
= VDET
1
VDET
··· (2)
(
)
RSENSE
RA
RSENSE
By using equations (1) and (2), the error is calculated as VDET
.
The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA RB
RSENSE (RA RB)
RA || RB
RSENSE
100 [%] =
100 [%]
··· (3)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
21
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
RA
RB
VHX = VHYS
1
··· (4)
(
)
A
RA
VDD
SENSE
RSENSE
OUT
VDX
VDET
RB
VSS
Figure 31 Detection Voltage External Setting Circuit
Caution 1. When externally setting the detection voltage, perform the operation with VDET = 10.0 V product.
Contact our sales office for details.
2. If the current flowing through RB is set to 1 A or less, the error may become larger.
3. If the parasitic resistance and parasitic inductance between VDX point A and point A VDD pin
are larger, oscillation may occur. Perform thorough evaluation using the actual application.
4. If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS
pin.
22
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
3. Delay circuit
The delay circuit has a function that adjusts the detection delay time (tRESET) from when the power supply voltage
(VDD) or SENSE pin voltage (VSENSE) reaches the detection voltage (VDET) or lower to when the output from OUT
pin inverts.
It also has a function that adjusts the release delay time (tDELAY) from when the power supply voltage (VDD) or
SENSE pin voltage (VSENSE) reaches the release voltage (VDET) to when the output from OUT pin inverts.
tRESET is determined by the delay coefficient, the delay capacitor (CN) and the detection delay time when the CN pin
is open (tRESET0), and the tDELAY is determined by the delay coefficient, the delay capacitor (CP) and the release
delay time when the CP pin is open (tDELAY0). They are calculated by the equation below.
tRESET [ms] = Delay coefficient CN [nF] tRESET0 [ms]
t
DELAY [ms] = Delay coefficient CP [nF] tDELAY0 [ms]
Table 19
Delay Coefficient
Operation
Temperature
Min.
2.41
2.41
2.40
Typ.
2.85
2.86
2.83
Max.
3.32
3.30
3.25
Ta = 85°C
Ta = 25°C
Ta = 40°C
Table 20
Detection Delay Time
when CN Pin is Open (tRESET0
Typ.
Release Delay Time
when CP Pin is Open (tDELAY0
Typ.
Operation
Temperature
)
)
Ta = 40°C to 85°C
0.35 ms
0.35 ms
Caution 1. Mounted board layout should be made in such a way that no current flows into or flows from
the CN pin or CP pin since the impedance of the CN pin and CP pin are high, otherwise correct
delay time cannot be provided.
2. There is no limit for the capacitance of CN and CP as long as the leakage current of the
capacitor can be ignored against the built-in constant current value (approximately 300 nA).
The leakage current may cause error in delay time. When the leakage current is larger than the
built-in constant current, no detect or release takes place.
3. The above equation will not guarantee successful operation. Determine the capacitance of CN
and CP through thorough evaluation including temperature characteristics in the actual usage
conditions.
When using an X8R equivalent capacitor, refer to the "2. Detection delay time (tRESET) vs.
Temperature (Ta)", "3. Detection delay time (tRESET) vs. Power supply voltage (VDD)", "5.
Release delay time (tDELAY) vs. Temperature (Ta)" and "6. Release delay time (tDELAY) vs.
Power supply voltage (VDD)" in " Reference Data" for details.
23
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Usage Precautions
1. Feed-through current during detection and release
In the S-1011 Series, the feed-through current flows at the time of detection and release. For this reason, if the
input impedance is high, oscillation may occur due to voltage drop caused by the feed-through current.
When using the S-1011 Series in configurations like those shown in Figure 32 and Figure 33, it is recommended
that input impedance be set to 1 k or less.
Determine the impedance through thorough evaluation including temperature characteristics.
RA
VDD
RA VDD
VDD
CP
VDD
CP
OUT
CN
SENSE
VSS
OUT
CN
VBAT
VBAT
VSS
Figure 32 VDD Detection Product
Figure 33 SENSE Detection Product
24
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
2. Power on and shut down sequence
SENSE detection products monitor SENSE pin voltage (VSENSE) while power is being supplied to the VDD pin.
Apply power in the order, the VDD pin then the SENSE pin.
In addition, when shutting down VDD pin, shut down the SENSE pin first, and shut down the VDD pin after the
detection delay time (tRESET) has elapsed.
V
DD
VDET
V
SENSE
VDET(S)
tDELAY
t
RESET
V
OUT
Figure 34
3. Falling power (reference)
Figure 35 shows the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where the release
status can be maintained when the VDD pin (VDD detection product) sharply drops to a voltage equal to or higher
than the detection voltage (VDET) during release status.
S-1011A50
Ta = 40C to 85C
40.0
30.0
20.0
10.0
0.0
0.1
1
10
t
F
[s]
Figure 35
t
F
*1
IH
V
VDET
V
P-P
*2
VDD
VIL
VDET
VSS
*1.
VIH = 36.0 V
*2. VIL = VDET(S) 1.0 V
Figure 36 VDD Pin Input Voltage Waveform
Caution Figure 35 shows the input voltage conditions which can maintain the release status. If the
voltage whose VP-P and tF are larger than these conditions is input to the VDD pin (VDD detection
product), the OUT pin may change to a detection status.
25
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
4. Detection delay time accuracy (reference)
Figure 37 and Figure 38 show the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where
the arbitrarily set detection delay time accuracy can be maintained when the VDD pin (VDD detection product)
sharply drops.
S-1011A50
40.0
S-1011A50
40.0
Ta = 40C to 85C
Ta = 40C to 85C
30.0
20.0
10.0
0.0
30.0
20.0
10.0
0.0
0.1
1
10
0.1
1
10
t
F
[s]
t
F
[s]
Figure 37 CN = 3.3 nF
Figure 38 CN = 100 nF
tF
*1
IH
V
VDET
V
P-P
VDD
VDET
*2
VIL
3.0 V
VSS
*1.
VIH = 36.0 V
*2. VIL = VDET(S) 1.0 V (3.0 V min.)
Figure 39 VDD Pin Input Voltage Waveform
Caution Figure 37 and Figure 38 show the input voltage conditions which can maintain the detection
delay time accuracy. If the voltage whose VP-P and tF are larger than these conditions is input to
the VDD pin (VDD detection product), the desired detection delay time may not be achieved.
26
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
5. VDD drop during release delay time (reference)
Figure 40 and Figure 41 show the relation between pulse width (tPW) and VDD lower limit (VDROP) where a release
signal can be output after the normal release delay time has elapsed when the VDD pin (VDD detection product)
instantaneously drops to the detection voltage (VDET) or lower and then increases to the release voltage (VDET) or
higher during release delay time.
S-1011A50
S-1011AA0
Ta = 40C to 85C, CP = CN = 3.3 nF,
Ta = 40C to 85C, CP = CN = 3.3 nF,
10000
10000
1000
100
10
1000
100
10
Inhibited Area
Inhibited Area
1
1
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
VDROP [V]
VDROP [V]
Figure 40
Figure 41
*1
*1
t
F
tPW
t
R
16 V
V
DD
VDET
VDROP
t
DELAY 0.8
t
DELAY
V
OUT
*1. tR = tF = 10 s
Figure 42 VDD Pin Input Voltage Waveform
Caution 1. Figure 40 and Figure 41 show the input voltage conditions when a release signal is output
after the normal release delay time has elapsed. When this is within the inhibited area, release
may erroneously be executed before the delay time completes.
2. When the VDD pin voltage is within the inhibited areas shown in Figure 40 and Figure 41
during release delay time, input 0 V to the VDD pin then restart the S-1011 Series.
27
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
28
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Characteristics (Typical Data)
1. Detection voltage (VDET), Release voltage (VDET) vs. Temperature (Ta)
1. 1 VDD detection product
1. 2 SENSE detection product
S-1011A50
S-1011E50
VDD = 16.0 V
5.40
5.40
VDET
VDET
VDET
5.30
5.20
5.10
5.00
4.90
5.30
5.20
5.10
5.00
4.90
VDET
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
2. Detection voltage (VDET), Release voltage (VDET) vs. Power supply voltage (VDD)
2. 1 SENSE detection product
S-1011E50
5.40
VDET
5.30
5.20
5.10
5.00
4.90
Ta =
40C
25C
Ta =
85C
Ta =
VDET
0.0
6.0 12.0 18.0 24.0 30.0 36.0
V
DD [V]
3. Current consumption (ISS) vs. Power supply voltage (VDD)
3. 1 VDD detection product
S-1011A50
VDD = 0 V 36.0 V
1.50
Ta = +85°C
1.00
0.50
Ta = +25°C
Ta = −40°C
0.00
0.0
6.0 12.0 18.0 24.0 30.0 36.0
V
DD [V]
3. 2 SENSE detection product
S-1011E50 VDD = 0 V 36.0 V,
VSENSE = VDET 0.1 V (during detection)
S-1011E50
VDD = 0 V 36.0 V,
VSENSE = VDET 0.1 V (during release)
1.50
1.00
0.50
0.00
1.50
Ta = −40°C
Ta = +25°C
1.00
0.50
Ta = +25°C
Ta = −40°C
Ta = +85°C
6.0 12.0 18.0 24.0 30.0 36.0
Ta = +85°C
6.0 12.0 18.0 24.0 30.0 36.0
0.00
0.0
0.0
V
DD [V]
VDD [V]
29
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
4. Current consumption (ISS) vs. Temperature (Ta)
4. 1 VDD detection product
4. 2 SENSE detection product
S-1011A50
S-1011E50
V
DD = VDET 0.1 V
VDD = 16.0 V, VSENSE = VDET 0.1 V
1.50
1.00
0.50
0.00
1.50
1.00
0.50
0.00
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
5. Current consumption during detection delay (ISS) vs. Temperature (Ta)
5. 1 VDD detection product
5. 2 SENSE detection product
S-1011A50
V
CN = 0.2 V
S-1011E50
VDD = 16.0 V, VCN = 0.2 V
3.00
3.00
2.00
1.00
0.00
2.00
1.00
0.00
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
6. Current consumption during release delay (ISS) vs. Temperature (Ta)
6. 1 VDD detection product
6. 2 SENSE detection product
S-1011A50
V
CP = 0.2 V
S-1011E50
VDD = 16.0 V, VCP = 0.2 V
3.00
3.00
2.00
1.00
0.00
2.00
1.00
0.00
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
30
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
7. Nch transistor output current (IOUT) vs. VDS
7. 1 SENSE detection product
S-1011E50
S-1011E50
V
DD = VSENSE = 4.5 V, Ta = 40°C
VDD = VSENSE = 4.5 V, Ta = 25°C
30.0
20.0
10.0
0.0
30.0
V
DD = 36.0 V
DD = 16.0 V
DD = 3.0 V
V
DD = 36.0 V
DD = 16.0 V
DD = 3.0 V
20.0
10.0
V
V
V
V
0.0
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.1
0.2
0.3
0.4
0.5
0.6
V
DS [V]
V
DS [V]
S-1011E50
V
DD = VSENSE = 4.5 V, Ta = 85°C
30.0
V
DD = 36.0 V
DD = 16.0 V
DD = 3.0 V
20.0
10.0
V
V
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V
DS [V]
8. Nch transistor output current (IOUT) vs. Power supply voltage (VDD)
8. 1 VDD detection product
8. 2 SENSE detection product
S-1011A50
V
DS = 0.05 V
S-1011E50
VSENSE = 4.5 V, VDS = 0.05 V
2.0
2.5
Ta = −40°C
2.0
1.5
1.0
0.5
0.0
1.5
1.0
Ta = −40°C
Ta = +25°C
Ta = +85°C
Ta = +25°C
0.5
0.0
Ta = +85°C
0.0
5.0
10.0
15.0
0.0
6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
VDD [V]
Remark VDS: Drain-to-source voltage of the output transistor
31
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
9. Minimum operation voltage (VOUT) vs. Power supply voltage (VDD)
9. 1 VDD detection product
S-1011A50
Pull-up to VDD, Pull-up resistance: 100 k
S-1011A50
Pull-up to 16.0 V, Pull-up resistance: 100 k
6.0
5.0
4.0
3.0
2.0
1.0
0.0
20.0
15.0
10.0
5.0
Ta = −40°C
Ta = +25°C
Ta = +85°C
Ta = −40°C
Ta = +25°C
Ta = +85°C
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
DD [V]
VDD [V]
9. 2 SENSE detection product
S-1011E50
VDD = 3.0 V,
S-1011E50
VDD = 3.0 V,
Pull-up to VDD, Pull-up resistance: 100 k
Pull-up to 16.0 V, Pull-up resistance: 100 k
20.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
15.0
10.0
5.0
Ta = −40°C
Ta = +25°C
Ta = −40°C
Ta = +25°C
Ta = +85°C
Ta = +85°C
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
SENSE [V]
VSENSE [V]
32
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
10. Dynamic response vs. Output pin capacitance(COUT) (CP pin, CN pin; open)
10. 1 VDD detection product
S-1011A50
Ta = 40°C
S-1011A50
Ta = 25°C
10
10
t
PHL
PLH
t
PHL
PLH
1
0.1
1
0.1
t
t
0.01
0.01
0.001
0.001
0.00001 0.0001
0.001
0.01
0.1
0.00001 0.0001
0.001
0.01
0.1
Output pin capacitance [F]
Output pin capacitance [F]
S-1011A50
Ta = 85°C
10
t
PHL
PLH
1
0.1
t
0.01
0.001
0.00001 0.0001
0.001
0.01
0.1
Output pin capacitance [F]
1 s
1 s
*1
IH
V
Input voltage
R
100 k
VDD
*2
IL
V
OUT
CN
tPHL
t
PLH
VDD
VDD1
V
DD1
VSS CP
V
V
Output voltage
V
DD1 50%
VDD1 50%
*1. VIH = 36.0 V
*2. VIL = 3.0 V
Figure 43 Test Condition of Response Time
Figure 44 Test Circuit of Response Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
33
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Reference Data
1. Detection delay time (tRESET
1. 1 VDD detection product
) vs. CN pin capacitance (CN) (Without output pin capacitance)
S-1011A50
1000
Ta = 85C
100
10
1
Ta = 25C
Ta = 40C
0.1
0.01
1000
0.1
1
10
100
CN [nF]
2. Detection delay time (tRESET
2. 1 VDD detection product
S-1011A50
)
vs. Temperature (Ta)
CN = 3.3 nF
12.0
10.0
8.0
6.0
4.0
2.0
0.0
40
25
0
25
50
75 85
Ta [C]
1 s
*1
*2
VIH
Input voltage
R
100 k
VDD
VIL
OUT
CN
tRESET
VDD
VDD
VSS CP
V
V
Output voltage
VDD 50%
CN
VSS
*1. VIH = VDET(S) 1.0 V
*2. VIL = VDET(S) 1.0 V
Figure 45 Test Condition of Detection Delay Time
Figure 46 Test Circuit of Detection Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
34
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
3. Detection delay time (tRESET
)
vs. Power supply voltage (VDD)
3. 1 SENSE detection product
S-1011E50
CN = 3.3 nF
12.0
Ta =
+25°C
Ta = +85°C
11.0
10.0
9.0
Ta =
−40°C
8.0
0.0
6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
1 s
*1
VIH
Input voltage
R
100 k
VDD
*2
VIL
OUT
CN
tRESET
SENSE
VSS CP
VDD
VDD
VSS
V
V
VDD 50%
Output voltage
VSENSE
CN
*1. VIH = VDET(S) 1.0 V
*2. VIL = VDET(S) 1.0 V
Figure 47 Test Condition of Detection Delay Time
Figure 48 Test Circuit of Detection Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
35
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
4. Release delay time (tDELAY
4. 1 VDD detection product
) vs. CP pin capacitance (CP) (Without output pin capacitance)
S-1011A50
1000
Ta = 85C
100
Ta = 25C
10
Ta = 40C
1
0.1
0.01
1000
0.1
1
10
100
CP [nF]
5. Release delay time (tDELAY
)
vs. Temperature (Ta)
5. 1 VDD detection product
S-1011A50
CP = 3.3 nF
12.0
10.0
8.0
6.0
4.0
2.0
0.0
40
25
0
25
50
75 85
Ta [C]
1 s
*1
*2
V
IH
Input voltage
R
100 k
VDD
V
IL
t
DELAY
OUT
CN
VDD
V
DD
VSS CP
V
V
Output voltage
V
DD 50%
CP
VSS
*1. VIH = VDET 1.0 V
*2. VIL = VDET 1.0 V
Figure 49 Test Condition of Release Delay Time
Figure 50 Test Circuit of Release Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
36
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
6. Release delay time (tDELAY
)
vs. Power supply voltage (VDD)
6. 1 SENSE detection product
S-1011E50
CP = 3.3 nF
Ta = 85C
12.0
Ta =
25C
11.0
10.0
9.0
Ta =
40C
8.0
0.0
6.0 12.0 18.0 24.0 30.0 36.0
VDD [V]
1 s
*1
V
IH
Input voltage
R
100 k
VDD
*2
V
IL
t
DELAY
OUT
CN
SENSE
VSS CP
VDD
V
DD
V
V
V
DD 50%
Output voltage
VSENSE
CP
VSS
*1. VIH = VDET 1.0 V
*2. VIL = VDET 1.0 V
Figure 51 Test Condition of Release Delay Time
Figure 52 Test Circuit of Release Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
37
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-1011 Series
Rev.1.2_02
Application Circuit Examples
1. Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the minimum operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1011 Series which has the low minimum operation voltage, the high-accuracy detection voltage and
the hysteresis width, reset circuits can be easily constructed as seen in Figure 53 and Figure 54.
VDD
VDD1
VDD1
VDD
VDD
SENSE
OUT
VSS CP CN
VSENSE
Microcomputer
Microcomputer
OUT
VSS CP CN
GND
GND
Figure 53 Example of Reset Circuit
(VDD detection product)
Figure 54 Example of Reset Circuit
(SENSE detection product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
38
HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
Thermal Characteristics
1. SOT-23-6
T
j
= 125C max.
1.0
Board 2
0.81 W
0.8
0.6
0.4
0.2
0
Board 1
0.63 W
0
50
100
150
Ambient temperature (Ta) [C]
Figure 55 Power Dissipation of Package (When Mounted on Board)
Table 21
1. 1 Board 1*1
76.2 mm
Item
Specification
Thermal resistance value
(ja)
159C/W
Size
114.3 mm 76.2 mm t1.6 mm
Material
FR-4
Number of copper foil layer
1
2
Land pattern and wiring for testing: t0.070 mm
2
Copper foil layer
3
4
74.2 mm 74.2 mm t0.070 mm
Thermal via
Figure 56
1. 2 Board 2*1
76.2 mm
Table 22
Specification
124C/W
Item
Thermal resistance value
(ja)
Size
114.3 mm 76.2 mm t1.6 mm
Material
FR-4
Number of copper foil layer
1
4
Land pattern and wiring for testing: t0.070 mm
74.2 mm 74.2 mm t0.035 mm
74.2 mm 74.2 mm t0.035 mm
74.2 mm 74.2 mm t0.070 mm
2
Copper foil layer
3
4
Thermal via
Figure 57
*1. The board is same in SOT-23-3, SOT-23-5 and SOT-23-6.
39
2.9±0.2
1.9±0.2
6
5
4
+0.1
-0.05
1
3
2
0.15
0.95
0.95
0.35±0.15
No. MP006-A-P-SD-2.1
TITLE
SOT236-A-PKG Dimensions
MP006-A-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
-0
2.0±0.05
0.25±0.1
ø1.5
+0.2
-0
ø1.0
4.0±0.1
1.4±0.2
3.2±0.2
3
4
2 1
6
5
Feed direction
No. MP006-A-C-SD-3.1
TITLE
SOT236-A-Carrier Tape
MP006-A-C-SD-3.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP006-A-R-SD-2.1
TITLE
SOT236-A-Reel
MP006-A-R-SD-2.1
No.
ANGLE
UNIT
QTY
3,000
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5. When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9. Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.2-2018.06
www.ablic.com
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