S-8206AAJ-I6T1U [ABLIC]

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION);


型号：	S-8206AAJ-I6T1U
厂家：	ABLIC
描述：	BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)
文件：	总28页 (文件大小：796K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S-8206A Series

BATTERY PROTECTION IC FOR 1-CELL PACK

(SECONDARY PROTECTION)

www.ablic.com

Rev.1.4_00

The S-8206A Series is used for secondary protection of lithium-ion / lithium polymer rechargeable batteries, and incorporates a

high-accuracy voltage detection circuit and a delay circuit.

 Features

• High-accuracy voltage detection circuit

Overcharge detection voltage

Overcharge release voltage

3.500 V to 5.000 V (5 mV step)

3.100 V to 4.950 V^*1

Accuracy ±20 mV

Accuracy ±50 mV

• Detection delay time is generated only by an internal circuit (external capacitors are unnecessary).

• Output logic is selectable:

• Output form is selectable:

• Wide operation temperature range

• Low current consumption

During operation:

Active "H", active "L"

CMOS output, Nch open-drain output

Ta = −40°C to +85°C

1.5 µA typ., 3.0 µA max. (Ta = +25°C)

• Lead-free (Sn 100%), halogen-free

*1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage

(Overcharge hysteresis voltage can be selected from a range of 0.05 V to 0.4 V in 50 mV step.)

 Applications

• Lithium-ion rechargeable battery pack

• Lithium polymer rechargeable battery pack

 Packages

• SNT-6A

• HSNT-6 (1212)

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Block Diagram

1. CMOS output, active "H"

VDD

Overcharge detection

comparator

Control logic

Delay circuit

Oscillator

VSS

Figure 1

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

2. CMOS output, active "L"

VDD

Overcharge detection

comparator

Control logic

Delay circuit

Oscillator

VSS

Figure 2

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

3. Nch open-drain output

VDD

Overcharge detection

comparator

Control logic

Delay circuit

VSS

Oscillator

Figure 3

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Product Name Structure

1. Product name

S-8206A xx

xxxx

Environmental code

Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specifications^*1

I6T1: SNT-6A, Tape

A6T2: HSNT-6 (1212), Tape

Serial code^*2

Sequentially set from AA to ZZ

*1. Refer to the tape drawing.

*2. Refer to "3. Product name list".

2. Packages

Table 1 Package Drawing Codes

Package Name

SNT-6A

HSNT-6 (1212)

Dimension

Tape

Reel

Land

PG006-A-P-SD

PM006-A-P-SD

PG006-A-C-SD

PM006-A-C-SD

PG006-A-R-SD

PM006-A-R-SD

PG006-A-L-SD

PM006-A-L-SD

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

3. Product name list

3. 1 SNT-6A

Table 2

Overcharge

Detection Voltage

Overcharge

Release Voltage

[V_CL]

Overcharge Detection

Delay Time^*1

Product Name

Output Logic^*2

Output Form^*3

[V_CU

]

[t_CU]

S-8206AAA-I6T1U

S-8206AAB-I6T1U

S-8206AAC-I6T1U

S-8206AAD-I6T1U

S-8206AAE-I6T1U

S-8206AAF-I6T1U

S-8206AAG-I6T1U

S-8206AAH-I6T1U

S-8206AAI-I6T1U

S-8206AAJ-I6T1U

S-8206AAL-I6T1U

4.500 V

4.550 V

4.150 V

4.250 V

4.150 V

4.250 V

4.450 V

4.400 V

4.350 V

4.570 V

4.600 V

4.150 V

4.200 V

4.000 V

4.100 V

4.000 V

4.100 V

4.150 V

4.100 V

4.050 V

4.220 V

4.250 V

2 s

Active "H"

Active "L"

Active "H"

CMOS output

Nch open-drain output

CMOS output

*1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable.

*2. Output logic active "H" / active "L" is selectable.

*3. Output form CMOS output / Nch open-drain output is selectable.

Remark Please contact our sales office for the products other than those specified above.

3. 2 HSNT-6 (1212)

Table 3

Overcharge

Detection Voltage

Overcharge

Release Voltage

[V_CL]

Overcharge Detection

Delay Time^*1

Product Name

Output Logic^*2

Output Form^*3

[V_CU

]

[t_CU]

S-8206AAA-A6T2U

S-8206AAB-A6T2U

4.500 V

4.550 V

4.150 V

4.200 V

2 s

Active "H"

CMOS output

*1. Overcharge detection delay time 1 s / 2 s / 4 s is selectable.

*2. Output logic active "H" / active "L" is selectable.

*3. Output form CMOS output / Nch open-drain output is selectable.

Remark Please contact our sales office for the products other than those specified above.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Pin Configurations

1. SNT-6A

Table 4

No connection

Pin No.

Symbol

NC^*1

Description

Connection pin of charge control FET gate

Input pin for test signal

Figure 4

VSS

Input pin for negative power supply

VDD

Input pin for positive power supply

Negative power supply pin for CO pin

*1. The NC pin is electrically open.

The NC pin can be connected to VDD pin or VSS pin.

2. HSNT-6 (1212)

Table 5

Pin No.

Symbol

Description

NC^*2

No connection

Connection pin of charge control FET gate

Input pin for test signal

VSS

VDD

Input pin for negative power supply

Input pin for positive power supply

Negative power supply pin for CO pin

Figure 5

*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VDD.

However, do not use it as the function of electrode.

*2. The NC pin is electrically open.

The NC pin can be connected to VDD pin or VSS pin.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Absolute Maximum Ratings

Table 6

(Ta = +25°C unless otherwise specified)

Item

Symbol

V_DS

Applied Pin

VDD

Absolute Maximum Rating

Unit

Input voltage between VDD pin and VSS pin

VM pin input voltage

V_SS− 0.3 to V_SS+ 6

V_DD− 28 to V_DD+ 0.3

V_SS− 0.3 to V_DD+ 0.3

V_VM− 0.3 to V_DD+ 0.3

V_VM− 0.3 to V_VM+ 28

400^*1

V_VM

V_DO

DO pin input voltage

CMOS output

Nch open-drain output

SNT-6A

CO pin output

voltage

V_CO

P_D

−

°C

Power dissipation

HSNT-6 (1212)

480^*1

Operation ambient temperature

Storage temperature

T_opr

T_stg

−40 to +85

−55 to +125

*1. When mounted on board

[Mounted board]

(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm

(2) Board name: JEDEC STANDARD51-7

Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical

damage. These values must therefore not be exceeded under any conditions.

700

600

HSNT-6 (1212)

500

SNT-6A

400

300

200

100

150

Ambient Temperature (Ta) [°C]

Figure 6 Power Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Electrical Characteristics

1. Ta = +25°C

Table 7

(Ta = +25°C unless otherwise specified)

Test

Circuit

Item

Detection Voltage

Symbol

Condition

Min.

Typ.

Max.

Unit

−

V_CU− 0.020

V_CU− 0.025

V_CL− 0.050

V_CU

V_CL

V_CU+ 0.020

V_CU+ 0.025

V_CL+ 0.050

V_CU

V_CL

Overcharge detection voltage

Ta = −10°C to +60°C^*1

−

Overcharge release voltage

Input Voltage

Operation voltage between VDD pin and

VSS pin

V_DSOP

1.5

−

6.0

3.0

−

Input Current

I_OPE

V_DD= 3.4 V, V_VM= 0 V

−

1.5

µA

Current consumption during operation

Output Resistance

R_COH1CMOS output

−

kΩ

MΩ

CO pin resistance "H" 1

CO pin resistance "L" 1

DO pin resistance "H"

DO pin resistance "L"

CO pin resistance "H" 2

CO pin resistance "L" 2

Output Current

R_COL1

R_DOH

R_DOL

−

R_COH2CMOS output, active "L"

R_COL2CMOS output, active "H"

−

I_COLL

Nch open-drain output

−

0.1

µA

CO pin leakage current "L"

Delay Time

t_CU

Overcharge detection delay time

−

t_CU× 0.7

t_CU× 1.3

−

*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by

design, not tested in production.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Test Circuits

Caution 1. Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (V_CO) are judged by the

threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to V_VM

2. Set SW to ON and OFF in Nch open-drain output and CMOS output, respectively.

1. Overcharge detection voltage, overcharge release voltage

(Test circuit 1)

1. 1 Active "H"

Overcharge detection voltage (V_CU) is defined as the voltage V1 at which V_COgoes from "L" to "H" when the voltage

V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (V_CL) is defined as

the voltage V1 at which V_COgoes from "H" to "L" when the voltage V1 is then gradually decreased. Overcharge

hysteresis voltage (V_HC) is defined as the difference between V_CUand V_CL.

1. 2 Active "L"

Overcharge detection voltage (V_CU) is defined as the voltage V1 at which V_COgoes from "H" to "L" when the

voltage V1 is gradually increased from the starting condition of V1 = 3.4 V. Overcharge release voltage (V_CL) is

defined as the voltage V1 at which V_COgoes from "L" to "H" when the voltage V1 is then gradually decreased.

Overcharge hysteresis voltage (V_HC) is defined as the difference between V_CUand V_CL.

2. Current consumption during operation

(Test circuit 2)

The current consumption during operation (I_OPE) is the current that flows through VDD pin (I_DD) under the set condition of

V1 = 3.4 V.

3. CO pin resistance "H" 1 (CMOS output)

(Test circuit 3)

3. 1 Active "H"

The CO pin resistance "H" 1 (R_COH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V,

V2 = 4.7 V.

3. 2 Active "L"

The CO pin resistance "H" 1 (R_COH1) is the resistance between VDD pin and CO pin under the set conditions of V1 = 3.4 V,

V2 = 3.0 V.

4. CO pin resistance "L" 1

(Test circuit 3)

4. 1 Active "H"

The CO pin resistance "L" 1 (R_COL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 3.4 V,

V2 = 0.4 V.

4. 2 Active "L"

The CO pin resistance "L" 1 (R_COL1) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V,

V2 = 0.4 V.

5. DO pin resistance "H"

(Test circuit 3)

The DO pin resistance "H" (R_DOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = 3.4 V,

V3 = 3.0 V.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

6. DO pin resistance "L"

(Test circuit 3)

The DO pin resistance "L" (R_DOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = 1.8 V,

V3 = 0.4 V.

7. CO pin resistance "H" 2 (CMOS output, active "L")

(Test circuit 3)

The CO pin resistance "H" 2 (R_COH2) is the resistance between VDD pin and CO pin under the set conditions of V1 = 5.1 V,

V2 = 0 V.

8. CO pin resistance "L" 2 (CMOS output, active "H")

(Test circuit 3)

The CO pin resistance "L" 2 (R_COL2) is the resistance between VM pin and CO pin under the set conditions of V1 = 5.1 V,

V2 = 5.1 V.

9. CO pin leakage current "L" (Nch open-drain output)

(Test circuit 3)

9. 1 Active "H"

The CO pin leakage current "L" (I_COLL) is the current that flows through CO pin (I_CO) under the set conditions of

V1 = 5.1 V, V2 = 28 V.

9. 2 Active "L"

The CO pin leakage current "L" (I_COLL) is the current that flows through CO pin (I_CO) under the set conditions of

V1 = 3.4 V, V2 = 28 V.

10. Overcharge detection delay time

(Test circuit 4)

10. 1 Active "H"

The overcharge detection delay time (t_CU) is the time needed for V_COto go to "H" just after the voltage V1 increases

and exceeds V_CUunder the set condition of V1 = 3.4 V.

10. 2 Active "L"

The overcharge detection delay time (t_CU) is the time needed for V_COto go to "L" just after the voltage V1 increases

and exceeds V_CUunder the set condition of V1 = 3.4 V.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

I_DD

R1 = 330 Ω

VDD

VSS

VDD

S-8206A Series

VSS

C1 = 0.1 µF

V V_DOV V_CO

COM

Figure 7 Test Circuit 1

Figure 8 Test Circuit 2

VDD

S-8206A Series

VSS

A I_DO

A I_CO

Oscilloscope Oscilloscope

COM

Figure 9 Test Circuit 3

Figure 10 Test Circuit 4

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Operation

Remark Refer to " Battery Protection IC Connection Example".

1. Overcharge detection status

The S-8206A Series monitors the voltage of the battery connected between VDD pin and VSS pin to detect overcharge.

When the battery voltage exceeds the overcharge detection voltage (V_CU) during charging in the normal status and the

condition continues for the overcharge detection delay time (t_CU) or longer, the S-8206A Series outputs overcharge

detection signal from the CO pin. This condition is called overcharge status. Connecting FET to the CO pin provides

charge control and a second protection.

2. Test mode

t_CUcan be shortened by forcibly setting the DO pin to V_SSlevel from external. When the DO pin is forcibly set to V_SSlevel

from external, t_CUwill be shortened to approximately 1/64.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Timing Charts

1. Overcharge detection

V_CU

V_CL(V_CU− V_HC

)

Battery voltage

V_DD

CO pin voltage

CMOS output

Active "H"

V_VM

V_DD

CO pin voltage

CMOS output

Active "L"

V_VM

V_DD

CO pin voltage

Nch open-drain output

Active "H"

High-Z

V_VM

V_DD

CO pin voltage

Nch open-drain output

Active "L"

High-Z

V_VM

Overcharge detection delay time (t_CU)

(2)

(1)

Status^*1

*1. (1): Normal status

(2): Overcharge status

Figure 11

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Battery Protection IC Connection Example

Figure 12 shows the connection example when CMOS output, active "H" product is used.

SCP

EB+

VDD

Battery

S-8206A Series

FET

VSS

EB−

Figure 12

Table 8 Constants for External Components

Symbol

FET

Part

Purpose

Min.

Typ.

Max.

Remark

N-channel

MOS FET

Charge control

−

ESD protection,

For power fluctuation

Resistor

150 Ω

330 Ω

1 kΩ

−

Capacitor For power fluctuation

0.068 µF 0.1 µF

1.0 µF

Caution 1. The above constants may be changed without notice.

2. It has not been confirmed whether the operation is normal or not in circuits other than the above

example of connection. In addition, the example of connection shown above and the constants do not

guarantee proper operation. Perform thorough evaluation using the actual application to set the

constants.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

[For SCP, contact]

Global Sales & Marketing Division, Dexerials Corporation

Gate City Osaki East Tower 8F, 1-11-2

Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan

TEL +81-3-5435-3946

 Precautions

• The application conditions for the input voltage, output voltage, and load current should not exceed the package power

dissipation.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic

protection circuit.

• ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by

products including this IC of patents owned by a third party.

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Characteristics (Typical Data)

1. Current consumption

1. 1 I_OPEvs. Ta

2. Detection voltage

2. 1 V_CUvs. Ta

2. 2 V_CLvs. Ta

3. Delay time

3. 1 t_CUvs. Ta

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

4. Output resistance

4. 1 R_COH1vs. V_CO

4. 2 R_COL1vs. V_CO

4. 3 R_DOHvs. V_DO

4. 4 R_DOLvs. V_DO

BATTERY PROTECTION IC FOR 1-CELL PACK (SECONDARY PROTECTION)

S-8206A Series

Rev.1.4_00

 Marking Specifications

1. SNT-6A

(1) to (3):

(4) to (6):

Product code (refer to Product name vs. Product code)

Lot number

Product name vs. Product code

Product Code

Product Name

(1)

(2)

(3)

S-8206AAA-I6T1U

S-8206AAB-I6T1U

S-8206AAC-I6T1U

S-8206AAD-I6T1U

S-8206AAE-I6T1U

S-8206AAF-I6T1U

S-8206AAG-I6T1U

S-8206AAH-I6T1U

S-8206AAI-I6T1U

S-8206AAJ-I6T1U

S-8206AAL-I6T1U

2. HSNT-6 (1212)

(1) to (3):

(4), (5):

Product code (refer to Product name vs. Product code)

Lot number

Product name vs. Product code

Product Code

Product Name

(1)

(2)

(3)

S-8206AAA-A6T2U

S-8206AAB-A6T2U

1.57±0.03

+0.05

-0.02

0.08

0.5

0.48±0.02

0.2±0.05

No. PG006-A-P-SD-2.1

SNT-6A-A-PKG Dimensions

PG006-A-P-SD-2.1

TITLE

No.

ANGLE

UNIT

ABLIC Inc.

+0.1

-0

ø1.5

4.0±0.1

2.0±0.05

0.25±0.05

+0.1

ø0.5

-0

4.0±0.1

0.65±0.05

1.85±0.05

Feed direction

No. PG006-A-C-SD-2.0

TITLE

SNT-6A-A-Carrier Tape

PG006-A-C-SD-2.0

No.

ANGLE

UNIT

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

No. PG006-A-R-SD-1.0

SNT-6A-A-Reel

TITLE

No.

PG006-A-R-SD-1.0

ANGLE

UNIT

5,000

QTY.

ABLIC Inc.

0.52

1.36

0.52

0.3

0.2

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

0.03 mm

SNT

1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).

2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).

Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.

2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm

or less from the land pattern surface.

3. Match the mask aperture size and aperture position with the land pattern.

4. Refer to "SNT Package User's Guide" for details.

(0.25 mm min. / 0.30 mm typ.)

(1.30 mm ~ 1.40 mm)

SNT-6A-A

-Land Recommendation

TITLE

No. PG006-A-L-SD-4.1

No.

PG006-A-L-SD-4.1

ANGLE

UNIT

ABLIC Inc.

1.00±0.05

0.38±0.02

0.40

+0.05

-0.02

0.08

1.20±0.04

The heat sink of back side has different electric

potential depending on the product.

Confirm specifications of each product.

Do not use it as the function of electrode.

0.20±0.05

No. PM006-A-P-SD-1.1

TITLE

HSNT-6-B-PKG Dimensions

No.

PM006-A-P-SD-1.1

ANGLE

UNIT

ABLIC Inc.

4.0±0.1

2.0±0.05

+0.1

-0

ø1.5

0.25±0.05

+0.1

-0

ø0.5

0.50±0.05

4.0±0.1

1.32±0.05

Feed direction

No. PM006-A-C-SD-2.0

TITLE

HSNT-6-B-Carrier Tape

PM006-A-C-SD-2.0

No.

ANGLE

UNIT

ABLIC Inc.

+1.0

- 0.0

9.0

11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

No. PM006-A-R-SD-1.0

TITLE

HSNT-6-B-Reel

No.

PM006-A-R-SD-1.0

ANGLE

5,000

QTY.

UNIT

ABLIC Inc.

1.04min.

Land Pattern

0.24min.

1.02

0.40±0.02 0.40±0.02

(1.22)

Caution It is recommended to solder the heat sink to a board

in order to ensure the heat radiation.

PKG

Metal Mask Pattern

Aperture ratio

Caution

Mask aperture ratio of the lead mounting part is 100%.

Mask aperture ratio of the heat sink mounting part is 40%.

Mask thickness: t0.10mm to 0.12 mm

100%

40%

t0.10mm ~ 0.12 mm

HSNT-6-B

TITLE

-Land Recommendation

No.

PM006-A-L-SD-2.0

ANGLE

UNIT

No. PM006-A-L-SD-2.0

ABLIC Inc.

Disclaimers (Handling Precautions)

1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and

application circuit examples, etc.) is current as of publishing date of this document and is subject to change without

notice.

2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of

any specific mass-production design.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products

described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other

right due to the use of the information described herein.

3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described

herein.

4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute

maximum ratings, operation voltage range and electrical characteristics, etc.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to

the use of the products outside their specified ranges.

5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they

are used and verify suitability, safety and other factors for the intended use.

6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related

laws, and follow the required procedures.

7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of

weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands

caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,

biological or chemical weapons or missiles, or use any other military purposes.

8. The products are not designed to be used as part of any device or equipment that may affect the human body, human

life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control

systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,

aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by

ABLIC, Inc. Do not apply the products to the above listed devices and equipments.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of

the products.

9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should

therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread

prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social

damage, etc. that may ensue from the products' failure or malfunction.

The entire system in which the products are used must be sufficiently evaluated and judged whether the products are

allowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the

product design by the customer depending on the intended use.

11. The products do not affect human health under normal use. However, they contain chemical substances and heavy

metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be

careful when handling these with the bare hands to prevent injuries, etc.

12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.

13. The information described herein contains copyright information and know-how of ABLIC Inc. The information

described herein does not convey any license under any intellectual property rights or any other rights belonging to

ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this

document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express

permission of ABLIC Inc.

14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales

representative.

15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into

the English language and the Chinese language, shall be controlling.

2.4-2019.07

www.ablic.com

S-8206AAJ-I6T1U [ABLIC]

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