S-8224AAS-I8T1U [ABLIC]
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION);
| 型号： | S-8224AAS-I8T1U |
| 厂家： | 
ABLIC |
| 描述： | BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) |
| 文件： | 总33页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8224A/B Series
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK
(SECONDARY PROTECTION)
www.ablic.com
© ABLIC Inc., 2017-2018
Rev.1.3_00
The S-8224A/B Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy
voltage detection circuits and delay circuits.
Short-circuits between cells accommodate series connection of two cells to four cells.
The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be
used.
Features
• High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n = 1 to 4)
3.600 V to 4.700 V (50 mV step)
Accuracy 20 mV (Ta = +25°C)
Accuracy 25 mV (Ta = −10°C to +60°C)
Overcharge hysteresis voltage n (n = 1 to 4)*1
0.0 mV to −550 mV (50 mV step)
−300 mV to −550 mV
−100 mV to −250 mV
−50 mV
Accuracy 20%
Accuracy 50 mV
Accuracy 25 mV
0.0 mV
Accuracy −25 mV to +20 mV
• Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary)
Overcharge detection delay time is selectable:
Overcharge release delay time is selectable:
• Built-in timer reset delay circuit
1 s, 2 s, 4 s, 6 s, 8 s
2 ms, 64 ms
• Output control function via CTL pin
• Output form is selectable (S-8224A Series):
• Output logic is selectable (S-8224A Series):
CMOS output, Nch open-drain output
Active "H", active "L"
• CO pin output voltage is limited to 11.5 V max. (S-8224B Series)*2
• High-withstand voltage:
Absolute maximum rating 28 V
• Wide operation voltage range:
3.6 V to 28 V
• Wide operation temperature range:
• Low current consumption
Ta = −40°C to +85°C
During operation (VCU − 1.0 V for each cell):
During overdischarge (VCU × 0.5 V for each cell):
• Lead-free (Sn 100%), halogen-free
0.25 μA typ., 0.6 μA max. (Ta = +25°C)
0.3 μA max. (Ta = +25°C)
*1. Select the overcharge hysteresis voltage calculated as the following formula.
(Overcharge detection voltage n) + (Overcharge hysteresis voltage n) ≥ 3.4 V
*2. Only output logic active "H" is available.
Application
• Lithium-ion rechargeable battery packs (for secondary protection)
Package
• SNT-8A
1
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Block Diagrams
1. S-8224A Series
1. 1 CMOS output product
VDD
VC1
Overcharge detection
comparator 1
+
−
VC2
VC3
VC4
VSS
Overcharge detection
comparator 2
+
−
CO
Control logic
Delay circuit
Oscillator
Overcharge detection
comparator 3
+
−
Overcharge detection
comparator 4
+
−
CO pin output
CTL
control circuit
Figure 1
2
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
1. 2 Nch open-drain output product
VDD
VC1
Overcharge detection
comparator 1
+
−
VC2
VC3
VC4
Overcharge detection
comparator 2
+
−
CO
Control logic
Delay circuit
Oscillator
Overcharge detection
comparator 3
+
−
Overcharge detection
comparator 4
+
−
VSS
CO pin output
control circuit
CTL
Figure 2
3
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
2. S-8224B Series
VDD
VC1
Overcharge detection
comparator 1
+
−
VC2
VC3
VC4
Overcharge detection
comparator 2
+
−
CO pin output voltage
limit circuit
CO
Control logic
Delay circuit
Oscillator
Overcharge detection
comparator 3
+
−
Overcharge detection
comparator 4
+
−
VSS
CO pin output
control circuit
CTL
Figure 3
4
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Product Name Structure
1. Product name
S-8224
x
xx
-
xxxx
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
I8T1: SNT-8A, Tape
Serial code*2
Sequentially set from AA to AZ
Product type
A:
B:
CMOS output, Nch open-drain output
CO pin output voltage 11.5 V max.
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name
SNT-8A
Dimension
PH008-A-P-SD
Tape
Reel
Land
PH008-A-C-SD
PH008-A-R-SD
PH008-A-L-SD
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BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
3. Product name list
3. 1 S-8224A Series
Table 2
Overcharge
Detection
Voltage
Overcharge
Hysteresis
Voltage
Overcharge
Detection
Overcharge
Release
Product Name
Output Form*3
Output Logic*4
Delay Time*1
Delay Time*2
[tCL]
[VCU
]
[VHC
]
[tCU
4 s
4 s
4 s
6 s
6 s
6 s
6 s
6 s
4 s
2 s
]
S-8224AAS-I8T1U
S-8224AAT-I8T1U
S-8224AAU-I8T1U
S-8224AAV-I8T1U
S-8224AAW-I8T1U
S-8224AAX-I8T1U
S-8224ABA-I8T1U
S-8224ABB-I8T1U
S-8224ABC-I8T1U
S-8224ABD-I8T1U
4.450 V
4.350 V
4.500 V
4.550 V
4.450 V
4.350 V
4.400 V
4.500 V
4.600 V
4.300 V
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
−400 mV
64 ms
64 ms
64 ms
64 ms
64 ms
64 ms
64 ms
64 ms
64 ms
64 ms
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
*1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable.
*2. Overcharge release delay time 2 ms / 64 ms is selectable.
*3. Output form CMOS output / Nch open-drain output is selectable.
*4. Output logic active "H" / active "L" is selectable.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
3. 2 S-8224B Series
Table 3
Overcharge
Detection
Voltage
Overcharge
Hysteresis
Voltage
Overcharge
Detection
Overcharge
Release
Delay Time*2
[tCL]
Product Name
Output Logic*3
Delay Time*1
[VCU
]
[VHC
]
[tCU
4 s
6 s
4 s
]
S-8224BAA-I8T1U
S-8224BAB-I8T1U
S-8224BAC-I8T1U
4.350 V
4.450 V
4.350 V
−400 mV
−400 mV
−400 mV
2 ms
Active "H"
Active "H"
Active "H"
64 ms
64 ms
*1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable.
*2. Overcharge release delay time 2 ms / 64 ms is selectable.
*3. Only output logic active "H" is available.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
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BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Pin Configuration
1. SNT-8A
Top view
Table 4
Pin No. Symbol
Description
Positive power supply input pin
1
2
3
4
8
7
6
5
1
2
VDD
VC1
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power supply input pin
3
4
5
6
VC2
VC3
VC4
VSS
Figure 4
Negative voltage connection pin of battery 4
CO pin output control pin
7
8
CTL
CO
FET gate connection pin for charge control
7
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Absolute Maximum Ratings
Table 5
Symbol
(Ta = +25°C unless otherwise specified)
Item
Applied Pin
Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin
VDS
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VSS
−
−
−
−
−
0.3 to VSS
0.3 to VSS
28 to VDD
0.3 to VDD
0.3 to VDD
0.3 to VSS
0.3 to VDD
+
+
+
+
+
+
+
28
28
V
V
V
V
V
V
V
VC1
Input pin voltage
VIN
VC2, VC3, VC4
CTL
0.3
0.3
0.3
28
CMOS output
Nch open-drain output
S-8224A Series
S-8224B Series
CO pin output
voltage
VCO
CO
−
−
0.3
Operation ambient temperature
Storage temperature
Topr
Tstg
−
−
−
40 to
+
85
°
°
C
C
−
40 to
+
125
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 6
Item
Symbol
Condition
Board A
Min.
−
−
−
−
Typ.
211
173
−
−
−
Max.
Unit
−
−
−
−
−
°C/W
°C/W
°C/W
°C/W
°C/W
Board B
Board C
Board D
Board E
Junction-to-ambient thermal resistance*1 θJA
SNT-8A
−
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
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BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Electrical Characteristics
Table 7
(Ta = +25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Detection voltage
VCU
− 0.020
VCU
VCU
+ 0.020
VCU
Ta = +25°C
Ta = −10°C to +60°C*1
VCU
VCU
V
1
Overcharge detection voltage n
(n = 1, 2, 3, 4)
VCUn
VHCn
VDSOP
V
V
V
1
1
1
− 0.025
+ 0.025
−550 mV
−250 mV
≤
≤
VHC
VHC
≤
≤
−300 mV
−100 mV
VHC
×
1.2
VHC VHC × 0.8
VHC
− 0.050
VHC
− 0.025
VHC
VHC
+ 0.050
VHC
+ 0.025
VHC
VHC
VHC
VHC
Overcharge hysteresis voltage n
(n = 1, 2, 3, 4)
VHC = −50 mV
V
V
1
1
VHC = 0.0 mV
− 0.025
+ 0.020
Input voltage
Operation voltage between
VDD pin and VSS pin
CTL pin input voltage "H"
CTL pin input voltage "L"
Output voltage
−
3.6
−
28
V
−
VCTLH
VCTLL
−
−
VDD × 0.95
−
−
−
V
V
2
2
−
VDD × 0.4
CO pin output voltage "H"
Input Current
VCOH
S-8224B Series
5.0
8.0
11.5
V
2
Current consumption
during operation
V1 = V2 = V3 = V4
= VCU − 1.0 V
V1 = V2 = V3 = V4
= VCU × 0.5 V
V1 = V2 = V3 = V4
= VCU − 1.0 V
V1 = V2 = V3 = V4
= VCU − 1.0 V
−
IOPE
IOPED
IVC1
−
−
0.25
0.6
0.3
0.3
0.3
μA
μA
μA
μA
3
3
4
4
Current consumption
during overdischarge
−
−
0
VC1 pin input current
−
VCn pin input current
(n = 2, 3, 4)
IVCn
−0.3
CTL pin input current "H"
CTL pin input current "L"
Output Current
ICTLH
ICTLL
0.6
1.3
2.0
μA
μA
4
4
−
−0.15
−
−
S-8224A Series
CO pin source current
ICOH
(CMOS output product),
S-8224B Series
−
−
−20
μA
5
CO pin sink current
CO pin leakage current
Delay Time
ICOL
−
20
−
−
−
μA
μA
5
5
S-8224A Series
(Nch open-drain output product)
ICOLL
−
0.1
Overcharge detection delay time tCU
Overcharge release delay time tCL
Overcharge timer reset delay time tTR
−
tCU × 0.8
tCU
2.0
64
12
−
tCU × 1.2
3.0
s
1
1
1
1
2
1
t
CL = 2 ms
1.6
51.2
6
ms
ms
ms
ms
ms
tCL = 64 ms
76.8
20
−
−
−
CTL pin response delay time
Transition time to test mode
tCTL
tTST
−
−
2.5
−
10
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
9
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Test Circuits
1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
1. 1 Overcharge detection voltage n (VCUn
)
Set V0 = 0 V, V1 = V2 = V3 = V4 = VCU − 0.05 V in test circuit 1. The overcharge detection voltage 1 (VCU1) is the V1
voltage when the CO pin output inverts after the voltage of V1 has been gradually increased.
Overcharge detection voltage (VCUn) (n = 2 to 4) can be determined in the same way as when n = 1.
1. 2 Overcharge hysteresis voltage n (VHCn
)
Set V0 = 0 V, V1 = VCU + 0.05 V, V2 = V3 = V4 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference
between V1 voltage and VCU1 when the CO pin output inverts again after the V1 voltage has been gradually
decreased.
Overcharge hysteresis voltage (VHCn) (n = 2 to 4) can be determined in the same way as when n = 1.
2. CTL pin input voltage (Test circuit 2)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
2. 1 CTL pin input voltage "H" (VCTLH
)
Set V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V. The CTL pin input voltage "H" (VCTLH) is the V5 voltage when the CO pin
output inverts after the voltage of V5 has been gradually increased.
2. 2 CTL pin input voltage "L" (VCTLL
)
Set V5 =14 V. The CTL pin input voltage "L" (VCTLL) is the V5 voltage when the CO pin output inverts after the voltage
of V5 has been gradually decreased.
3. Output voltage (S-8224B Series) (Test circuit 2)
3. 1 CO pin output voltage "H"
The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V1 = V2 = V3 = V4 =
3.5 V, V5 = 0 V.
4. Input current (Test circuit 4)
4. 1 CTL pin input current "H" (ICTLH
)
Set SW2 and SW3 to ON and OFF, respectively.
The CTL pin input current "H" (ICTLH) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V.
4. 2 CTL pin input current "L" (ICTLL
)
Set SW2 and SW3 to OFF and ON, respectively.
The CTL pin input current "L" (ICTLL) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V.
10
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
5. Output current (Test circuit 5)
5. 1 CMOS output product in S-8224A Series
Set SW4 and SW5 to OFF.
5. 1. 1 Active "H"
(1) CO pin source current (ICOH
)
Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH
)
at that time.
(2) CO pin sink current (ICOL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at
that time.
5. 1. 2 Active “L”
(1) CO pin source current (ICOH
)
Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH
)
at that time.
(2) CO pin sink current (ICOL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at
that time.
5. 2 Nch open-drain output product in S-8224A Series
Set SW4 and SW5 to OFF.
5. 2. 1 Active "H"
(1) CO pin leakage current (ICOLL
)
Set SW5 to ON after setting V1 to V4 = 7 V, V5 = 0 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL
)
at that time.
(2) CO pin sink current (ICOL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at
that time.
5. 2. 2 Active "L"
(1) CO pin leakage current (ICOLL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL
at that time.
)
(2) CO pin sink current (ICOL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at
that time.
5. 3 S-8224B Series
Set SW4 and SW5 to OFF.
5. 3. 1 CO pin source current (ICOH
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = VCOH − 0.5 V. I2 is the CO pin source current
(ICOH) at that time.
5. 3. 2 CO pin sink current (ICOL
)
Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that
time.
11
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
6. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. The overcharge detection delay time (tCU) is the
time period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL)
is the time period until the CO pin output inverts.
7. CTL pin response delay time (tCTL) (Test circuit 2)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
Decrease V5 down to 0 V after setting V1 = V2 = V3 = V4 = 3.5 V, V5 = 14 V. The CTL pin response delay time (tCTL) is
the time period until the CO pin output inverts.
8. Overcharge timer reset delay time (tTR) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after
setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time
period until the CO pin output inverts.
When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since the
first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise.
The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time.
9. Transition time to test mode (tTST) (Test circuit 1)
Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in
Nch open-drain output product of the S-8224A Series.
Increase V0 up to 8.5 V, and decrease V0 again to 0 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V.
When the period from when V0 was raised to when it has fallen is short, if an overcharge detection operation is
performed subsequently, the delay time is tCU. However, when the period from when V0 is raised to when it has fallen is
gradually made longer, the delay time during the subsequent overcharge detection operation is shorter than tCU. The
transition time to test mode (tTST) is the period from when V0 was raised to when it has fallen at that time.
12
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
100 kΩ
100 kΩ
SW1
SW1
S-8224A/B Series
S-8224A/B Series
VDD
CO
CTL
VSS
VDD
CO
CTL
VSS
V0
V1
V2
VC1
VC2
VC1
VC2
V
V
V1
V2
V5
V4
V4
VC3
VC4
VC3
VC4
V3
V3
Figure 5 Test Circuit 1
Figure 6 Test Circuit 2
SW2
ICTLH
IOPE
IOPED
S-8224A/B Series
S-8224A/B Series
A
A
VDD
VC1
VC2
CO
CTL
VSS
VDD
VC1
VC2
CO
CTL
VSS
IVC1
A
ICTLL
A
IVC2
SW3
V1
V2
V1
A
IVC3
A
V4
V4
V2
IVC4
A
VC3
VC4
VC3
VC4
V3
V3
Figure 7 Test Circuit 3
Figure 8 Test Circuit 4
V6
A
A
I1
SW4
S-8224A/B Series
VDD
CO
CTL
VSS
SW5
VC1
VC2
VC3
V5
V4
V1
V2
V
I2
VC4
V7
V3
Figure 9 Test Circuit 5
13
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Operation
Remark Refer to " Battery Protection IC Connection Examples".
1. Normal status
If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCU) + the overcharge hysteresis
voltage (VHC)", the CO pin output changes to "L" (active "H") or "H" (active "L"). This is called normal status.
2. Overcharge status
When the voltage of one of the batteries exceeds VCU during charging under normal conditions and the status is
retained for the overcharge detection delay time (tCU) or longer, CO pin output inverts. This status is called overcharge
status. Connecting FET to the CO pin provides charge control and a second protection.
If the voltage of each of the batteries is lower than VCU + VHC and the status is retained for the overcharge release delay
time (tCL) or longer, S-8224A/B Series changes to normal status.
3. Overcharge timer reset function
When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during
tCU from when VCU is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge
release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time
the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCU has been
exceeded, counting tCU resumes.
14
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
4. CTL pin
The S-8224A/B Series has control pins.
In the S-8224A/B Series, the CTL pin is used to control the output voltage of the CO pin. The CTL pin takes precedence
over the overcharge detection circuit.
Table 8 Status Set by CTL Pin
CTL Pin
CO Pin
"H"
Normal status*1
Detection status
Detection status
Open
"L"
*1. The status is controlled by the overcharge detection circuit.
–
CTL*1
+
Pull-down resistor
*1. In the S-8224A/B Series, the inversion voltage "H" to "L" or "L" to "H" of the CTL pin is the VDD pin voltage −
2.8 V typ., and does not have the hysteresis.
Figure 10 Internal Equivalent Circuit of CTL Pin
Caution In the S-8224A/B Series, since the CTL pin implements high resistance of 7 MΩ to 24 MΩ for pull
down, be careful of external noise application. If an external noise is applied, the CO pin may
become "H". Perform thorough evaluation using the actual application.
15
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
5. Test mode
In the S-8224A/B Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the VC1 pin voltage for at least
10 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = +25 °C). The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin.
If the CO pin becomes detection status when the delay time has elapsed after overcharge detection, the latch for
retaining the test mode is reset and the S-8224A/B Series exits from the test mode.
VDD pin voltage
VC1 pin voltage
8.5 V or
higher
Pin voltage
VHCn
VCUn
Battery voltage
(n = 1 to 4)
Test mode
tTST = 10 ms max.
CO pin
(Active "H")
CO pin
(Active "L")
32 ms typ.
Caution 1. Set the test mode when no batteries are overcharged.
tCL
2. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
Figure 11
16
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Timing Charts
1. Overcharge detection operation
VHCn
VCUn
Battery voltage
(n = 1 to 4)
tTR or longer tTR or shorter
tTR or shorter
CTL pin
CO pin
(Active "H")
CO pin
(Actve "L")
tCU
tCL
Figure 12
17
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
2. Overcharge timer reset operation
VHCn
tTR or shorter
t
TR or longer
tTR or shorter
VCUn
Battery voltage
(n = 1 to 4)
tCU or
shorter
tTR
CO pin
(Active "H")
Timer reset
tCU
CO pin
(Active "L")
Figure 13
18
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Battery Protection IC Connection Examples
1. 4-serial cell
SCP
EB+
VDD
RVDD
CVDD
VC1
R1
C1
C2
C3
C4
BAT1
BAT2
BAT3
BAT4
VC2
S-8224A/B
Series
R2
R3
R4
VC3
FET*1
VC4
CO
DP
VSS
CTL
External
input
RCTL
EB−
*1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage
of 12 V can be used.
Figure 14
Table 9 Constants for External Components
No.
1
Part
R1 to R4
Min.
0.3
Typ.
1
Max.
10
Unit
kΩ
μF
Ω
0.01
300
2
C1 to C4, CVDD
RVDD
0.1
330
1
3
1000
Caution 1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than
the above example of connection. In addition, the example of connection shown above
and the constant will not guarantee successful operation. Perform thorough evaluation
using the actual application to set the constant.
3. Set the same constants to R1 to R4 and to C1 to C4 and CVDD
.
4. Since the CO pin may become detection status transiently when the battery is being
connected, be sure to connect the positive terminal of BAT1 last in order to prevent the
terminal protection fuse from cutoff.
19
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
2. 3-serial cell
SCP
EB+
VDD
VD1
VC2
RVDD
CVDD
R1
R2
R3
C1
BAT1
BAT2
BAT3
S-8224A/B
Series
C2
VC3
VC4
FET*1
C3
CO
DP
VSS
CTL
External
input
RCTL
EB−
*1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of
12 V can be used.
Figure 15
Table 10 Constants for External Components
No.
1
Part
R1 to R3
Min.
0.3
Typ.
1
Max.
10
Unit
kΩ
μF
Ω
0.01
300
0.1
330
1
2
C1 to C3, CVDD
RVDD
1000
3
Caution 1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R3 and to C1 to C3 and CVDD
.
4. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.
20
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
3. 2-serial cell
SCP
EB+
VDD
VC1
VC2
VC3
RVDD
CVDD
R1
C1
BAT1
BAT2
R2
S-8224A/B
Series
C2
FET
VC4
CO
DP
VSS
CTL
External
input
RCTL
EB−
Figure 16
Table 11 Constants for External Components
No.
1
Part
R1 to R2
Min.
0.3
Typ.
1
Max.
10
Unit
kΩ
μF
Ω
0.01
300
0.1
330
1
2
C1 to C2, CVDD
RVDD
1000
3
Caution 1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R2, and to C1 to C2 and CVDD
.
4. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.
21
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Precaution
• Do not connect batteries charged with VCU + VHC or higher.
• If the connected batteries include a battery charged with VCU + VHC or higher, the S-8224A/B series may become
overcharge status after all pins are connected.
• In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform
thorough evaluation with the actual application circuit.
• Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figures in " Battery
Protection IC Connection Examples".
• The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
22
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Example of Application Circuit
1. Overheat protection via PTC
SCP
EB+
VDD
RVDD
CVDD
VC1
R1
C1
C2
C3
C4
BAT1
BAT2
BAT3
BAT4
VC2
S-8224A/B
Series
R2
R3
R4
VC3
FET*1
VC4
VSS
CO
CTL
First protection IC
PTC
CCTL
EB−
*1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of
12 V can be used.
Figure 17
Caution 1. The above connection example will not guarantee successful operation. Perform thorough
evaluation using the actual application.
2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in
the S-8224A/B Series, connect the PTC before connecting batteries.
3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the
S-8224A/B Series.
4. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL +81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
[For PTC, contact]
Murata Manufacturing Co., Ltd.
Thermistor Products Department
Nagaokakyo-shi, Kyoto, 617-8555, Japan
TEL +81-75-955-6863
Contact Us: http://www.murata.com/contact/index.html
23
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Characteristics (Typical Data)
1. Detection voltage
1. 1 VCU vs. Ta
1. 2 VCU + VHC vs. Ta
VCU = 4.500 V
VHC = −400 mV
4.200
4.150
4.100
4.050
4.520
4.510
4.500
4.490
4.480
4.000
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
2. Current consumption
2. 1 IOPE vs. Ta
2. 2 IOPED vs. Ta
VDD = 14 V
VDD = 9 V
0.5
0.4
0.3
0.2
0.1
0.0
0.3
0.2
0.1
0.0
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
2. 3 IOPE vs. VDD
Ta = +25°C
80
60
40
20
0
0
5
10
15
20
25
30
V
DD [V]
3. Delay time
3. 1 tCU vs. Ta
VDD = 15.7 V
2.0
1.5
1.0
0.5
0.0
40 25
0
25
Ta [C]
50
75 85
24
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
4. CTL pin
4. 1 VCTLL vs. Ta
4. 2 ICTLH vs. Ta
VDD = 14 V
VDD = 14 V
12.0
11.5
11.0
10.5
10.0
2.5
2.0
1.5
1.0
0.5
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
5. Output current
5. 1 ICOH vs. VDD (S-8224A Series)
5. 2 ICOH vs. VDD (S-8224B Series)
Ta = +25°C
Ta = +25°C
80
100
120
140
160
180
200
10
20
30
40
50
0
5
10
15
20
25
30
0
5
10
15
20
25
30
V
DD [V]
VDD [V]
5. 3 ICOL vs. VDD
5. 4 ICOLL vs. VDD
Ta = +25°C
Ta = +25°C
100
80
60
40
20
0
0.10
0.08
0.06
0.04
0.02
0.00
0
0
5
10
15
20
25
30
5
10
15
20
25
30
V
DD [V]
VDD [V]
6. Output voltage
6. 1 VCOH vs. VDD
12
10
8
6
4
2
0
0
5
10
15
20
25
30
V
DD [V]
25
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8224A/B Series
Rev.1.3_00
Marking Specifications
1. SNT-8A
Top view
(1)
Blank
8
7
6
5
(2) to (4)
(5), (6)
(7) to (11)
Product code (Refer to Product name vs. Product code)
Blank
Lot number
(1) (2) (3) (4)
(5) (6) (7) (8)
(9) (10) (11
)
1
2
3
4
Product name vs. Product code
Product code
Product code
Product name
Product name
(2)
(3)
R
R
R
R
R
R
Z
(4)
S
(2)
5
(3)
S
(4)
A
S-8224AAS-I8T1U
S-8224AAT-I8T1U
S-8224AAU-I8T1U
S-8224AAV-I8T1U
S-8224AAW-I8T1U
S-8224AAX-I8T1U
S-8224ABA-I8T1U
S-8224ABB-I8T1U
S-8224ABC-I8T1U
S-8224ABD-I8T1U
5
5
5
5
5
5
6
6
6
6
S-8224BAA-I8T1U
S-8224BAB-I8T1U
S-8224BAC-I8T1U
T
5
S
B
U
V
5
S
C
W
Y
A
Z
B
Z
C
D
Z
26
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.3_00
S-8224A/B Series
Power Dissipation
SNT-8A
Tj = 125C max.
1.0
0.8
B
0.6
A
0.4
0.2
0.0
0
25
50
75
100 125 150 175
Ambient temperature (Ta) [C]
Board
Power Dissipation (PD)
A
B
C
D
E
0.47 W
0.58 W
−
−
−
27
SNT-8A Test Board
No. SNT8A-A-Board-SD-1.0
ABLIC Inc.
1.97±0.03
6
5
8
7
+0.05
-0.02
0.08
1
2
3
4
0.5
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
-0
4.0±0.1
2.0±0.05
0.25±0.05
ø1.5
0.65±0.05
ø0.5±0.1
4.0±0.1
2.25±0.05
4 3 2 1
5 6 7 8
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
PH008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
SNT-8A-A-Reel
TITLE
No.
PH008-A-R-SD-1.0
5,000
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
0.52
2
2.01
0.52
1
0.2
0.3
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
0.03 mm
3.
4.
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
SNT-8A-A
-Land Recommendation
TITLE
No.
No. PH008-A-L-SD-4.1
PH008-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
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