S-8245DAA-FGT1U [ABLIC]
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK;
| 型号： | S-8245DAA-FGT1U |
| 厂家： | 
ABLIC |
| 描述： | BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK |
| 文件： | 总43页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8245B/D Series
BATTERY PROTECTION IC
FOR 3-SERIAL TO 5-SERIAL CELL PACK
www.ablic.com
© ABLIC Inc., 2018
Rev.1.4_00
The S-8245B/D Series is a protection IC for 3-serial to 5-serial cell lithium-ion rechargeable batteries, which includes
high-accuracy voltage detection circuits and delay circuits. It is suitable for protecting 3-serial to 5-serial cell lithium-ion
rechargeable battery packs from overcharge, overdischarge, and overcurrent.
Connecting an NTC, it allows for the temperature detection at four different points: high temperature detection during
charging, low temperature detection during charging, high temperature detection during discharging, and low temperature
detection during discharging.
Features
High-accuracy voltage detection for each cell
Overcharge detection voltage n (n = 1 to 5):
Overcharge release voltage n (n = 1 to 5):
Overdischarge detection voltage n (n = 1 to 5):
Overdischarge release voltage n (n = 1 to 5):
Three-level discharge overcurrent detection:
Discharge overcurrent 1 detection voltage:
Discharge overcurrent 2 detection voltage:
Load short-circuiting detection voltage:
3.550 V to 4.600 V (50 mV step)
3.150 V to 4.600 V*1
2.000 V to 3.200 V (100 mV step)
2.000 V to 3.400 V*2
Accuracy 20 mV
Accuracy 50 mV
Accuracy 80 mV
Accuracy 100 mV
0.020 V to 0.300 V (10 mV step)
0.040 V to 0.500 V (20 mV step)
0.100 V to 1.000 V (25 mV step)
Accuracy 10 mV
Accuracy 15 mV
Accuracy 50 mV
Charge overcurrent detection:
Charge overcurrent detection voltage:
0.300 V to 0.020 V (10 mV step)
Accuracy 10 mV
Each delay time is settable by an external capacitor
(Load short-circuiting detection delay time and temperature detection delay time are internally fixed)
Independent control of charge inhibition, discharge inhibition, and power-saving by each control pin
0 V battery charge function is selectable:
Power-down function is selectable:
CIT pin internal resistance value is selectable:
Available, unavailable
Available, unavailable
831 k typ., 8.31 M typ.
CO and DO pin output voltage is limited to 15 V max. respectively
Switching control for 3-serial to 5-serial cell is possible by inputting voltage to the SEL1 pin and the SEL2 pin
Temperature detection is possible at four different points by connecting an NTC
High temperature detection ratio during charging / discharging: 0.600 to 0.900 (0.005 step)
Low temperature detection ratio during charging / discharging: 0.030 to 0.400 (0.005 step)
Accuracy 0.005
Accuracy 0.005
High-withstand voltage:
Wide operation voltage range:
Wide operation temperature range:
Low current consumption
During operation:
Absolute maximum rating 28 V
5 V to 24 V
Ta = 40C to 85C
20 A max. (Ta = 25C)
0.5 A max. (Ta = 25C)
0.1 A max. (Ta = 25C)
During power-down:
During power-saving:
Lead-free (Sn 100%), halogen-free
*1. Overcharge release voltage = Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage n (n = 1 to 5) is selectable in 0 V to 0.4 V in 50 mV step)
*2. Overdischarge release voltage = Overdischarge detection voltage Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage n (n = 1 to 5) is selectable in 0 V to 0.7 V in 100 mV step)
Application
Lithium-ion rechargeable battery pack
Package
24-Pin SSOP
1
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Block Diagram
VDD
TH
Temperature detection circuit
VC1
Overcharge 1
VREG
CTLC
Voltage regulator
Overdischarge 1
VC2
VC3
VC4
VC5
CTLD
Overcharge 2
Overdischarge 2
PSI
CCT
Overcharge 3
CDT
CIT
Overdischarge 3
CIT2
CICT
Control circuit
Overcharge 4
Overdischarge 4
CO pin output voltage
limit circuit
Overcharge 5
CO
DO pin output voltage
limit circuit
Overdischarge 5
VSS
DO
SEL1
SEL2
Discharge
overcurrent 1
PSO
VM
Discharge
overcurrent 2
Load
short-circuiting
RVMD
RVMS
Charge
overcurrent
VINI
Remark Diodes in the figure are parasitic diodes.
Figure 1
2
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Product Name Structure
1. Product name
S-8245
x
xx
-
FGT1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
FGT1: 24-Pin SSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
Product type
B:
D:
For application circuit with an integrated charge and discharge path
For application circuit with separate charge and discharge paths
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Code
Package Name
24-Pin SSOP
Dimension
FS024-B-P-SD
Tape
Reel
FS024-B-C-SD
FS024-B-R-SD
3
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. Product name list
3. 1 S-8245B Series
Table 2 (1 / 2)
Discharge Discharge
Overcurrent Overcurrent Short-circuiting Overcurrent
1 Detection 2 Detection
Voltage Voltage
Load
Charge
Overcharge Overcharge Overdischarge Overdischarge
Detection
Voltage
Release
Voltage
[VCL]
Detection
Voltage
[VDL]
Release
Voltage
[VDU]
Product Name
Detection
Voltage
[VSHORT
Detection
Voltage
[VCIOV]
[VCU
]
[VDIOV1
0.020 V
0.100 V
]
[VDIOV2
0.040 V
0.200 V
]
]
S-8245BAA-FGT1U 4.100 V
S-8245BAB-FGT1U 4.250 V
4.050 V
4.150 V
2.600 V
2.500 V
2.700 V
3.000 V
0.100 V
0.500 V
0.020 V
0.100 V
Table 2 (2 / 2)
CIT Pin High Temperature Low Temperature High Temperature Low Temperature
0 V Battery
Power-
down
Internal
Resistance
Value*3
Detection Ratio
during
Detection Ratio
during
Detection Ratio
during
Discharging
Detection Ratio
during
Discharging
Product Name
Charge
Function*1 Function*2
Charging
Charging
[RCIT
]
[rTHCH
]
[rTHCL
]
[rTHDH
]
[rTHDL]
S-8245BAA-FGT1U Available Available 831 k
S-8245BAB-FGT1U Unavailable Available 831 k
0.670
0.670
0.270
0.270
0.795
0.795
0.190
0.190
*1. 0 V battery charge function "available" / "unavailable" is selectable.
*2. Power-down function "available" / "unavailable" is selectable.
*3. CIT pin internal resistance value 831 k typ. / 8.31 M typ. is selectable.
Remark Please contact our sales office for products other than those specified above.
3. 2 S-8245D Series
Table 3 (1 / 2)
Discharge Discharge
Overcurrent Overcurrent Short-circuiting Overcurrent
1 Detection 2 Detection
Voltage Voltage
Load
Charge
Overcharge Overcharge Overdischarge Overdischarge
Detection
Voltage
Release
Voltage
[VCL]
Detection
Voltage
[VDL]
Release
Voltage
[VDU]
Product Name
Detection
Voltage
[VSHORT
Detection
Voltage
[VCIOV]
[VCU
]
[VDIOV1
0.020 V
0.100 V
]
[VDIOV2
0.040 V
0.200 V
]
]
S-8245DAA-FGT1U 4.100 V
S-8245DAB-FGT1U 4.250 V
4.050 V
4.150 V
2.600 V
2.500 V
2.700 V
3.000 V
0.100 V
0.500 V
0.020 V
0.100 V
Table 3 (2 / 2)
CIT Pin High Temperature Low Temperature High Temperature Low Temperature
0 V Battery
Power-
down
Internal
Resistance
Value*3
Detection Ratio
during
Detection Ratio
during
Detection Ratio
during
Discharging
Detection Ratio
during
Discharging
Product Name
Charge
Function*1 Function*2
Charging
Charging
[RCIT
]
[rTHCH
]
[rTHCL
]
[rTHDH
]
[rTHDL]
S-8245DAA-FGT1U Unavailable Available 831 k
S-8245DAB-FGT1U Unavailable Available 831 k
0.670
0.670
0.270
0.270
0.795
0.795
0.190
0.190
*1. 0 V battery charge function "available" / "unavailable" is selectable.
*2. Power-down function "available" / "unavailable" is selectable.
*3. CIT pin internal resistance value 831 k typ. / 8.31 M typ. is selectable.
Remark Please contact our sales office for products other than those specified above.
4
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Pin Configuration
1. 24-Pin SSOP
Table 4
Top view
Pin No. Symbol
Description
1
2
3
4
TH
Input pin for temperature detection
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Input pin for positive power supply,
VDD
VC1
VC2
3
connection pin for positive voltage of battery 1
Connection pin for positive voltage of battery 1
Connection pin for negative voltage of battery 1,
connection pin for positive voltage of battery 2
Connection pin for negative voltage of battery 2,
connection pin for positive voltage of battery 3
Connection pin for negative voltage of battery 3,
connection pin for positive voltage of battery 4
Connection pin for negative voltage of battery 4,
connection pin for positive voltage of battery 5
Input pin for negative power supply,
4
5
6
7
8
9
5
6
7
VC3
VC4
VC5
10
11
12
Figure 2
8
9
VSS
VINI
connection pin for negative voltage of battery 5
Voltage detection pin between VSS pin and VINI pin
Switching pins for number of cells in series
10
11
SEL1
SEL2
[SEL1, SEL2] = ["L", "L"] :
[SEL1, SEL2] = ["L", "H"] :
[SEL1, SEL2] = ["H", "L"] :
[SEL1, SEL2] = ["H", "H"] :
5-serial cell
4-serial cell
3-serial cell
Setting inhibited
Capacitor connection pin for delay
for charge overcurrent detection
12
13
14
15
16
CICT
CCT
CDT
CIT
Capacitor connection pin for delay
for overcharge detection voltage
Capacitor connection pin for delay
for overdischarge detection voltage
Capacitor connection pin for delay
for discharge overcurrent 1 detection
Capacitor connection pin for delay
for discharge overcurrent 2 detection
Output pin for power-saving signal (CMOS output)
Connection pin of discharge control FET gate (CMOS output)
Connection pin of charge control FET gate
(Pch open-drain output)
CIT2
17
18
PSO
DO
19
CO
20
21
22
23
24
VM
Voltage detection pin between VSS pin and VM pin
Control pin for CO pin output
CTLC
CTLD
PSI
Control pin for DO pin output
Control pin for Power-saving
VREG
Voltage output pin for temperature detection
5
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Absolute Maximum Ratings
Table 5
(Ta = 25°C unless otherwise specified)
Item
Symbol
Applied Pin
Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin VDS
VDD
VSS 0.3 to VSS 28
V
VC1, VC2, VC3, VC4, VC5,
CCT, CDT, CIT, CIT2, CICT,
SEL1, SEL2, TH,
Input pin voltage 1
VIN1
VSS 0.3 to VDD 0.3
V
CTLC, CTLD, PSI
Input pin voltage 2
VIN2
VM, VINI
VDD 28 to VDD 0.3
VSS 0.3 to VDD 0.3
VDD 28 to VDD 0.3
40 to 85
V
V
Output pin voltage 1
Output pin voltage 2
Operation ambient temperature
Storage temperature
VOUT1
VOUT2
Topr
DO, PSO, VREG
CO
V
°C
°C
Tstg
40 to 125
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 6
Item
Symbol
Condition
Board A
Min.
Typ.
70
60
Max.
Unit
C/W
C/W
C/W
C/W
C/W
Board B
Board C
Board D
Board E
Junction-to-ambient thermal resistance*1 JA
24-Pin SSOP
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
6
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Electrical Characteristics
Table 7 (1 / 3)
(V1 = V2 = V3 = V4 = V5 = 3.5 V, Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Detection Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
Overcharge detection voltage n
(n = 1 to 5)
V1 = V2 = V3 = V4 = V5 =
VCUn 0.050 V
VCUn
0.020
VCUn
0.020
VCUn
VCUn
VCLn
V
V
V
V
V
V
V
V
1
1
1
1
1
1
1
1
Overcharge release voltage n
(n = 1 to 5)
VCLn
0.050
VDLn
0.080
VCLn
0.050
VDLn
0.080
VCLn
Overdischarge detection voltage n
(n = 1 to 5)
VDLn
VDLn
Overdischarge release voltage n
(n = 1 to 5)
VDUn
0.100
VDUn
0.100
VDUn
VDUn
Discharge overcurrent 1
detection voltage
VDIOV1
0.010
VDIOV1
VDIOV1
VDIOV2
VSHORT
VCIOV
VDIOV1
VDIOV2
VSHORT
VCIOV
0.010
Discharge overcurrent 2
detection voltage
VDIOV2
0.015
VSHORT
0.050
VDIOV2
0.015
VSHORT
0.050
Load short-circuiting detection
voltage
Charge overcurrent detection
voltage
VCIOV
0.010
VCIOV
0.010
Delay Time Function*1
CCT pin internal resistance
CDT pin internal resistance
RCCT
RCDT
V1 = VCU 0.025
V1 = VDL 0.085
RCIT = 831 k
RCIT = 8.31 M
6.15
615
615
6.15
123
123
8.31
831
831
8.31
166
166
10.20
1020
1020
10.20
204
M
k
k
M
k
k
1
1
1
1
1
1
CIT pin internal resistance
RCIT
CIT2 pin internal resistance
CICT pin internal resistance
RCIT2
RCICT
204
VDS
0.68
VDS
0.70
VDS
0.72
CCT pin detection voltage
CDT pin detection voltage
CIT pin detection voltage
CIT2 pin detection voltage
CICT pin detection voltage
VCCT
VCDT
VCIT
V1 = VCU 0.025
V
V
1
1
1
1
1
1
VDS
0.68
VDS
0.70
VDS
0.72
V1 = VDL 0.085
VDS
0.68
VDS
0.70
VDS
0.72
V
VDS
0.68
VDS
0.70
VDS
0.72
VCIT2
VCICT
V
VDS
0.68
VDS
0.70
VDS
0.72
V
Load short-circuiting detection
delay time
tSHORT Internally fixed delay time
100
5
300
600
24
s
Input Voltage
Operation voltage between
VDD pin and VSS pin
Fixed output voltage of DO pin
and CO pin
VDSOP
V
*1. Refer to "6. Delay time setting" in " Operation" for details of the delay time function.
7
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Table 7 (2 / 3)
(V1 = V2 = V3 = V4 = V5 = 3.5 V, Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Current
Current consumption during
operation
IOPE
IPDN
IPSV
10
20
0.5
0.1
A
A
A
1
1
1
Current consumption during
power-down
V1 = V2 = V3 = V4 = V5 = 1.5 V
Current consumption during
power-saving
VC1 pin current
IVC1
IVC2
IVC3
IVC4
IVC5
0.25
0.0
0.0
0.0
0.0
0.50
0.8
0.8
0.8
0.8
A
A
A
A
A
1
1
1
1
1
VC2 pin current
0.8
0.8
0.8
0.8
VC3 pin current
VC4 pin current
VC5 pin current
Internal Resistance
Resistance between VM pin and
VDD pin
RVMD
RVMS
V1 = V2 = V3 = V4 = V5 = 1.5 V
1.35
7.5
2.70
15.0
5.40
30.0
M
k
1
1
Resistance between VM pin and
VSS pin
Output Pin
CO pin voltage "H"*1
DO pin voltage "H"*2
CO pin source current
CO pin leakage current
DO pin source current
DO pin sink current
PSO pin source current
PSO pin sink current
0 V Battery Charge Function
VCOH
VDOH
ICOH
ICOL
VCOH VDS
VDOH VDS
11.0
11.0
10
10
10
1
13.0
13.0
15.0
15.0
0.1
10
10
V
1
1
1
1
1
1
1
1
V
A
A
A
A
A
A
V1 = V2 = V3 = V4 = V5 = 5.6 V
IDOH
IDOL
IPSOH
IPSOL
V1 = V2 = V3 = V4 = V5 = 1.9 V
1
0 V battery charge function
"available",
V1 = V2 = V3 = V4 = V5 = 0 V
0 V battery charge function
"unavailable"
0 V battery charge starting
charger voltage
V0CHA
0.8
1.3
1.5
1.5
V
V
1
1
0 V battery charge inhibition
battery voltage n (n = 1 to 5)
V0INHn
1.0
*1. When VCOH VDS, VCOH = VDD
*2. When VDOH VDS, VDOH = VDD
Remark VDS: Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
8
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Table 7 (3 / 3)
(V1 = V2 = V3 = V4 = V5 = 3.5 V, Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Control Pin
SEL1 pin voltage "H"
VSEL1H
VSEL2H
VSEL1L
VSEL2L
VCTLC
VCTLD
VPSI
VDS 0.95
VDS 0.95
0.7
V
V
1
SEL2 pin voltage "H"
SEL1 pin voltage "L"
VDS 0.05
VDS 0.05
2.0
V
SEL2 pin voltage "L"
0.1
V
CTLC pin reverse voltage
CTLD pin reverse voltage
PSI pin reverse voltage
CTLC pin response delay time
CTLD pin response delay time
PSI pin response delay time
CTLC pin curent "H"
V
0.1
0.7
2.0
V
1
0.1
4.0
8.0
V
1
tCTLC
0.275
0.275
0.3
0.500
0.500
0.9
0.725
0.725
3.0
ms
ms
ms
A
A
A
A
A
A
1
tCTLD
1
tPSI
1
ICTLCH
ICTLCL
ICTLDH
ICTLDL
IPSIH
0.1
0.45
0.1
0.45
0.0
0.0
0.1
1
CTLC pin curent "L"
0.20
0.0
0.05
0.1
1
CTLD pin curent "H"
1
CTLD pin curent "L"
0.20
0.2
0.05
0.4
1
PSI pin curent "H"
1
PSI pin curent "L"
IPSIL
0.1
0.0
0.1
1
Temperature Detection Function
Output voltage for temperature
detection
Voltage between VDD pin and
VREG pin
VREG
rTHCH
rTHCL
rTHDH
rTHDL
VCHG
4.0
5.0
6.0
V
2
2
2
2
2
High temperature detection ratio
during charging
rTHCH
0.005
rTHCH
0.005
rTHCH = (VREG VTH) / VREG
rTHCL = (VREG VTH) / VREG
rTHDH = (VREG VTH) / VREG
rTHDL = (VREG VTH) / VREG
rTHCH
rTHCL
rTHDH
rTHDL
Low temperature detection ratio
during charging
rTHCL
0.005
rTHCL
0.005
High temperature detection ratio
during discharging
rTHDH
0.005
rTHDH
0.005
Low temperature detection ratio
during discharging
rTHDL
0.005
rTHDL
0.005
Charge-discharge discriminating
voltage
0.03
0.02
0.01
V
s
2
2
Temperature detection delay time tTH
1.0
2.0
3.0
9
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Test Circuits
Unless otherwise specified, for the CO pin output voltage (VCO), DO pin output voltage (VDO) and PSO pin output voltage
(VPSO), "L" or "H" is judged as follows.
L : [VCO, VDO, VPSO] VDS 0.1 V
H : [VCO, VDO, VPSO] VDS 0.1 V
Remark VDS: Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
1. Test circuit 1
10 k
0.1 F
10 k
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
PSI 23
CTLD 22
CTLC 21
VM 20
A
A
A
A
A
A
A
V1
V2
V3
A
A
CO 19
DO 18
A
A
S-8245B/D
V4
V5
7 VC5
8 VSS
9 VINI
PSO 17
CIT2 16
CIT 15
A
A
A
10 SEL1
11 SEL2
12 CICT
A
A
CDT 14
A
A
CCT 13
SW3 SW4 SW5
SW6
SW7
SW8 SW9
SW2
SW1
V
V
V
V7
V8 V9 V10 V11
V12
V13
V14 V15 V16 V17 V18
V6
1 M
Figure 3 Test Circuit 1
This section provides explanations of Test items using Test circuit 1.
Perform each test after setting as shown in Table 8.
Table 8 Initial Setting of Test Circuit 1 (1 / 2)
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
3.5 V 3.5 V 3.5 V 3.5 V 3.5 V
0 V
Table 8 Initial Setting of Test Circuit 1 (2 / 2)
V15
0 V
V16
VDS
V17
VDS
V18
VDS
SW1
OFF
SW2
OFF
SW3
OFF
SW4
OFF
SW5
OFF
SW6
OFF
SW7
OFF
SW8
ON
SW9
OFF
10
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
1. 1 Overcharge detection voltage n (VCUn), overcharge release voltage n (VCLn
)
When the voltage V1 is gradually increased after setting V1 = V2 = V3 = V4 = V5 = VCUn 0.05 V and VCO
changes from "H" to "L", V1 is defined as the overcharge detection voltage 1 (VCU1). When the voltage V1 is then
gradually decreased after setting V2 = V3 = V4 = V5 = 3.5 V and V15 = 5 mV and VCO changes from "L" to "H",
V1 is defined as the overcharge release voltage 1 (VCL1).
Overcharge detection voltage n (VCUn) and overcharge release voltage n (VCLn) (n = 2 to 5) can be determined in
the same way as when n = 1.
1. 2 Overdischarge detection voltage n (VDLn), overdischarge release voltage n (VDUn
)
When the voltage V1 is gradually decreased and VDO changes from "H" to "L", V1 is defined as the overdischarge
detection voltage 1 (VDL1). When the voltage V1 is then gradually increased after setting V15 = 0.1 V and VDO
changes from "L" to "H", V1 is defined as the overdischarge release voltage 1 (VDU1).
Overdischarge detection voltage n (VDLn) and overdischarge release voltage n (VDUn) (n = 2 to 5) can be
determined in the same way as when n = 1.
1. 3 Discharge overcurrent 1 detection voltage (VDIOV1
)
When the voltage V6 is gradually increased and VDO changes from "H" to "L", V6 is defined as the discharge
overcurrent 1 detection voltage (VDIOV1).
1. 4 Discharge overcurrent 2 detection voltage (VDIOV2
)
When the voltage V6 is gradually increased after setting V10 = 0 V and SW4 to ON and VDO changes from "H" to
"L", V6 is defined as the discharge overcurrent 2 detection voltage (VDIOV2).
1. 5 Load short-circuiting detection voltage (VSHORT
)
When the voltage V6 is gradually increased after setting V10 = V11 = 0 V and SW4 and SW5 to ON and VDO
changes from "H" to "L", V6 is defined as the load short-circuiting detection voltage (VSHORT).
1. 6 Charge overcurrent detection voltage (VCIOV
)
When the voltage V6 is gradually decreased and VCO changes from "H" to "L", V6 is defined as the charge
overcurrent detection voltage (VCIOV).
1. 7 CCT pin internal resistance (RCCT), CCT pin detection voltage (VCCT
)
The CCT pin internal resistance (RCCT) is defined by RCCT = VDS / ICCT under the set conditions of V1 = VCU1
0.025 V after setting V8 = 0 V and setting SW2 to ON. When the voltage V8 is then gradually increased and VCO
changes from "H" to "L", V8 is defined as the CCT pin detection voltage (VCCT).
1. 8 CDT pin internal resistance (RCDT), CDT pin detection voltage (VCDT
)
The CDT pin internal resistance (RCDT) is defined by RCDT = VDS / ICDT under the set conditions of V1 = VDL1
0.085 V after setting V9 = 0 V and setting SW3 to ON. When the voltage V9 is then gradually increased and VDO
changes from "H" to "L", V9 is defined as the CDT pin detection voltage (VCDT).
1. 9 CIT pin internal resistance (RCIT), CIT pin detection voltage (VCIT
)
The CIT pin internal resistance (RCIT) is defined by RCIT = VDS / ICIT under the set conditions of V6 = VDIOV1 0.015
V after setting V10 = 0 V and setting SW4 to ON. When the voltage V10 is then gradually increased and VDO
changes from "H" to "L", V10 is defined as the CIT pin detection voltage (VCIT).
1. 10 CIT2 pin internal resistance (RCIT2), CIT2 pin detection voltage (VCIT2
)
The CIT2 pin internal resistance (RCIT2) is defined by RCIT2 = VDS / ICIT2 under the set conditions of V6 = VDIOV2
0.020 V after setting V10 = V11 = 0 V and setting SW4 and SW5 to ON. When the voltage V11 is then gradually
increased and VDO changes from "H" to "L", V11 is defined as the CIT2 pin detection voltage (VCIT2).
11
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
1. 11 CICT pin internal resistance (RCICT), CICT pin detection voltage (VCICT
)
The CICT pin internal resistance (RCICT) is defined by RCICT = VDS / ICICT under the set conditions of V6 = VCIOV
0.015 V after setting V7 = 0 V and setting SW1 to ON. When the voltage V7 is then gradually increased and VCO
changes from "H" to "L", V7 is defined as the CICT pin detection voltage (VCICT).
1. 12 Load short-circuiting detection delay time (tSHORT
)
The load short-circuiting detection delay time (tSHORT) is the time period from when the voltage V6 changes to V6 =
VSHORT 0.055 V until when VDO changes from "H" to "L" after setting V10 = V11 = 0 V and setting SW4 and SW5
to ON.
1. 13 Current consumption during operation (IOPE
)
The current consumption during operation (IOPE) is IVSS when SW8 is OFF.
1. 14 Current consumption during power-down (IPDN
)
The current consumption during power-down (IPDN) is IVSS when V1 = V2 = V3 = V4 = V5 = 1.5 V, V15 = VDS and
SW8 is OFF.
1. 15 Current consumption during power-saving (IPSV
)
The current consumption during power-saving (IPSV) is IVSS when V18 = 0 V and SW8 is OFF.
1. 16 Resistance between VM pin and VDD pin (RVMD
)
The resistance between VM pin and VDD pin (RVMD) is defined by RVMD = VDS / IVM when setting V1 = V2 = V3 =
V4 = V5 = 1.5 V.
1. 17 Resistance between VM pin and VSS pin (RVMS
)
The resistance between VM pin and VSS pin (RVMS) is defined by RVMS = V15 / IVM when setting V6 = VDIOV1
0.015 V and V15 = 2.0 V.
1. 18 CO pin source current (ICOH
)
The CO pin source current (ICOH) is ICO when V14 = VCOH 0.5 V, SW8 is OFF, and SW9 is ON.
1. 19 CO pin leakage current (ICOL
)
The CO pin leakage current (ICOL) is ICO when V1 = V2 = V3 = V4 = V5 = 5.6 V, V14 = 0 V, SW8 is OFF, and SW9
is ON.
1. 20 DO pin source current (IDOH
)
The DO pin source current (IDOH) is IDO when V13 = VDOH 0.5 V and SW7 is ON.
1. 21 DO pin sink current (IDOL
)
The DO pin sink current (IDOL) is IDO when V1 = V2 = V3 = V4 = V5 = 1.9 V, V13 = 0.5 V, and SW7 is ON.
1. 22 PSO pin source current (IPSOH
)
The PSO pin source current (IPSOH) is IPSO when V18 = 0 V, V12 = VDS 0.5 V, and SW6 is ON.
1. 23 PSO pin sink current (IPSOL
)
The PSO pin sink current (IPSOL) is IPSO when V12 = 0.5 V and SW6 is ON.
12
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
1. 24 0 V battery charge starting charger voltage (V0CHA) (0 V battery charge function "available")
When the voltage V15 is gradually decreased after setting V1 = V2 = V3 = V4 = V5 = 0 V and VCO is "H", the
absolute value of V15 is defined as the 0 V battery charge starting charger voltage (V0CHA).
1. 25 0 V battery charge inhibition battery voltage n (V0INHn) (0 V battery charge function "unavailable")
When the voltage V1 is gradually decreased and VCO changes from "H" to "L", V1 is defined as the 0 V battery
charge inhibition battery voltage 1 (V0INH1).
0 V battery charge inhibition battery voltage n (V0INHn) (n = 2 to 5) can be determined in the same way as when n =
1.
1. 26 CTLC pin reverse voltage (VCTLC
)
When the voltage V16 is gradually decreased and VCO changes from "H" to "L", V16 is defined as the CTLC pin
reverse voltage (VCTLC).
1. 27 CTLD pin reverse voltage (VCTLD
)
When the voltage V17 is gradually decreased and VDO changes from "H" to "L", V17 is defined as the CTLD pin
reverse voltage (VCTLD).
1. 28 PSI pin reverse voltage (VPSI
)
When the voltage V18 is gradually decreased and VPSO changes from "L" to "H", V18 is defined as the PSI pin
reverse voltage (VPSI).
1. 29 CTLC pin response delay time (tCTLC
)
The CTLC pin response delay time (tCTLC) is the time period from when the voltage V16 changes to V16 = 0 V until
when VCO changes from "H" to "L".
1. 30 CTLD pin response delay time (tCTLD
)
The CTLD pin response delay time (tCTLD) is the time period from when the voltage V17 changes to V17 = 0 V until
when VDO changes from "H" to "L".
1. 31 PSI pin response delay time (tPSI
)
The PSI pin response delay time (tPSI) is the time period from when the voltage V18 changes to V18 = 0 V until
when VPSO changes from "L" to "H".
1. 32 CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL
)
The CTLC pin current "H" (ICTLCH) is ICTLC when V16 = VDS
The CTLC pin current "L" (ICTLCL) is ICTLC when V16 = 0 V.
.
1. 33 CTLD pin current "H" (ICTLDH), CTLD pin current "L" (ICTLDL
)
The CTLD pin current "H" (ICTLDH) is ICTLD when V17 = VDS
The CTLD pin current "L" (ICTLDL) is ICTLD when V17 = 0 V.
.
1. 34 PSI pin current "H" (IPSIH), PSI pin current "L" (IPSIL
)
The PSI pin current "H" (IPSIH) is IPSI when V18 = VDS
The PSI pin current "L" (IPSIL) is IPSI when V18 = 0 V.
.
13
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
2. Test circuit 2
V
20 k
0.1 F
V7
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
PSI 23
CTLD 22
CTLC 21
VM 20
V1
V2
V3
V4
V5
CO 19
S-8245B/D
7 VC5
8 VSS
9 VINI
DO 18
PSO 17
CIT2 16
CIT 15
10 SEL1
11 SEL2
CDT 14
12 CICT
CCT 13
V
V
V6
1 M
Figure 4 Test Circuit 2
This section provides explanations of Test items using Test circuit 2.
Perform each test after setting as shown in Table 9.
Table 9 Initial Setting of Test Circuit 2
V1
V2
V3
V4
V5
V6
V7*1
2.5 V
3.5 V
3.5 V
3.5 V
3.5 V
3.5 V
0 V
*1. V7 is an absolute value.
14
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
2. 1 Output voltage for temperature detection (VREG
)
The maximum voltage between the VDD pin and VREG pin is defined as the output voltage for temperature
detection (VREG).
2. 2 High temperature detection ratio during charging (rTHCH
)
When the voltage V7 is gradually decreased after setting V6 = 0.03 V and VCO changes from "H" to "L" and VDO
changes from "H" to "L", the high temperature detection ratio during charging (rTHCH) is defined by (VREG V7) /
VREG
.
2. 3 Low temperature detection ratio during charging (rTHCL
)
When the voltage V7 is gradually increased after setting V6 = 0.03 V and VCO changes from "H" to "L" and VDO
changes from "H" to "L", the low temperature detection ratio during charging (rTHCL) is defined by (VREG V7) /
VREG
.
2. 4 High temperature detection ratio during discharging (rTHDH
When the voltage V7 is gradually decreased and VCO changes from "H" to "L" and VDO changes from "H" to "L", the
high temperature detection ratio during discharging (rTHDH) is defined by (VREG V7) / VREG
)
.
2. 5 Low temperature detection ratio during discharging (rTHDL
When the voltage V7 is gradually increased and VCO changes from "H" to "L" and VDO changes from "H" to "L", the
low temperature detection ratio during discharging (rTHDL) is defined by (VREG V7) / VREG
)
.
2. 6 Charge-discharge discriminating voltage (VCHG
)
When the voltage V6 is gradually decreased after setting (1 rTHDH) VREG V7 (1 rTHCH) VREG and VCO
changes from "H" to "L" and VDO changes from "H" to "L", V6 is defined as the charge-discharge discriminating
voltage (VCHG).
2. 7 Temperature detection delay time (tTH
The temperature detection delay time (tTH) is the time period from when the voltage V7 changes to 0 V until when
CO changes from "H" to "L" and VDO changes from "H" to "L".
)
V
15
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Operation
Remark Refer to " Connection Examples of Battery Protection IC".
1. Normal status
The status when the CO pin output voltage (VCO) = "H", DO pin output voltage (VDO) = "H" and PSO pin output voltage
(VPSO) = "L" is the normal status.
All the conditions mentioned below should be satisfied for returning to normal status.
The voltage of each of the batteries is in the range from the overcharge detection voltage n (VCUn) to
overdischarge detection voltage n (VDLn).
The VINI pin voltage is in the range of the charge overcurrent detection voltage (VCIOV) to the discharge
overcurrent 1 detection voltage (VDIOV1).
The CTLC pin voltage, CTLD pin voltage, and PSI pin voltage are higher than the CTLC pin reverse voltage
(VCTLC), CTLD pin reverse voltage (VCTLD), and PSI pin reverse voltage (VPSI), respectively.
Either (1) or (2) below is satisfied for the TH pin voltage (VTH).
(1) When VVM VCHG
(2) When VVM VCHG
:
:
(1 rTHCH) VREG VTH (1 rTHCL) VREG
(1 rTHDH) VREG VTH (1 rTHDL) VREG
Caution After a battery is connected, there may be cases when discharging cannot be performed. In this
case, the S-8245B/D Series returns to the normal status when any of the following conditions is
satisfied.
(1) Connecting a charger
(2) Shorting between the VM pin and the VSS pin
(3) Changing the PSI pin voltage to be VDS 0 V VDS
Remark VVM
VCHG
rTHCH
rTHCL
rTHDH
:
VM pin voltage
Charge-discharge discriminating voltage
:
:
:
:
High temperature detection ratio during charging
Low temperature detection ratio during charging
High temperature detection ratio during discharging
Low temperature detection ratio during discharging
Output voltage for temperature detection
rTHDL
:
VREG
:
VDS
:
Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
2. Overcharge status
When the voltage of any of the batteries exceeds the overcharge detection voltage n (VCUn) and the status continues
*1
for the overcharge detection delay time (tCU
)
or longer, the CO pin changes to high impedance. This is the
overcharge status. The CO pin is pulled down to EB by an external resistor so that the charge control FET is turned
off to stop charging.
The overcharge status is released if either condition mentioned below is satisfied.
(1) VVM 0 V, and voltage of battery VCLn
(2) VVM 0 V, and voltage of all batteries VCUn
*1. Refer to "6. Delay time setting" for details.
Remark VVM
VDS
VCUn
VCLn
:
:
VM pin voltage
Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
Overcharge detection voltage n (n = 1 to 5)
Overcharge release voltage n (n = 1 to 5)
:
:
16
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. Overdischarge status
When the voltage of any of the batteries falls below the overdischarge detection voltage n (VDLn) and the status
continues for the overdischarge detection delay time (tDL)*1 or longer, the DO pin changes to the VSS level. This is the
overdischarge status. The discharge control FET is turned off to stop discharging.
The overdischarge status is released if either condition mentioned below is satisfied.
(1) VVM VCHG, and voltage of all batteries VDLn
(2) VVM VCHG, and voltage of battery VDUn
*1. Refer to "6. Delay time setting" for details.
Remark VVM
VCHG
VDLn
VDUn
:
VM pin voltage
:
Charge-discharge discriminating voltage
Overdischarge detection voltage n (n = 1 to 5)
Overdischarge release voltage n (n = 1 to 5)
:
:
3. 1 With power-down function
When S-8245B/D Series reaches the overdischarge status, the VM pin is pulled up to the VDD level by a resistance
between VM pin and VDD pin (RVMD). If the voltage difference between the VDD pin and the VM pin decreases to
1.0 V typ. or lower, the power-down function starts to operate and most operations in the S-8245B/D Series halt. In
this case, the CO pin changes to high impedance, and the PSO pin changes to the VDD level.
The power-down function is released when the VM pin voltage changes to 0.7 V typ. or lower.
4. Discharge overcurrent status
When the discharge current increases to a certain value or more, the VINI pin voltage increases to the level of
discharge overcurrent 1 detection voltage (VDIOV1) or higher. If the status continues for the discharge overcurrent 1
detection delay time (tDIOV1)
*1 or longer, the DO pin changes to the VSS level. This is the discharge overcurrent status.
The discharge control FET is turned off to stop discharging. The VM pin is pulled down to the VSS level by resistance
between VM pin and VSS pin (RVMS).
Discharge overcurrent is detected at the following three levels: VDIOV1, VDIOV2, and VSHORT. When discharge
overcurrent 2 detection voltage (VDIOV2) and load short-circuiting detection voltage (VSHORT) are detected, the same
operations as VDIOV1 detection are performed.
The discharge overcurrent status is released if the following conditions are satisfied.
S-8245B Series: VVM VDS / 2 typ.
S-8245D Series: VVM VDS / 4 typ.
*1. Refer to "6. Delay time setting" for details.
Remark VVM
:
VM pin voltage
VDS
:
Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
5. Charge overcurrent status
When the charge current increases to a certain value or more, the VINI pin voltage decreases to the level of charge
overcurrent detection voltage (VCIOV) or lower. If the status continues for the charge overcurrent detection delay time
*1
(tCIOV
)
or longer, the CO pin changes to high impedance. This is the charge overcurrent status. The charge control
FET is turned off to stop charging. The VM pin is pulled up to the VDD level by resistance between VM pin and VDD
pin (RVMD).
The charge overcurrent status is released if VVM 0 V typ.
*1. Refer to "6. Delay time setting" for details.
Remark VVM
:
VM pin voltage
VDS
:
Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
17
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
6. Delay time setting
Users are able to set delay time for the period from when the S-8245B/D Series detects change in the voltage of any
of the batteries or the VINI pin until when it outputs to the CO pin or the DO pin. Each delay time is determined by a
resistor in the S-8245B/D Series and an external capacitor.
In the overchage detection, when the voltage of any of the batteries exceeds overcharge detection voltage n (VCUn),
the S-8245B/D Series starts charging to the CCT pin's capacitor (CCCT) via the CCT pin internal resistance (RCCT).
After a certain period, the CO pin changes to high impedance when the CCT pin reaches the CCT pin detection
voltage (VCCT). This period is overcharge detection delay time (tCU).
t
CU is calculated using the following equation.
t
CU [s] = ln (1 VCCT / VDS) CCCT [F] RCCT [M]
= ln (1 0.7 typ.) CCCT [F] 8.31 [M] typ.
= 10.0 [M] typ. CCCT [F]
Overdischarge detection delay time (tDL), discharge overcurrent 1 detection delay time (tDIOV1), discharge overcurrent 2
detection delay time (tDIOV2) and charge overcurrent detection delay time (tCIOV) are calculated using the following
equations as well.
t
t
t
t
DL [ms] = ln (1 VCDT / VDS) CCDT [F] RCDT [k]
DIOV1 [ms] = ln (1 VCIT / VDS) CCIT [F] RCIT [k]
DIOV2 [ms] = ln (1 VCIT2 / VDS) CCIT2 [F] RCIT2 [k]
CIOV [ms] = ln (1 VCICT / VDS) CCICT [F] RCICT [k]
When CCCT = CCDT = CCIT = CCIT2 = CCICT = 0.1 [F], each delay time is calculated as follows.
t
t
t
t
t
t
CU [s] = 10.0 [M] typ. 0.1 [F] = 1.0 [s] typ.
DL [ms] = 1000 [k] typ. 0.1 [F] = 100 [ms] typ.
DIOV1 [ms] = 1000 [k] typ. 0.1 [F] = 100 [ms] typ. (when RCIT = 831 k typ.)
DIOV1 [ms] = 10.0 [M] typ. 0.1 [F] = 1.0 [s] typ. (when RCIT = 8.31 M typ.)
DIOV2 [ms] = 200 [k] typ. 0.1 [F] = 20 [ms] typ.
CIOV [ms] = 200 [k] typ. 0.1 [F] = 20 [ms] typ.
Load short-circuiting detection delay time (tSHORT) is fixed internally.
Remark VDS Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
:
7. 0 V Battery charge function
Regarding how to charge a self-discharged battery (0 V battery), users are able to select either function mentioned
below.
(1) 0 V battery charge function "available"
A 0 V battery is charged when charger voltage is higher than V0CHA
(2) 0 V battery charge function "unavailable"
.
A 0 V battery is not charged when the voltage of any of the batteries is V0INHn or lower.
Caution When the VDD pin voltage is lower than the minimum value of operation voltage between the VDD
pin and VSS pin (VDSOP), the S-8245B/D Series' operation is not assured.
Remark V0CHA
:
0 V battery charge starting charger voltage
V0INHn
:
0 V battery charge inhibition battery voltage n (n = 1 to 5)
18
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
8. SEL1 pin and SEL2 pin
Switching control for 3-serial to 5-serial cell is possible by inputting voltage to the SEL1 pin and the SEL2 pin.
Be sure to use the SEL1 pin and the SEL2 pin at the "H" or "L" level.
Table 10 Settings of SEL1 Pin and SEL2 Pin
SEL1 Pin
SEL2 Pin
Setting
"L"
"L"
"H"
"H"
"L"
"H"
"L"
"H"
5-serial cell
4-serial cell
3-serial cell
Setting inhibited
Remark "H" is the status when VSEL1 VSEL1H, VSEL2 VSEL2H, and "L" is the status when VSEL1
VSEL1L, VSEL2 VSEL2L
.
VSEL1H
VSEL2H
:
:
SEL1 pin voltage "H"
SEL2 pin voltage "H"
SEL1 pin voltage "L"
SEL2 pin voltage "L"
VSEL1L
VSEL2L
:
:
9. CTLC pin and CTLD pin
The CTLC pin controls the CO pin, and the CTLD pin controls the DO pin. Thus it is possible for users to control the
CO pin and the DO pin respectively. These controls precede the battery protection circuit.
Table 11 Status Set by CTLC Pin
CTLC Pin
CO Pin
High impedance
"H"
VSS level CTLC pin voltage VCTLC
VCTLC CTLC pin voltage VDD level
Remark VCTLC
:
CTLC pin reverse voltage
Table 12 Status Set by CTLD Pin
CTLD Pin
DO Pin
VSS level CTLD pin voltage VCTLD
VCTLD CTLD pin voltage VDD level
VSS level
"H"
Remark VCTLD
:
CTLD pin reverse voltage
19
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
10. PSI pin
When the PSI pin is activated, the power-saving function starts to operate and most operations halt. In this case, the
CO pin changes to high impedance, DO pin changes to the VSS level, and the PSO pin changes to the VDD level.
Table 13 Status Set by PSI Pin
PSI Pin
CO Pin
DO Pin
PSO Pin
VSS level
VDD level
VPSI PSI pin voltage VDD level
VSS level PSI pin voltage VPSI
"H"
High impedance
"H"
VSS level
Remark VPSI: PSI pin reverse voltage
The S-8245B/D Series is initialized and the power-saving function is released by deactivating the PSI pin. As a result,
each detection operation is carried out after returning to the normal status.
11. Temperature detection
Serially connect an NTC and a low temperature-dependent resistor (RTH) between the VDD pin and the VREG pin,
and then connect their middle point to the TH pin. It allows for temperature detection at four different points: high
temperature detection during charging, low temperature detection during charging, high temperature detection during
discharging, low temperature detection during discharging.
When the temperature rises, according to the NTC temperature characteristics, the resistance (RNTC) decreases, and
the ratio between RNTC and RTH changes, and then the TH pin voltage (VTH) increases.
When the temperature falls, according to the NTC temperature characteristics, the resistance (RNTC) increases, and
the ratio between RNTC and RTH changes, and then the TH pin voltage (VTH) decreases.
The temperature detection during charging and temperature detection during discharging switch by comparing the VM
pin voltage (VVM) and charge-discharge discriminating voltage (VCHG).
If the relation between RNTC, RTH, and VVM satisfies the itemized condition in Table 14 in each temperature detection,
and each status continues for the temperature detection delay time (tTH) or longer, the CO pin changes to high
impedance, and the DO pin changes to the VSS level. This is the temperature protection status.
If the itemized condition in Table 14 is not satisfied in each temperature detection, and each status continues for tTH or
longer, the temperature protection status is released.
Table 14 Conditions for Each Temperature Detection
Item
TH Pin
VM Pin
VVM VCHG
VVM VCHG
VVM VCHG
VVM VCHG
CO Pin
DO Pin
High temperature detection during charging
Low temperature detection during charging
rTHCH RTH / (RNTC RTH
rTHCL RTH / (RNTC RTH
)
)
High impedance VSS level
High temperature detection during discharging rTHDH RTH / (RNTC RTH
Low temperature detection during discharging rTHDL RTH / (RNTC RTH
)
)
Remark rTHCH
rTHCL
rTHDH
rTHDL
:
:
:
:
High temperature detection ratio during charging
Low temperature detection ratio during charging
High temperature detection ratio during discharging
Low temperature detection ratio during discharging
20
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
The detection temperature can be set according to the NTC and RTH characteristics.
For example, if RNTC*1 and RTH (10 k) are connected to the S-8245BAA, each detection temperature is as follows.
Table 15
Item
Temperature Detection Ratio
THCH = 0.670
RNTC
Detection Temperature
Temperature for high temperature detection
during charging
r
r
r
r
4.9 k
45C
Temperature for low temperature detection
during charging
THCL = 0.270
THDH = 0.795
THDL = 0.190
27.0 k
2.6 k
0C
65C
10C
Temperature for high temperature detection
during discharging
Temperature for low temperature detection
during discharging
42.6 k
*1. The calculation method for RNTC is as follows.
rTHCL = RTH / (RNTC RTH
)
RNTC = RTH / rTHCL RTH
= 10 k / 0.270 10 k
= 27.0 k
When low temperature during charging is detected, RNTC = 27.0 k, so detection temperature = 0C according to
the RNTC characteristics shown in Figure 5.
RNTC = 10 k, Ta = 25C, B constant (25 / 85C) = 3434K
200
180
160
140
120
100
80
60
40
20
0
0
25
50
75 85
40
25
Ta [C]
Figure 5 Example of RNTC Characteristics
Remark Temperature detection is carried out intermittently for 512 ms typ. per cycle, of which 1 ms typ. is the
detection operation period.
The VREG pin voltage is output only during detection operation. During other periods, the VREG pin is at
the VDD level.
Regarding details of intermittent operation, refer to "4. Temperature detection (High temperature
detection during charging)" in " Timing Charts".
21
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Timing Charts
1. Overcharge detection, overdischarge detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
(n = 1 to 5)
VDD
DO pin voltage
VSS
VCOH
CO pin voltage
High-Z
High-Z
VEB
VDD
VDD 0.7 V typ.
VM pin voltage
VSS
VEB
Charger connection
Load connection
Overdischarge detection
Overcharge detection
delay time (tDL
)
delay time (tCU
)
Status*1
(With power-down function)
(1)
(2)
(1)
(3)
(4)
(1)
*1. (1) : Normal status
(2) : Overcharge status
(3) : Overdischarge status
(4) : Power-down status
Figure 6
22
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
2. Discharge overcurrent detection
VHC
VCUn
VCLn
Battery voltage
VDUn
VDLn
VHD
(n = 1 to 5)
VDOH
DO pin voltage
VSS
VCOH
CO pin voltage
VEB
VDD
VM pin voltage
VSS
VDD
VSHORT
VDIOV2
VDIOV1
VSS
VINI pin voltage
Load connection
Discharge overcurrent 1
detection delay time (tDIOV1
Load short-circuiting
detection delay time (tSHORT
Discharge overcurrent 2
detection delay time (tDIOV2
)
)
)
(2)
(1)
(2)
(1)
(2)
(1)
(1)
Status*1
*1. (1) : Normal status
(2) : Discharge overcurrent status
Figure 7
23
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. Charge overcurrent detection
VHC
VCUn
VCLn
Battery voltage
VHD
VDUn
VDLn
(n = 1 to 5)
VDOH
DO pin voltage
VSS
VCOH
High-Z
High-Z
High-Z
CO pin voltage
VEB
VDD
VM pin voltage
VINI pin voltage
VSS
VEB
VDD
VSS
VCIOV
Charger connection
Load connection
Charge overcurrent detection
delay time (tCIOV
Charge overcurrent detection
delay time (tCIOV
)
)
Status*1
(4) (3)
(2)
(1)
(1)
(1)
(2)
(With power-down function)
*1. (1) : Normal status
(2) : Charge overcurrent status
(3) : Overdischarge status
(4) : Power-down status
Figure 8
24
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
4. Temperature detection (High temperature detection during charging)
VDD
VTHCH = (1 rTHCH) VREG
TH pin voltage
V
THCL = (1 rTHCL) VREG
VREG
VDOH
DO pin voltage
VSS
VCOH
CO pin voltage
High-Z
VEB
VDD
VM pin voltage
VSS
VCHG
VEB
Charger connection
Status*1
Temperature detection delay time (tTH
)
(3)
(3)
(2)
(3)
(3)
(2)
(2)
(3)
(2)
(2)
(2)
(1)
(4)
*1. (1) : Normal status
(2) : Temperature detection sleep time
(3) : Temperature detection awake time
(4) : Temperature protection status
Figure 9
25
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Connection Examples of Battery Protection IC
1. S-8245B Series (5-serial cell with an integrated charge and discharge path)
EB
NTC
CTH
RTH
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
7 VC5
8 VSS
9 VINI
PSI 23
RPSI
RVDD
RVC1
RVC2
CVDD
CVC1
CVC2
CVC3
CVC4
CVC5
CTLD 22
RCTLD
RCTLC
CTLC 21
VM 20
RVC3
RVC4
RVC5
CO 19
S-8245B
DO 18
PSO 17
CIT2 16
CIT 15
10 SEL1
11 SEL2
12 CICT
CDT 14
CCT 13
RVM
RDO
RCO
CCICT
RVINI
CCCT
CCIT2
EB
CCDT CCIT
R
SEL1 RSEL2
RSENSE
Charge control FET
Discharge control FET
Remark Regarding the recommended values for external components, refer to "Table 16 Constants for External
Components".
Figure 10
26
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
2. S-8245B Series (4-serial cell with an integrated charge and discharge path)
EB
NTC
CTH
RTH
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
7 VC5
8 VSS
9 VINI
PSI 23
RPSI
RVDD
RVC1
RVC2
CVDD
CVC1
CVC2
CVC3
CVC4
CTLD 22
RCTLD
RCTLC
CTLC 21
VM 20
RVC3
RVC4
RVC5
CO 19
S-8245B
DO 18
PSO 17
CIT2 16
CIT 15
RSEL2
10 SEL1
11 SEL2
12 CICT
CDT 14
CCT 13
RVM
RDO
RCO
CCICT
RVINI
CCCT
CCIT2
EB
CCDT CCIT
RSEL1
RSENSE
Discharge control FET Charge control FET
Remark Regarding the recommended values for external components, refer to "Table 16 Constants for External
Components".
Figure 11
27
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. S-8245B Series (3-serial cell with an integrated charge and discharge path)
EB
NTC
CTH
RTH
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
7 VC5
8 VSS
9 VINI
PSI 23
RPSI
RVDD
RVC1
RVC2
CVDD
CVC1
CVC2
CVC3
CTLD 22
RCTLD
RCTLC
CTLC 21
VM 20
RVC3
RVC4
RVC5
CO 19
S-8245B
DO 18
PSO 17
CIT2 16
CIT 15
RSEL1
10 SEL1
11 SEL2
12 CICT
CDT 14
CCT 13
RVM
RDO
RCO
CCICT
RVINI
CCCT
CCIT2
EB
CCDT CCIT
RSEL2
RSENSE
Discharge control FET Charge control FET
Remark Regarding the recommended values for external components, refer to "Table 16 Constants for External
Components".
Figure 12
28
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
4. S-8245D Series (5-serial cell with separate charge and discharge paths)
EB
NTC
CTH
RTH
1 TH
VREG 24
2 VDD
3 VC1
4 VC2
5 VC3
6 VC4
7 VC5
8 VSS
9 VINI
PSI 23
RPSI
CVDD
RVDD
CTLD 22
CVC1
CVC2
RCTLD
RCTLC
RVC1
RVC2
CTLC 21
VM 20
REB
RVC3
RVC4
RVC5
CVC3
CVC4
CVC5
CO 19
S-8245D
DO 18
PSO 17
CIT2 16
CIT 15
10 SEL1
11 SEL2
12 CICT
CDT 14
RVM
RCO
CCT 13
RDO
CCICT
RVINI
CCCT
CCIT2
EB
CCDT CCIT
RSEL1 RSEL2
RSENSE
DIS
Charge control FET
Discharge control FET
Remark Regarding the recommended values for external components, refer to "Table 16 Constants for External
Components".
Figure 13
29
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Table 16 Constants for External Components
Symbol
Min.
68
Typ.
100
1.00
1
Max.
100
1.00
5.1
5.1
5.1
20.0
10
10.00
1.000
0.1
Unit
*1
RVDD
k
k
k
k
k
M
k
M
k
k
m
F
F
F
F
F
F
F
F
RVCn (n = 1 to 5)*1
0.68
1
RSEL1, RSEL2
RVINI
1.0
1.0
1.0
1.0
1.0
0.68
0.068
0.01
0.01
0.01
0.01
0.01
0.1
1.0
2.0
5.1
5.1
5.1
10
RCTLC, RCTLD, RPSI
RVM
RCO
RDO
REB
NTC
RTH
10
10
RSENSE
*1
CVDD
1.00
0.100
0.10
0.10
0.10
0.10
0.10
0.1
CVCn (n = 1 to 5)*1
CCCT
CCDT
CCIT
CCIT2
CCICT
CTH
D1
*1. RVDD CVDD = 100 F is recommended.
Set filter constants to satisfy RVC1 CVC1 = RVC2 CVC2 = RVC3 CVC3 = RVC4 CVC4 = RVC5 CVC5 = RVDD CVDD
.
Caution 1. The above constants may be changed without notice.
2. Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with
the actual application is needed to determine the proper constants when setting the filter constants
between the VDD pin and VSS pin. Contact our sales office if setting the constants between the
VDD pin and VSS pin to anything other than the recommended values.
3. It has not been confirmed whether the operation is normal or not in circuits other than the
connection examples. In addition, the connection examples and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
30
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
Batteries can be connected in any order; however, there may be cases when discharging cannot be performed after a
battery is connected. In this case, the S-8245B/D Series returns to the normal status when any of the following
conditions is satisfied.
(1) Connecting a charger
(2) Shorting between the VM pin and the VSS pin
(3) Changing the PSI pin voltage to be VDS 0 V VDS
Remark VDS: Input voltage between the VDD pin and VSS pin (V1 V2 V3 V4 V5)
If an overcharged battery and an overdischarged battery intermix, the S-8245B/D Series will change to the overcharge
and overdischarge statuses. Therefore, in this case, both charging and discharging are impossible.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
31
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs. VDS
1. 2 IOPE vs. Ta
Ta = 25C
VDS = 17.5 V
40
30
20
10
0
40
30
20
10
0
40
25
0
0
0
25
50
75 85
0
5
10
10
10
15
20
20
20
25
30
Ta [
C]
V
V
V
DS [V]
1. 3 IPDN vs. VDS
1. 4 IPDN vs. Ta
Ta = 25C
VDS = 7.5 V
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
40
25
25
50
75 85
0
5
15
25
30
Ta [C]
DS [V]
1. 5 IPSV vs. VDS
1. 6 IPSV vs. Ta
Ta = 25C
VDS = 17.5 V
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0.0
0.0
40 25
25
50
75 85
0
5
15
25
30
Ta [C]
DS [V]
32
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
2. Detection voltage, release voltage
2. 1 VCU vs. Ta
2. 2 VCL vs. Ta
S-8245BAA
4.12
S-8245BAA
4.100
4.11
4.10
4.09
4.08
4.075
4.050
4.025
4.000
40
25
0
25
50
75 85
40
25
0
25
50
75 85
Ta [C]
Ta [C]
2. 3 VDL vs. Ta
2. 4 VDU vs. Ta
S-8245BAA
2.68
S-8245BAA
2.80
2.75
2.70
2.65
2.60
2.64
2.60
2.56
2.52
40
25
0
25
50
75 85
40
25
0
0
0
25
50
75 85
Ta [C]
Ta [C]
2. 5 VDIOV1 vs. Ta
2. 6 VDIOV2 vs. Ta
S-8245BAA
0.030
VDS = 17.5 V
S-8245BAA
0.055
VDS = 17.5 V
0.050
0.045
0.040
0.035
0.030
0.025
0.025
0.020
0.015
0.010
40
25
25
50
75 85
40
25
0
25
50
75 85
Ta [
C]
Ta [
C]
2. 7
V
SHORT vs. Ta
2. 8 VCIOV vs. Ta
S-8245BAA
0.150
VDS = 17.5 V
S-8245BAA
VDS = 17.5 V
0.010
0.125
0.100
0.075
0.050
0.015
0.020
0.025
0.030
40
25
25
50
75 85
40
25
0
25
50
75 85
Ta [
C]
Ta [C]
33
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. Delay time function
3. 1 RCCT vs. Ta
3. 2 VCCT vs. Ta
VDS = 19 V
VDS = 19 V
16
12
8
14.0
13.5
13.0
12.5
12.0
4
0
40
25
0
0
0
0
25
50
75 85
40
25
0
0
0
0
25
50
75 85
Ta [
C]
Ta [
C]
3. 3 RCDT vs. Ta
3. 4 VCDT vs. Ta
VDS = 15.5 V
VDS = 15.5 V
1500
1250
1000
750
500
250
0
12
11
10
9
8
40
25
25
50
75 85
40
25
25
50
75 85
Ta [
C]
Ta [
C]
3. 5 RCIT vs. Ta
3. 6 VCIT vs. Ta
VDS = 17.5 V
VDS = 17.5 V
1500
1250
1000
750
500
250
0
14
13
12
11
10
40
25
25
50
75 85
40
25
25
50
75 85
Ta [
C]
Ta [
C]
3. 7 RCIT2 vs. Ta
3. 8 VCIT2 vs. Ta
VDS = 17.5 V
VDS = 17.5 V
300
250
200
150
100
50
14
13
12
11
10
0
40
25
25
50
75 85
40
25
25
50
75 85
Ta [
C]
Ta [C]
34
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
3. 9
RCICT vs. Ta
3. 10 VCICT vs. Ta
VDS = 17.5 V
VDS = 17.5 V
300
250
200
150
100
50
14
13
12
11
10
0
40
25
0
25
50
75 85
40
25
0
25
Ta [ C]
50
75 85
Ta [
C]
3. 11 tSHORT vs. Ta
VDS = 17.5 V
340
320
300
280
260
40
25
0
25
50
75 85
Ta [C]
35
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
4. Output pin
4. 1 ICOH vs. VDS
4. 2 ICOL vs. VDS
Ta = 25C
Ta = 25C
1600
1200
800
400
0
0.10
0.08
0.06
0.04
0.02
0.00
0
5
10
15
20
20
20
25
30
0
5
10
15
20
20
20
25
30
V
DS [V]
V
DS [V]
4. 3 IDOH vs. VDS
4. 4 IDOL vs. VDS
Ta = 25C
Ta = 25C
6000
5000
4000
3000
2000
1000
0
2500
2000
1500
1000
500
0
0
5
10
10
0
15
25
30
0
5
10
10
0
15
25
30
V
DS [V]
V
DS [V]
4. 5 IPSOH vs. VDS
4. 6 IPSOL vs. VDS
Ta = 25C
Ta = 25C
10
8
10
8
6
6
4
4
2
2
0
0
0
5
15
25
30
0
5
15
25
30
V
DS [V]
VDS [V]
4. 7 VCOH vs. Ta
4. 8 VDOH vs. Ta
VDS = 17.5 V
VDS = 17.5 V
15
14
13
12
11
15
14
13
12
11
40
25
25
Ta [ C]
50
75 85
40
25
25
Ta [ C]
50
75 85
36
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
5. Temperature detection function
5. 1 rTHCH vs. Ta
5. 2 rTHCL vs. Ta
VDS = 17.5 V
VDS = 17.5 V
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
40
25
0
25
50
75 85
40
25
0
0
0
25
50
75 85
Ta [
C]
Ta [
C]
5. 3 rTHDH vs. Ta
5. 4 rTHDL vs. Ta
VDS = 17.5 V
VDS = 17.5 V
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
0.4
0.2
0.0
40
25
0
25
50
75 85
40
25
25
50
75 85
Ta [
C]
Ta [
C]
5. 5 VREG vs. Ta
5. 6 VCHG vs. Ta
VDS = 17.5 V
VDS = 17.5 V
6.0
5.5
5.0
4.5
4.0
0.010
0.015
0.020
0.025
0.030
40
25
0
25
50
75 85
40
25
25
50
75 85
Ta [
C]
Ta [C]
5. 7
tTH vs. Ta
VDS = 17.5 V
3.0
2.5
2.0
1.5
1.0
40
25
0
25
50
75 85
Ta [C]
37
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8245B/D Series
Rev.1.4_00
Power Dissipation
24-Pin SSOP
T = 125C max.
j
2.0
1.5
1.0
0.5
0.0
B
A
0
25
50
75
100 125 150 175
Ambient temperature (Ta) [C]
Board
Power Dissipation (PD)
A
B
C
D
E
1.43 W
1.67 W
38
24-Pin SSOP Test Board
No. SSOP24-A-Board-SD-1.0
ABLIC Inc.
7.9±0.2
24
13
+0.1
-0.05
0.15
12
1
0.65
0.22±0.1
No. FS024-B-P-SD-1.0
TITLE
SSOP24-B-PKG Dimensions
FS024-B-P-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
-0
4.0±0.1
ø1.5
2.0±0.1
1.5±0.05
+0.1
ø1.5
-0
0.3±0.05
12.0±0.1
8.15±0.1
24
13
1
12
Feed direction
No. FS024-B-C-SD-1.0
TITLE
No.
SSOP24-B-Carrier Tape
FS024-B-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
60°
17.4±1.0
21.4±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FS024-B-R-SD-1.0
TITLE
SSOP24-B-Reel
No.
FS024-B-R-SD-1.0
ANGLE
UNIT
3000
QTY.
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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