S-8249AAB-M6T1U [ABLIC]
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION;
| 型号： | S-8249AAB-M6T1U |
| 厂家： | 
ABLIC |
| 描述： | VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION 局域网 监视器 |
| 文件： | 总23页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8249 Series
www.ablic.com
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
© ABLIC Inc., 2015-2017
Rev.1.4_01
The S-8249 Series is a voltage monitoring IC with a cell balancing function and includes a high-accuracy voltage
detection circuit and a delay circuit.
The S-8249 Series is suitable for cell balancing and overcharge protection of batteries and capacitors.
Features
High-accuracy voltage detection circuit
Cell balancing detection voltage: 2.0 V to 4.6 V (5 mV step)
Accuracy 12 mV (2.0 V VBU 2.4 V)
Accuracy 0.5% (2.4 V VBU 4.6 V)
Accuracy 24 mV (2.0 V VBL 2.4 V)
Accuracy 1.0% (2.4 V VBL 4.6 V)
Accuracy 12 mV (2.0 V VCU 2.4 V)
Accuracy 0.5% (2.4 V VCU 4.6 V)
Accuracy 24 mV (2.0 V VCL 2.4 V)
Accuracy 1.0% (2.4 V VCL 4.6 V)
Cell balancing release voltage:
Overcharge detection voltage:
Overcharge release voltage:
2.0 V to 4.6 V*1
2.0 V to 4.6 V (5 mV step)
2.0 V to 4.6 V*2
Built-in Nch transistor with ON resistance of 5 typ. between the CB pin and the VSS pin
Current consumption: 2.0 A max. (Ta = 25°C)
Delay times are generated only by an internal circuit (External capacitors are unnecessary).
CO pin output form and output logic are selectable: CMOS output Active "H", active "L"
Nch open-drain output Active "H", active "L"
_____
Switchable to power-saving mode by using the CE pin
Operation temperature range:
Ta = 40°C to 85°C
Lead-free (Sn 100%), halogen-free
*1. Cell balancing release voltage = Cell balancing detection voltage Cell balancing hysteresis voltage
(Cell balancing hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.)
*2. Overcharge release voltage = Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.)
Applications
Rechargeable battery module
Capacitor module
Package
SOT-23-6
1
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Block Diagram
VDD
CB
Control circuit
Delay circuit
CO
DP
1 M
Power-saving mode
switching circuit
_____
CE
1 M
VSS
*1. All diodes shown in the figure are parasitic diodes.
Figure 1
2
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Product Name Structure
1. Product name
S-8249A xx
-
M6T1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M6T1:SOT-23-6, Tape
Serial code
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
2. Package
Table 1 Package Drawing Codes
Package Name
SOT-23-6
Dimension
Tape
Reel
MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD
3. Product name list
Table 2 (2 / 1)
Cell Balancing Cell Balancing Overcharge Overcharge
Detection
Voltage
[VBU
Release
Voltage
Detection
Voltage
Release
Voltage
CO Pin
CO Pin
Combination of
Delay Time
Product Name
Output Form
Output Logic
]
[VBL
]
[VCU
]
[VCL]
S-8249AAA-M6T1U
S-8249AAB-M6T1U
S-8249AAC-M6T1U
S-8249AAD-M6T1U
S-8249AAE-M6T1U
S-8249AAF-M6T1U
S-8249AAG-M6T1U
S-8249AAH-M6T1U
S-8249AAI-M6T1U
S-8249AAK-M6T1U
S-8249AAL-M6T1U
S-8249AAM-M6T1U
S-8249AAN-M6T1U
S-8249AAO-M6T1U
S-8249AAP-M6T1U
S-8249AAQ-M6T1U
S-8249AAR-M6T1U
S-8249AAS-M6T1U
S-8249AAT-M6T1U
S-8249AAU-M6T1U
S-8249AAV-M6T1U
S-8249AAW-M6T1U
S-8249AAY-M6T1U
2.600 V
3.000 V
3.000 V
3.100 V
3.100 V
2.600 V
2.400 V
2.400 V
2.100 V
2.400 V
2.100 V
2.620 V
3.300 V
2.000 V
3.700 V
3.800 V
2.800 V
2.800 V
2.800 V
2.500 V
2.300 V
2.650 V
4.150 V
2.600 V
3.000 V
3.000 V
3.100 V
3.100 V
2.600 V
2.400 V
2.400 V
2.100 V
2.400 V
2.000 V
2.520 V
3.300 V
2.000 V
3.700 V
3.800 V
2.800 V
2.800 V
2.800 V
2.400 V
2.200 V
2.600 V
4.150 V
2.750 V
3.150 V
3.200 V
3.250 V
3.300 V
2.800 V
2.900 V
3.000 V
3.000 V
3.200 V
3.200 V
2.800 V
4.080 V
3.000 V
4.500 V
4.080 V
3.150 V
3.200 V
3.100 V
3.800 V
3.800 V
2.750 V
4.275 V
2.750 V
3.150 V
3.200 V
3.250 V
3.300 V
2.800 V
2.900 V
3.000 V
3.000 V
3.200 V
3.200 V
2.700 V
3.930 V
3.000 V
4.500 V
3.930 V
3.150 V
3.200 V
3.100 V
3.700 V
3.700 V
2.650 V
4.275 V
CMOS output
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
Nch open-drain output Active "L"
CMOS output Active "H"
3
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Table 2 (2 / 2)
Cell Balancing Cell Balancing Overcharge Overcharge
Detection
Voltage
Release
Voltage
Detection
Voltage
Release
Voltage
CO Pin
CO Pin
Combination of
Delay Time
Product Name
Output Form
Output Logic
[VBU
]
[VBL
]
[VCU
]
[VCL]
S-8249ABA-M6T1U
S-8249ABB-M6T1U
S-8249ABC-M6T1U
3.650 V
4.350 V
4.200 V
3.550 V
4.350 V
4.200 V
3.800 V
4.425 V
4.300 V
3.500 V
4.325 V
4.200 V
CMOS output
Active "L"
Active "L"
Active "L"
(3)
(3)
(4)
CMOS output
CMOS output
Remark1. Contact our sales office for the products with detection voltage values other than those specified above.
2. Set VCU > VBU
.
3. Refer to Table 3 for details about combinations of delay times.
Table 3
Cell Balancing
Detection Delay Time Release Delay Time
[tBU [tBL
Cell Balancing
Overcharge Detection Overcharge Release
Delay Time Delay Time
[tCU [tCL
Combination of
Delay Time
]
]
]
]
(1)
(2)
(3)
(4)
128 ms
128 ms
64 ms
1.0 ms
1.0 ms
2.0 ms
2.0 ms
128 ms
1024 ms
256 ms
256 ms
1.0 ms
1.0 ms
2.0 ms
1.0 ms
64 ms
Remark
The delay times can be changed within the ranges listed above. For details, please contact our sales
office.
Table 4
Delay Time
Symbol
tBU
Selection Range
Remark
Cell balancing detection
delay time*1
Select a value
from the left.
Select a value
from the left.
Select a value
from the left.
Select a value
from the left.
128 ms*2
64 ms
0.5 ms
64 ms
0.5 ms
256 ms 512 ms 1024 ms
2.0 ms
Cell balancing release
delay time
1.0 ms*2
tBL
tCU
tCL
Overcharge detection
delay time*1
128 ms*2
256 ms 512 ms 1024 ms
Overcharge release
delay time
1.0 ms*2
2.0 ms
*1. Set tCU tBU
.
*2. The value is the delay time of the standard products.
4
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Pin Configuration
1. SOT-23-6
Table 5
Pin No.
Symbol
CO
Description
Top view
1
2
Output pin for overcharge signal
Input pin for negative power supply
Test mode switching pin
6
5
4
VSS
3
4
DP
"H": Test mode (used to shorten the delay time)
"L": Normal operation mode
Power-saving mode switching pin
"H": Power-saving mode
1
2
3
_____
CE
"L": Normal operation mode
Figure 2
5
6
VDD
CB
Input pin for positive power supply
Output pin for cell balancing signal
(Nch open-drain output)
5
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Absolute Maximum Ratings
Table 6
(Ta = 25°C unless otherwise specified)
Item
Symbol
VDS
Applied Pin
Absolute Maximum Rating
Unit
Input voltage between VDD pin and
VSS pin
VDD
___
VSS 0.3 to VSS 6.0
V
CE, DP
Input pin voltage
VIN
VSS 0.3 to VDD 0.3 VSS 6.0
VSS 0.3 to VDD 0.3 VSS 6.0
100 (40°C to 85°C)
40 to 85
V
V
Output pin voltage
VOUT
ICB
CO, CB
CB
Output pin current
mA
°C
°C
Operation ambient temperature
Storage temperature
Topr
Tstg
55 to 125
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 7
Item
Symbol
Condition
Board A
Min.
Typ.
159
124
Max.
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Board B
Board C
Board D
Board E
Junction-to-ambient thermal resistance*1 JA
SOT-23-6
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
6
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Electrical Characteristics
For details about the test circuits and testing method, refer to " Test Circuit".
Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF.
Table 8 (1 / 2)
(Ta = 25°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Detection voltage
VBU
0.012
VBU
0.012
2.0 V VBU 2.4 V
2.4 V VBU 4.6 V
2.0 V VBL 2.4 V
2.4 V VBL 4.6 V
VBU
VBU
VBL
VBL
VCU
VCU
VCL
V
V
V
V
V
V
V
V
Cell balancing detection
voltage
VBU
SW1 = ON
SW1 = ON
VBU
0.995
VBL
0.024
VBL
0.99
VBU
1.005
VBL
0.024
VBL
1.01
Cell balancing release
voltage
VBL
VCU
VCL
VCU
0.012
VCU
0.012
2.0 V VCU 2.4 V
2.4 V VCU 4.6 V
2.0 V VCL 2.4 V
2.4 V VCL 4.6 V
Overcharge detection
voltage
VCU
0.995
VCL
0.024
VCL
VCU
1.005
VCL
0.024
VCL
Overcharge release
voltage
VCL
0.99
1.01
Temperature coefficient
VBU
Ta VBU
VCU
Ta VCU
Detection voltage
ppm/
°C
ppm/
°C
Ta = 40°C to 85°C*3
Ta = 40°C to 85°C*3
100
100
350
350
temperature coefficient 1*1
Detection voltage
temperature coefficient 2*2
Input voltage
Operation voltage between
VDD pin and VSS pin
Voltages output from CO pin and
CB pin are fixed
VDS
1.5
5.0
V
_____
VDD
0.9
_____
V
V
V
V
VCE
H
CE pin voltage "H"
_____
VDD
_____
VCE
L
CE pin voltage "L"
0.1
VDD
0.9
DP pin voltage "H"
DP pin voltage "L"
VDPH
VDPL
VDD
0.1
Input current
Current consumption
during operation
Current consumption
during power-saving
IOPE
IPSV
IVDD when V1 = VBL 0.1 V
1.2
2.0
0.1
A
A
IVDD when V1 = V2 = VBL 0.1 V
*1. A change in the temperature of the detection voltage [mV/°C] is calculated by using the following equation.
VBU
Ta
VBU
Ta VBU
mV/°C = V
V
BU [ ]
ppm/°C 1000
[ ]
[
]
*2. A change in the temperature of the detection voltage [mV/°C] is calculated by using the following equation.
VCU
Ta
VCU
Ta VCU
mV/°C = V
V
CU [ ]
ppm/°C 1000
[ ]
[
]
*3. Since products are not screened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
VBU VCU
Remark 1.
,
:
Change in temperature of detection voltage
Set detection voltage
Ta
Ta
2.
3.
V
BU, VCU:
VBU
VCU
,
: Detection voltage temperature coefficient
Ta VBU Ta VCU
7
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Table 8 (2 / 2)
(Ta = 25°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Delay time
Cell balancing detection
delay time
tBU
tBU 0.8
tBL 0.8
tCU 0.8
tCL 0.8
tBU
tBL
tCU
tBU 1.2 ms
tBL 1.2 ms
tCU 1.2 ms
tCL 1.2 ms
Cell balancing release
delay time
tBL
tCU
tCL
Overcharge detection delay
time
Overcharge release delay
time
tCL
Output current
CB pin output current
V1 = VBU 0.1 V, SW2 = ON,
V4 = 0.5 V
V1 = VBL 0.1 V, SW2 = ON,
V4 = 6.0 V
CB pin sink current
ICBS
ICBL
30
mA
A
CB pin leakage current
0.1
CO pin output current (output form: CMOS output, output logic: active "H")
V1 = VCL 0.1 V, SW4 = ON,
V5 = 0.5 V
V1 = VCU 0.1 V, SW4 = ON,
V5 = V1 0.5 V
CO pin sink current
ICOL
ICOH
5.0
1.0
mA
mA
CO pin source current
CO pin output current (output form: CMOS output, output logic: active "L")
V1 = VCU 0.1 V, SW4 = ON,
V5 = 0.5 V
V1 = VCL 0.1 V, SW4 = ON,
V5 = V1 0.5 V
CO pin sink current
ICOL
ICOH
5.0
1.0
mA
mA
CO pin source current
CO pin output current (output form: Nch open-drain output, output logic: active "H")
V1 = VCL 0.1 V, SW4 = ON,
V5 = 0.5 V
V1 = VCU 0.1 V, SW4 = ON,
V5 = 6.0 V
CO pin sink current
ICOL
5.0
mA
A
CO pin leakage current
ICOHL
0.1
CO pin output current (output form: Nch open-drain output, output logic: active "L")
V1 = VCU 0.1 V, SW4 = ON,
V5 = 0.5 V
V1 = VCL 0.1 V, SW4 = ON,
V5 = 6.0 V
CO pin sink current
ICOL
5.0
mA
A
CO pin leakage current
ICOHL
0.1
8
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Test Circuit
RCB = 100 k
RCO = 100 k
SW1
SW3
IVDD
A
VDD
VSS
CO
CB
S-8249
Series
V1
DP
_____
CE
SW2
SW4
V5
ICO
V2
V3
V4
ICB
A
A
Figure 3
Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF.
_____
1. CE pin voltage "H"
_____
_____
CE pin voltage "H" (VCEH) is defined as the voltage at which IVDD is changed from IOPE to IPSV when V2 is increased
from 0 V after setting V1 = VBL 0.1 V.
_____
2. CE pin voltage "L"
_____
_____
CE pin voltage "L" (VCE ) is defined as the voltage at which IVDD is changed from IPSV to IOPE when V2 is decreased
L
from VBL 0.1 V after setting V1 = V2 = VBL 0.1 V.
3. DP pin voltage "H"*1
DP pin voltage "H" (VDPH) is defined as the voltage at which the test mode is switched when V3 is increased from
0 V after setting V1 = VBL 0.1 V.
4. DP pin voltage "L" *1
DP pin voltage "L" (VDPL) is defined as the voltage at which the normal operation mode is switched when V3 is
decreased from VBL 0.1 V after setting V1 = V3 = VBL 0.1 V.
5. Cell balancing detection delay time
Cell balancing detection delay time (tBU) is defined as the time from when SW1 is set to ON and V1 is set to VBU
0.1 V to when the CB pin output is inverted after setting V1 to VBU 0.1 V.
6. Cell balancing release delay time
Cell balancing release delay time (tBL) is defined as the time from when SW1 is set to ON and V1 is set to VBL
0.1 V to when the CB pin output is inverted after setting V1 to VBL 0.1 V.
7. Overcharge detection delay time
Overcharge detection delay time (tCU) is defined as the time from when SW1 is set to ON and V1 is set to VCU
0.1 V to when the CO pin output is inverted after setting V1 to VCU 0.1 V.
8. Overcharge release delay time
Overcharge release delay time (tCL) is defined as the time from when SW1 is set to ON and V1 is set to VCL
0.1 V to when the CO pin output is inverted after setting V1 to VCL 0.1 V.
*1. For details about switching to the test mode by using the DP pin, refer to "5. DP pin" in " Operation".
9
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Standard Circuit
VDD
CO
DP
RVDD
C
VDD
S-8249
Series
CB
R
CB
_____
VSS
CE
Figure 4
Table 9 Constants for External Components
Symbol
RVDD
Part
Purpose
ESD
protection,
for power
fluctuation
control
Min.
Typ.
Max.
Remark
Resistance should be as small as possible to
Resistor
150
330 1.0 k avoid worsening the overcharge detection
accuracy due to current consumption.*1
For power
fluctuation
control
Connect a capacitor of 0.068 F or more
CVDD
Capacitor
Resistor
0.068 F 0.1 F 1.0 F
between VDD pin and VSS pin.*1
For setting
the cell
balancing
current value
Set the required cell balancing current value
depending on "2. Cell balancing status" in
" Operation".*2
RCB
*1. When connecting a resistor less than 150 to RVDD or a capacitor less than 0.068 F to CVDD, the S-8249 Series
may malfunction when power is largely fluctuated.
*2. Set the cell balancing current value so that RCB does not exceed the power dissipation.
Cautions 1. The above constants may be changed without notice.
2. The example of connection shown above and the constant do not guarantee proper operation.
Perform thorough evaluation using the actual application to set the constant.
10
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Operation
Remark Refer to " Standard Circuit".
1. Normal status
In the S-8249 Series, if the voltage between the VDD pin and the VSS pin (VDS) has not reached the cell
balancing detection voltage (VBU), the CB pin output is in the high-impedance status. The CO pin output status
varies according to the output form and output logic selected, as shown in Table 10. This is the normal status.
Table 10
CO Pin Output Form and Output Logic CB Pin Output CO Pin Output
CMOS output, active "H"
"H"
"H"
"H"
"H"
"L"
"H"
"L"
"H"
CMOS output, active "L"
Nch open-drain output, active "H"
Nch open-drain output, active "L"
2. Cell balancing status
In the S-8249 Series, if VDS is VBU or higher and this status continues for the cell balancing detection delay time
(tBU) or longer, the CB pin output becomes "L". This is the cell balancing status.
The cell balancing status is released when VDS drops to the cell balancing release voltage (VBL) or lower and this
status continues for the cell balancing release delay time (tBL) or longer.
The S-8249 Series includes an Nch transistor with ON resistance of 5 typ. (RCBON) between the CB pin and the
VSS pin, thus causing the cell balancing current (ICB) to flow in cell balancing status, and the cell balancing
operation to start.
By connecting a resistor (RCB) to the CB pin, ICB in cell balancing status can be calculated by using the following
equation.
ICB = VBU / (RCBONRCB
)
S-8249 Series
VDD
CB
RCB
ICB
Control
circuit
RCBON
= 5 typ.
VSS
Figure 5
11
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
3. Overcharge status
In the S-8249 Series, if VDS is the overcharge detection voltage (VCU) or higher and this status continues for the
overcharge detection delay time (tCU) or longer, the CO pin output is inverted. The CO pin output status varies
according to the output form and output logic selected, as shown in Table 11. This is the overcharge status. In
the overcharge status, the CB pin output becomes "L".
Table 11
CO Pin Output Form and Output Logic CB Pin Output CO Pin Output
CMOS output, active "H"
"L"
"L"
"L"
"L"
"H"
"L"
"H"
"L"
CMOS output, active "L"
Nch open-drain output, active "H"
Nch open-drain output, active "L"
The overcharge status is released when VDS drops to the overcharge release voltage (VCL) or lower and this
status continues for the overcharge release delay time (tCL) or longer.
_____
4. CE pin
_____
The S-8249 Series has the CE pin (Power-saving mode switching pin). The S-8249 Series is set to
_____
_____
power-saving mode by inputting a voltage of VCE or higher to the CE pin.
H
Table 12
___
CE Pin
Status
_____
Open (VCE = VSS
)
Normal operation mode
Power-saving mode
Normal operation mode
_____
_____
"H" (VCE VCE
)
H
_____
_____
"L" (VCE VCE
)
L
In power-saving mode, the current consumption is decreased to current consumption during power-saving (IPSV).
The CB pin or the CO pin output in power-saving mode is the same as that in the normal status.
_____
The__C__E_ pin is pulled down to VSS by the internal resistor. When in a mode other than power-saving mode, leave
the CE pin open or short it with VSS
.
12
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
5. DP pin
The S-8249 Series has the DP pin (Test mode switching pin). The S-8249 Series is set to test mode (used to
shorten the delay time) by inputting a voltage of VDPH or higher to the DP pin.
Table 13
DP Pin
Open (VDP = VSS
"H" (VDP VDPH
"L" (VDP VDPL
Status
Normal operation mode
Test mode
)
)
)
Normal operation mode
In test mode, the cell balancing detection delay time (tBU) and overcharge detection delay time (tCU) are
shortened to 1/64 of the delay time in the normal operation mode.
The DP pin is pulled down to VSS by the internal resistor. When in a mode other than test mode, leave the DP
pin open or short it with VSS
.
13
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Timing Chart
VCU
VCL (VCUVHC
)
Battery voltage
VBU
VBL (VBUVHB
)
*1
VCB
CB pin voltage
VSS
VDD
CO pin voltage
(Active "H")
VSS
VDD
CO pin voltage
(Active "L")
VSS
Charger connection
Cell balancing detection delay time
Cell balancing release delay time (tBL
(2) (1)
(
tBU)
tBU
Overcharge detection delay time
Overcharge release delay time
(2) (3) (2)
(tCU)
)
(
tCL
)
tBL
(1)
(1)
Status*2
*1. The CB pin is pulled up by the external resistor.
*2. (1): Normal status
(2): Cell balancing status
(3): Overcharge status
Remark The charger is assumed to charge with a constant current.
Figure 6
14
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement
by products including this IC of patents owned by a third party.
15
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs. Ta
1. 2 IPSV vs. Ta
VDD = VBL 0.1 V
VDD = VBL 0.1 V
2.50
2.00
1.50
1.00
0.50
0.10
0.08
0.06
0.04
0.02
0.00
0.00
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
1. 3 IOPE vs. VDD
4.00
3.00
2.00
1.00
0.00
0.0
1.0
2.0
3.0
4.0
5.0
V
DD [V]
2. Cell balancing detection / release voltage, overcharge detection / release voltage and delay
times
2. 1 VBU vs. Ta
2. 2 VBL vs. Ta
2.62
2.64
2.61
2.60
2.59
2.62
2.60
2.58
2.58
2.56
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
2. 3 VCU vs. Ta
2. 4 VCL vs. Ta
2.77
2.76
2.75
2.74
2.79
2.77
2.75
2.73
2.73
2.71
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
16
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
2. 5 tBU vs. Ta
2. 6 tBL vs. Ta
160
140
120
100
1.2
1.1
1.0
0.9
0.8
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
2. 7 tCU vs. Ta
2. 8 tCL vs. Ta
160
1.2
1.1
1.0
0.9
0.8
140
120
100
40 25
0
25
50
75 85
40 25
0
25
50
75 85
Ta [C]
Ta [C]
3. Output current
3. 1 ICBL vs. VCB
3. 2 ICBS vs. VCB
Ta = 25C, VDD = VBL 0.1 V
Ta = 25C, VDD = VBU 0.1 V
0.10
0.08
0.06
0.04
0.02
0.00
400
300
200
100
0
0.0
1.0
2.0
3.0
4.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
V
CB [V]
VCB [V]
3. 3 ICOH vs. VCO
3. 4 ICOL vs. VCO
Ta = 25C, VDD = VCU 0.1 V
Ta = 25C, VDD = VCL 0.1 V
8.0
6.0
4.0
2.0
0.0
40.0
30.0
20.0
10.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
CO [V]
V
CO [V]
17
VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION
S-8249 Series
Rev.1.4_01
Power Dissipation
SOT-23-6
Tj = 125C max.
1.0
0.8
B
0.6
0.4
0.2
0.0
A
0
25
50
75
100 125 150 175
Ambient temperature (Ta) [C]
Board
Power Dissipation (PD)
A
B
C
D
E
0.63 W
0.81 W
18
SOT-23-3/3S/5/6 Test Board
No. SOT23x-A-Board-SD-2.0
ABLIC Inc.
2.9±0.2
1.9±0.2
6
5
4
+0.1
-0.05
1
3
2
0.15
0.95
0.95
0.35±0.15
No. MP006-A-P-SD-2.1
TITLE
SOT236-A-PKG Dimensions
MP006-A-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
-0
2.0±0.05
0.25±0.1
ø1.5
+0.2
-0
ø1.0
4.0±0.1
1.4±0.2
3.2±0.2
3
4
2 1
6
5
Feed direction
No. MP006-A-C-SD-3.1
TITLE
SOT236-A-Carrier Tape
MP006-A-C-SD-3.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP006-A-R-SD-2.1
TITLE
SOT236-A-Reel
MP006-A-R-SD-2.1
No.
ANGLE
UNIT
QTY
3,000
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
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