ALVD-0.750MHZ-D-P-T [ABRACON]
PECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN;
| 型号： | ALVD-0.750MHZ-D-P-T |
| 厂家： | 
ABRACON |
| 描述： | PECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN 机械 振荡器 |
| 文件： | 总3页 (文件大小：1702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD
RoHS
7.0 x 5.0 x 1.8mm
Pb
Compliant
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FEATURES:
APPLICATIONS:
• Based on a proprietary digital multiplier
• Tri-State Output
• SONET, xDSL
• SDH, CPE
• STB
• Low Phase Jitter
• 3.3V +/- 5% operation
• Ceramic SMD, low profile package
STANDARD SPECIFICATIONS:
ARAMETERS
P
ABRACON P/N:
ALVD Series
Frequency range:
750 KHz to 800 MHz
0°C to +70°C (see options)
-55°C to +125°C
Operating temperature:
Storage temperature:
Overall frequency stability:
Supply voltage (Vdd):
±50 ppm max. (see options)
3.3V ± 10%
Voltage control (VC):
Symmetry at 1/2 Vdd:
Output Level:
0.3VDC min, 1.65VDC typ, 3.0 VDC max.
40/60% max.
See options (PECL, CMOS, or LVDS)
± 50ppm (see option)
Pullability:
Tristate Function:
"1" (VIH >= 0.7* Vdd) or open: Oscillation
"0" (VIL < 0.3* Vdd) : Hi Z
±5 ppm max.
Aging per year:
RMS Phase Jitter:
Period Jitter (peak to peak):
Phase Noise:
3ps typical, 5ps max. (12KHz~20MHz)
35 ps typical
-112 dBc/Hz @ 1kHz Offset from 155.52MHz
-125 dBc/Hz @ 10kHz Offset from 155.52MHz
-123 dBc/Hz @ 100KHz Offset from 155.52MHz
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100KHz Offset from 622.08MHz
PECL:
Supply current (IDD):
25mA max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<700MHz)
Output Logic High: Vdd-1.025V min, Vdd-0.880V max.
Output Logic Low: Vdd-1.810V min. Vdd-1.620V max.
Symmetry (Duty Cycle): 45% min, 50% typ, 55% max,
Rise time: 0.6nSec typ,1.5nS max
Fall time: 0.6nSec typ, 1.5nS max
CMOS:
Supply current (IDD):15
mA max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz), 40mA max (96MHz<Fo<700MHz)
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 1.2ns typ, 1.6ns max.
Output Clock Duty Cycle [Measured @ 50% VDD]: 45% min, 50% typical, 55% max
LVDS:
Supply current (IDD):25
mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<700MHz)
Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max
Output Differential Voltage (VOD): 247mV min, 355mV typical, 454mV max
VDD Magnitude Change (? VOD): -50mV min, 50mV max
Output High Voltage : VOH = 1.4V typical, 1.6V max.
Output Low Voltage: VOL = 0.9V min, 1.1V typical
Offset Voltage [RL = 100?? : VOS = 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Change [RL = 100?? : ? VOS = 0mV min, 3mV typical, 25mV max
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] = ±1?A typical, ±10?A max.
Differential Clock Rise Time (tr) [RL=100? , CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max
Differential Clock Fall Time (tf) [RL=100? , CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max
Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.22.09
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001| www.abracon.com
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD
RoHS
7.0 x 5.0 x 1.8mm
Pb
Compliant
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PIN ASSIGNMENTS
Name
Vc
Tristate
GND
Q
DESRIPTION
Voltage Control
PIN #
1
2
3
4
5
6
Tristate
Ground
PECL, LVDS, or CMOS Output.
Complimentary PECL,LVDS, or NC.
VDD Connection.
Q
VDD
TRI-STATE PIN OPERATION:
OUTPUT TYPE
PIN 2 logic level*
Output State (Tri-state)
OPTION
0 (Default)
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
P
P1
V
PECL
PECL1
LVDS
1
0
1
0
1(Default)
0
1(Default)
C
CMOS
*Connect to VDD for logic level "1", connect to ground for logic level "0".
OPTIONS & PART IDENTIFICATION:
(Left blank if standard)
ALVD - Frequency - - - - -
Frequency
Frequency Stability
Packaging
XX.XXXXMHz
R
K
H
±25ppm max.
±30ppm max.
±35ppm max.
Blank
Bulk
Tape and
Reel
T
Operating Temp.
D
E
F
N
L
-10ºC~60ºC
-20ºC~70ºC
-30ºC~70ºC
-30ºC~85ºC
-40ºC~85ºC
Output Level
Pullability
P
P1
V
PECL
PECL1
LVDS
N100
±100ppm
C
CMOS
OUTLINE DRAWING:
PIN #
1
Function
Vc
Tri-state
GND
Q
Note: Recommend using
an approximately 0.01uF
bypass capacitor between
PIN 3 and 6.
2
3
4
*5
Q
VDD
*Complimentary PECL/LVDS or NC.
6
Dimensions: inches (mm)
Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.22.09
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001| www.abracon.com
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD
RoHS
7.0 x 5.0 x 1.8mm
Pb
Compliant
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Tape and reel (1,000pcs/reel)
TAPE & REEL:
Dimensions: mm
REFLOW PROFILE:
NOTE: Abracon manufactured products are intended for general commercial and industrial use. For applications requiring
high reliability and/or presenting extreme operating environment, written consent & authorization from Abracon is required.
Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.22.09
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001| www.abracon.com
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
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