APV-FREQ-L-R-V-T [ABRACON]

LVDS Output Clock Oscillator, 38MHz Min, 640MHz Max, CERAMIC,SMD, 4 PIN;
APV-FREQ-L-R-V-T
型号: APV-FREQ-L-R-V-T
厂家: ABRACON    ABRACON
描述:

LVDS Output Clock Oscillator, 38MHz Min, 640MHz Max, CERAMIC,SMD, 4 PIN

文件: 总2页 (文件大小:750K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CERAMICC SSMMD CRYSSTTAALL CLOCK OSCILLATTOORR  
APV SERIES  
: PRELIMINARY  
5.0 x 7.0 x 1.8mm  
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APPLICATIONS:  
• SONET, Fiber Channel, SERDES  
HDTV, OBSAI, CPRI, PCI Express, 1394  
FEATURES:  
• Low Jitter  
• CMOS, PECL or LVDS Output  
• Low Power ( 2.5, 3.3V )  
• Sub 1pS ( 12kHz - 20MHz )  
STANDARD SPECIFICATIONS:  
PARAMETERS  
Frequency Range  
38 MHz to 640 MHz  
Operating Temperature  
Storage Temperature  
0°C to + 70°C (see options)  
-55°C to +125°C  
Overall Frequency Stability  
Supply Voltage (Vdd)  
Phase Jitter RMS (12KHz-20MHz)  
Period Jitter (peak to peak)  
Tri-State Function  
50 ppm maꢀx (see options)  
2x25V to 3x63V (2x5V to 3x3V 10ꢁ)  
0x5pS Typ, 1pS Maꢀ  
20pS typx, 30pS maꢀ up to 320 MHz; 50pS typx, 70pS maꢀ 321MHz to 640MHz  
For CMOS and LVDS = "1" (VIH ³ 0x7* Vdd) or open: Oscillation;  
"0" (VIL < 0x3* Vdd): No oscillation/Hi Z  
For PECL See TriState Pin Operation table P Option Standard PECL OE  
"0" (VIL < 0x3* Vdd): or Open: Oscillation; "1" (VIH ³ 0x7* Vdd): No oscillation/Hi Z  
P Option = "1" (VIH ³ 0x7* Vdd) or open: Oscillation;  
"0" (VIL < 0x3* Vdd): No oscillation/Hi Z  
PECL  
65mA maꢀ (for 38MHz<Fo<320MHz), 90mA maꢀ (320MHz<Fo<640MHz)  
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx  
Supply Current (IDD)  
Symmetry (Duty Cycle)  
Output Logic High  
Output Logic Low  
Rise time  
VDD -1x025V min, VDD -0x880V maꢀx  
VDD -1x810V min, VDD -1x620V maꢀx  
1x5ns maꢀ, 0x6nSec typical  
Fall time  
1x5ns maꢀ, 0x6nSec typical  
CMOS  
30mA maꢀ (38MHz<Fo<320MHz)  
45ꢁ min, 50ꢁ typ, 55ꢁ maꢀ,  
(0x3V ~ 3x0V w/15 pF load) 0x7nS Typx; (20ꢁ-80ꢁ w/50Ω Load) 0x3nS Typx  
Supply Current  
Symmetry (Duty Cycle)  
Rise/ Fall Time  
LVDS  
45mA maꢀ(for 38MHz<Fo<320MHz), 70mA maꢀ (320MHz<Fo<640MHz)  
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ  
Supply Current (IDD)  
Output Clock Duty Cycle @ 1x25V  
Output Differential Voltage (VOD  
)
247mV min, 355mV typical, 454mV maꢀ  
-50mV min, 50mV maꢀ  
VDD Magnitude Change (VOD  
)
Output High Voltage  
VOH = 1x6V maꢀ, 1x4V typical  
Output Low Voltage  
VOL = 0x9V min, 1x1V typical  
Offset Voltage [RL = 100  
Offset Magnitude Voltage[RL = 100  
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]  
Differential Clock Rise Time (tr) [RL=100 , CL=10pF]  
Differential Clock Fall Time (tf) [RL=100 , CL=10pF]  
]  
VOS = 1x125V min, 1x2V typical, 1x375V maꢀ  
VOS = 0mV min, 3mV typical, 25mV maꢀ  
10µA maꢀ, 1µA typical  
0x7ns typical, 1x0ns maꢀ, 0x2nS min  
0x7ns typical, 1x0ns maꢀ, 0x2nS min  
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ABRACON IS  
ISO 9001 / QS 9000  
CERTTIIFFIED  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com  
CERAMICC SSMMD CRYSSTTAALL CLOCK OSCILLATTOORR  
APV SERIES  
: PRELIMINARY  
5.0 x 7.0 x 1.8mm  
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MARKING:  
PIN ASSIGNMENTS:  
- TUH  
Frequency  
PIN #  
NAME  
Tri-state  
NC  
GND  
Q
DESCRIPTION  
T=First “ten” digit of frequency,  
U=First “unit” of frequency,  
H=First “tenth” digit of freq,  
Ex: 100 for 10.0MHz;  
1
2
3
4
5
6
Tri-state  
No Connect  
Ground  
PECL, LVDS  
Complimentary PECL, LVDS  
VDD Connection  
143 for 14.31818 MHz)  
- APV ZYX (Z: Month, A to L;  
Y: Year, 5 for 2005;  
Q
VDD  
X: Traceability Code)  
TRI-STATE PIN OPERATION:  
OUTPUT TYPE OPTION PIN 1 LOGIC LEVEL*  
OUTPUT STATE  
Enabled  
0 (Default)  
P
P1  
V
PECL  
PECL1  
LVDS  
1
Tri-state  
1
Enabled  
0
0
Tri-state  
Tri-state  
1 (Default)  
0
Enabled  
Tri-state  
C
CMOS  
1 (Default)  
Enabled  
*Connect to VDD from logic level "1", connect to ground for logic level "0".  
OPTIONS AND PART IDENTIFICATION (Left blank if standard)  
:
APVX - Frequency - Temperature - Frequency Stability - Output - Packaging  
Output options:  
Vdd options:  
Blank  
Temperature:  
E for -20°C to +70°C  
L for -40°C to +85°C  
Stability options:  
R for 25 ppm max  
S for 20 ppm max  
(3.3Vdc 10ꢀV)  
(2.5Vdc 10ꢀV)  
P = PECL  
P1 = PECL1  
V = LVDS  
1
Packaging option: T for Tape and Reel  
C = CMOS  
(1,000pcs/reel)  
PECL & LVDS DRAWING:  
CMOS DRAWING:  
PIN #  
NAME  
Tri-state  
GND/Case  
Output  
1
2
3
4
Vdd  
Dimensions: inch (mm)  
Dimensions: inch (mm)  
ABRACON IS  
ISO 9001 / QS 9000  
CERTTIIFFIED  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com  

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