ACE24AC512EDPTH [ACE]
Two-wire Serial EEPROM;
| 型号： | ACE24AC512EDPTH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | Two-wire Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：1294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE24AC512E
Two-wire Serial EEPROM
Description
The ACE24AC512E series are 524,288 bits of serial Electrical Erasable and Programmable Read Only
Memory, commonly known as EEPROM. They are organized as 65,536 words of 8 bits (one byte) each.
The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead
TSSOP and 8-lead USON3*2-8 packages. A standard 2-wire serial interface is used to address all read
and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of
applications.
Features
⚫
Low voltage and low power operations:
ACE24AC512E: VCC = 1.8V to 5.5V
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
⚫
Maximum Standby current < 1µA
128 bytes page write mode.
Partial page write operation allowed.
Internally organized: 65,536 × 8 (512K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
1 MHz (2.5-5.5V), 400 kHz (1.8V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40℃to 85℃).
Standard 8-lead DIP/SOP/MSOP/TSSOP/ USON3*2-8 Pb-free packages.
Absolute Maximum Ratings
Industrial operating temperature:
-40℃ to 85℃
-50℃to 125℃
-0.3V to VCC + 0.3V
8V
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
ESD Protection on all pins:
>4000V
Notice: Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional
operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme
conditions may affect device reliability or functionality.
VER 1.1
1
ACE24AC512E
Two-wire Serial EEPROM
Packaging Type
DIP-8
SOP-8
TSSOP-8
MSOP-8
USON3*2-8
Pin Configurations
Pin Name
Functions
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
AO-A2
SDA
SCL
WP
Write Protect
No-Connect
NC
Ordering information
ACE24AC512E XX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
TM: TSSOP-8
DP: DIP-8
OM: MSOP-8
UA8: USON3*2-8
VER 1.1
2
ACE24AC512E
Two-wire Serial EEPROM
Block Diagram
Pin Descriptions
A. DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.
B. SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
C. SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
D. WRITE PROTECT (WP)
The ACE24AC512E device has a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all
programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not
affected by the WP pin’s input level.
VER 1.1
3
ACE24AC512E
Two-wire Serial EEPROM
Memory Organization
The ACE24AC512E devices have 512 pages respectively. Since each page has 128 bytes, random word
addressing to ACE24AC512E will require 16 bits data word addresses respectively.
Device Operation
(A) Serial Clock And Data Transitions
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a start or stop condition
as described below.
(B) Start Condition
With SCL VIH, a SDA transition from high to low is interpreted as a start condition. All valid
commands must begin with a start condition.
(C) Stop Condition
With SCL VIH, a SDA transition from low to high is interpreted as a stop condition. All valid read or
write commands end with a stop condition. The device goes into the standby mode if it is after a read
command. A stop condition after page or byte write command will trigger the chip into the standby
mode after the self-timed internal programming finish (see Figure 1).
(D) Acknowledge
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
acknowledge signal occurs on the 9th serial clock after each word.
(E) Standby Mode
The EEPROM goes into low power standby mode after a fresh power up, after receiving a stop bit in
read mode, or after completing a self-time internal programming operation.
Figure 1: Timing diagram for start and stop conditions
VER 1.1
4
ACE24AC512E
Two-wire Serial EEPROM
Figure 2: Timing diagram for output acknowledge
Device Addressing
The 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke
a valid read or write command. The first four most significant bits of the device address must be 1010,
which is common to all serial EEPROM devices. The next three bits are device address bits. These three
device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a
match is made, the EEPROM device outputs an acknowledge signal after the 8th read/write bit, otherwise
the chip will go into standby mode. However, matching may not be needed for some or all device address
bits (5th, 6thand 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then
the chip goes into read mode. If a “0” is detected, the device enters programming mode.
VER 1.1
5
ACE24AC512E
Two-wire Serial EEPROM
Write Operations
(A) Byte Write
A write operation requires two 8-bit data word address following the device address word and
acknowledge signal. Upon receipt of this address, the EEPROM will respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again
output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence
with a stop condition. At this time the EEPROM enters into an internally-timed write cycle state. All
inputs are disabled during this write cycle and the EEPROM will not respond until the writing is
completed (figure 3).
(B) Page Write
The 512K EEPROM are capable of 128-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. The microcontroller can transmit up to 127 more data
words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond
with a “0” after each data word is received. The microcontroller must terminate the page write
sequence with a stop condition (see Figure 4).
The lower five bits of the data word address are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page row
location. If more than 64 data words are transmitted to the EEPROM, the data word address will
“roll over” and the previous data will be overwritten.
(C) Acknowledge Polling
Acknowledge polling may be used to poll the programming status during a self-timed internal
programming. By issuing a valid read or write address command, the EEPROM will not acknowledge
at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the
programming completes and the chip has returned to the standby mode, the device will return a valid
acknowledge signal at the 9th clock cycle.
VER 1.1
6
ACE24AC512E
Two-wire Serial EEPROM
Read Operations
The read command is similar to the write command except the 8th read/write bit in address word is set to
“1”. The three read operation modes are described as follows:
(A) Current Address Read
The EEPROM internal address word counter maintains the last read or write address plus one if the
power supply to the device has not been cut off. To initiate a current address read operation, the
micro- controller issues a start bit and a valid device address word with the read/write bit (8th) set to
“1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8-bit
data word will then be serially clocked out. The internal address word counter will then automatically
increase by one. For current address read the micro-controller will not issue an acknowledge signal
on the 18th clock cycle. The micro-controller issues a valid stop bit after the 18th clock cycle to
terminate the read operation. The device then returns to standby mode (see Figure 5).
(B) Sequential Read
The sequential read is very similar to current address read. The micro-controller issues a start bit
and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with
an acknowledge signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked
out. Meanwhile the internally address word counter will then automatically increase by one.
Unlike current address read, the micro-controller sends an acknowledge signal on the 18th clock
cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the
acknowledge signal, the EEPROM will serially clocked out an 8-bit data word based on the
incremented internal address counter. If the micro-controller needs another data, it sends out an
acknowledge signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out.
This sequential read continues as long as the micro-controller sends an acknowledge signal after
receiving a new data word. When the internal address counter reaches its maximum valid address, it
rolls over to the beginning of the memory array address. Similar to current address read, the micro-
controller can terminate the sequential read by not acknowledging the last data word received, but
sending a stop bit afterwards instead (figure 6).
(C) Random Read
Random read is a two-steps process. The first step is to initialize the internal address counter with a
target read address using a “dummy write” instruction. The second step is a current address read.
To initialize the internal address counter with a target read address, the micro-controller issues a
start bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM
will then acknowledge. The micro-controller will then send two address words. Again, the EEPROM
will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller
performs a current address read instruction to read the data. Note that once a start bit is issued, the
EEPROM will reset the internal programming process and continue to execute the new instruction -
which is to read the current address (figure 7).
VER 1.1
7
ACE24AC512E
Two-wire Serial EEPROM
Figure 3: Byte Write
Figure 4: Page Write
Figure 5: Current Address Read
Figure 6: Sequential Read
VER 1.1
8
ACE24AC512E
Two-wire Serial EEPROM
Figure 7: Random Read
Figure 8: SCL and SDA Bus Timing
Electrical Specifications
A. Power-Up Requirements
During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to
the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A
decoupling cap should be connected to the VCC PAD which is no smaller than 10nF.
B. Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-
up sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the device will
not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that
brings the device out of Reset and into Standby mode. The system designer must ensure the
instructions are not sent to the device until the VCC supply has reached a stable value greater than
or equal to the minimum VCC level.
VER 1.1
9
ACE24AC512E
Two-wire Serial EEPROM
Figure 9: Power on and Power down
If an event occurs in the system where the VCC level supplied to the device drops below the maximum
VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the
VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in
compliance with the requirements defined in this section.
VER 1.1 10
ACE24AC512E
Two-wire Serial EEPROM
AC Characteristics
Symbol
1.8V
2.5~5.5V
Parameter
Units
Min
Max
Min
Max
fSCL
TLOW
THIGH
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
400
1000
kHz
µs
1.3
0.6
0.6
0.2
µs
TI
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can Start(1)
Start Hold Time
100
0.9
50
ns
TAA
0.55
µs
TBUF
1.3
0.5
µs
THD.STA
TSU.STA
THD.DAT
TSU.DAT
TR
0.6
0.6
0
0.25
0.25
0
µs
µs
µs
ns
µs
ns
µs
ns
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
100
100
0.3
0.3
TF
300
100
TSU.STO
TDH
Stop Setup Time
0.6
50
0.25
50
Data Out Hold Time
Time required after VCC is stable before
the device can accept commands
Minimum time at Vcc=0V between power
cycles
tPUP
100
500
100
500
µs
tPOFF
tWR
ms
Write cycle time
5
5
ms
Write
Cycles
Endurance(1)
1,000,000
25℃, Page Mode, 3.3V
Notes:
1. This Parameter is expected by characterization but are not fully screened by test.
2. AC Measurement conditions:
RL (Connects to Vcc): 1.3KΩ
Input Pulse Voltages: 0.3Vcc to 0.7VCC
Input and output timing reference Voltages: 0.5VCC
VER 1.1 11
ACE24AC512E
Two-wire Serial EEPROM
DC Characteristics
Symbol
VCC1
ICC
Parameter
Test Condition
Min
Typ
Max
5.5
1.0
3.0
Units
V
24AC512 supply VCC
Supply Read Current
Supply Write Current
Supply Current
1.8
VCC@5.0V SCL=100 kHz
VCC@5.0V SCL=100 kHz
VCC@1.8V,VIN = VCC or VSS
VCC@2.5V,VIN = VCC or VSS
VCC@5.0V,VIN = VCC or VSS
VIN= VCC or VSS
0.4
2.0
mA
mA
µA
µA
µA
µA
µA
V
ICC
ISB1
ISB2
ISB3
ILI
<1.0
<1.0
<1.0
Supply Current
Supply Current
Input Leakage Current
Output Leakage Current
Input Low Level
3.0
3.0
VIN= VCC or VSS
ILO
VIL
-0.6
VCC*0.3
VCC+0.5
0.4
VIH
Input High Level
VCC*0.7
V
VCC@3.0V, IOL= 2.1 mA
VCC@1.8V, IOL= 0.15 mA
VOL2
VOL1
Output Low Level
Output Low Level
V
0.4
V
VER 1.1 12
ACE24AC512E
Two-wire Serial EEPROM
Packaging information
DIP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
B
3.710
0.510
3.200
0.380
4.310
0.146
0.020
0.126
0.015
0.170
3.600
0.570
0.142
0.022
B1
C
1.524（BSC）
0.060（BSC）
0.204
9.000
6.200
7.320
0.360
9.400
6.600
7.920
0.008
0.354
0.244
0.288
0.014
0.370
0.260
0.312
D
E
E1
e
2.540 (BSC)
0.100（BSC）
L
3.000
8.400
3.600
9.000
0.118
0.331
0.142
0.354
E2
VER 1.1 13
ACE24AC512E
Two-wire Serial EEPROM
Packaging information
SOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
0.053
0.004
0.053
0.013
0.006
0.185
0.150
0.228
0.069
0.010
0.061
0.020
0.010
0.200
0.157
0.244
c
D
E
E1
e
1.270 (BSC)
0.050 (BSC)
L
0.400
0°
1.270
8°
0.016
0°
0.050
8°
θ
VER 1.1 14
ACE24AC512E
Two-wire Serial EEPROM
Packaging information
MSOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
0.820
0.020
0.750
0.250
0.090
2.900
1.100
0.150
0.950
0.380
0.230
3.100
0.320
0.001
0.030
0.010
0.004
0.114
0.043
0.006
0.037
0.015
0.009
0.122
c
D
e
0.65 (BSC)
0.026 (BSC)
E
2.900
4.750
0.400
0°
3.100
5.050
0.800
6°
0.114
0.187
0.016
0°
0.122
0.199
0.031
6°
E1
L
θ
VER 1.1 15
ACE24AC512E
Two-wire Serial EEPROM
Packaging information
TSSOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
D
E
2.900
4.300
0.190
0.090
6.250
3.100
4.500
0.300
0.200
6.550
1.100
1.000
0.150
0.114
0.169
0.007
0.004
0.246
0.122
0.177
0.012
0.008
0.258
0.043
0.039
0.006
b
c
E1
A
A2
A1
e
0.800
0.020
0.031
0.001
0.65 (BSC)
0.25 (TYP)
0.026 (BSC)
L
0.500
1°
0.700
7°
0.020
0.028
H
0.01 (TYP)
θ
1°
7°
VER 1.1 16
ACE24AC512E
Two-wire Serial EEPROM
Packaging information
USON3*2-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
0.550
0.050
0.300
Min
Max
0.021
0.002
0.039
A
A1
b
0.450
0.000
0.180
0.017
0.000
0.007
b1
c
0.160REF
0.006REF
0.100
1.900
1.400
0.200
2.100
1.600
0.004
0.075
0.055
0.008
0.083
0.062
D
D2
e
0.500BSC
1.500BSC
0.020BSC
0.059BSC
0.114
Nd
E
2.900
1.500
0.300
0.200
3.100
1.700
0.500
0.300
0.122
0.067
0.020
0.12
E2
L
0.059
0.012
0.066
h
VER 1.1 17
ACE24AC512E
Two-wire Serial EEPROM
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Technology Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.1 18
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明