ACE24LA08UA8TH [ACE]
Two-wire Serial EEPROM;
| 型号： | ACE24LA08UA8TH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | Two-wire Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：1112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Description
The ACE24LA02.04.08.16A provides 2048/4096/8192/16384 bits of serial electrically erasable and
programmable read- only memory (EEPROM), organized as 256/512/1024/2048 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential.
Features
Compatible with all I2C bidirectional data transfer protocol
Memory array:
2K bits (256X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) of EEPROM
Page size: 16 bytes
Single supply voltage and high speed:1 MHz
Random and sequential Read modes
Write:
Byte Write within 3 ms
Page Write within 3 ms
Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise Suppression
High-reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
Enhanced ESD/Latch-up protection
HBM 8000V
8-lead PDIP/SOP/TSSOP/USON3*2-8 and CSP4 packages
Absolute Maximum Ratings
DC Supply Voltage
-0.3V to 6.5V
GND-0.3V to VCC+0.3V
-40℃ to 85℃
-65℃ to 150℃
8000V
Input / Output Voltage
Operating Temperature
Storage Temperature
Electrostatic pulse (Human Body model)
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are
stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the
operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions
for extended periods may affect device reliability.
VER 1.1
1
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging Type
SOP-8
TSSOP-8
DIP-8
USON3*2-8
CSP-4
Pin Configurations
Type
Pin Name
AO-A2
SDA
Functions
I
I/O
I
Address Inputs
Serial Data
SCL
Serial Clock Input
Write Protect
Ground
I
WP
P
P
GND
VCC
Power Supply
Ordering information
ACE24LA XX A XX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
TM: TSSOP-8
DP: DIP-8
UA8: USON3*2-8
CP4：CSP-4
02: 2K bit
04: 4K bit
08: 8K bit
16: 16K bit
VER 1.1
2
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Block Diagram
VER 1.1
3
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Pin Descriptions
Device/Page Addresses (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard wire for the ACE24LA02.04.08.16A Eight
2K/4K/8K/16K devices may be addressed on a single bus system (device addressing is discussed in
detail under the Device Addressing section).
Serial Data (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed
with any number of other open-drain or open- collector devices.
Serial Clock (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
Write Protect (WP):
The ACE24LA02.04.08.16A has a Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations when connected to ground (GND). When the
Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in
the following Table 1.
Table1. Write Protect
Part of theArray Protected
WP Pin Status
ACE24LA02.04.08.16A
At VCC
Full Array
At GND
Normal Read / Write Operations
Memory Organization
ACE24LA02A, 2K SERIAL EEPROM: Internally organized with 16 pages of 16 bytes each, the 2K
requires an 8- bit data word address for random word addressing.
ACE24LA04A, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K
requires a 9- bit data word address for random word addressing.
ACE24LA08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10- bit data word address for random word addressing.
ACE24LA16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word addressing.
Device Operation
Clock and Data Transitions:
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during
SCL low time periods (see Figure 1). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
VER 1.1
4
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command
(see Figure2).
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2).
Acknowledge:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Standby Mode:
The ACE24LA02.04.08.16A features a low-power standby mode which is enabled: (a) upon power- up
and (b) after the receipt of the STOP bit and the completion of any internal operations.
Memory Reset:
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDAhigh in each cycle while SCL is high and then.
3. Create a start condition.
Figure 1: Data Validity
VER 1.1
5
Figure 2: Start and Stop Definition
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Figure 3: Output Acknowledge
Device Addressing
The 2K/4K/8K/16K EEPROM devices all require an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see Figure 4)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits
as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must
compare to their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page
address bit. The two device address bits must compare to their corresponding hardwired input pins. The
A0 pin is no connecting.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page
addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are
no connecting.
The 16K does not use any device address bits but instead the 3 bits are used for memory page
addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most
significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip
will return to a standby state.
Write Operations
Byte Write:
A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock
in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
VER 1.1
6
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At
this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs
are disabled during this write cycle and the EEPROM will not respond until the write is complete (see
Figure 5).
Page Write:
The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of
16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data
word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The
EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the
page write sequence with a stop condition (see Figure 6).
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the
receipt of each data word. The higher data word address bits are not incremented, retaining the memory
page row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K)
data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will
be overwritten.
Acknowledge Polling:
Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge
polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will
the EEPROM respond with a "0", allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to "1". There are three read operations: current address read,
random address read and sequential read.
Current Address Read:
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address "roll over" during read is from the last byte of the last memory page to the first
byte of the first page. The address "roll over" during write is from the last byte of the current page to the
first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in
and acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input "0" but does generate a following stop condition (see
Figure 7).
VER 1.1
7
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Random Read:
A random read requires a "dummy" byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address
read by sending a device address with the read/write select bit high. The EEPROM acknowledges the
device address and serially clocks out the data word. The microcontroller does not respond with a "0" but
does generate a following stop condition (see Figure 8)
Sequential Read:
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives
an acknowledge, it will continue to increment the data word address and serially clock out sequential data
words. When the memory address limit is reached, the data word address will "roll over" and the
sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a "0" but does generate a following stop condition (see Figure9).
MSB
LSB
2K
4K
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
R/W
1
1
1
0
P0
P0
P0
R/W
R/W
R/W
8K
0
P1
P1
16K
P2
Figure 4: Device Address
Figure 5: Byte write
VER 1.1
8
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Figure 6: Page write
Figure 7: Current Address Read
Figure 8: Random Read
Figure 9: Sequential Read
VER 1.1
9
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Pin Capacitance
Applicable over recommended operating range from: TA = 25℃, f = 1.0 MHz, VCC = +1.7V.
Symbol
CI/O
Test Condition
Max
8
Units Conditions
Input / Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
pF
pF
V
I/O = 0V
CIN
6
VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, (unless otherwise noted).
Symbol
VCC1
VCC2
ICC1
Parameter
Test Condition
Min
1.7
2.5
Typ
Max
5.5
Units
Supply Voltage
V
5.5
Supply Current VCC=5.0V
Supply Current VCC=5.0V
Standby Current VCC=5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
Read at 400kHz
Write at 400 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
VCC=1.7V to 5.5V
VCC=1.7V to 5.5V
IOL = 3.0 mA
0.14
0.28
0.03
0.10
0.05
0.3
mA
mA
µA
µA
µA
V
ICC2
0.5
ISB1
0.5
ILI
1.0
ILO
1.0
VIL1
-0.3
VCC*0.3
VCC+0.3
0.2
VIH1
VOL1
VOL2
Input High Level
VCC*0.7
V
Output Low Level VCC=1.7V
Output Low Level VCC=5.0V
V
IOL = 3.0 mA
0.4
V
VER 1.1
10
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
AC Characteristics
Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate
and 100 pF (unless otherwise noted)
1.7V≦VCC<2.5V
2.5V≦VCC≦5.5V
Symbol
Parameter
Units
Min
Typ
Max
Min
Typ
Max
fSCL
TLOW
THIGH
TI
Clock Frequency, SCL
Clock Pulse Width Low
400
1000
kHz
s
0.6
0.4
0.6
0.4
Clock Pulse Width High
s
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can Start
50
50
ns
s
TAA
0.1
0.5
0.55
0.1
0.5
0.55
TBUF
s
THD.STA
TSU.STA
THD.DAT
TSU.DAT
TR
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time (1)
Inputs Fall Time (1)
Stop Setup Time
0.25
0.25
0.
0.25
0.25
0
s
s
s
100
100
ns
0.3
0.3
0.3
0.3
µs
TF
µs
TSU.STO
TDH
0.25
50
0.25
50
s
Data Out Hold Time
Write Cycle Time
ns
TWR
1.9
3
1.9
3
ms
Write
Cycles
Endurance
Notes:
5.0V, 25℃, Page Mode(1)
1M
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions: RL (connects to VCC): 1.3 k
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: 50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading on the user's system.
VER 1.1
11
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Bus Timing
Figure 10． SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11． SCL: Serial Clock, SDA: Serial Data I/O
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
VER 1.1
12
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging information
DIP-8
SYMBOL
MIN
NOM
MAX
NOTE
2
A
A2
b
0.210
0.195
0.022
0.070
0.045
0.014
0.400
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
D1
E
0.310
0.250
0.325
0.280
E1
e
0.100BSC
0.300BSC
0.130
eA
L
4
2
0.115
0.150
VER 1.1
13
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging information
SOP-8
SYMBOL
MIN
1.35
0.10
0.31
0.17
4.80
3.81
5.79
NOM
MAX
1.75
0.25
0.51
0.25
5.00
3.99
6.20
A
A1
b
C
D
E1
E
e
1.27BSC
L
0.40
0"
1.27
8"
Φ
VER 1.1
14
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging information
TSSOP-8
SYMBOL
MIN
NOM
3.00
MAX
3.10
NOTE
2,5
D
E
2.90
6.40BSC
4.40
E1
A
4.30
4.50
1.20
1.05
0.30
3,5
4
A2
b
0.80
0.19
1.00
e
0.65BC
0.60
L
0.45
0.75
L1
1.00REF
VER 1.1
15
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging information
USON3*2-8
COMMON DIMENSION(MM)
PKG
REF
A
UT:ULTRA THIN
NOM
MIN
>0.50
0.00
MAX
0.60
0.05
0.55
A1
A3
D
0.15REF
2.00
1.95
2.95
0.20
0.20
1.25
1.15
2.05
3.05
0.30
0.40
1.50
1.40
E
3.00
b
0.25
L
0.30
D2
E2
e
1.40
1.30
0.50BSC
VER 1.1
16
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Packaging information
CSP-4
SYMBOL
A
MIN
NOM
0.290
MAX
0.270
0.310
A1
0.045
0.055
0.065
A2
D
0.215
0.738
0.235
0.255
0.778
0.758
D1
E
0.400BSC
0.688
0.668
0.160
0.708
0.200
E1
b
0.400BSC
0.180
x1
x2
y1
y2
0.144 REF
0.144 REF
0.179 REF
0.179 REF
VER 1.1
17
ACE24LA02.04.08.16A
Two-wire Serial EEPROM
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.1
18
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