ACE24LA1024ATMTH [ACE]
Two-wire Serial EEPROM;
| 型号： | ACE24LA1024ATMTH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | Two-wire Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE24LA1024A
Two-wire Serial EEPROM
Description
The ACE24LA1024A provides 1048576 bits of serial electrically erasable and programmable read-
only memory (EEPROM), organized as 131072 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential.
The ACE24LA1024A offers an additional page, named the Identification Page (256 bytes). The
Identification Page can be used to store sensitive application parameters which can be (later)
permanently locked in Read-only mode.
Features
Compatible with all I2C bidirectional data transfer protocol
Memory array:
1024 Kbits (128 Kbytes) of EEPROM
Page size: 256 bytes
Additional Write lockable page
Single supply voltage and high speed: 400kHz@2.0V
Random and sequential Read modes
Write:
Byte Write within 5 ms
Page Write within 5 ms
Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
High-reliability
Endurance: 4 Million Write Cycles
Data Retention: 100 Years
Enhanced ESD/Latch-up protection
HBM 8000V
8-lead PDIP/SOP/TSSOP/USON3*2/CSP packages
Absolute Maximum Ratings
DC Supply Voltage
-0.3V to 6.5V
GND-0.3V to VCC+0.3V
-40℃ to 85℃
Input / Output Voltage
Operating Temperature
Storage Temperature
-65℃ to 150℃
8000V
Electrostatic pulse (Human Body model)
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are
stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the
operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions
for extended periods may affect device reliability.
VER 1.3
1
ACE24LA1024A
Two-wire Serial EEPROM
Packaging Type
SOP-8
TSSOP-8
DIP-8
USON3*2-8
CSP-8
Pin Configurations
Type
Pin Name
A1-A2
SDA
Functions
I
I/O
I
Address Inputs
Serial Data
SCL
Serial Clock Input
Write Protect
Ground
I
WP
P
P
GND
VCC
Power Supply
Ordering information
ACE24LA1024A XX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
TM: TSSOP-8
DP: DIP-8
UA8: USON3*2-8
CP8：CSP-8
VER 1.3
2
ACE24LA1024A
Two-wire Serial EEPROM
Block Diagram
Pin Descriptions
Device/Page Addresses (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard wire for the ACE24LA1024A. Eight 256K
devices may be addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section).
Serial Data (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed
with any number of other open-drain or open- collector devices.
Serial Clock (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
Write Protect (WP):
The ACE24LA1024A has a Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations when connected to ground (GND). When the
Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in
the following Table 1.
Table1. Write Protect
WP Pin Status
At VCC
ACE24LA1024A
Full (1024K) Array
At GND
Normal Read / Write Operations
VER 1.3
3
ACE24LA1024A
Two-wire Serial EEPROM
Functional Description
Memory Organization
ACE24LA1024A, 1M Serial EEPROM:
Internally organized with 512 pages of 256 bytes each, the 1M requires a 17-bit data word address for
random word addressing.
Device Operation
Clock and Data Transitions:
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during
SCL low time periods (see Figure 1). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command
(see Figure 2).
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2).
Acknowledge:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Standby Mode:
The ACE24LA1024A features a low-power standby mode which is enabled: (a) upon power- up and (b)
after the receipt of the STOP bit and the completion of any internal operations.
Memory Reset:
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high and then.
3. Create a start condition.
VER 1.3
4
ACE24LA1024A
Two-wire Serial EEPROM
Figure 1: Data Validity
Figure 2: Start and Stop Definition
Figure 3: Output Acknowledge
VER 1.3
5
ACE24LA1024A
Two-wire Serial EEPROM
Device Addressing
The 1M EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 4)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits
as shown. This is common to all the Serial EEPROM devices.
The 1M EEPROM uses A2 and A1 device address bits to allow as much as eight devices on the same
bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use
an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip
will return to a standby state.
Figure 4: Device Address and two 8-bit data word address
DATA SECURITY: The ACE24LA1024A has a hardware data protection scheme that allows the user to
write protect the entire memory when the WP pin is at VCC.
VER 1.3
6
ACE24LA1024A
Two-wire Serial EEPROM
Write Operations
Byte Write:
A write operation requires two 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock
in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At
this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs
are disabled during this write cycle and the EEPROM will not respond until the write is complete (see
Figure 5).
Figure 5. Byte Write
Page Write:
A write operation requires two 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock
in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At
this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs
are disabled during this write cycle and the EEPROM will not respond until the write is complete (see
Figure 6).
Figure 6. Page Write
VER 1.3
7
ACE24LA1024A
Two-wire Serial EEPROM
The data word address lower eight bits are internally incremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location. When
the word address, internally generated, reaches the page boundary, the following byte is placed
at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data
word address will "roll over" and previous data will be overwritten.
Write Identification Page:
The Identification Page (256 bytes) is an additional page which can be written and (later) permanently
locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction
uses the same protocol and format as Page Write (into memory array), except for the following
differences:
Device type identifier = 1011b
MSB address bits B16/B8 are don't care except for address bit B10 which must be "0".
LSB address bits B7/B0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification Page
instruction are not acknowledged (NoAck).
Acknowledge Polling:
Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge
polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will
the EEPROM respond with a "0", allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to "1". There are three read operations: current address read,
random address read and sequential read.
Current Address Read:
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address "roll over" during read is from the last byte of the last memory page to the first
byte of the first page. The address "roll over" during write is from the last byte of the current page to the
first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in
and acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input "0" but does generate a following stop condition (see
Figure 7).
VER 1.3
8
ACE24LA1024A
Two-wire Serial EEPROM
Figure 7. Current Address Read
Random Read:
A random read requires a "dummy" byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address
read by sending a device address with the read/write select bit high. The EEPROM acknowledges the
device address and serially clocks out the data word. The microcontroller does not respond with a "0" but
does generate a following stop condition (see Figure 8)
Figure 8. Random Read
Sequential Read:
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives
an acknowledge, it will continue to increment the data word address and serially clock out sequential data
words. When the memory address limit is reached, the data word address will "roll over" and the
sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a "0" but does generate a following stop condition (see Figure9).
Figure 9. Sequential Read
VER 1.3
9
ACE24LA1024A
Two-wire Serial EEPROM
Read identification page: The Identification Page (256 bytes) is an additional page which can be written
and (later) permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This instruction
uses the same protocol and format as the Random Address Read (from memory array) with device type
identifier defined as 1011b. The MSB address bits B16/B8 are don't care, the LSB address bits B7/B0
define the byte address inside the Identification Page. The number of bytes to read in the ID page must
not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number
of bytes should be less than or equal to 246, as the ID page boundary is 256 bytes)
Lock Identification Page: The Lock Identification Page instruction (Lock ID) permanently locks the
Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array)
with the following specific conditions:
Device type identifier = 1011b
Address bit B10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
DC Characteristics
Applicable over recommended operating range from: TA = -40℃ to 85℃, VCC = 2V to 5.5V, (unless otherwise noted).
Parameter
Symbol
VCC1
ICC1
Min
Typ
Max
5.5
Units
V
Condition
Supply Voltage
2.0
Supply Current VCC=5.0V
Supply Current VCC=5.0V
Supply Current VCC=5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
0.26
0.28
0.03
0.10
0.05
0.5
mA
mA
μA
μA
μA
V
READ at 400KHZ
WRITE at 400KHZ
VIN=VCC or VSS
VIN=VCC or VSS
VOUT=VCC or VSS
VCC=1.7V to 5.5V
VCC=1.7V to 5.5V
IOL=2.1mA
ICC2
0.5
ISB1
0.5
IL1
1.0
ILO
1.0
VIL1
-0.3
VCC×0.3
VCC+0.3
0.2
Input HighLevel
VIH1
VOL1
VOL2
VCC×0.7
V
Output Low Level VCC=1.7V
Output Low Level VCC=5.0V
V
0.4
V
IOL=3.0mA
Pin Capacitance
Applicable over recommended operating range from: TA = 25℃, f = 400kHz, VCC = 2.7V.
Parameter
Symbol
I/O
CIN
Max
8
Units
Condition
VI/O = 0V
VIN = 0V
Input/Output Capacitance(SDA)
Input Capacitance(A1,A2,SCL)
C
pF
pF
6
VER 1.3
10
ACE24LA1024A
Two-wire Serial EEPROM
AC Characteristics
Applicable over recommended operating range from TA = -40℃ to 85℃, VCC = 2.0V to 5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
2.0V≦VCC<2.5V
2.5V≦VCC<5.5V
Parameter
Symbol
Units
Min
Typ
Max
Min
Typ
Max
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can Start
Start Hold Time
fSCL
TLOW
THIGH
TI
400
1000
KHZ
μs
1.3
0.6
0.5
0.26
μs
50
50
ns
TAA
0.9
0.45
μs
TBUF
1.3
0.5
μs
THD.STA
TSU.STA
THD.DAT
TSU.DAT
TR
0.6
0.6
0
0.25
0.25
0
μs
μs
Start Setup Time
Data In Hold Time
μs
Data In Setup Time
100
100
ns
Inputs Rise Time (1)
Inputs Fall Time (1)
0.3
0.3
0.12
0.12
μs
TF
μs
Stop Setup Time
TSU.STO
TDH
0.6
50
0.25
50
μs
Data Out Hold Time
Write Cycle Time
ns
TWR
3.5
5
3.5
5
ms
Write
Cycle
5.0V, 25℃, Page Mode(1)
Endurance
4M
4M
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions: RL (connects to VCC): 1.3 k
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: 50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading on the user's system.
VER 1.3
11
ACE24LA1024A
Two-wire Serial EEPROM
Figure 10. SCL: Serial Clock, SDA: Serial Data I/O
Figure 11. SCL: Serial Clock, SDA: Serial Data I/O
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
VER 1.3
12
ACE24LA1024A
Two-wire Serial EEPROM
Packaging information
DIP-8
SYMBOL
MIN
NOM
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
NOTE
2
A
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
D1
E
0.310
0.250
0.325
0.280
E1
e
0.100BSC
0.300BSC
0.130
eA
L
4
2
0.115
0.150
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional
information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed
0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010
(0.25 mm).
VER 1.3
13
ACE24LA1024A
Two-wire Serial EEPROM
Packaging information
SOP-8
SYMBOL
MIN
1.35
0.10
0.31
0.17
4.80
3.81
5.79
NOM
MAX
1.75
0.25
0.51
0.25
5.00
3.99
6.20
A
A1
b
C
D
E1
E
1.27BSC
e
L
0.40
0"
1.27
8"
Φ
Notes:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper
dimensions, tolerances, datums, etc.
VER 1.3
14
ACE24LA1024A
Two-wire Serial EEPROM
Packaging information
TSSOP-8
SYMBOL
MIN
NOM
3.00
MAX
3.10
NOTE
2,5
D
E
2.90
6.40BSC
4.40
E1
A
4.30
4.50
1.20
1.05
0.30
3,5
4
A2
b
0.80
0.19
1.00
e
0.65BC
0.60
L
0.45
0.75
L1
1.00REF
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximummaterial condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
VER 1.3
15
ACE24LA1024A
Two-wire Serial EEPROM
Packaging information
USON3*2-8
COMMON DIMENSION(MM)
PKG
REF
A
UT:ULTRA THIN
NOM
MIN
>0.50
0.00
MAX
0.60
0.05
0.55
A1
A3
D
0.15REF
2.00
1.95
2.95
0.20
0.20
1.25
1.15
2.05
3.05
0.30
0.40
1.50
1.40
E
3.00
b
0.25
L
0.30
D2
E2
e
1.40
1.30
0.50BSC
VER 1.3
16
ACE24LA1024A
Two-wire Serial EEPROM
Packaging information
CSP-8
SYMBOL
MIN
NOM
0.465
MAX
0.505
0.210
0.295
1.984
1.520
A
A1
A2
D
0.425
0.170
0.255
1.944
1.480
0.190
0.275
1.964
E
1.500
e
1.000BSC
0.866BSC
0.500BSC
0.500BSC
0.270BSC
0.549
e1
e2
e3
b
F
0.529
0.230
0.569
0.270
G
0.250
VER 1.3
17
ACE24LA1024A
Two-wire Serial EEPROM
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.3
18
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