ACE25AA640GUB8TH [ACE]
Serial NOR Flash Memory 3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase;型号: | ACE25AA640GUB8TH |
厂家: | ACE TECHNOLOGY CO., LTD. |
描述: | Serial NOR Flash Memory 3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase |
文件: | 总65页 (文件大小:2782K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Description
The ACE25AA640G (64M-bit) Serial Peripheral Interface (SPI). and supports the Dual/Quad SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output data is transferred wit speed
of 432 Mbits/s.
Features
64M-bit Serial Flash
8192K-byte
256 bytes per programmable page
Support SFDP & Unique ID
Standard, Dual, Quad SPI
Standard SPI: SCLK, CS#, SI, SO, SO, WP#, HOLD#
Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
QPI: SCLK, CS#, IO0, IO1, IO2, IO3
Flexible Architecture
Sector of 4K-byte
Block of 32/64k-byte
Advanced security Features
4*256-Byte Security Registers With OTP Lock
Software/Hardware Write Protection
Write protect all/portion of memory via software
Enable/Disable protection with WP# Pin
Top or Bottom, Sector or Block selection
Package Options
See 1.1 Available Ordering OPN
All Pb-free packages are compliant RoHS, Halogen-Free and REACH.
Temperature Range & Moisture Sensitivity Level
Industrial Level Temperature (-40~+85°C), MSL3
Industrial Plus Level Temperature (-40°C to +105°C), MSL1
Low Power Consumption
20mA maximum active current
0.2uA maximum standby current
VER 1.1
1
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Single Power Supply Voltage: Full voltage range:2.7~3.6V
Minimum 100,000 Program/Erase Cycle
High Speed Clock Frequency
108MHz for fast read with 30PF load
Dual I/O Data transfer up to 216Mbits/s
Quad I/O Data transfer up to 432Mbits/s
QPI Mode Data transfer up to 384Mbits/s
Continuous Read With 8/16/32/64-byte Wrap
Program/Erase Speed
Page Program time: 250uS typical
Sector Erase time: 60ms typical
Block Erase time: 0.15/0.25s typical
Chip Erase time: 20s typical
Absolute Maximum Ratings
Parameter
Value
-40 to 85
-65 to 150
200
Unit
℃
Ambient Operating Temperature
Storage Temperature
Output Short Circuit Current
Applied Input/Output Voltage
VCC
℃
mA
V
-0.5 to 4.0
-0.5 to 4.0
V
VER 1.1
2
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging Type
SOP-8/SOP-8L
USON4*3-8/ USON4*4-8(0.55~0.80)
WSON-8
Pin Configurations
I/O
Pin Name
CS#
Functions
Chip Select Input
I
SO(IO1)
WP#(IO2)
VSS
I/O
I/O
Data Output(Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI(IO0)
SCLK
I/O
I
Data Input(Data Input Output 0)
Serial Clock Input
HOLD#(IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Ordering information
ACE25AA640G XX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
UB8: USON4*3-8
UD8A: USON4*4-8(0.55~0.80)
MM: WSON-8
VER 1.1
3
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Block Diagram
Uniform Block Sector Architecture
ACE25AA640G 64K Bytes Block SectorArchitecture
Block
Sector
2047
……
Address Range
7FF000H
……
7FFFFFH
……
127
2032
2031
……
2016
……
……
……
……
……
……
47
7F0000H
7EF000H
……
7F0FFFH
7EFFFFH
……
126
……
……
2
7E0000H
7E0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
02F000H
02FFFFH
……
……
……
32
31
……
16
15
……
0
020000H
01F000H
……
010000H
00F000H
……
020FFFH
01FFFFH
……
010FFFH
00FFFFH
……
1
0
000000H
000FFFH
VER 1.1
4
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Device Operation
The ACE25AA640G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK. Note: “WP#” & “HOLD#” pin require external pull-up.
Dual SPI
The ACE25AA640G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O
Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the
device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins
become bidirectional I/O pins: IO0 and IO1. Note: “WP#” & “HOLD#” pin require external pull-up.
Quad SPI
The ACE25AA640G supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be
transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI
command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins
become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status
Register to be set .
QPI
The ACE25AA640G supports Quad Peripheral Interface (QPI) operations only when the device is
switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command.
The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and
QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and
“Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and
after software reset using “”Reset (99H)” command, the default state of the device is Standard/Dual/Quad
SPI mode. The QPI mode requires the non- volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress .
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
VER 1.1
5
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip,
the HOLD# must be at high and then CS# must be at low.
Data Protection
The ACE25AA640G provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
The Block Protect (BP4, BP3, BP2, BP1,BP0) bits define the section of the memory array that can be
read but not change
Hardware Protection Mode:
WP# going low to protected the BP0~BP4 bits and SRP bit
Deep Power-Down Mode:
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the
Release from Deep Power-Down Mode command
VER 1.1
6
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table 1.ACE25AA640G Protected Area Sizes (CMP=0)
Status bit
Memory Content
BP4
X
0
BP3 BP2 BP1 BP0
Blocks
Addresses
None
Density
None
128KB
256KB
512KB
1MB
Portion
None
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
None
126 to 127 7E0000H – 7FFFFFH
124 to 127 7C0000H – 7FFFFFH
120 to 127 780000H – 7FFFFFH
112 to 127 700000H – 7FFFFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
0
0
0
0
96 to 127
64 to 127
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
127
600000H – 7FFFFFH
400000H – 7FFFFFH
000000H – 01FFFFH
000000H – 03FFFFH
000000H – 07FFFFH
000000H – 0FFFFFH
000000H – 1FFFFFH
000000H – 3FFFFFH
000000H – 7FFFFFH
7FF000H – 7FFFFFH
7FE000H – 7FFFFFH
7FC000H – 7FFFFFH
7F8000H – 7FFFFFH
7F8000H – 7FFFFFH
000000H – 000FFFH
000000H – 001FFFH
000000H – 003FFFH
000000H – 007FFFH
000000H – 007FFFH
2MB
0
4MB
0
128KB
256KB
512KB
1MB
0
0
0
0
2MB
0
4MB
X
1
8MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
1
127
8KB
1
127
16KB
32KB
32KB
4KB
1
127
1
127
1
0
1
0
8KB
1
0
16KB
32KB
32KB
1
0
1
0
VER 1.1
7
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table 1.1ACE25AA640G Protected Area Sizes (CMP=1)
Status bit
Memory Content
BP4
X
0
BP3 BP2 BP1 BP0
Blocks
Addresses
000000H – 7FFFFFH
Density
ALL
Portion
ALL
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
ALL
0 to 125 000000H – 7DFFFFH
0 to 123 000000H – 7BFFFFH
8064KB
7936KB
7680KB
7MB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Upper 1/2
Upper 63/64
Upper 31/32
Upper15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
0
0
0 to 119
0 to 111
0 to 95
0 to 63
000000H – 77FFFFH
000000H – 6FFFFFH
000000H – 5FFFFFH
000000H – 4FFFFFH
0
0
6MB
0
4MB
0
2 to 127 020000H – 7FFFFFH
4 to 127 040000H – 7FFFFFH
8 to 127 080000H – 7FFFFFH
16 to 127 100000H – 7FFFFFH
32 to 127 200000H – 7FFFFFH
64 to 127 400000H – 7FFFFFH
8064KB
7936KB
7680KB
7MB
0
0
0
0
6MB
0
4MB
X
1
NONE
NONE
NONE
8188KB
8184KB
8176KB
8160KB
8160KB
8188KB
8184KB
8176KB
8160KB
8160KB
0 to 127 000000H – 7FEFFFH
0 to 127 000000H – 7FDFFFH
0 to 127 000000H – 7FBFFFH
L-2047/2048
L-1023/1024
L-511/512
L-255/256
L-255/256
U-2047/2048
U-1023/1024
U-511/512
U-255/256
U-255/256
1
1
1
0 to 127
0 to 127
000000H – 7F7FFFH
000000H – 7F7FFFH
1
1
0 to 127 001000H – 7FFFFFH
0 to 127 002000H – 7FFFFFH
0 to 127 004000H – 7FFFFFH
0 to 127 008000H – 7FFFFFH
0 to 127 008000H – 7FFFFFH
1
1
1
1
VER 1.1
8
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Status Register
S15
S14
S13
S12
S11
S10
LB
S9
S8
SUS
CMP
Reserved
Reserved
Reserved
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register
progress, When WIP bit sets 0, means the device is not in program/ erase/ write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1
the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase command is accepted.
BP4, BP3,BP2, BP1,BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status
Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined in Table1) becomes protected against Page Program (PP), Sector
Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is
executed if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, BP0)
bits are 1 and CMP=1.
SRP1,SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bit is a non-volatile Read/Write bit in the status register.
The SRP bit controls the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable protection.
VER 1.1
9
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
SRP1 SRP0 WP#
Status Register
Description
The Status Register can be written to after a Write
Enable command, WEL=1.(Default)
0
0
0
1
0
1
1
0
1
X
0
Software Protected
Hardware Protected
Hardware Unprotected
WP#=0, the Status Register locked and cannot be
written until the next power-up.
WP#=1, the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to
again until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot
be written to.
1
Power Supply Lock-
Down(1)(2)
X
X
1
One-Time Program(2)
Notes:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE bit
is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard
SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write
protect control and status to the Security Registers. The default state of LB is 0, the security registers are
unlocked. LB can be set to 1 using the Write Register instruction. LB is One Time Programmable, once it’s
set to 1, the Security Registers will become read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the
BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory
Protection table for details. The default setting is CMP=0.
VER 1.1
10
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Commands Description
All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code
must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges
of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the
command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be
driven high after the last bit of the command sequence has been shifted in. For the command of Read,
Fast Read, Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a
data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an
exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will
happen and WEL will not be reset.
Table2. Commands
Command Name Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
n-Bytes
Write Enable
06H
50H
Write Enable for
Volatile Status
Register
Write Disable
04H
05H
Read Status
Register
(S7-S0)
(S15-S8)
(S7-S0)
(continuous)
(continuous)
(continuous)
Read Status
Register-1
Write Status
Register
35H
01H
(S15-S8)
Read Data
Fast Read
03H
0BH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0) (Next byte) (continuous)
dummy
dummy
(D7-D0) (continuous)
(D7-D0)(1) (continuous)
Dual Output Fast
Read
3BH
A23-A16
A15-A8
A7-A0
VER 1.1
11
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
A7-A0
Dual I/O Fast Read BBH
A23-A8(2)
A23-A16
(D7-D0)(1)
A7-A0
(continuous)
(D7-D0)(3) (continuous)
(continuous)
M7-M0(2)
Quad Output Fast
6BH
A15-A8
dummy
Read
A23-A0
M7-M0(4)
A23-A0
Quad I/O Fast Read EBH
Dummy(5) (D7-D0)(3)
Dummy(6) (D7-D0)(3)
Quad I/O Word Fast
E7H
(continuous)
Read
M7-M0(4)
Continuous Read
FFH
Reset
Page Program
02H
32H
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0) (Next byte)
(D7-D0)(3)
Quad Page
Program
Sector Erase
20H
52H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Block Erase(32KB)
Block Erase(64KB) D8H
Chip Erase
Enable QPI
C7/60H
38H
Set Burst with Wrap 77H
Deep Power-Down B9H
dummy
dummy
dummy
dummy
dummy
dummy
W6-W4
(DID7-DID0
)
Release From Deep ABH
(continuous)
Release From Deep
ABH
Power-Down
Manufacturer/Devic
(MID7- (DID7-DID0
90H
e ID
dummy
A23-A8
dummy
00H
(continuous)
(continuous)
MID0)
)
Manufacturer/Devic
92H
A7-A0,
M[7:0]
(M7-M0 )
(ID7-ID0)
(M7-M0 )
(ID7-ID0)
e ID by Dual I/O
Manufacturer/Devic
94H
A23-A0,
M[7:0]
dummy
e ID by Quad I/O
VER 1.1
12
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Serial Flash
Discoverable
Parameters
5AH
A23-A16
00H
A15-A8
01H
A7-A0
94H
dummy
dummy
(D7-D0) (continuous)
Read Unique ID
5AH
9FH
(D7-D0) (continuous)
(continuous)
(MID7-
MID0)
(JDID15-
JDID8)
(JDID7-
JDID0)
Read Identification
Erase Security
Register(8)
44H
42H
48H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Program Security
Register(8)
(D7-D0) (Next byte)
dummy (D7-D0)
Read Security
Register(8)
Enable Reset
Reset
66H
99H
VER 1.1
13
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table2a. Commands (QPI)
Command Name
Clock Number
Byte1
(0,1)
06H
Byte2
Byte3
Byte4
Byte5
Byte6
(6,7)
(10,11)
(2,3)
(4,5)
(8,9)
Write Enable
Write Enable for Volatile
Status Register
50H
Write Disable
04H
05H
Read Status Register
Read Status Register-1
Write Status Register
Page Program
(S7-S0)
35H
(S15-S8)
01H
(S7-S0) (S15-S8)
02H
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
(Next byte)
Sector Erase
20H
Block Erase(32KB)
Block Erase(64KB)
Chip Erase
52H
D8H
C7/60H
B9H
C0H
0BH
0CH
Deep Power-Down
Set Read Parameters
Fast Read
P7-P0
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
dummy
dummy
(D7-D0)
(D7-D0)
Burst Read with Wrap
dummy(5 (D7-D0)(3
Quad I/O Fast Read
EBH
A23-A0
)
)
Release from Deep Power-
Down, And Read Device
ID(10)
ABH
90H
dummy
dummy dummy * N (ID7-ID0)
MID7~MID
dummyx
2
Manufacturer/Device ID(11)
00H
dummy * N
(ID7-ID0)
0
Disable QPI
FFH
66H
99H
Enable Reset
Reset
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
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2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8,A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9,A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Quad I/O Fast Read Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Quad I/O Word Fast Read Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Quad I/O Word Fast Read Data: the lowest address bit must be 0
8. Security Registers Address :
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
9. QPI Command, Address, Data input/output format:
CLK# 0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
10. QPI mode: Release from Deep Power-Down, And Read Device ID (ABH)
N dummy cycles should be inserted before ID read cycle, refer to C0H command
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11. QPI mode: Manufacturer/Device ID (90H)
N dummy cycles should be inserted before ID read cycle, refer to C0H command
ID Definitions
Operation Code
M7-M0
0B
ID15-ID8
40
ID7-ID0
17
9FH
90H
ABH
0B
16
16
Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command
sequence: CS# goes low→sending the Write Enable command→CS# goes high.
Figure1. Write Enable Sequence Diagram
Figure1a. Write Enable Sequence Diagram (QPI)
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Write Enable for Volatile Status Register (50H )
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write
Enable for Volatile Status Register command must be issued prior to a Write Status Register command
and any other commands can't be inserted between them. Otherwise, Write Enable for Volatile Status
Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write
Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure2. Write Enable for Volatile Status Register Sequence Diagram
Figure2a. Write Enable for Volatile Status Register Sequence Diagram (QPI)
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Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable
command sequence: CS# goes low→sending Write Disable command→CS# goes high. The WEL bit is
reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,
Sector Erase, Block Erase and Chip Erase commands.
Figure3. Write Disable Sequence Diagram
Figure3a. Write Disable Sequence Diagram (QPI)
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Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may
be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one
of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously. For command
code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output
Status Register bits S15~S8.
Figure4. Read Status Register Sequence Diagram
Figure4a. Read Status Register Sequence Diagram (QPI)
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Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After
the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S13, S12, S11, S1 and S0 of the
Status Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not,
the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the
data byte, the CMP and QE bit will be cleared to 0. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register can still be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is
completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect
(BP4, BP3,BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the
Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode
is entered.
Figure5. Write Status Register Sequence Diagram
Figure5a. Write Status Register Sequence Diagram (QPI)
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Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address
after each byte of data is shifted out. Therefore, the whole memory can be read with a single Read Data
Bytes (READ) command. During an Erase, Program or Write cycle, Read Data Byte (READ) command
will be rejected without affecting the cycle in progress.
Figure6. Read Data Bytes Sequence Diagram
Read Data Bytes At Higher Speed (Fast Read)(0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed
by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency f , during the falling edge of SCLK. The first byte address can be at any location. The address
C
is automatically incremented to the next higher address after each byte of data is shifted out.
Figure7. Read Data Bytes at Higher Speed Sequence Diagram
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Fast Read (0BH) in QPI Mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is
configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on
the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8.
When the dummy cycle is configured to 4, addr [0] input must be 0.
Figure7a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)
Dual Output Fast Read (3BH )
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per
clock cycle from SI and SO. The command sequence is shown in Figure 8. The first byte addressed can
be at any location. The address is automatically incremented to the next address after each byte of data is
shifted out.
Figure8. Dual Output Fast Read Sequence Diagram
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Quad Output Fast Read (6BH )
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per
clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is automatically incremented to the next address after
each byte of data is shifted out.
Figure9. Quad Output Fast Read Sequence Diagram
Dual I/O Fast Read(BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the
capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI
and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted
out 2-bit per clock cycle from SI and SO. The command sequence is shown in Figure 10. The first byte
addressed can be at any location. The address is automatically incremented to the next address after
each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7- 0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then
lowered) does not require the BBH command code. The command sequence is shown in figure 10a. If the
“Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be
used to reset (M5- 4) before issuing normal command.
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Figure10. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure10a. Dual I/O Fast Read Sequence Diagram (M5-4=(1, 0))
Quad I/O Fast Read(EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bits per
clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory
contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in
Figure 11. The first byte addressed can be at any location. The address is automatically incremented to
the next address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9)
must be set to enable for the Quad I/O Fast read command.
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Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then
lowered) does not re- quire the EBH command code. The command sequence is shown in Figure 11a. If
the “Continuous Read Mode” (M5- 4) do not equal (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be
used to reset (M5- 4) before issuing normal command.
Figure11.Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure11a.Quad I/O Fast Read Sequence Diagram (M5-4=(1, 0))
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Quad I/O Fast Read with ““8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either
enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page.
The output data starts at the initial address specified in the command, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is
used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the
wrap around section within a page.
Quad I/O Fast Read (EBH) in QPI mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure11b. In QPI mode, the
number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a
wide range application with different needs for either maximum Fast Read frequency or minimum data
access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as
either 4/6/8. When the dummy cycle is configured to 4, addr[0] input must be 0. In QPI mode, the
“Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode”
feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not
available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data
length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used.
Figure11b.Quad I/O Fast Read Sequence Diagram (M5-4=(1, 0))
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Quad I/O Word Fast Read(E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the
lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in
followed Figure 12. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of
Status Register (S9) must be set to enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and
then lowered) does not require the E7H command code. The command sequence is shown in followed
Figure 12a. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires
the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M7-0) before issuing normal command.
Figure12.Quad I/O Word Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure12a.Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
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Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by
issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command
can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a
256-byte page. The output data starts at the initial address specified in the command, once it reaches the
ending boundary of the 8/16/32/64- byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows
applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a
fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap
Around” operation while W6-W5 is used to specify the length of the wrap around section within a page.
Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in
standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low →Send Set Burst with
Wrap command →Send 24 dummy bits →Send 8 bits “Wrap bits” →CS# goes high
W4=0
W4=1(default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
N/A
0,0
0,1
1,0
1,1
Yes
Yes
Yes
Yes
No
No
No
No
16-byte
N/A
32-byte
N/A
64-byte
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read”
and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte
section within any page. To exit the “Wrap Around” function and return to normal read operation, another
Set Burst with Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap
(0CH)” command should be used to perform the Read Operation with “Wrap Around” feature. The Wrap
Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by
“Set Read Parameters (C0H) command.
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Figure13.Set Burst With Wrap Sequence Diagram
Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the current page are programmed from the start
address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must
be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes
low →sending Page Program command →3-byte address on SI →at least 1 byte data on SI →CS# goes
high. The command sequence is shown in Figure14. If more than 256 bytes are sent to the device,
previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed
correctly within the same page. If less than 256 data bytes are sent to device, they are correctly
programmed at the requested addresses without having any effects on the other bytes of the same page.
CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page
Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated.
While the Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. As some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) is not executed.
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Figure14. Page Program Sequence Diagram
Figure14a. Page Program Sequence Diagram (QPI)
Quad Page Program (QPP) (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and
IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write
Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit
before sending the Page Program command. The Quad Page Program command is entered by driving
CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO
pins.
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The command sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested ad- dresses without having any effects on the other bytes of the same page. CS# must be
driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page
Program command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is
initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) will not be executed.
Figure15. Quad Page Program Sequence Diagram
Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase
(SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI.
Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven
low for the entire duration of the sequence.
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The Sector Erase command sequence: CS# goes low→sending Sector Erase command→3-byte address
on SI→CS# goes high. The command sequence is shown in Figure16. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not
executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset. A Sector Erase( (SE) command applied to a sector which is protected by
the Block Protect(BP4, BP3,BP2, BP1, and BP0) bit (see Table1 &1.1) will not be executed. Note: Power
disruption during erase operation will cause incomplete erase, thus recommend to perform a re-erase
once power resume.
Figure16. Sector Erase Sequence Diagram
Figure16a. Sector Erase Sequence Diagram (QPI)
32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The
32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and
three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE)
command. CS# must be driven low for the entire duration of the sequence.
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32
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
The 32KB Block Erase command sequence: CS# goes low→sending 32KB Block Erase command→
3-byte address on SI→CS# goes high. The command sequence is shown in Figure17. CS# must be
driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block
Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a
block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1 & 1.1) will not
be executed. Note: Power disruption during erase operation will cause incomplete erase, thus
recommend to perform a re-erase once power resume.
Figure17. 32KB Block Erase Sequence Diagram
Figure17a. 32KB Block Erase Sequence Diagram (QPI)
64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The
64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and
three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE)
command. CS# must be driven low for the entire duration of the sequence.
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
The 64KB Block Erase command sequence: CS# goes low→sending 64KB Block Erase command→
3-byte address on SI→CS# goes high. The command sequence is shown in Figure18. CS# must be
driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block
Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Block Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset t. A
64KB Block Erase (BE) commands applied to a block which is protected by the Block Protect (BP4,
BP3,BP2, BP1, BP0) bits (see Table1 & 1.1) will not be executed. Note: Power disruption during erase
operation will cause incomplete erase, thus recommend to perform a re-erase once power resume.
Figure18. 64KB Block Erase Sequence Diagram
Figure18a. 64KB Block Erase Sequence Diagram (QPI)
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)
command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS#
must be driven Low for the entire duration of the sequence.
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
The Chip Erase command sequence: CS# goes low→sending Chip Erase command→CS# goes high.
The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the
command code has been latch in, otherwise the Chip Erase command is not executed. As soon as CS# is
driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle
is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip
Erase (CE) command is executed if the Block protected by (BP2, BP1, BP0) bits. The Chip Erase(CE)
command is ignored if one or more sectors are protected. Note: Power disruption during erase operation
will cause incomplete erase, thus recommend to perform a re-erase once power resume.
Figure19. Chip Erase Sequence Diagram
Figure19a. Chip Erase Sequence Diagram (QPI)
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest
consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program
and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if
there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The
Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once
the device has entered the Deep Power- Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the
device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low→sending Deep Power-Down command→
CS# goes high. The command sequence is shown in Figure 20. CS# must be driven high after the eighth
bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not
executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to
ICC2 and the Deep Power- Down Mode is entered. Any Deep Power-Down (DP) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure20. Deep Power-Down Sequence Diagram
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Figure20a. Release Power-Down Sequence Diagram (QPI)
Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read/Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or obtain the devices electronic identification (ID)
number. To release the device from the Power-Down state, the command is issued by driving the CS# pin
low, shifting the instruction code “ABH” and driving CS# high as shown in Figure21. Release from
Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other command are accepted. The CS# pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in
Figure21b. The Device ID value for the ACE25AA640G is listed in Manufacturer and Device Identification
table. The Device ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is
the same as previously described, and shown in Figure 21b, except that after CS# is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other command will be accepted. If the Release from Power-Down/Device
ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the
command is ignored and will not have any effect on the current cycle.
VER 1.1
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Figure21. Deep Power-Down Sequence Diagram
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Figure21a. Release Power-Down Sequence Diagram (QPI)
Figure21b. Release Power-Down /Read Device ID Sequence Diagram
Figure21c. Release Power-Down /Read Device ID Sequence Diagram (QPI)
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device
ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The
command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first is shown in Figure 22. If the 24-bit address is
initially set to 000001H, the Device ID will be read first. In QPI mode the dummy cycles can be configured
by C0H command. When the dummy cycle is configured to 4, addr [0] input must be 0.
Figure22. Read Manufacture ID/ Device ID Sequence Diagram
Figure22a. Read Manufacture ID/ Device ID Sequence Diagram (QPI)
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down /
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID
by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out
on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 23 If the 24-bit address
is initially set to 000001H, the Device ID will be read first.
Figure23. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down
/ Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID
by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H”
followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID
are shifted out on the falling edge of SCLK with most significant bit (MSB) first is shown in Figure 24. If the
24-bit address is initially set to 000001H, the Device ID will be read first.
Figure24. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed
by two bytes of device identification. The device identification indicates the memory type in the first byte,
and the memory capacity of the device in the second byte. Any Read Identification (RDID) command
while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress. The Read identification (RDID) command should not be issued while the device is in Deep
Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is
shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on
Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command
sequence is shown in Figure25. The Read Identification (RDID) command is terminated by driving CS# to
high at any time during data output. When CS# is driven high, the device is put in the Standby Mode.
Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute
commands.
Figure25. Read Identification ID Sequence Diagram
Erase Security Registers (44H)
The ACE25AA640G provides four 256-byte Security Registers which only erased all at once but able to
program individually. These registers may be used by the system manufacturers to store security and
other important information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low→sending Erase Security Registers
Command→CS# goes high. The command sequence is shown in Figure 26. CS# must be driven high
after the eighth bit of the command code has been latched in, otherwise the Erase Security Registers
command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle
(whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit.
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it
is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The
Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers.
Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security
Registers command will be ignored.
A23-A16
A15-A10
000000
Address
A9-A0
00000000
Security Registers
Don’Care
Figure26. Erase Security Registers command Sequence Diagram
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to
256 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security
Registers command. The Program Security Registers command is entered by driving CS# Low, followed
by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is
driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the
Program Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
VER 1.1
42
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
A15-A8
00H
Address
A23-A16
00H
A7-A0
Security Registers 0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
Byte Address
00H
01H
00H
02H
00H
03H
Figure27. Program Security Registers command Sequence Diagram
Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3- byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The
address is automatically incremented to the next address after each byte of data is shifted out. Once the
A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is
completed by driving CS# high.
Address
A23-A16
A15-A10
000000
A9-A0
Security Register
00000000
Address
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Figure28. Read Security Registers Command Sequence Diagram
Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy
clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command,
and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command.
The “Wrap Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will
remain unchanged when the device is switched from Standard SPI mode to QPI mode
P5-P4
0 0
Dummy Clocks
Maximum Read Freq.
80MHz
P1-P0
0 0
Wrap Length
8-byte
4
4
6
8
0 1
80MHz
0 1
16-byte
1 0
96MHz
1 0
32-byte
1 1
108MHz
1 1
64-byte
Figure29. Set Read Parameters Command Sequence Diagram
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI
mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the
“Wrap Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy
clocks can be configured by the “Set Read Parameters (C0H)” command. When the dummy cycle is
configured to 4, addr[0] input must be 0.
Figure30. Burst Read with Wrap Command Sequence Diagram
Enable QPI (38H)
The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can
switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands.
In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1
first, and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)”
command will be ignored and the device will remain in SPI mode. When the device is switched from SPI
mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap
Length setting will remain unchanged.
Figure31. Enable QPI Mode Command Sequence Diagram
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Continuous Read Mode Reset (CRMR) (FFH)/ Disable QPI (FFH)/ Continuous Read Mode
Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to
further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read
operations do not require the BBH/EBH/E7H command code.
Because the ACE25AA640G has no hardware reset pin, so if Continuous Read Mode bits are set to
“AXH”, the ACE25AA640G will not recognize any standard SPI commands. So Continuous Read Mode
Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI
command to be recognized. The command sequence is show in Figure32.
Figure32. Continuous Read Mode Reset Sequence Diagram
Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command
must be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable
Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. When the
device is in QPI mode, the first FFH command will exit continuous read mode and the second FFH
command will exit QPI mode.
Figure32a. Disable QPI Mode Command Sequence Diagram
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status
Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting
(P7-P0),Continuous Read Mode bit setting (M7-M0)and Wrap Bit Setting(W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low→Sending Enable Reset command→
CS# goes high→CS# goes low→Sending Reset command→CS# goes high. Once the Reset command is
accepted by the device, the device will take approximately tRST_R to reset. During this period, no
command will be accepted. Data corruption may happy if there is an on-going or suspended internal
Erase or Program operation when Reset command sequence is accepted by the device. It is
recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset
command sequence.
Figure33. Enable Reset and Reset command Sequence Diagram
Figure33a. Enable Reset and Reset command Sequence Diagram (QPI)
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing
the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables.
These parameter tables can be interrogated by host system software to enable adjustments needed to
accommodate divergent features from multiple vendors. The concept is similar to the one found in the
Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216.
Figure34. Read Serial Flash Discoverable Parameter Command Sequence Diagram
Figure34a. Read Serial Flash Discoverable Parameter Command Sequence Diagram (QPI)
VER 1.1
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Read Unique ID (RUID)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
ACE25AA640G device. The Unique ID can be used in conjunction with user software methods to help
prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low→ sending Read Unique ID command→00H→
01H→94H→Dummy byte→128bit Unique ID Out→ CS# goes high.
The command sequence is show below.
Figure35. Read Unique ID (RUID) Sequence (Command 5 AH)
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table 3. Signature and Parameter Identification Data Values
Add(H) DW Add
Data
Data
Description
Comment
(Byte)
00H
01H
02H
03H
04H
05H
06H
(Bit)
07:00
15:08
23:16
31:24
07:00
15:08
23:16
53H
46H
44H
50H
00H
01H
01H
53H
46H
44H
50H
00H
01H
01H
SFDP Signature
Fixed:50444653H
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameters Headers
Start from 00H
Start from 01H
Start from 00H
Contains 0xFFH and
can never be changed
Unused
07H
08H
09H
0AH
0BH
31:24
07:00
15:08
23:16
31:24
FFH
00H
00H
01H
09H
FFH
00H
00H
01H
09H
00H: It indicates a JEDEC
specified header
ID number (JEDEC)
Parameter Table Minor Revision
Number
Start from 0x00H
Start from 0x01H
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
0CH
0DH
0EH
07:00
15:08
23:16
30H
00H
00H
30H
00H
00H
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Contains 0xFFH and can never
be changed
Unused
0FH
10H
11H
31:24
07:00
15:08
FFH
0BH
00H
FFH
0BH
00H
ID Number(Manufacturer ID)
It is indicates manufacturer ID
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
12H
13H
23:16
31:24
01H
03H
01H
03H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14H
15H
16H
07:00
15:08
23:16
60H
00H
00H
60H
00H
00H
First address of Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
Contains 0xFFH and can never
be changed
17H
31:24
FFH
FFH
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table 4. Parameter Table (0): JEDEC Flash Parameter Tables
Add(H) DW Add
Description
Comment
Data
Data
(Byte)
(Bit)
00: Reserved; 01: 4KB erase;
10: Reserved; 11: not support
4KB erase
Block/Sector Erase Size
Write Granularity
01:00
02
01b
1b
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit 1:
Volatile statusbit (BP status
register bit)
Write Enable Instruction Requested
for Writing to Volatile
03
0b
30H
E5H
0: Use 50H Opcode, 1: Use 06H
Opcode, Note: If target flash
status register is Nonvolatile,
then bits 3 and 4must be set to
00b.
Write Enable Opcode Select for
Writing to Volatile Status Registers
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
(1-1-2) Fast Read
31H
32H
33H
15:08
16
20H
1b
20H
F1H
FFH
0=Not support, 1=Support
00: 3Byte only, 01: 3 or
4Byte,10: 4Byte only, 11:
Reserved
Address Bytes Number used in
addressing flash array
18:17
19
00b
0b
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
22
1b
23
1b
Unused
31:24
FFH
Flash Memory Density
37H:34H 31:00
007FFFFFH
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 00100b
states
Clocks) not support
38H
39H
3AH
3BH
44H
(1-4-4) Fast Read Number of Mode
Bits
000b:Mode Bits not support
07:05
15:08
010b
(1-4-4) Fast Read Opcode
EBH
EBH
08H
6BH
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16 01000b
states
Clocks) not support
(1-1-4) Fast Read Number of Mode
Bits
000b:Mode Bits not support
23:21
31:24
000b
6BH
(1-1-4) Fast Read Opcode
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ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Add(H) DW Add
Description
Comment
Data
Data
(Byte)
(Bit)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 01000b
states
Clocks) not support
3CH
3DH
3EH
3FH
40H
08H
3BH
42H
BBH
EEH
(1-1-2) Fast Read Number of Mode
Bits
000b: Mode Bits not support
07:05
15:08
000b
3BH
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of Wait
states
20:16 00010b
(1-2-2) Fast Read Number of Mode
Bits
23:21
010b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBH
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
(4-4-4) Fast Read
Unused
07:05
111b
Unused
43H:41H 31:08 0xFFH 0xFFH
45H:44H 15:00 0xFFH 0xFFH
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16 00000b
states
Clocks) not support
46H
00H
(2-2-2) Fast Read Number of Mode
Bits
000b: Mode Bits not support
23:21
31:24
000b
FFH
(2-2-2) Fast Read Opcode
Unused
47H
FFH
49H:48H 15:00 0xFFH 0xFFH
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16 00000b
states
Clocks) not support
4AH
00H
(4-4-4) Fast Read Number of Mode
Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
000b
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
(4-4-4) Fast Read Opcode
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 4 erase Opcode
VER 1.1
52
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Table 5. Parameter Table (1): Flash Parameter Tables
Add(H) DW Add
(Byte) (Bit)
Description
Comment
Data
Data
2000H=2.000V
2700H=2.700V
3600H=3.600V
Vcc Supply Maximum Voltage
61H:60H 15:00
3600H 3600H
2700H 2700H
1650H=1.650V
2250H=2.250V
2300H=2.300V
2700H=2.700V
Vcc Supply Minimum Voltage
63H:62H 31:16
HW Reset# pin
HW Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
0=not support 1=support
Should be issue Reset
00
01
02
03
0b
0b
1b
0b
Deep Power Down Mode
SW Reset
SW Reset Opcode
Enable(66H) before Reset 65H:64H 11:04
cmd
99H 7994H
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
1b
1b
1b
0b
14
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
66H
67H
23:16
FFH
FFH
64H
08H:support 8B wrap-around
read 16H:8B&16B
Wrap-Around Read data length
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
Individual block lock Opcode
Individual block lock Volatile protect
bit default protect status
Secured OTP
00
01
0b
0b
0=Volatile 1=Nonvolatile
09:02
10
FFH
0b
0=protect 1=unprotect
E3FCH
6BH:68H
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
0b
0b
Read Lock
Permanent Lock
13
1b
Unused
15:14
11b
Unused
31:16 FFFFH FFFFH
VER 1.1
53
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Electrical Characteristics
Power-On Timing
Table6. Power-Up Timing and Write Inhibit Threshold
Symbol
tVSL
Parameter
VCC(min) To CS# Low
Min
10
1
Max
Unit
us
tPUW
Time Delay Before Write Instruction
Write Inhibit Voltage
10
ms
V
VWI
1
2.5
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The
Status Register contains 00H (all Status Register bits are 0).
Data Retention and Endurance
Parameter
Typical
20
Unit
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
100K
Latch up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
VCC Current
Min
-1.0V
Max
VCC+1.0V
100mA
-100mA
VER 1.1
54
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Capacitance Measurement Condition
Symbol
Parameter
Input Capacitance
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
VIN=0V
C
IN
C
OUT
Output Capacitance
8
VOUT=0V
C
L
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Figure36. Input Test Waveform and MeasurementLevel
VER 1.1
55
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
DC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
±2
Unit
μA
I
Input Leakage Current
Output Leakage Current
Standby Current
LI
I
±2
μA
LO
CS#=VCC VIN=VCC or
VSS
I
12
0.1
15
13
5
20
μA
CC1
CS#=VCC VIN=VCC or
VSS
I
Deep Power-Down Current
0.2
μA
CC2
CLK=0.1VCC/0.9VCC at
120MHz ,Q=Open(*1I/O)
CLK=0.1VCC/0.9VCC at
80MHz,Open(*1,*2,4I/O)
CLK=0.1VCC/0.9VCC at
50MHz ,Q=Open(*1I/O)
20
I
Operating Current(Read)
18
mA
CC3
7
I
Operating Current(PP)
Operating Current(WRSR)
Operating Current(SE)
Operating Current(BE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
20
mA
mA
mA
mA
V
CC4
I
20
CC5
I
20
CC6
I
20
CC7
V
IL
-0.5
0.2VCC
VCC+0.4
0.4
V
IH
Input High Voltage
0.7VCC
V
V
Output Low Voltage
Output High Voltage
IOL=1.6mA
IOH=-100uA
V
OL
V
VCC-0.2
V
OH
VER 1.1
56
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
AC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V,CL=30pf)
Symbol
Parameter
Min.
Typ
Max.
Unit
Serial Clock Frequency For: Fast
Read(0BH),Dual Output(3BH),Dual I/O(BBH)
Serial Clock Frequency For: Dual I/O(BBH),
Quad I/O(EBH),Quad Output(6BH)
f
108
MHz
C
f
f
108
96
MHz
MHz
MHz
C1
C2
Serial Clock Frequency For QPl (0BH, EBH)
Serial Clock Frequency For: Read(03H),Read
Device ID(9FH),Read Manufacture ID(90H)
f
80
R
t
CLH
Serial Clock High Time
Serial Clock Low Time
5
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
t
CLL
t
t
CLCH
CHCL
Serial Clock Rise Time(Slew Rate)
Serial Clock Fall Time(Slew Rate)
CS# Active Setup Time
0.2
0.2
5
t
SLCH
t
t
CHSH
SHCH
CS# Active Hold Time
5
CS# Not Active Setup Time
CS# Not Active Hold Time
5
t
CHSL
5
t
SHSL
SHQZ
CLQX
DVCH
CHDX
CS# High Time (read/write)
Output Disable Time
20
t
t
6
Output Hold Time
1
2
2
5
5
5
5
t
t
Data In Setup Time
Data In Hold Time
t
HLCH
Hold# Low Setup Time(relative to Clock)
Hold# High Setup Time(relative to Clock)
Hold# High Hold Time(relative to Clock)
Hold# Low Hold Time(relative to Clock)
Hold# Low To High-Z Output
Hold# Low To Low-Z Output
Clock Low To Output Valid
t
t
t
HHCH
t
CHHL
CHHH
t
HLQZ
6
6
HHQX
t
CLQV
6.5
t
WHSL
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
20
t
SHWL
tDP
100
0.1
VER 1.1
57
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
CS# High To Standby Mode Without Electronic
Signature Read
t
t
RES1
RES2
20
20
us
us
CS# High To Standby Mode With Electronic
Signature Read
CS# High To Next Command After Reset
(from read)
CS# High To Next Command After Reset
(from program)
CS# High To Next Command After Reset
(from erase)
tRST_R
tRST_P
tRST_E
20
20
12
us
us
ms
t
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
50
0.25
50
300
0.7
ms
ms
ms
s
W
t
t
t
PP
SE
BE
CE
300
Block Erase Time(32K Bytes/64K Bytes)
Chip Erase Time
0.15/0.25 0.5/0.75
20 60
t
s
Figure37. Serial Input Timing
Figure38. Output Timing
VER 1.1
58
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Figure39. Hold Timing
Notes:
Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray
etc.), please advise in advance.
VER 1.1
59
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging information
SOP-8
Dimensions In Millimeters
Symbol
Min
Norm
Max
A
A1
A2
b
1.350
0.100
1.300
0.330
0.190
4.700
3.800
1.750
0.250
1.500
0.510
0.250
5.000
4.000
c
D
4.900
3.900
1.270
6.000
0.350
0.635
1.040
E1
e
E
5.800
0.250
0.508
0.837
0°
6.200
0.500
0.762
1.243
8°
h
L
L1
θ
VER 1.1
60
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging information
SOP-8L (208mil)
Dimensions In Millimeters
Symbol
Min
1.75
0.05
0.33
0.30
0.17
0.15
5.13
7.70
5.18
Norm
1.95
0.15
Max
2.16
0.25
0.51
0.48
0.25
0.23
5.33
8.10
5.38
A
A1
b
b1
c
c1
D
5.23
7.90
E
E1
e
5.28
1.27BSC
0.65
L
0.50
0°
0.80
8°
θ
VER 1.1
61
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging information
USON4*3-8
Dimensions In Millimeters
Symbol
Min
0.50
0.00
0.25
Norm
0.55
Max
0.60
0.05
0.35
A
A1
b
0.02
0.30
b1
c
0.20REF
0.15
0.10
3.90
0.70
0.20
4.10
0.90
D
4.00
D2
e
0.80
0.80BSC
0.80BSC
2.40BSC
3.00
e1
Nd
E
2.90
0.10
0.55
3.10
0.30
0.65
E2
L
0.20
0.60
L1
L2
h
0.05REF
0.10REF
0.15
0.10
0.20
VER 1.1
62
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging information
USON4*4-8(0.55~0.80)
Dimensions In Millimeters
Symbol
Min
0.50
0.00
0.25
0.15
0.10
3.90
2.90
Norm
0.55
Max
0.60
0.05
0.35
0.25
0.25
4.10
3.10
A
A1
b
0.02
0.30
b1
c
0.20
0.15
D
4.00
D2
Ne
e
3.00
2.40BSC
0.80BSC
4.00
E
3.90
2.20
0.35
0.25
4.10
2.40
0.45
0.35
E2
L
2.30
0.40
h
0.30
VER 1.1
63
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Packaging information
WSON-8
Dimensions In Millimeters
Symbol
Min
0.70
0.00
Norm
0.75
0.02
0.20
6.00
5.00
3.40
4.00
1.27
0.40
0.60
Max
0.80
0.04
A
A1
A2
D
5.90
4.90
3.30
3.90
6.10
5.10
3.50
4.10
E
D2
E2
e
b
0.35
0.55
0.45
0.65
L
VER 1.1
64
ACE25AA640G
Serial NOR Flash Memory
3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.1
65
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