A1280A-1PL84M [ACTEL]
Field Programmable Gate Array, 1232 CLBs, 8000 Gates, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | A1280A-1PL84M |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 1232 CLBs, 8000 Gates, CMOS, PQCC84, PLASTIC, LCC-84 栅 可编程逻辑 |
| 文件： | 总38页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v4.0.1
ACT™ 2 Family FPGAs
Features
• Up to 8000 Gate Array Gates
• Datapath Performance at 105 MHz
(20,000 PLD equivalent gates)
• 16-Bit Accumulator Performance to 39 MHz
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL® Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0-micron CMOS Technology
Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
2,500
6,250
63
4,000
10,000
100
8,000
20,000
200
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
25
40
80
Logic Modules
S-Modules
C-Modules
451
231
220
684
348
336
1,232
624
608
Flip-Flops (maximum)
382
568
998
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
36
15
250,000
36
15
400,000
36
15
750,000
User I/Os (maximum)
Packages1
83
104
140
100 CPGA
100 PQFP
100 VQFP
84 PLCC
132 CPGA
144 PQFP
176 TQFP
84 PLCC
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
Performance2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
85 MHz
67 MHz
36 MHz
Notes:
1. See the “Product Plan” on page 3 for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
December 2000
1
© 2000 Actel Corporation
ACT™ 2 Family FPGAs
Description
The ACT™ 2 family represents Actel’s second generation of
field programmable gate arrays (FPGAs). The ACT 2 family
presents a two-module architecture, consisting of C-modules
and S-modules. These modules are optimized for both
combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining downward compatibility
technology. This revolutionary architecture offers gate array
design flexibility, high performance, and fast
time-to-production with user programming. The ACT 2
family is supported by the Designer and Designer Advantage
Systems, which offers automatic pin assignment, validation
of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic
probe capabilities. The systems are supported on the
following platforms: 386/486™ PC, Sun™, and HP™
workstations. The systems provide CAE interfaces to the
following design environments: Cadence, Viewlogic®,
Mentor Graphics®, and OrCAD™.
with the ACT
1 design environment and upward
compatibility with the ACT 3 design environment. The
devices are implemented in silicon gate, 1.0-µm, two-level
metal CMOS, and employ Actel’s PLICE® antifuse
Ordering Information
A1280
A
–
1
PG
176
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I
= Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0-µm CMOS process
Part Number
A1225 = 2500 Gates
A1240 = 4000 Gates
A1280 = 8000 Gates
2
v4.0
ACT™ 2 Family FPGAs
Product Plan
Speed Grade*
Application
Std
–1
–2
C
I
M
B
A1225A Device
100-pin Ceramic Pin Grid Array (PG)
100-pin Plastic Quad Flat Pack (PQ)
100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) ✔
✔
✔
✔
✔
✔
—
—
—
—
—
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
—
84-pin Plastic Leaded Chip Carrier (PL)
✔
✔
✔
✔
✔
A1240A Device
132-pin Ceramic Pin Grid Array (PG)
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
✔
✔
✔
✔
✔
✔
—
—
✔
✔
✔
✔
✔
✔
—
—
—
144-pin Plastic Quad Flat Pack (PQ)
84-pin Plastic Leaded Chip Carrier (PL)
✔
✔
✔
✔
✔
✔
—
—
✔
✔
—
A1280A Device
176-pin Ceramic Pin Grid Array (PG)
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
✔
✔
✔
✔
✔
✔
—
—
✔
✔
✔
✔
✔
✔
—
—
—
—
160-pin Plastic Quad Flat Pack (PQ)
172-pin Ceramic Quad Flat Pack (CQ)
✔
✔
✔
✔
✔
✔
✔
—
✔
✔
Contact your Actel sales representatives for product availability.
Applications: C = Commercial Availability: ✔ = Available
= Industrial
*Speed Grade: –1 = Approx. 15% faster than Standard
–2 = Approx. 25% faster than Standard
I
P = Planned
M = Military
— = Not Planned
B = MIL-STD-883
Device Resources
User I/Os
CPGA
PQFP
PLCC CQFP
TQFP
VQFP
Device
Logic
Series Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin
A1225A
A1240A
A1280A
451
684
2500
4000
8000
—
—
—
104
—
83
—
—
—
—
—
104
—
83
—
—
72
72
72
—
—
—
83
—
—
104
140
1232
140
125
140
.
v4.0
3
ACT™ 2 Family FPGAs
Operating Conditions
Absolute Maximum Ratings1
Recommended Operating Conditions
Free air temperature range
Commercia Industria
Parameter
l
l
Military Units
Symbol
Parameter
Limits
Units
Temperature
Range1
–40 to
+85
–55 to
°C
VCC
VI
DC Supply Voltage
Input Voltage
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
20
V
V
0 to +70
+125
Power
Supply
Tolerance
VO
Output Voltage
V
5
10
10
%VCC
I/O Source/Sink
Current2
mA
IIO
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
TSTG Storage Temperature
Notes:
–65 to +150
°C
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5 V or less than GND – 0.5 V, the internal
protection diode will be forward biased and can draw excessive
current.
Electrical Specifications
Commercial
Industrial
Military
Max.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Units
1
VOH
(IOH = –10 mA) 2
(IOH = –6 mA)
(IOH = –4 mA)
(IOL = 10 mA) 2
(IOL = 6 mA)
2.4
V
V
3.84
3.7
3.7
V
1
VOL
0.5
0.33
0.8
V
0.40
0.8
0.40
0.8
V
VIL
–0.3
–0.3
–0.3
V
VIH
2.0
VCC + 0.3
500
2.0
VCC + 0.3
500
2.0
VCC + 0.3
500
V
2
Input Transition Time tR, tF
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
ns
pF
mA
µA
10
10
10
2
10
20
–10
10
–10
10
–10
10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.
5. VOUT , VIN = VCC or GND.
4
v4.0
ACT™ 2 Family FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
Max. junction temp. (°C) – Max. commercial temp.
----------------------------------------------------------------------------------------------------------------------------
150°C – 70°C
---------------------------------
=
= 2.4 W
θja (°C/W)
33°C/W
θja
Still Air
θja
300 ft/min
Package Type
Pin Count
θjc
Units
Ceramic Pin Grid Array
100
132
176
5
5
8
35
30
23
17
15
12
°C/W
°C/W
°C/W
Ceramic Quad Flat Pack
Plastic Quad Flat Pack1
172
8
25
15
°C/W
100
144
160
13
15
15
48
40
38
40
32
30
°C/W
°C/W
°C/W
Plastic Leaded Chip Carrier2
Very Thin Quad Flat Pack3
Thin Quad Flat Pack4
84
12
12
15
37
43
32
28
35
25
°C/W
°C/W
°C/W
100
176
Notes:(Maximum Power in Still Air)
1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin).
2. Maximum Power Dissipation for PLCC packages is 2.7 Watts.
3. Maximum Power Dissipation for VQFP packages is 2.3 Watts.
4. Maximum Power Dissipation for TQFP packages is 3.1 Watts.
Power Dissipation
greater reduction in board-level power dissipation can be
achieved.
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
I
OH * (VCC – VOH) * M
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst case conditions.
Where:
ICC standby is the current flowing when no inputs or outputs
are changing.
ICC
VCC
Power
2 mA
5.25V
10.5 mW
I
CC active is the current flowing due to CMOS switching.
OL, IOH are TTL sink/source currents.
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with
all outputs driving low, and 140 mW with all outputs driving
high. The actual dissipation will average somewhere
between as I/Os switch states with time.
I
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL
.
M equals the number of outputs driving TTL loads to VOH
.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided
into two components: static and active.
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
Static Power Component
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
v4.0
5
ACT™ 2 Family FPGAs
and load device inputs. An additional component of the
active power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
r2
= Fixed capacitance due to second routed array
clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
Equivalent Capacitance
CEQCR = Equivalent capacitance of routed array clock in
pF
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (µW) = CEQ * VCC2 * F
(1)
CL
fm
fn
= Output lead capacitance in pF
Where:
CEQ is the equivalent capacitance expressed in pF.
CC is the power supply in volts.
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
V
fp
F is the switching frequency in MHz.
fq1
fq2
Equivalent capacitance is calculated by measuring ICC
active at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results
may be used over a wide range of operating conditions.
Equivalent capacitance values are shown below.
Fixed Capacitance Values for Actel FPGAs
(pF)
r1
r2
Device Type
routed_Clk1
routed_Clk2
A1225A
A1240A
A1280A
106
134
168
106.0
134.2
167.8
CEQ Values for Actel FPGAs
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer Loads (CEQCR
)
5.8
12.9
23.8
3.9
)
)
)
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs
+ (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR
fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR
fq2)routed_Clk2
Logic Modules (m)
80% of modules
# inputs/4
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q1)
# outputs/4
*
40%of
*
sequential
modules
+ (r2 * fq2)routed_Clk2
]
(2)
Second routed array clock loads (q2)
40%of
Where:
sequential
modules
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
Load capacitance (CL)
35 pF
p
Average logic module switching rate (fm) F/10
q1
= Number of clock loads on the first routed array
clock
Average input switching rate (fn)
Average output switching rate (fp)
Average first routed array clock rate (fq1)
F/5
F/10
F
q2
r1
= Number of clock loads on the second routed
array clock
Average second routed array clock rate F/2
(fq2)
= Fixed capacitance due to first routed array
clock
6
v4.0
ACT™ 2 Family FPGAs
ACT 2 Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
t
INYL = 2.6 ns
tIRD2 = 4.8 ns†
tDLH = 8.0 ns
tRD1 = 1.4 ns
tRD2 = 1.7 ns
D
Q
tPD = 3.8 ns
tRD4 = 3.1 ns
tRD8 = 4.7 ns
I/O Module
G
t
DLH = 8.0 ns
Sequential
Logic Module
tINH = 2.0 ns
tINSU = 4.0 ns
tINGL = 4.7 ns
Combin-
atorial
Logic
D
D
G
Q
Q
tRD1 = 1.4 ns
tENHZ = 7.1 ns
included
in t
SUD
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 9.0 ns
tCO = 3.8 ns
tSUD = 0.4 ns
tHD = 0.0 ns
ARRAY
CLOCKS
tCKH = 11.8 ns
FO = 256
FMAX = 100 MHz
*Values shown for A1240A-2 at worst-case commercial conditions.
† Input Module Predicted Routing Delay
v4.0
7
ACT™ 2 Family FPGAs
Parameter Measurement
Output Buffer Delays
E
D
PAD To AC test loads (shown below)
TRIBUFF
VCC
VCC
VCC
In
GND
1.5 V
50%
VOH
E
GND
10%
50%
E
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5 V
VOL
PAD
VOL
PAD
PAD
GND
1.5 V
1.5 V
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
AC Test Loads
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
Input Buffer Delays
Module Delays
S
A
B
Y
Y
PAD
INBUF
VCC
GND
S, A or B
50% 50%
VCC
3 V
50%
Y
50%
PAD
0 V
50%
1.5 V
VCC
1.5 V
GND
tPLH
tPHL
Y
GND
50%
VCC
50%
Y
GND
tPLH
50%
tPHL
tINYH
tINYL
8
v4.0
ACT™ 2 Family FPGAs
Sequential Module Timing Characteristics
Flip-Flops and Latches
D
E
CLK
Y
PRE
CLR
(Positive edge triggered)
tHD
D1
tA
tWCLKA
tSUD
G, CLK
tSUENA
tWCLKI
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
v4.0
9
ACT™ 2 Family FPGAs
Sequential Timing Characteristics (continued)
Input Buffer Latches
PAD
DATA
IBDL
G
PAD
CLK
CLKBUF
DATA
G
tINH
tINSU
tHEXT
CLK
tSUEXT
Output Buffer Latches
D
G
PAD
OBDLHS
D
G
tOUTSU
tOUTH
10
v4.0
ACT™ 2 Family FPGAs
Timing Derating Factor (Temperature and Voltage)
Industrial
Military
Min.
0.69
Max.
1.11
Min.
0.67
Max.
1.23
(Commercial Minimum/Maximum Specification) x
Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C) and
Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
–40
0
25
70
85
125
4.50
4.75
5.00
5.25
5.50
0.75
0.71
0.69
0.68
0.67
0.79
0.75
0.72
0.69
0.69
0.86
0.82
0.80
0.77
0.76
0.92
0.87
0.85
0.82
0.81
1.06
1.00
0.97
0.95
0.93
1.11
1.05
1.02
0.98
0.97
1.23
1.16
1.13
1.09
1.08
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75V, 70°C)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
125˚C
85˚C
70˚C
25˚C
0˚C
–40˚C
–55˚C
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
v4.0
11
ACT™ 2 Family FPGAs
A1225A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.7
2.3
2.8
4.4
1.2
1.9
2.6
3.1
4.9
1.4
2.2
3.0
3.7
5.8
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.0
0.8
0.0
0.0
0.9
0.0
0.0
1.0
0.0
ns
ns
ns
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.5
4.5
5.0
5.0
6.0
6.0
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
9.4
0.0
0.4
0.0
0.4
11.0
0.0
0.4
0.0
0.4
13.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop (Latch) Clock
Frequency
105.0
90.0
75.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
12
v4.0
ACT™ 2 Family FPGAs
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Unit
s
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.6
5.0
4.7
3.3
3.0
5.7
5.4
3.8
3.5
6.6
6.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.1
4.6
5.3
5.7
7.4
4.6
5.2
6.0
6.4
8.3
5.4
6.1
7.1
7.6
9.8
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
tCKL
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
ns
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
Input High to Low
Minimum Pulse Width
High
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
ns
Minimum Pulse Width
Low
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
ns
FO = 32
FO = 256
0.7
3.5
0.7
3.5
0.7
3.5
Maximum Skew
ns
Input Latch External
Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
ns
Input Latch External
Hold
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
FO = 32
FO = 256
7.7
8.1
8.3
8.8
9.1
10.0
Minimum Period
ns
FO = 32
FO = 256
130.0
125.0
120.0
115.0
110.0
100.0
fMAX
Maximum Frequency
MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device
prior to shipment.
v4.0
13
ACT™ 2 Family FPGAs
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2’ Speed
‘–1’ Speed
Min. Max.
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.0
10.1
8.9
9.0
11.4
10.0
13.2
8.0
10.6
13.4
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.09
0.16
ns
8.9
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.2
0.07
0.12
ns
dTLH
dTHL
Delta Low to High
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.1
8.4
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
8.9
10.0
13.2
8.0
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.16
0.12
ns
8.9
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.2
0.12
0.09
ns
dTLH
dTHL
Note:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
14
v4.0
ACT™ 2 Family FPGAs
A1240A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.4
1.7
2.3
3.1
4.7
1.5
2.0
2.6
3.5
5.4
1.8
2.3
3.0
4.1
6.3
ns
ns
ns
ns
ns
Sequential Timing Characteristics3, 4
Flip-Flop (Latch) Data Input
Setup
tSUD
0.4
0.0
0.4
0.0
0.5
0.0
ns
ns
Flip-Flop (Latch) Data Input
Hold
tHD
tSUENA
tHENA
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.8
0.0
0.9
0.0
1.0
0.0
ns
ns
Flip-Flop (Latch) Clock Active
Pulse Width
tWCLKA
tWASYN
4.5
4.5
6.0
6.0
6.5
6.5
ns
ns
Flip-Flop (Latch)
Asynchronous Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
9.8
0.0
0.4
0.0
0.4
12.0
0.0
0.4
0.0
0.4
15.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU
Flip-Flop (Latch) Clock
Frequency
fMAX
100.0
80.0
66.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
v4.0
15
ACT™ 2 Family FPGAs
A1240A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.6
5.0
4.7
3.3
3.0
5.7
5.4
3.8
3.5
6.6
6.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.2
4.8
5.4
5.9
7.9
4.8
5.4
6.1
6.7
8.9
5.6
6.4
ns
ns
ns
ns
ns
7.2
7.9
10.5
Global Clock Network
tCKH Input Low to High
tCKL
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
ns
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
Input High to Low
Minimum Pulse Width
High
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
ns
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
Minimum Pulse Width Low
Maximum Skew
ns
FO = 32
FO = 256
0.5
2.5
0.5
2.5
0.5
2.5
ns
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
Input Latch External Setup
Input Latch External Hold
Minimum Period
ns
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
FO = 32
FO = 256
8.1
8.8
9.1
10.0
11.1
11.7
ns
FO = 32
FO = 256
125.0
115.0
110.0
100.0
90.0
85.0
fMAX
Maximum Frequency
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required todetermine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
16
v4.0
ACT™ 2 Family FPGAs
A1240A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2’ Speed
Min. Max.
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.0
10.1
8.9
9.0
11.4
10.0
13.2
8.0
10.6
13.4
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.7
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.09
0.16
ns
9.0
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.2
0.07
0.12
ns
dTLH
dTHL
Delta Low to High
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.2
8.4
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
8.9
10.0
13.2
8.0
ns
11.7
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.16
0.12
ns
9.0
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.2
0.12
0.09
ns
dTLH
dTHL
Note:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
v4.0
17
ACT™ 2 Family FPGAs
A1280A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
5.0
5.0
5.0
5.0
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.7
2.5
3.0
3.7
6.7
2.0
2.8
3.4
4.2
7.5
2.3
3.3
4.0
4.9
8.8
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.0
0.8
0.0
0.0
0.9
0.0
0.0
1.0
0.0
ns
ns
ns
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
5.5
5.5
6.0
6.0
7.0
7.0
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
11.7
0.0
0.4
0.0
0.4
13.3
0.0
0.4
0.0
0.4
18.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop (Latch) Clock
Frequency
85.0
75.0
50.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
18
v4.0
ACT™ 2 Family FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Min.
Max.
Min.
Max.
Min.
Max.
Units
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.7
5.0
4.8
3.3
3.0
5.7
5.4
3.8
3.5
6.6
6.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.6
5.2
5.6
6.5
9.4
5.1
5.9
6.0
6.9
ns
ns
ns
ns
ns
6.3
7.4
7.3
8.6
10.5
12.4
Global Clock Network
tCKH Input Low to High
tCKL
FO = 32
FO = 384
10.2
13.1
11.0
14.6
12.8
17.2
ns
ns
FO = 32
FO = 384
10.2
13.3
11.0
14.9
12.8
17.5
Input High to Low
Minimum Pulse Width
High
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
ns
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
Minimum Pulse Width Low
Maximum Skew
ns
FO = 32
FO = 384
0.5
2.5
0.5
2.5
0.5
2.5
ns
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
Input Latch External Setup
Input Latch External Hold
Minimum Period
ns
FO = 32
FO = 384
7.0
11.2
7.0
11.2
7.0
11.2
ns
FO = 32
FO = 384
9.6
10.6
11.2
12.6
13.3
15.3
ns
FO = 32
FO = 384
105.0
95.0
90.0
80.0
75.0
65.0
fMAX
Maximum Frequency
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
v4.0
19
ACT™ 2 Family FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2’ Speed
Min. Max.
‘–1’ Speed
Min. Max.
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.1
9.0
10.6
13.4
11.8
15.5
9.4
ns
tDHL
10.2
9.0
11.4
10.0
13.2
8.0
ns
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.8
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.09
0.16
ns
9.0
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.3
0.07
0.12
ns
dTLH
dTHL
Delta Low to High
Delta High to Low
ns/pF
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.3
8.5
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
tDHL
ns
tENZH
tENZL
tENHZ
tENLZ
tGLH
9.0
10.0
13.2
8.0
ns
11.8
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.16
0.12
ns
9.0
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.3
0.12
0.09
ns
dTLH
dTHL
Note:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
20
v4.0
ACT™ 2 Family FPGAs
Pin Description
CLKA
Clock A (Input)
PRA
Probe A (Output)
TTL Clock input for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when debugging has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRA is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
CLKB
Clock B (Input)
TTL Clock input for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
PRB
Probe B (Output)
The Probe B pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe A pin to allow real-time diagnostic output of any
signal path within the device. The Probe B pin can be used
as a user-defined I/O when debugging has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRB is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins
(DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the
special functions are active. When the MODE pin is LOW,
the pins function as I/Os. To provide Actionprobe capability,
the MODE pin should be terminated to GND through a 10K
resistor so that the MODE pin can be pulled high when
required.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
VCC
5.0V Supply Voltage
HIGH supply voltage.
NC
No Connection
This pin is not connected to circuitry within the device.
v4.0
21
ACT™ 2 Family FPGAs
Package Pin Assignments
84-Pin PLCC
1
84
84-Pin
PLCC
Signal
A1225A Function
A1240A Function
A1280A Function
2
CLKB, I/O
PRB, I/O
GND
CLKB, I/O
PRB, I/O
GND
CLKB, I/O
PRB, I/O
GND
4
6
10
12
22
23
28
DCLK, I/O
MODE
VCC
DCLK, I/O
MODE
VCC
DCLK, I/O
MODE
VCC
VCC
VCC
VCC
GND
GND
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
22
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments
84-Pin PLCC
1
84
84-Pin
PLCC
Signal
A1225A Function
A1240A Function
A1280A Function
43
49
63
64
65
70
76
81
83
84
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
23
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
100-Pin PQFP
100-Pin
PQFP
100
1
Pin Number
A1225A Function
Pin Number
A1225A Function
2
DCLK, I/O
MODE
GND
66
67
72
79
84
87
89
90
92
94
96
VCC
4
VCC
9
GND
16
17
22
34
40
46
57
64
65
VCC
SDI, I/O
GND
VCC
GND
PRA, I/O
CLKA, I/O
VCC
GND
VCC
GND
CLKB, I/O
PRB, I/O
GND
GND
GND
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
24
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
144-Pin PQFP
1
144
144-Pin
PQFP
v4.0
25
ACT™ 2 Family FPGAs
144-Pin PQFP
Pin Number
A1240A Function
Pin Number
A1240A Function
2
MODE
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
89
VCC
9
90
VCC
10
91
VCC
11
92
VCC
18
93
VCC
19
100
101
102
110
116
117
118
123
125
126
127
128
130
132
136
137
138
144
GND
20
GND
21
GND
28
SDI, I/O
GND
29
30
GND
44
GND
45
PRA, I/O
CLKA, I/O
VCC
46
54
55
VCC
56
VCC
64
CLKB, I/O
PRB, I/O
GND
65
79
80
GND
81
GND
88
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
26
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
160-Pin PQFP
160
1
160-Pin
PQFP
v4.0
27
ACT™ 2 Family FPGAs
160-Pin PQFP
Pin Number
A1280A Function
Pin Number
A1280A Function
2
DCLK, I/O
VCC
69
80
GND
GND
VCC
GND
VCC
GND
GND
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
MODE
GND
6
11
GND
86
16
PRB, I/O
CLKB, I/O
VCC
89
18
98
20
99
21
CLKA, I/O
PRA, I/O
GND
109
114
120
125
130
135
138
139
140
145
150
155
159
160
23
30
35
VCC
38
SDI, I/O
GND
40
44
GND
49
GND
54
VCC
57
VCC
58
VCC
59
GND
60
VCC
61
GND
64
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
28
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
100-Pin VQFP
100
1
100-Pin
VQFP
100-Pin VQFP
Pin Number
A1225A Function
Pin Number
A1225A Function
2
MODE
GND
VCC
VCC
GND
GND
VCC
GND
GND
GND
VCC
VCC
65
70
77
82
85
87
88
90
92
94
100
VCC
7
GND
14
15
20
32
38
44
55
62
63
64
SDI, I/O
GND
PRA, I/O
CLKA, I/O
VCC
CLKB, I/O
PRB, I/O
GND
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
29
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
176-Pin TQFP
176
1
176-Pin
TQFP
30
v4.0
ACT™ 2 Family FPGAs
176-Pin TQFP
Pin Number A1240A Function A1280A Function
Pin Number A1240A Function A1280A Function
1
GND
MODE
NC
GND
MODE
NC
101
103
106
107
108
109
110
111
112
113
114
115
116
121
124
125
126
133
135
136
140
143
144
145
147
151
152
154
155
156
158
160
161
165
166
168
170
173
175
NC
NC
2
NC
I/O
8
GND
NC
GND
I/O
10
11
13
18
19
20
22
23
24
25
26
27
28
29
33
37
38
45
52
54
55
57
61
64
66
67
68
74
77
78
80
82
86
89
96
97
NC
I/O
NC
I/O
NC
I/O
NC
VCC
GND
I/O
GND
VCC
GND
VCC
VCC
NC
GND
VCC
GND
VCC
VCC
I/O
GND
NC
NC
I/O
NC
I/O
GND
NC
GND
VCC
VCC
I/O
NC
I/O
VCC
NC
NC
VCC
NC
NC
NC
I/O
NC
I/O
VCC
NC
VCC
I/O
NC
I/O
NC
NC
NC
NC
GND
SDI, I/O
NC
GND
SDI, I/O
I/O
NC
I/O
NC
NC
GND
NC
GND
VCC
I/O
NC
VCC
I/O
NC
NC
NC
I/O
NC
I/O
NC
NC
NC
NC
NC
I/O
NC
I/O
NC
I/O
NC
I/O
PRA, I/O
CLKA, I/O
VCC
GND
CLKB, I/O
PRB, I/O
NC
PRA, I/O
CLKA, I/O
VCC
GND
CLKB, I/O
PRB, I/O
I/O
NC
I/O
GND
VCC
NC
GND
VCC
I/O
NC
NC
NC
I/O
NC
I/O
NC
NC
NC
VCC
I/O
NC
I/O
NC
NC
I/O
GND
NC
GND
I/O
NC
VCC
I/O
NC
NC
I/O
DCLK, I/O
DCLK, I/O
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
31
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
172-Pin CQFP
172
Pin #1
Index
1
172-Pin
CQFP
172-Pin CQFP
Pin Number
A1280A Function
Pin Number
A1280A Function
1
7
MODE
GND
VCC
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
GND
VCC
GND
VCC
GND
GND
GND
107
108
109
110
113
118
123
131
136
141
148
150
151
152
154
156
161
166
171
VCC
GND
12
17
22
23
24
27
32
37
50
55
65
66
75
80
98
103
106
VCC
VCC
VCC
GND
GND
SDI, I/O
VCC
GND
PRA, I/O
CLKA, I/O
VCC
GND
CLKB, I/O
PRB, I/O
GND
VCC
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
32
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
100-Pin CPGA
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
100-Pin
CPGA
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin
Pin Number
A1225A Function
Pin Number
A1225A Function
A4
A7
B6
C2
C3
C5
C6
C7
C8
D6
D10
E3
PRB, I/O
PRA, I/O
VCC
E11
F3
VCC
VCC
VCC
VCC
GND
VCC
GND
GND
GND
GND
VCC
F9
MODE
DCLK, I/O
GND
F10
F11
G1
G3
G9
J5
CLKA, I/O
GND
SDI, I/O
CLKB, I/O
GND
J7
K6
GND
Note:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
33
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
132-Pin CPGA
1
2
3
4
5
6
7
8
9
10 11 12 13
A
B
C
D
E
F
A
B
C
D
E
F
132-Pin
CPGA
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Pin Number
A1240A Function
Pin Number
A1240A Function
A1
B5
B6
B7
B8
B9
B12
C3
C5
C6
C7
C9
D7
E3
E11
E12
F4
MODE
GND
G2
G3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
GND
GND
VCC
GND
GND
CLKB, I/O
CLKA, I/O
PRA, I/O
GND
G4
G10
G11
G12
G13
H13
J2
SDI, I/O
DCLK, I/O
GND
PRB, I/O
VCC
J3
J11
K7
GND
VCC
K12
L5
GND
GND
L7
GND
L9
GND
M9
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
34
v4.0
ACT™ 2 Family FPGAs
Package Pin Assignments (continued)
176-Pin CPGA
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
176-Pin
CPGA
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Pin Number
A1280A Function
Pin Number
A1280A Function
A9
B3
CLKA, I/O
DCLK, I/O
CLKB, I/O
SDI, I/O
MODE
GND
H2
H3
VCC
VCC
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
GND
GND
GND
VCC
GND
GND
GND
VCC
GND
VCC
B8
H4
B14
C3
H12
H13
H14
J4
C8
C9
PRA, I/O
GND
D4
J12
J13
J14
K4
D5
VCC
D6
GND
D7
PRB, I/O
VCC
D8
K12
L4
D10
D11
D12
E4
GND
VCC
M4
GND
M5
GND
M6
E12
F4
GND
M8
VCC
M10
M11
M12
N8
F12
G4
G12
GND
GND
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
35
ACT™ 2 Family FPGAs
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (production (unmarked) v4.0.1–web-only)
Page
In the 176-Pin CPGA package, pin A3 was incorrectly assigned as CLKA, I/O. A3 is a
user I/O. Pin A9 is CLKA, I/O
unspecified
35
Data Sheet Categories
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories
are as follows:
Advanced
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
Preliminary
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unmarked (production)
The data sheet contains information that is considered to be final.
36
v4.0
ACT™ 2 Family FPGAs
v4.0
37
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Actel Asia-Pacific
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +44 (0)1256 305600
Fax: +44 (0)1256 355420
Tel: (408) 739-1010
Fax: (408) 739-1540
Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
5172104-6/12.00
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