A14100BP-1RQ208C [ACTEL]
Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 125MHz, 1377-Cell, CMOS, PQFP208, HEAT SINK, POWER, PLASTIC, MO-143, RQFP-208;
| 型号： | A14100BP-1RQ208C |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 125MHz, 1377-Cell, CMOS, PQFP208, HEAT SINK, POWER, PLASTIC, MO-143, RQFP-208 栅 |
| 文件： | 总40页 (文件大小：1250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Accelerator Series FPGAs:
ACT 3 PCI-Compliant Family
Features
•
•
•
•
Highly Predictable, Synthesis-Friendly Architecture
Supports High-Level Design Methodologies.
•
•
•
•
•
•
•
Up to 10,000 Gate Array Equivalent Gates.
Up to 250 MHz On-Chip Performance.
9.0 ns Clock-to-Output.
100% Module Utilization with Automatic Place and Route
Tools.
Deterministic, User-Controllable Timing via DirectTime
Software Tool.
Up to 1,153 Dedicated Flip-Flops.
Up to 228 User-Programmable I/O Pins.
PCI-Compliant I/O Drivers.
VHDL and Verilog-HDL Models for PCI Target, Master, and
Bridge Functions.
Four High-Speed, Low-Skew Clocks.
ACT 3 PCI-Compliant Devices
Device
A1460BP
A14100BP
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages (40 Gates)
20-Pin PAL Equivalent Packages (100 Gates)
6,000
15,000
150
10,000
25,000
250
60
100
Logic Modules
S-Module
C-Module
848
432
416
1,377
697
680
1
Dedicated Flip-Flops
768
168
1,153
228
User I/Os (Maximum)
2
Packages (By Pin Count)
PQFP
RQFP
TQFP
BGA
160, 208
—
—
208
—
176
225
313
3
Performance (Maximum, Worst-Case Commercial)
4
Chip-to-Chip
97 MHz
63 MHz
110 MHz
150 MHz
150 MHz
9.0 ns
93 MHz
63 MHz
105 MHz
150 MHz
150 MHz
9.5 ns
Accumulators (16-Bit)
Loadable Counter (16-Bit)
Prescaled Loadable Counters (16-Bit)
Datapath, Shift Registers
Clock-to-Output (Pad-to-Pad)
Notes:
1. One flip-flop per S-module, two flip-flops per I/O module.
2. See Product Plan on page 3 for package availability.
3. Based on A1460BP-2, and A14100BP-2.
4. Clock-to-Output + Set-Up
March 1997
1
© 1997 Actel Corporation
Description
Actel enhanced the popular ACT 3 Accelerator Series family timing specifications detailed in the PCI specification.
version 2.1. ACT 3 devices comply 100% to the electrical and
of FPGAs to include PCI-compliant I/O drivers. ACT 3 FPGAs
are based upon Actel’s proprietary antifuse technology and
However, as with all programmable logic devices, the
performance of the final product depends upon the user’s
design and optimization techniques.
0.6 micron CMOS process. ACT 3 devices offer
a
high-performance, PCI-compliant programmable solution.
The ACT 3 PCI-compliant family delivers 200 MHz on-chip
operation and 9.0 nanosecond clock-to-output performance
with capacities spanning from 6,000 to 10,000 gate array
equivalent gates. The PCI-compliant ACT 3 devices are
denoted with a “BP” designator and are shown in the ordering
information chart.
Predictable Performance* (Worst-Case Commercial)
Accumulators (16-Bit)
Loadable Counters (16-Bit)
63 MHz
110 MHz
Actel’s ACT 3 PCI-compliant devices provide a high-capacity,
synthesis-friendly programmable solution to PCI applications.
The following headings detail the pertinent PCI Local Bus
Specifications along with the corresponding ACT 3
parameters. The section numbers in the notes denote the
pertinent section in the PCI Local Bus Specification
Prescaled Loadable Counters (16-Bit)
Shift Registers
250 MHz
250 MHz
Ordering Information
A14100
BP –
RQ
208
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I
= Industrial (–40 to +85°C)
Package Lead Count
Package Type
PQ = Plastic Quad Flatpack
RQ = Plastic Power Quad Flatpack
TQ = Thin (1.4 mm) Quad Flatpack
BG = Plastic Ball Grid Array
Speed Grade
Std = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
Die Revision
Part Number
A1460BP = 6000 Gates
A14100BP = 10000 Gates
2
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Product Plan
Speed Grade*
Application
Std
–1
–2
–3
C
I
A1460BP Device
160-Pin Plastic Quad Flatpack (PQFP)
176-Pin Thin Quad Flatpack (TQFP)
208-Pin Plastic Quad Flatpack (PQFP)
225-Pin Plastic Ball Grid Array (BGA)
✔
P
✔
P
✔
P
✔
P
✔
P
✔
P
✔
P
✔
P
✔
P
✔
P
P
P
P
—
A14100BP Device
208-Pin Power Quad Flatpack (RQFP)
313-Pin Plastic Ball Grid Array (BGA)
✔
P
✔
P
✔
P
✔
P
✔
P
P
—
Note: P = Planned, ✔ = Availiable.
Plastic Device Resources
User I/Os
TQFP
PQFP, RQFP
BGA
Device Series
Logic Modules
Gates
160-Pin
208-Pin
176-Pin
225-Pin
313-Pin
A1460BP
848
6000
131
—
167
175
151
—
168
—
—
A14100BP
1377
10000
228
IOPCL
Dedicated (Hard-Wired)
I/O Preset/Clear (Input)
Pin Description
CLKA
Clock A (Input)
TTL input for I/O preset or clear. This global input is directly
wired to the preset and clear inputs of all I/O registers. This
pin functions as an I/O when no I/O preset or clear macros
are used.
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
CLKB
Clock B (Input)
NC
No Connection
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
This pin is not connected to circuitry within the device.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide ActionProbe capability, the
MODE pin should be terminated to GND through a 10K
resistor, allowing the MODE pin to be pulled HIGH when
required.
HCLK
Dedicated (Hard-Wired)
Array Clock (Input)
TTL clock input for sequential modules. This input is directly
wired to each S-module, and offers clock speeds independent
of the number of S-modules being driven. This pin can also be
used as an I/O.
IOCLK
Dedicated (Hard-Wired)
I/O Clock (Input)
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
TTL clock input for I/O modules. This input is directly wired
to each I/O module, and offers clock speeds independent of
the number of I/O modules being driven. This pin can also be
used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are automatically driven LOW by the Designer Series software.
3
PRA
Probe A (Output)
functionally equivalent to the 1200XL C-module and
implements high fanin combinatorial macros, such as 5-input
ANDs and 5-input ORs, and is available for use as a CM8 hard
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow macro. The S-module is designed to implement high-speed
real-time diagnostic output of any signal path within the
device. The PRA pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities
can be permanently disabled to protect programmed design
confidentiality. PRA is accessible when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
sequential functions within a single module. S-modules
consist of a full C-module driving a flip-flop, allowing an
additional level of logic to be implemented without additional
propagation delay. It is available for use as DFM8A/B and
DLM8A/B hard macros. C-modules and S-modules are
arranged in pairs called module pairs; module pairs are
arranged in alternating patterns and make up the bulk of the
array. This arrangement allows the placement software to
support two-module macros of four types: CC, CS, SC, and SS.
The C-module implements the following function:
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The PRB pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities
can be permanently disabled to protect programmed design
confidentiality. PRB is accessible when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0
* D11
where: S0 = A0 * B0 and S1 = A1 + B1
The S-module contains a full implementation of the C-module
plus a clearable sequential element that can either
implement a latch or flip-flop function. The S-module can
implement any function implemented by the C-module,
allowing complex combinatorial-sequential functions to be
implemented with no delay penalty. The Designer Series
development system will automatically combine any
C-module macro driving an S-module macro into the
S-module, freeing up a logic module and eliminating a module
delay.
V
5V Supply Voltage
CC
HIGH supply voltage.
GND
Ground
LOW supply voltage.
The clear input (CLR) is accessible from the routing channel.
In addition, the clock input may be connected to one of three
clock networks: CLK0, CLK1, or HCLK. The C-module and
S-module functional descriptions are shown in Figures 2
and 3. The clock selection multiplexor selects the clock input
to the S-module.
Architecture
This section of the data sheet is meant to familiarize the user
with the architecture of the ACT 3 family of FPGA devices. A
generic description of the family will be presented first,
followed by a detailed description of the logic blocks, routing
structure, antifuses, and special function circuits. The
on-chip circuitry required to program the devices is not
covered.
I/O Modules
I/O modules provide an interface between the array and the
I/O pad drivers. I/O modules are located in the array and
access the routing channels in a fashion similar to logic
modules. There are two types of I/O modules: side/side and
top/bottom. The I/O module schematic is shown in Figure 4.
UO1 and UO2 are inputs from the routing channel: one for the
routing channel above and one for the routing channel below
the module. The top/bottom I/O modules interact with only
one channel and therefore have only one UO input. The
signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops, and each
flip-flop is connected to the dedicated I/O clock (IOCLK).
Topology
The ACT 3 family architecture is composed of six key
elements: logic modules, I/O modules, I/O pad drivers, routing
tracks, clock networks, and programming and test circuits.
The basic structure is similar for all devices in the family,
differing only in the number of rows, columns, and I/Os. The
array itself consists of alternating rows of modules and
channels. The logic modules and channels are in the center
of the array; the I/O modules are located along the array
periphery. A simplified floor plan is depicted in Figure 1.
Logic Modules
Each flip-flop can be bypassed by non-sequential I/Os. In
addition, each flip-flop contains a data enable input that can
be accessed from the routing channels (ODE and IDE). The
asynchronous preset/clear input is driven by the dedicated
ACT 3 logic modules are enhanced versions of the 1200XL
family logic modules. As in the 1200XL family, there are two
types of modules: C-modules and S-modules. The C-module is
4
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
An Array with n Rows and m Columns
0
1
2
3
4
5
c–1
c
c+1
m m+1 m+2 m+3
Columns
Rows
n+1
Channels
n+2
IO IO IO IO IO IO
Top I/Os
IO IO IO CLKM
n+1
n
IO IO BIN S
IO IO BIN S
IO IO BIN S
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
C
C
C
C
S
S
S
S
IO IO
n
IO IO
IO IO
n–1
•
•
•
n–1
•
•
•
2
2
IO IO
IO IO BIN S
Left I/Os
1
0
1
0
Right I/Os
Bottom I/Os
BIO IO IO IO IO IO
IO IO IO IO IO IO
Figure 1 • Generalized Floor Plan of ACT 3 Device
The I/O module output Y is used to bring pad signals into the
array or to feed the output register back into the array. This
allows the output register to be used in high-speed state
machine applications. Side I/O modules have a dedicated
output segment for Y extending into the routing channels
above and below (similar to logic modules). Top/Bottom I/O
modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses
and LVTs (F-fuses and LVTs are explained in detail in the
routing section).
D00
D01
OUT
Y
D10
D11
S1
S0
I/O Pad Drivers
All pad drivers are capable of being tri-state. Each buffer
connects to an associated I/O module with four signals: OE
(Output Enable), IE (Input Enable), DataOut, and DataIn.
Special signals used only during programming and test also
connect to the pad drivers: OUTEN (global output enable),
INEN (global input enable), and SLEW (individual slew
selection). See Figure 5.
A1 B1
A0 B0
Figure 2 • C-Module Diagram
preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O-module-by-I/O-module basis.
5
D00
D01
Y
D
Q
OUT
D10
D11
S1
S0
CLK
CLR
A1 B1
A0 B0
Figure 3 • S-Module Diagram
OTB
0
U01
U02
MUX
DATAOUT
0
1
MUX
Q
D
1
CLR/PRE
ODE
IDE
IEN
0
1
2
3
S0
S1
Y
MUX
1
MUX
D
Q
0
DATAIN
CLR/PRE
IOPCL
IOCLK
Figure 4 • Function Diagram for I/O Module
6
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
the input of S-modules or I/O modules. There are two
dedicated clock networks: one for the array registers (HCLK),
and one for the I/O registers (IOCLK). The clock networks
are accessed by special I/Os.
OE
SLEW
Routed Clocks
The routed clock networks are referred to as CLK0 and CLK1.
Each network is connected to a clock module (CLKMOD)
that selects the source of the clock signal, and may be driven
as follows (see Figure 6):
DATAOUT
•
•
•
•
Externally from the CLKA Pad
Externally from the CLKB Pad
Internally from the CLKINA Input
Internally from the CLKINB Input
PAD
DATAIN
IEN
The clock modules are located in the top row of the I/O
modules. Clock drivers and a dedicated horizontal clock track
are located in each horizontal routing channel. The function
of the clock module is determined by the selection of clock
macros from the macro library. The macro CLKBUF is used to
connect one of the two external clock pins to a clock network,
and the macro CLKINT is used to connect an internally
generated clock signal to a clock network. Since both clock
networks are identical, the user may use either CLK0 or
CLK1. Routed clocks can also be used to drive high-fanout
nets like resets, output enables, or data enables. This saves
logic modules and results in performance increases in some
cases.
INEN
OUTEN
Figure 5 • Function Diagram for I/O Pad Driver
Special I/Os
The special I/Os are of two types: temporary and permanent.
Temporary special I/Os are used during programming and
testing, and function as normal I/Os when the MODE pin is
inactive. Permanent special I/Os are user-programmed as
either normal I/Os or special I/Os. Their function does not
change once the device has been programmed. The
permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input
buffer (HCLK), the hard-wired I/O clock input buffer
(IOCLK), and the hard-wired I/O register preset/clear input
buffer (IOPCL). Their function is determined by the I/O
macros selected.
CLKB
CLKA
CLKINB
CLKINA
From
Pads
S0
S1
Internal
Signal
CLKMOD
CLKO(17)
CLKO(16)
CLKO(15)
Clock Networks
The ACT 3 architecture contains four clock networks: two
high-performance dedicated clock networks and two
general-purpose routed networks. The high-performance
networks function up to 200 MHz, while the general-purpose
routed networks function up to 150 MHz.
Clock
Drivers
CLKO(2)
CLKO(1)
Dedicated Clocks
Dedicated clock networks support high performance by
providing sub-nanosecond skew and predictable
performance. Dedicated clock networks contain no
programming elements in the path from the I/O pad driver to
Clock Tracks
Figure 6 • Clock Networks
7
Routing Structure
shown in Figure 7. Undedicated horizontal routing tracks are
used to route signal nets. Dedicated routing tracks are used
for the global clock networks, and for power and ground
tie-off tracks.
The ACT 3 architecture uses vertical and horizontal routing
tracks to connect the various logic and I/O modules. These
routing tracks are metal interconnects that may either be of
continuous length or broken into segments. Segments can be
joined together at the ends using antifuses to increase their
lengths up to the full length of the track.
Vertical Routing
Vertical tracks are of three types: input, output, and long.
Vertical tracks are also divided into one or more segments,
with each segment in an input track dedicated to the input of
a particular module. Each segment in an output track is
dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array
where edge effects occur. LVTs contain either one or two
segments. An example of vertical routing tracks and segments
is shown in Figure 8.
Horizontal Routing
Horizontal channels are located between the rows of modules,
and are composed of several routing tracks. The horizontal
routing tracks within the channel are divided into one or
more segments. The minimum horizontal segment length is
the width of a module pair, and the maximum horizontal
segment length is the full length of the channel. Any segment
that spans more than one-third of the row’s length is
considered a long horizontal segment. A typical channel is
Module Row
HCLK
CLK0
NVCC
SIGNAL
Track
SIGNAL
(LHT)
Segment
|
|
|
|
|
|
|
HF
SIGNAL
NVSS
CLK1
Module Row
Figure 7 • Horizontal Routing Tracks and Segments
8
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
LVTs
Module Row
Channel
S-Module
C-Module
VF
XF
Verticle Input
Segment
FF
S-Module
C-Module
Figure 8 • Vertical Routing Tracks and Segments
Antifuse Connections
Module Interface
An antifuse is a “normally open” structure as opposed to the
“normally closed” fuse structure used in PROMs or PALs. The
use of antifuses to implement a programmable logic device
results in highly testable structures, as well as an efficient
programming architecture. The structure is highly testable
because there are no pre-existing connections; temporary
connections can be made using pass transistors. These
temporary connections can isolate individual antifuses to be
programmed, as well as isolate individual circuit structures to
be tested. This can be done both before and after
programming. For example, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.
Connections to logic and I/O modules are made through
vertical segments that connect to the module inputs and
outputs. These vertical segments lie on vertical tracks that
span the entire height of the array.
Module Input Connections
The tracks dedicated to module inputs are segmented by pass
transistors in each module row. During normal user
operation, the pass transistors are inactive, which isolates the
inputs of a module from the inputs of the module directly
above or below it. During certain test modes, the pass
transistors are active to verify the continuity of the metal
tracks. Vertical input segments span only the channel above
or the channel below. The logic modules are arranged such
that half of the inputs are connected to the channel above
and half of the inputs to segments in the channel below, as
shown in Figure 9.
Four types of antifuse connections are used in the routing
structure of the ACT 3 array. The physical structure of the
antifuse is identical in each case; only the usage differs.
Table 1 shows four types of antifuses.
Module Output Connections
Table 1 • Antifuse Types
Module outputs have dedicated output segments. Output
segments extend vertically two channels above and two
channels below, except at the top or bottom of the array.
Output segments twist, as shown in Figure 10, so that only
four vertical tracks are required.
XF
HF
VF
FF
Horizontal-to-Vertical Connection
Horizontal-to-Horizontal Connection
Vertical-to-Vertical Connection
“Fast” Vertical Connection
LVT Connections
Examples of all four types of connections are shown in
Figures 7 and 8.
Outputs may also connect to non-dedicated segments called
long vertical tracks (LVTs). Each module pair in the array
shares four LVTs that span the length of the column. Any
module in the column pair can connect to one of the LVTs in
9
the column using an FF connection. The FF connection uses
antifuses connected directly to the driver stage of the module
output, bypassing the isolation transistor. FF antifuses are
programmed at a higher current level than HF, VF, or XF
antifuses to produce a lower resistance value.
C-module and S-module inputs can be connected to the clock
networks. To further reduce loading on the clock network,
only a subset of the horizontal routing tracks can connect to
the clock inputs of the S-module.
Programming and Test Circuits
Antifuse Connections
The array of logic and I/O modules is surrounded by test and
programming circuits controlled by the temporary special I/O
pins MODE, SDI, and DCLK. The function of these pins is
similar in all ACT family devices. The ACT 3 family also
includes support for two ActionProbe circuits, allowing
complete observability of any logic or I/O module in the array
using the temporary special I/O pins PRA and PRB.
In general, every intersection of a vertical segment and a
horizontal segment contains an unprogrammed antifuse
(XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of the
input has antifuses on the clock tracks. Only a few of the
Y+2
Y+1
Y+2
Y+1
B1 B0
A1 D10 D11
D01 D00
B0
B1 D01
Y
Y
A0
D10
A0 D11 A1
Y-1
Y-1
Y-2
Y-2
LVTs
C-Modules
S-Modules
Figure 9 • Logic Module Routing Interface
10
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
5V Operating Conditions
Recommended Operating Conditions
Parameter
Commercial Industrial Military Units
1
Absolute Maximum Ratings
Free Air Temperature Range
Temperature 0 to +70
–40 to +85 –55 to
+125
°C
1
Range
Symbol Parameter
Limits
–0.5 to +7.0
Units
5V Power
Supply
Tolerance
±5
±10
±10
%V
CC
V
V
V
DC Supply Voltage
Input Voltage
V
CC
–0.5 to V +0.5
CC
V
I
Note:
Output Voltage
I/O Source Sink
–0.5 to V +0.5
CC
V
1. Ambient temperature (T ) is used for commercial and
O
A
industrial; case temperature (T ) is used for military.
C
I
±20
mA
IO
2
Current
Electrical Specifications
T
Storage Temperature –65 to +150
°C
STG
The PCI bus specifies I/O drivers in terms of the DC and AC
characteristics. However, since the PCI bus drivers spend a
relatively large proportion of time transitioning from one
power rail to the other, PCI drivers are primarily
characterized by their V/I curves (Tables 2 and 3).
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than V + 0.5V or less than GND – 0.5V, the internal protection
CC
diodes will forward-bias and can draw excessive current.
11
Output Drive Characteristics
for 5.0V Signaling
ACT 3 PCI device I/O drivers were designed specifically for
typical output drive characteristics of the 5.0V ACT 3 devices.
ACT 3 output drivers are compliant with the PCI Local Bus
Specification.
high-performance PCI systems. Figures 10 and 11 show the
Table 2 • DC Specification for 5.0V Signaling1
PCI
ACT 3
Symbol Parameter
Condition
Minimum
Maximum
Minimum
Maximum
Units
2
V
V
V
Supply Voltage
4.75
2
5.25
4.75
2
5.25
V + 0.5
CC
V
V
CC
IH
IL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
V
+ 0.5
CC
–0.5
0.8
–0.3
—
0.8
V
I
I
V
V
= 2.7
=0.5
70
10
µA
µA
V
IH
IL
IN
–70
—
–10
IN
V
V
I
= –2 mA
= 3 mA,
2.4
3.7
OH
OUT
I
OUT
Output Low Voltage
0.55
—
0.33
V
OL
6 mA
C
C
Input Pin Capacitance
CLK Pin Capacitance
Pin Inductance
10
12
20
—
—
—
10
10
pF
pF
nH
IN
5
CLK
PIN
3
L
< 8 nH
Notes:
1. PCI Local Bus Specification Section 4.2.1.1.
2. Maximum rating for V –0.5V to 7.0V. Refer to Accelerator Series FPGAs ACT 3 family data sheet.
CC
3. Dependent upon the chosen package. PCI recommends QFP packaging to reduce pin inductance and capacitance.
Table 3 • AC Specifications for 5.0V Signaling1
PCI
Minimum
ACT 3
Maximum Minimum Maximum Units
Symbol Parameter
Low Clamp Current
Condition
I
–5 < V ≤ –1
–25 + (V +1)
IN
–60
–10
mA
CL
IN
/0.015
Slew (r) Output Rise Slew Rate
Slew (f) Output Lall Slew Rate
Note:
0.4V to 2.4V load
2.4V to 0.4V load
1
1
5
5
1.8
2.8
2.8
4.3
V/ns
V/ns
1. PCI Local Bus Specification Section 4.2.1.2.
12
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
500
PCI I Maximum
OL
450
400
350
300
250
200
150
I
(mA)
OL
ACT 3 PCI I
OL
100
50
0
PCI I Minimum
OL
0
0.40 0.80 1.20 1.60 2.00 2.40 2.80 3.20 3.60 4.00 4.40
(V)
V
OUT
Figure 10 • Typical Output Drive Characteristics (Based upon simulation data)
0
0.40 0.80 1.20 1.60 2.00 2.40 2.80 3.20 3.60 4.00 4.40
0
–20
PCI I
Minimum
OH
–40
–60
ACT 3 PCI I
OH
–80
I
(mA)
OH
–100
–120
–140
–160
–180
PCI I
Maximum
OH
V
(V)
OUT
Figure 11 • Typical Output Drive Characteristics (Based upon simulation data)
13
System Timing Specification
PCI Models
Tables 4 and 5 list the critical PCI timing parameters and the
corresponding timing parameter for the ACT 3 PCI-compliant
devices.
Actel provides synthesizable VHDL and Verilog-HDL models
for a PCI target interface, a PCI master interface, and a
PCI-to-PCI bridge interface. Consult your local Actel sales
representative for more details.
Table 4 • Clock Specification for 33 MHz PCI1
PCI
ACT 3
Symbol
Parameter
Minimum
Maximum
Minimum
Maximum
Units
T
T
T
CLK Cycle Time
CLK High Time
CLK Low Time
30
11
11
—
—
—
4.0
1.9
1.9
—
—
—
ns
ns
ns
CYC
HIGH
LOW
Note:
1. PCI Local Bus Specification Section 4.2.3.1.
Table 5 • Timing Parameters for 33 MHz PCI1
PCI
ACT 3
Symbol
Parameter
Minimum
Maximum
Minimum
Maximum
Units
T
T
CLK to Signal Valid—Bused Signals
CLK to Signal Valid—Point-to-Point
Float to active
2
11
12
—
28
—
—
—
2.0
2.0
2.0
—
9.0
9.0
4.0
ns
ns
ns
ns
ns
ns
ns
VAL
2
VAL(PTP)
T
2
—
ON
2
T
Active to Float
8.3
OFF
T
Input Set-Up Time to CLK—Bused Signals
Input Set-Up Time to CLK—Point-to-Point
Input Hold to CLK
7
1.5
1.5
0
—
—
—
SU
T
T
10, 12
0
SU(PTP)
H
Notes:
1. For information only. These values represent registered I/O timing used in the PCI macro implementation for an A1460BP-2 device. Please
see the PCI macro specification for more information on timing and speed bin requirements.
2.
T
is system dependent. ACT 3 PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
OFF
14
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Package Thermal Characteristics
Maximum junction temperature is 150°C.
The device junction to case thermal characteristic is θjc, and
the junction to ambient air characteristic is θja. The thermal
characteristics for θja are shown with two different air flow
rates.
A sample calculation of the absolute maximum power
dissipation allowed for CPGA 175-pin package at
commercial temperature and still air is as follows:
a
Max. Junction Temp. (°C) – Max. Ambient Temp. (°C)
Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 3 . 2 W
θja (°C/W) 25°C/W
150°C – 70°C
θ
θ
ja
ja
1
Package Type
Pin Count
θ
Still Air
300 ft/min
Units
jc
Plastic Quad Flatpack
160
208
10
10
33
33
26
26
°C/W
°C/W
Thin Quad Flatpack
Power Quad Flatpack
Plastic Ball Grid Array
176
208
11
32
17
25
13
°C/W
°C/W
°C/W
°C/W
0.4
225
313
10
10
25
23
19
17
Note:
1. Maximum power dissipation in still air for 160-pin PQFP package is 2.4 watts, 208-pin PQFP package is 2.4 watts, 100-pin PQFP package is
1.6 watts, 100-pin VQFP package is 1.9 watts, 176-pin TQFP package is 2.5 watts, 84-pin PLCC package is 2.2 watts, 208-pin RQFP package is
4.7 watts, 225-pin BGA package is 3.2 watts, 313-pin BGA package is 3.5 watts.
Power Dissipation
The static power dissipated by TTL loads depends on the
number of outputs driving HIGH or LOW and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all
outputs driving LOW, and 140 mW with all outputs driving
HIGH. The actual dissipation will average somewhere
between as I/Os switch states with time.
P = [ICC standby+ Iactive] * VCC + IOL * VOL * N + IOH
*
(VCC – V ) * M
(1)
OH
Where:
ICC standby is the current flowing when no inputs or
outputs are changing.
I
active is the current flowing due to CMOS switching.
OL, IOH are TTL sink/source currents.
Active Power Component
I
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This frequency-
dependent component is a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
V , VOH are TTL level output voltages.
OL
N equals the number of outputs driving TTL loads to
V .
OL
M equals the number of outputs driving TTL loads to
V .
OH
An accurate determination of N and M is problematical
because their values depend on the design and on the system
I/O. The power can be divided into two components: static
and active.
Static Power Component
Equivalent Capacitance
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
The power dissipated by a CMOS circuit can be expressed by
Equation 2.
Power (µW) = CEQ * V 2 * F
(2)
CC
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst-case conditions.
Where:
CEQ is the equivalent capacitance expressed in pF.
CC is the power supply in volts.
F is the switching frequency in MHz.
V
ICC
V
Power
CC
2mA
5.25 V
10.5 mW
15
Equivalent capacitance is calculated by measuring ICC active
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
Where:
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
= Number of clock loads on the first routed
array clock
range of frequencies at a fixed value of V . Equivalent
CC
p
capacitance is frequency-independent, allowing the results to
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
q1
q2
r1
r2
s1
s2
= Number of clock loads on the second routed
array clock
C
Values for Actel FPGAs
EQ
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer Loads (CEQCR
Dedicated Clock Buffer Loads (CEQCD
I/O Clock Buffer Loads (CEQCI
)
6.7
7.2
= Fixed capacitance due to first routed array
clock
)
)
10.4
1.6
= Fixed capacitance due to second routed array
clock
)
)
0.7
= Fixed number of clock loads on the dedicated
array clock
)
0.9
= Fixed number of clock loads on the dedicated
I/O clock
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 3 shows a piece-wise linear summation
over all components.
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in
pF
Power =V 2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs
+
CC
(p * (CEQO+ CL) * fp)outputs
+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2
CEQCR = Equivalent capacitance of routed array clock
in pF
CEQCD = Equivalent capacitance of dedicated array
clock in pF
+ (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk
+ (s2 * CEQCI * fs2)IO_Clk
]
(3)
CEQCI = Equivalent capacitance of dedicated I/O clock
in pF
CL
fm
fn
fp
fq1
fq2
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in
MHz
fs1
fs2
= Average dedicated array clock rate in MHz
= Average dedicated I/O clock rate in MHz
16
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Fixed Capacitance Values for Actel FPGAs
(pF)
r1
routed_Clk1
165
r2
Device Type
A1460BP
routed_Clk2
165
195
A14100BP
195
Fixed Clock Loads (s /s
1
)
2
s1
s2
Clock Loads on
Clock Loads on
Device Type
Dedicated Array
Clock
Dedicated I/O
Clock
A1460BP
432
697
168
228
A14100BP
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios that can be generally used to predict the
upper limits of power dissipation.
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
= 80% of Modules
= # Inputs/4
= # Output/4
First Routed Array Clock Loads = 40% of Sequential
(q1) Modules
Second Routed Array Clock Loads = 40% of Sequential
(q2)
Modules
Load Capacitance (CL)
= 35 pF
Average Logic Module Switching = F/10
Rate (fm)
Average Input Switching Rate (fn) = F/5
Average Output Switching Rate (fp) = F/10
Average First Routed Array Clock = F/2
Rate (fq1)
Average Second Routed Array = F/2
Clock Rate (fq2)
Average Dedicated Array Clock = F
Rate (fs1)
Average Dedicated I/O Clock Rate = F
(fs2)
17
ACT 3 Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
t
= 2.8 ns
INY
t
= 1.2 ns
IRD2
t
= 5.0 ns
DHS
t
= 0.9 ns
= 1.7 ns
= 2.8 ns
RD1
D
Q
t
= 2.0 ns
PD
t
RD4
RD8
t
I/O Module
t
= 5.0 ns
DHS
Sequential
Logic Module
t
= 0.0 ns
= 1.8 ns
= 4.7 ns
INH
t
t
INSU
ICKY
Combin-
atorial
D
D
Q
Q
t
= 0.9 ns
t
= 4.0 ns
RD1
ENZHS
Logic
included
in t
SUD
t
= 0.7 ns
= 0.7 ns
OUTH
t
OUTSU
t
= 2.0 ns
t
= 0.5 ns
= 0.0 ns
CO
SUD
ARRAY
CLOCK
t
HD
t
= 3.0 ns
HCKH
F
= 250 MHz
HMAX
t
= 7.5 ns
(pad-pad)
CKHS
I/O CLOCK
F
= 250 MHz
IOMAX
*Values shown for A1425A-3.
18
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Output Buffer Delays
E
D
To AC test loads (shown below)
PAD
TRIBUFF
V
V
V
CC
CC
CC
D
GND
1.5V
50%
E
GND
10%
50%
E
GND
90%
50%
50%
CC
50%
50%
V
V
V
OH
OH
1.5V
VOL
PAD
VOL
PAD
PAD
GND
1.5V
1.5V
t
t
t
t
t
t
ENHSZ
DHS
DHS
ENZHS
ENHSZ
ENZHS
AC Test Loads
Load 2
(Used to measure rising/falling edges)
Load 1
(Used to measure propagation delay)
VCC
GND
To the output under test
35 pF
R to V for t /t
CC
PLZ PZL
R to GND for t
/t
PHZ PZH
R = 1 kW
35 pF
To the output under test
Input Buffer Delays
Module Delays
S
Y
A
B
Y
PAD
INBUF
V
CC
GND
S, A or B
50% 50%
3V
V
CC
PAD
0V
1.5V
1.5V
50%
Y
50%
V
CC
GND
t
t
50%
PD
PD
Y
GND
50%
V
Y
CC
GND
50%
50%
t
t
INY
INY
t
t
PD
PD
19
Sequential Module Timing Characteristics
Flip-Flops
D
Q
CLK
CLR
(Positive Edge Triggered)
t
HD
D
t
t
t
A
WCLKA
SUD
CLK
t
WCLKA
t
CO
Q
t
CLR
CLR
t
WASYN
I/O Module: Sequential Input Timing Characteristics
D
E
Y
PRE
CLR
IOCLK
(Positive Edge Triggered)
t
INH
D
t
t
IOP
t
IOPWH
INSU
IOCLK
t
t
t
IDEH
IDESU
IOPWL
E
Y
t
ICKY
t
ICLRY
PRE, CLR
t
IOASPW
20
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
I/O Module: Sequential Output Timing Characteristics
Q
D
E
PRE
CLR
IOCLK
Y
(Positive Edge Triggered)
t
OUTH
D
t
t
t
IOP
IOPWH
OUTSU
IOCLK
t
t
ODESU
IOPWL
E
Y
t
OCKY
t
t
,
CKHS
CKLS
Q
t
OCLRY
PRE, CLR
t
IOASPW
21
Predictable Performance:
Timing Characteristics
Tightest Delay Distributions
Timing characteristics for ACT 3 devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all ACT 3 family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is complete.
Delay values may then be determined by using the ALS timer
utility or performing simulation with post-layout delays.
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer lengths of routing track.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical paths.
Critical nets are determined by net property assignment prior
to placement and routing. Up to 6% of the nets in a design may
be designated as critical, while 90% of the nets in a design are
typical.
The ACT 3 family delivers the tightest fanout delay
distribution of any FPGA. This tight distribution is achieved in
two ways: by decreasing the delay of the interconnect
elements and by decreasing the number of interconnect
elements per path.
Actel’s patented PLICE antifuse offers
resistive/capacitive interconnect. The ACT
antifuses offer nominal levels of 200Ω resistance and 6
a
very low
family’s
3
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of the nets in a
fully utilized device require long tracks. Long tracks
contribute approximately 4 ns to 14 ns delay, and is
represented statistically in higher fanout (FO=8) routing
delays (noted in the Specifications section).
femtofarad (fF) capacitance per antifuse.
The ACT 3 fanout distribution is also tighter than alternative
devices due to the low number of antifuses required per
interconnect path. The ACT
3 family’s proprietary
architecture limits the number of antifuses per path to only
four, with 90% of interconnects using only two antifuses.
The ACT 3 family’s tight fanout delay distribution offers an
FPGA design environment in which fanout can be traded for
the increased performance of reduced logic level designs.
This also simplifies performance estimates when designing
with ACT 3 devices.
Timing Derating
ACT 3 devices are manufactured in a CMOS process;
therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Table 6 • Logic Module and Routing Delay by Fanout (ns)
(Worst-Case Commercial Conditions)
Speed
FO=1
FO=2
FO=3
FO=4
FO=8
–3
2.9
3.2
3.4
3.7
4.8
22
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Timing Derating Factor (Temperature and Voltage)
Industrial
Military
Min.
Max.
Min.
Max.
(Commercial Minimum/Maximum Specification) x
0.66
1.07
0.63
1.17
Timing Derating Factor for Designs at Typical Temperature (T = 25°C)
J
and Voltage (5.0V)
(Commercial Maximum Specification) x
0.85
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, T = 4.75V, 70°C)
J
–55
0.72
0.70
0.68
0.66
0.63
–40
0.76
0.73
0.71
0.69
0.66
0
25
70
85
125
1.17
1.12
1.09
1.06
1.01
4.50
4.75
5.00
5.25
5.50
0.85
0.82
0.79
0.77
0.74
0.90
0.87
0.84
0.82
0.79
1.04
1.00
0.97
0.94
0.90
1.07
1.03
1.00
0.97
0.93
Junction Temperature and Voltage Derating Curves
(Normalized to Worst-Case Commercial, T = 4.75V, 70°C)
J
1.20
1.10
1.00
0.90
0.80
0.70
0.60
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
23
A1460BP Timing Characteristics
1
(Worst-Case Commercial Conditions, V
= 4.75V,
T
= 70°C)
J
CC
2
Logic Module Propagation Delays
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
Internal Array Module
Sequential Clock to Q
2.0
2.0
2.0
2.3
2.3
2.3
2.6
2.6
2.6
3.0
3.0
3.0
ns
ns
ns
PD
CO
CLR
Asynchronous Clear to Q
3
Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.2
1.4
1.7
2.8
1.0
1.4
1.6
1.9
3.2
1.1
1.6
1.8
2.2
3.6
1.3
1.8
2.1
2.5
4.2
ns
ns
ns
ns
ns
RD1
RD2
RD3
RD4
RD8
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Latch Data Input Set-Up
Latch Data Input Hold
0.5
0.0
0.5
0.0
2.4
2.4
5.0
0.6
0.0
0.6
0.0
3.2
3.2
6.8
0.7
0.0
0.7
0.0
3.8
3.8
8.0
0.8
0.0
0.8
0.0
4.8
4.8
10.0
ns
ns
SUD
HD
ns
SUD
HD
ns
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
ns
WASYN
WCLKA
A
ns
ns
200
150
125
100
MHz
MAX
Notes:
1.
2. For dual-module macros, use t + t + t
V
= 3.0V for 3.3V specifications.
CC
or t + t + t
or t + t + t
, whichever is appropriate.
SUD
PD RD1
PDn
CO RD1
PDn
PD1
RD1
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
24
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
A1460BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
I/O Module Input Propagation Delays
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
t
Input Data Pad to Y
2.8
4.7
4.7
3.2
5.3
5.3
3.6
6.0
6.0
4.2
7.0
7.0
ns
ns
ns
INY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
ICKY
OCKY
ICLRY
Input Asynchronous
Clear to Y
4.7
4.7
5.3
5.3
6.0
6.0
7.0
7.0
ns
ns
t
Output Asynchronous
Clear to Y
OCLRY
1
Predicted Input Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.2
1.4
1.7
2.8
1.0
1.4
1.6
1.9
3.2
1.1
1.6
1.8
2.2
3.6
1.3
1.8
2.1
2.5
4.2
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD8
I/O Module Sequential Timing
t
t
t
t
t
t
t
t
Input F-F Data Hold
(w.r.t. IOCLK Pad)
INH
0.0
1.3
0.0
5.8
0.7
0.7
0.3
1.3
0.0
1.5
0.0
6.5
0.8
0.8
0.4
1.5
0.0
1.8
0.0
7.5
0.9
0.9
0.4
1.7
0.0
2.0
0.0
8.6
1.0
1.0
0.5
2.0
ns
ns
ns
ns
ns
ns
ns
ns
Input F-F Data Set-Up
(w.r.t. IOCLK Pad)
INSU
Input Data Enable Hold
(w.r.t. IOCLK Pad)
IDEH
Input Data Enable Set-Up
(w.r.t. IOCLK Pad)
IDESU
OUTH
OUTSU
ODEH
ODESU
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Set-Up
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Set-Up
(w.r.t. IOCLK Pad)
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
25
A1460BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
1
I/O Module – TTL Output Timing
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Min. Max. Units
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
t
t
t
Data to Pad, High Slew
Data to Pad, Low Slew
5.0
8.0
5.6
9.0
6.4
7.5
ns
ns
DHS
10.2
12.0
DLS
Enable to Pad, Z to H/L,
High Slew
ENZHS
4.0
7.4
7.8
7.4
9.0
4.5
8.3
8.7
8.3
9.0
5.1
9.4
6.0
ns
ns
ns
ns
ns
t
t
t
t
t
Enable to Pad, Z to H/L,
Low Slew
ENZLS
ENHSZ
ENLSZ
CKHS
CKLS
11.0
11.6
11.0
11.5
Enable to Pad, H/L to Z,
High Slew
9.9
Enable to Pad, H/L to Z,
Low Slew
9.4
IOCLK Pad to Pad H/L,
High Slew
10.0
IOCLK Pad to Pad H/L,
Low Slew
12.8
0.02
0.05
0.04
0.05
12.8
0.02
0.05
0.04
0.05
15.3
0.03
0.06
0.04
0.06
17.0
0.03
0.07
0.05
0.07
ns
d
d
d
d
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
ns/pF
ns/pF
ns/pF
ns/pF
TLHHS
TLHLS
THLHS
THLLS
Delta High to Low, Low Slew
1
I/O Module – CMOS Output Timing
t
t
t
Data to Pad, High Slew
Data to Pad, Low Slew
6.2
7.0
7.9
9.3
ns
ns
DHS
11.7
13.1
14.9
17.5
DLS
Enable to Pad, Z to H/L,
High Slew
ENZHS
5.2
8.9
5.9
10.0
8.3
6.6
11.3
9.4
7.8
ns
ns
ns
ns
ns
t
t
t
t
t
Enable to Pad, Z to H/L,
Low Slew
ENZLS
ENHSZ
ENLSZ
CKHS
CKLS
13.3
11.0
11.0
13.8
Enable to Pad, H/L to Z,
High Slew
7.4
Enable to Pad, H/L to Z,
Low Slew
7.4
8.3
9.4
IOCLK Pad to Pad H/L,
High Slew
10.4
10.4
12.1
IOCLK Pad to Pad H/L,
Low Slew
14.5
0.04
0.07
0.03
0.04
14.5
0.04
0.08
0.03
0.04
17.4
0.05
0.09
0.03
0.04
19.3
0.06
0.11
0.04
0.05
ns
d
d
d
d
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns/pF
ns/pF
ns/pF
ns/pF
TLHHS
TLHLS
THLHS
THLLS
Note:
1. Delays based on 35pF loading.
26
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
A1460BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Dedicated (Hard-Wired) I/O Clock Network
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
Input Low to High
IOCKH
(Pad to I/O Module Input)
2.3
2.6
3.0
3.5
ns
ns
ns
t
t
t
Minimum Pulse Width High
Minimum Pulse Width Low
2.4
2.4
3.2
3.2
3.8
3.8
4.8
4.8
IOPWH
IOPWL
IOSAPW
Minimum Asynchronous Pulse
Width
2.4
5.0
3.2
6.8
3.8
8.0
4.8
ns
ns
t
t
f
Maximum Skew
0.6
0.6
0.6
0.6
IOCKSW
IOP
Minimum Period
Maximum Frequency
10.0
ns
200
150
125
100
MHz
IOMAX
Dedicated (Hard-Wired) Array Clock Network
t
Input Low to High
HCKH
(Pad to S-Module Input)
3.7
3.7
4.1
4.1
4.7
4.7
5.5
5.5
ns
t
Input High to Low
(Pad to S-Module Input)
HCKL
ns
ns
t
t
t
t
f
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
2.4
2.4
3.2
3.2
3.8
3.8
4.8
4.8
HPWH
HPWL
HCKSW
HP
ns
0.6
0.6
0.6
0.6
ns
Minimum Period
5.0
6.8
8.0
10.0
ns
Maximum Frequency
200
150
125
100
MHz
HMAX
Routed Array Clock Networks
t
t
t
t
t
t
f
Input Low to High (FO=256)
Input High to Low (FO=256)
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
Maximum Skew (FO=128)
6.0
6.0
6.8
6.8
7.7
7.7
9.0
9.0
ns
ns
RCKH
RCKL
RPWH
RPWL
RCKSW
RP
4.1
4.1
4.5
4.5
5.4
5.4
6.1
6.1
ns
ns
1.2
1.4
1.6
90
1.8
80
ns
Minimum Period (FO=256)
Maximum Frequency (FO=256)
8.3
9.3
11.1
12.5
ns
120
105
MHz
RMAX
Clock-to-Clock Skews
t
t
I/O Clock to H-Clock Skew
0.0
2.6
0.0
2.7
0.0
2.9
0.0
3.0
ns
IOHCKSW
IORCKSW
I/O Clock to R-Clock Skew
(FO = 64)
(FO = 216)
0.0
0.0
1.7
5.0
0.0
0.0
1.7
5.0
0.0
0.0
1.7
5.0
0.0
0.0
1.7
5.0
ns
ns
t
H-Clock to R-Clock Skew
(FO = 64)
HRCKSW
0.0
0.0
1.3
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
(FO = 216)
Note:
1. Delays based on 35pF loading.
27
A14100BP Timing Characteristics
1
(Worst-Case Commercial Conditions, V
= 4.75V,
T
= 70°C)
J
CC
2
Logic Module Propagation Delays
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
Internal Array Module
Sequential Clock to Q
2.0
2.0
2.0
2.3
2.3
2.3
2.6
2.6
2.6
3.0
3.0
3.0
ns
ns
ns
PD
CO
CLR
Asynchronous Clear to Q
3
Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.2
1.4
1.7
2.8
1.0
1.4
1.6
1.9
3.2
1.1
1.6
1.8
2.2
3.6
1.3
1.8
2.1
2.5
4.2
ns
ns
ns
ns
ns
RD1
RD2
RD3
RD4
RD8
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Latch Data Input Set-Up
Latch Data Input Hold
0.5
0.0
0.5
0.0
2.4
2.4
5.0
0.6
0.0
0.6
0.0
3.2
3.2
6.8
0.8
0.5
0.8
0.5
3.8
3.8
8.0
0.8
0.5
0.8
0.5
4.8
4.8
10.0
ns
ns
SUD
HD
ns
SUD
HD
ns
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
ns
WASYN
WCLKA
A
ns
ns
200
150
125
100
MHz
MAX
Notes:
1.
2. For dual-module macros, use t + t + t
V
= 3.0V for 3.3V specifications.
CC
, t + t + t
or t + t + t
, whichever is appropriate.
SUD
PD RD1
PDn CO RD1
PDn
PD1
RD1
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
28
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
A14100BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
I/O Module Input Propagation Delays
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
t
Input Data Pad to Y
2.8
4.7
4.7
3.2
5.3
5.3
3.6
6.0
6.0
4.2
7.0
7.0
ns
ns
ns
INY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
ICKY
OCKY
ICLRY
Input Asynchronous
Clear to Y
4.7
4.7
5.3
5.3
6.0
6.0
7.0
7.0
ns
ns
t
Output Asynchronous
Clear to Y
OCLRY
1
Predicted Input Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.2
1.4
1.7
2.8
1.0
1.4
1.6
1.9
3.2
1.1
1.6
1.8
2.2
3.6
1.3
1.8
2.1
2.5
4.2
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD8
I/O Module Sequential Timing
t
t
t
t
t
t
t
t
Input F-F Data Hold
(w.r.t. IOCLK Pad)
INH
0.0
1.2
0.0
5.8
0.7
0.7
0.3
1.3
0.0
1.4
0.0
6.5
0.8
0.8
0.4
1.5
0.0
1.5
0.0
7.5
1.0
1.0
0.5
2.0
0.0
1.8
0.0
8.6
1.0
1.0
0.5
2.0
ns
ns
ns
ns
ns
ns
ns
ns
Input F-F Data Set-Up
(w.r.t. IOCLK Pad)
INSU
Input Data Enable Hold
(w.r.t. IOCLK Pad)
IDEH
Input Data Enable Set-Up
(w.r.t. IOCLK Pad)
IDESU
OUTH
OUTSU
ODEH
ODESU
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Set-Up
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Set-Up
(w.r.t. IOCLK Pad)
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
29
A14100BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
1
I/O Module – TTL Output Timing
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Min. Max. Units
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
t
t
t
Data to Pad, High Slew
Data to Pad, Low Slew
5.0
8.0
5.6
9.0
6.4
7.5
ns
ns
DHS
10.2
12.0
DLS
Enable to Pad, Z to H/L,
High Slew
ENZHS
4.0
7.4
8.0
7.4
9.5
4.5
8.3
9.0
8.3
9.5
5.1
9.4
6.0
ns
ns
ns
ns
ns
ns
t
t
t
t
t
Enable to Pad, Z to H/L,
Low Slew
ENZLS
ENHSZ
ENLSZ
CKHS
CKLS
11.0
12.0
11.0
12.0
17.0
Enable to Pad, H/L to Z,
High Slew
10.2
9.4
Enable to Pad, H/L to Z,
Low Slew
IOCLK Pad to Pad H/L,
High Slew
10.5
IOCLK Pad to Pad H/L,
Low Slew
12.8
0.02
0.05
0.04
0.05
12.8
0.02
0.05
0.04
0.05
15.3
0.03
0.06
0.04
0.06
d
d
d
d
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
0.03 ns/pF
0.07 ns/pF
0.05 ns/pF
0.07 ns/pF
TLHHS
TLHLS
THLHS
THLLS
Delta High to Low, Low Slew
1
I/O Module – CMOS Output Timing
t
t
t
Data to Pad, High Slew
Data to Pad, Low Slew
6.2
7.0
7.9
9.3
ns
ns
DHS
11.7
13.1
14.9
17.5
DLS
Enable to Pad, Z to H/L,
High Slew
ENZHS
5.2
8.9
5.9
10.0
9.0
6.6
11.3
10.0
9.4
7.8
ns
ns
ns
ns
ns
ns
t
t
t
t
t
Enable to Pad, Z to H/L,
Low Slew
ENZLS
ENHSZ
ENLSZ
CKHS
CKLS
13.3
12.0
11.0
13.8
19.3
Enable to Pad, H/L to Z,
High Slew
8.0
Enable to Pad, H/L to Z,
Low Slew
7.4
8.3
IOCLK Pad to Pad H/L,
High Slew
10.4
10.4
12.4
IOCLK Pad to Pad H/L,
Low Slew
14.5
0.04
0.07
0.03
0.04
14.5
0.04
0.08
0.03
0.04
17.4
0.05
0.09
0.03
0.04
d
d
d
d
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
0.06 ns/pF
0.11 ns/pF
0.04 ns/pF
0.05 ns/pF
TLHHS
TLHLS
THLHS
THLLS
Note:
1. Delays based on 35pF loading.
30
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
A14100BP Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Dedicated (Hard-Wired) I/O Clock Network
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
Input Low to High
IOCKH
(Pad to I/O Module Input)
2.3
2.6
3.0
3.5
ns
ns
ns
t
t
t
Minimum Pulse Width High
Minimum Pulse Width Low
2.4
2.4
3.3
3.3
3.8
3.8
4.8
4.8
IOPWH
IOPWL
IOSAPW
Minimum Asynchronous Pulse
Width
2.4
5.0
3.3
6.8
3.8
8.0
4.8
ns
ns
t
t
f
Maximum Skew
0.6
0.6
0.7
0.8
IOCKSW
Minimum Period
Maximum Frequency
10.0
ns
IOP
200
150
125
100
MHz
IOMAX
Dedicated (Hard-Wired) Array Clock Network
t
Input Low to High
HCKH
(Pad to S-Module Input)
3.7
3.7
4.1
4.1
4.7
4.7
5.5
5.5
ns
t
Input High to Low
(Pad to S-Module Input)
HCKL
ns
ns
t
t
t
t
f
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
2.4
2.4
3.3
3.3
3.8
3.8
4.8
4.8
HPWH
HPWL
HCKSW
HP
ns
0.6
0.6
0.7
0.8
ns
Minimum Period
5.0
6.8
8.0
10.0
ns
Maximum Frequency
200
150
125
100
MHz
HMAX
Routed Array Clock Networks
t
t
t
Input Low to High (FO=256)
Input High to Low (FO=256)
6.0
6.0
6.8
6.8
7.7
7.7
9.0
9.0
ns
ns
RCKH
RCKL
RPWH
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
4.1
4.1
4.5
4.5
5.4
5.4
6.1
6.1
ns
t
RPWL
ns
ns
t
t
f
Maximum Skew (FO=128)
Minimum Period (FO=256)
Maximum Frequency (FO=256)
1.2
1.4
1.6
90
1.8
80
RCKSW
8.3
9.3
11.1
12.5
ns
RP
120
105
MHz
RMAX
Clock-to-Clock Skews
t
t
I/O Clock to H-Clock Skew
0.0
2.6
0.0
2.7
0.0
2.9
0.0
3.0
ns
IOHCKSW
I/O Clock to R-Clock Skew
(FO = 64)
(FO = 350)
IORCKSW
0.0
0.0
1.7
5.0
0.0
0.0
17
5.0
0.0
0.0
1.7
5.0
0.0
0.0
1.7
5.0
ns
ns
t
H-Clock to R-Clock Skew
(FO = 64)
HRCKSW
0.0
0.0
1.3
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
(FO = 350)
Note:
1. Delays based on 35pF loading.
31
Package Pin Assignments
160-Pin PQFP (Top View)
1
2
3
4
5
6
7
8
9
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
160-Pin
PQFP
82
81
32
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
160-Pin PQFP
Pin
Number
A1460BP
Function
Pin
Number
A1460BP
Function
1
GND
90
V
V
CC
2
SDI, I/O
I/O
91
CC
5
92
I/O
9
MODE
93
I/O
10
14
15
18
19
20
24
27
28
29
40
41
43
45
46
47
49
51
53
58
59
60
62
63
74
75
76
77
78
80
81
V
98
GND
CC
I/O
99
V
CC
GND
100
103
107
109
110
111
112
113
119
120
121
124
127
136
137
138
139
140
141
142
143
145
147
149
151
153
154
160
I/O
V
GND
I/O
CC
GND
I/O
I/O
I/O
V
CC
I/O
GND
V
V
V
CC
CC
CC
I/O
GND
I/O
I/O
IOCLK, I/O
GND
I/O
I/O
I/O
V
I/O
CC
I/O
CLKA, I/O
CLKB, I/O
I/O
I/O
V
CC
I/O
GND
PRB, I/O
GND
V
CC
GND
PRA, I/O
I/O
V
CC
HCLK, I/O
GND
I/O
I/O
I/O
V
I/O
CC
I/O
I/O
I/O
I/O
I/O
V
CC
IOPCL, I/O
GND
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. NC: Denotes “No Connection”
3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.
33
Package Pin Assignments (continued)
176-Pin TQFP (Top View)
1
2
3
4
5
6
7
8
9
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-Pin
TQFP
98
97
96
95
94
93
92
91
90
89
34
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
176-Pin TQFP
Pin
Number
A1460BP
Function
Pin
Number
A1460BP
Function
1
GND
98
V
V
CC
2
SDI, I/O
MODE
99
CC
10
11
20
21
22
23
32
33
44
49
51
63
64
65
66
67
69
82
83
88
89
108
109
110
119
121
122
123
124
132
133
138
152
153
154
155
156
157
158
170
176
GND
V
V
CC
CC
I/O
GND
I/O
GND
V
I/O
CC
GND
V
CC
V
V
GND
CC
CC
V
CC
GND
I/O
IOCLK, I/O
GND
I/O
I/O
I/O
CLKA, I/O
CLKB, I/O
PRB, I/O
GND
V
CC
V
V
GND
CC
CC
V
CC
HCLK, I/O
I/O
PRA, I/O
I/O
I/O
I/O
IOPCL, I/O
GND
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. NC: Denotes “No Connection”
3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.
35
Package Pin Assignments (continued)
208-Pin PQFP, RQFP (Top View)
1
2
3
4
5
6
7
8
9
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
208-Pin
PQFP, RQFP
36
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
208-Pin PQFP, RQFP
A1460BP
Function
A14100BP
Function
A1460BP
Function
A14100BP
Function
Pin Number
Pin Number
1
2
GND
GND
115
116
129
130
131
132
145
146
147
148
156
157
158
164
180
181
182
183
184
185
186
195
201
205
208
V
V
CC
CC
SDI, I/O
MODE
SDI, I/O
MODE
NC
I/O
11
12
25
26
27
28
40
41
52
53
60
65
76
77
78
79
80
82
98
102
104
105
114
GND
GND
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
GND
GND
GND
GND
V
V
V
V
CC
CC
CC
CC
V
V
CC
CC
GND
GND
GND
NC
GND
I/O
V
V
V
V
CC
CC
CC
CC
V
V
CC
CC
GND
NC
GND
I/O
IOCLK, I/O
GND
IOCLK, I/O
GND
V
V
NC
I/O
CC
CC
NC
I/O
V
V
CC
CC
PRB, I/O
GND
PRB, I/O
GND
CLKA, I/O
CLKB, I/O
CLKA, I/O
CLKB, I/O
V
V
V
V
CC
CC
CC
CC
GND
GND
GND
GND
V
V
V
V
CC
CC
CC
CC
HCLK, I/O
HCLK, I/O
GND
GND
V
V
PRA, I/O
NC
PRA, I/O
I/O
CC
CC
NC
I/O
IOPCL, I/O
GND
IOPCL, I/O
GND
V
V
CC
CC
NC
I/O
V
V
DCLK, I/O
DCLK, I/O
CC
CC
Notes:
1. All unlisted pin numbers are user I/Os.
2. NC: Denotes “No Connection”
3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.
37
Package Pin Assignments (continued)
225-Pin BGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A1460BP
Function
Location
CLKA or I/O
CLKB or I/O
DCLK or I/O
GND
C8
B8
B2
A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15
HCLK or I/O
IOCLK or I/O
IOPCL or I/O
MODE
P9
B14
P14
D1
NC
A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14
PRA OR I/O
PRB or I/O
SDI or I/O
A7
L7
D4
V
A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13
CC
Notes:
1. Unused I/O pins are designated as outputs by ALS and are driven LOW.
2. All unassigned pins are available for use as I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.
38
Accelerator Series FPGAs: ACT 3 PCI-Compliant Family
Package Pin Assignments (continued)
313-Pin BGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
E
F
A
B
C
D
E
F
G
G
H
J
H
J
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
U
V
V
W
W
Y
Y
AA
AA
AB
AC
AB
AC
AD
AE
AD
AE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A14100BP
Function
Location
CLKA or I/O
CLKB or I/O
DCLK or I/O
GND
J13
G13
B2
A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13
HCLK or I/O
IOCLK or I/O
IOPCL or I/O
MODE
T14
B24
AD24
G3
NC
A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25,
D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7,
N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24
PRA OR I/O
PRB or I/O
SDI or I/O
H12
AD12
C1
V
AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24
CC
Notes:
1. Unused I/O pins are designated as outputs by ALS and are driven LOW.
2. All unassigned pins are available for use as I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND.
39
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
955 East Arques Avenue
Sunnyvale, California 94086
USA
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
Tel: 408.739.1010
Fax: 408.739.1540
Tel: +44.(0)1256.305600
Fax: +44.(0)1256.355420
5172121-1
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