A32100XLV-FPQB_技术文档

Discontinued – v3.0

Integrator Series FPGAs:

1200XL and 3200DX Families

Features

General Description

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel’s proprietary antifuse

technology and 0.6-micron double metal CMOS process,

Integrator Series devices offer a fine-grained, register-rich

architecture with embedded dual-port SRAM and

wide-decode circuitry.

High Capacity

• 2,500 to 30,000 Logic Gates

• Up to 3Kbits Configurable Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Up to 250 User-Programmable I/O Pins

High Performance

• 225 MHz Performance

• 5 ns Dual-Port SRAM Access

• 100 MHz FIFOs

Integrator Series’ 3200DX and 1200XL families were

designed to integrate system logic which is typically

implemented in multiple CPLDs, PALs, and FPGAs. These

devices provide the features and performance required for

today’s complex, high-speed digital logic systems. The

3200DX family offers fast dual-port SRAM for implementing

FIFOs, LIFOs, and temporary data storage. The large

number of storage elements can efficiently address

applications requiring wide datapath manipulation and

transformation functions such as telecommunications,

networking, and DSP.

• 7.5 ns 35-Bit Address Decode

Ease-of-Integration

• Synthesis-Friendly Architecture Supports ASIC Design

Methodologies.

• 95–100% Device Utilization using Automatic

Place-and-Route Tools.

• Deterministic, User-Controllable Timing Via Timing

Driven Software Tools with Up To 100% Pin Fixing.

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

Integrator Series Product Profile Family

1200XL

3200DX

Device

A1225XL

A1240XL

A1280XL

A3265DX

A32100DX

A32140DX

A32200DX

A32300DX

Capacity

Logic Gates

SRAM Bits

1

2,500

N/A

4,000

N/A

8,000

N/A

6,500

N/A

10,000

2,048

14,000

N/A

20,000

2,560

30,000

3,072

Logic Modules

Sequential

Combinatorial

Decode

231

220

N/A

348

336

N/A

624

608

N/A

510

475

20

700

662

20

954

912

24

1,230

1,184

24

1,888

1,833

28

SRAM Modules

(64x4 or 32x8)

N/A

231

2

N/A

348

2

N/A

624

2

N/A

510

2

8

N/A

954

2

10

1,230

6

12

1,888

6

Dedicated Flip-Flops

Clocks

700

6

User I/O (Maximum)

JTAG

83

104

No

140

No

126

No

152

Yes

176

Yes

202

Yes

250

Yes

No

PL84

PQ160

PQ208

TQ176

CQ84

PQ208

RQ208

RQ240

CQ208

CQ256

RQ208

RQ240

CQ256

Packages

PL84

PL84 PQ100

PQ144

TQ176

PL84

PQ160 PQ208

TQ176

PQ100

PQ160

TQ176

PQ160

PQ208

TQ176

CQ256

PQ100

VQ100

PG100

PG132

PG176 CQ172

Note: Logic gate capacity does not include SRAM bits as logic.

February 2001

1

Integrator Series FPGAs: 1200XL and 3200DX Families

Ordering Information

A1225

XL

V

–

PQ

100

C

Application (Temperature Range)

C = Commercial (0 to +70°C)

I

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

CQ = Ceramic Quad Flat Pack

PG = Ceramic Pin Grid Array

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

RQ = Plastic Power Quad Flat Pack

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

Speed Grade

Blank = Standard Speed

1 = Approximately 15% Faster than Standard

2 = Approximately 25% Faster than Standard

3 = Approximately 35% Faster than Standard

F = Approximately 30% Slower than Standard

Operating Voltage

V = 3.3 Volt

Blank = 5.0 Volt

Die Revision

XL = 1200XL Family

DX = 3200DX Family

Part Number

A1225

=

2500 Gates

4000 Gates

6500 Gates

8000 Gates

10000 Gates

14000 Gates

20000 Gates

30000 Gates

A1240

A3265

A1280

A32100

A32140

A32200

A32300

Note: This family has been discontinued.

2

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Product Plan

Speed Grade*

Application

–F

Std

–1

–2

–3

C

I

M

B

A1225XL Device

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

100-Pin Ceramic Pin Grid Array (CPGA)

A1225XLV Device

✔

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A1240XL Device

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

132-Pin Ceramic Pin Grid Array (CPGA)

144-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A1240XLV Device

✔

—

✔

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A3265DX Device

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

160-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A3265DXV Device

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A1280XL Device

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

160-Pin Plastic Quad Flat Pack (PQFP)

172-Pin Ceramic Quad Flat Pack (CQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

176-Pin Ceramic Pin Grid Array (CPGA)

208-Pin Plastic Quad Flat Pack (PQFP)

A1280XLV Device

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A32100DX Device

—

✔

—

✔

—

84-Pin Ceramic Quad Flat Pack (CQFP)

—

✔

—

✔

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

160-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

Contact your Actel sales representative for product availability.

Applications:

C

I

=

Commercial

Industrial

Military

Availability:

✔

P

=

Available

Planned

*Speed Grade:

–1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35% faster than Standard

–F = Approx. 40% slower than Standard

M

— = Not Planned

† Only Std, –1, –2 Speed Grade

• Only Std, –1 Speed Grade

Discontinued – v3.0

3

Integrator Series FPGAs: 1200XL and 3200DX Families

Product Plan (Continued)

Speed Grade*

Application

–F

Std

–1

–2

–3

C

I

M

B

176-Pin Thin Plastic Quad Flat Pack (TQFP)

✔

—

A32100DXV Device

84-Pin Plastic Leaded Chip Carrier (PLCC)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A32140DX Device

—

✔

—

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

160-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

256-Pin Ceramic Quad Flat Pack (CQFP)

A32140DXV Device

✔

—

✔

—

✔

—

✔

—

✔

84-Pin Plastic Leaded Chip Carrier (PLCC)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A32200DX Device

—

✔

—

✔

—

208-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Plastic Power Quad Flat Pack (RQFP)

240-Pin Plastic Power Quad Flat Pack (RQFP)

208-Pin Ceramic Quad Flat Pack (CQFP)

256-Pin Ceramic Quad Flat Pack (CQFP)

A32200DXV Device

✔

—

✔

—

✔

—

✔

—

✔

—

✔

208-Pin Plastic Quad Flat Pack (PQFP)

240-Pin Plastic Power Quad Flat Pack (RQFP)

A32300DX Device

—

✔

—

✔

—

208-Pin Plastic Power Quad Flat Pack (RQFP)

240-Pin Plastic Power Quad Flat Pack (RQFP)

256-Pin Ceramic Quad Flat Pack (CQFP)

A32300DXV Device

✔

—

✔

—

✔

—

✔

—

✔

—

✔

208-Pin Plastic Power Quad Flat Pack (RQFP)

—

✔

—

✔

—

240-Pin Plastic Power Quad Flat Pack (RQFP)

Contact your Actel sales representative for product availability.

Applications:

C

I

=

Commercial

Industrial

Military

Availability:

✔

P

=

Available

Planned

*Speed Grade:

–1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35% faster than Standard

–F = Approx. 40% slower than Standard

M

— = Not Planned

† Only Std, –1, –2 Speed Grade

• Only Std, –1 Speed Grade

4

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Development Tool Support

18-channel logic analyzer. Silicon Explorer II allows

designers to complete the design verification process at

their desks and reduces verification time from several hours

per cycle to only a few seconds.

The devices are fully supported by Actel’s line of FPGA

development tools, including the Actel DeskTOP series and

Designer Advantage tools. The Actel DeskTOP series is an

integrated design environment for PCs that includes design

entry, simulation, synthesis, and place and route tools.

Designer Advantage, Actel’s suite of FPGA development

point tools for PCs and Workstations, includes the ACTgen

Macro Builder, timing-driven place and route and analysis

tools, and device programming software.

Integrator Series Architectural

Overview

The 1200XL and 3200DX architecture is composed of

fine-grained building blocks which produce fast, efficient

logic designs. All devices within the Integrator Series are

composed of logic modules, routing resources, clock

networks, and I/O modules which are the building blocks to

design fast logic designs. In addition, a subset of devices

contain embedded dual-port SRAM and wide-decode

modules. The dual-port SRAM modules are optimized for

high-speed datapath functions such as FIFOs, LIFOs, and

scratchpad memory. The “Integrator Series Product Profile

Family” on page 1 lists the specific logic resources

contained within each device.

In addition, the devices contain ActionProbe circuitry that

provides built-in access to every node in a design, enabling

100 percent real-time observation and analysis of a device's

internal logic nodes without design iteration. The probe

circuitry is accessed by Silicon Explorer II, an easy-to-use

integrated verification and logic analysis tool that can

sample data at 100 MHz (asynchronous) or 66 MHz

(synchronous). Silicon Explorer II attaches to a PC’s

standard COM port, turning the PC into a fully functional

Plastic Device Resources

User I/Os

PQFP 144-Pin PQFP 160-Pin PQFP 208-Pin

PQFP

RQFP

Device

A1225XL

PLCC 84-Pin VQFP 100-Pin

TQFP 176-Pin

100-Pin

240-Pin

72

—

83

—

83

—

104

—

103

126

140

142

150

—

A1240XL

A3265DX

A1280XL

125

—

140

152

176

176*

176

—

A32100DX

A32140DX

A32200DX

A32300DX

—

202

—

Package Definitions (Consult your local Actel Sales Representative for product availability.)

PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array, VQFP = Very Thin Quad Flat

Pack, RQFP = Plastic Power Quad Flat Pack

* Also available in RQFP 208-pin.

Hermetic Device Resources

User I/Os

CPGA

176-Pin

CQFP

84-Pin

CQFP

172-Pin

CQFP

208-Pin

CQFP

256-Pin

Device

A1280XL

140

—

60

—

140

—

A32100DX

A32140DX

A32200DX

A32300DX

—

176

202

212

—

176

—

Package Definitions (Consult your local Actel Sales Representative for product availability.)

CPGA = Ceramic Pin Grid Array, CQFP = Ceramic Quad Flat Pack

Discontinued – v3.0

5

Integrator Series FPGAs: 1200XL and 3200DX Families

Logic Modules

either a D-type flip-flop or a transparent latch. To increase

3200DX and 1200XL devices contain three types of logic

modules: combinatorial (C-modules), sequential

flexibility, the S-module register can be bypassed so that it

implements purely combinatorial logic.

(S-modules), and decode (D-modules). 1200XL devices

contain only the C-module and S-module, while the 3200DX

devices contain D-modules and dual-port SRAM modules in

addition to the S-module and C-module.

A0

B0

S0

The C-module is shown in Figure 1 and implements the

following function:

D00

Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11

D01

Y

where:

D10

D11

S0=A0*B0

S1=A1+B1

S1

The S-module shown in Figure 2 is designed to implement

high-speed sequential functions within a single logic

module. The S-module implements the same combinatorial

logic function as the C-module while adding a sequential

element. The sequential element can be configured as

A1

B1

Figure 1 • C-Module Implementation

D00

D01

D00

D01

OUT

Y

D

Q

Y

D

Q

D10

S0

D11

S1

D11

S1

S0

GATE

CLR

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D00

D01

D0

Y

OUT

Y

D

Q

D10

S0

D1

D11

S1

GATE

S

CLR

Up to 8-Input Function (Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 2 • S-Module Implementation

6

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX devices contain a third type of logic module,

D-modules, which are arranged around the periphery of the

device. D-modules contain wide-decode circuitry which

provides a fast, wide-input AND function similar to that

found in product term architectures (Figure 3). The

D-module allows 3200DX devices to perform wide-decode

functions at speeds comparable CPLDs and PAL devices.

The output of the D-module has a programmable inverter

for active HIGH or LOW assertion. The D-module output is

hard-wired to an output pin or can be fed back into the

array to be incorporated into other logic.

modules can be cascaded together to form memory spaces

of user-definable width and depth. A block diagram of the

3200DX dual-port SRAM block is shown in Figure 4.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

Dual-Port SRAM Modules

Several 3200DX devices contain dual-port SRAM modules

that have been optimized for synchronous or asynchronous

applications. The SRAM modules are arranged in 256-bit

blocks which can be configured as 32x8 or 64x4 (refer to

“Integrator Series Product Profile Family” on page 1 for the

number of SRAM blocks within a particular device). SRAM

Feedback to Array

Figure 3 • D-Module Implementation

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 Bits)

WRAD[5:0]

[5:0]

Read

Logic

Latches

REN

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 4 • 3200DX Dual-Port SRAM Block

The 3200DX SRAM modules are true dual-port structures

containing independent READ and WRITE ports. Each

SRAM module contains six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM block contain independent

clocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The SRAM

block contains eight data inputs (WD[7:0]) and eight

outputs (RD[7:0]) which are connected to segmented

vertical routing tracks.

The 3200DX dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring fast

FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory functions,

Discontinued – v3.0

7

Integrator Series FPGAs: 1200XL and 3200DX Families

such as FIFOs, LIFOs, and RAM arrays. Additionally, unused

SRAM blocks can be used to implement registers for other

logic within the design.

be joined together at the ends using antifuses to increase

their lengths up to the full length of the track. All

interconnects can be accomplished with a maximum of four

antifuses.

I/O Modules

Horizontal Routing

The I/O modules provide the interface between the device

pins and the logic array. Figure 5 is a block diagram of the

I/O module. A variety of user functions, determined by a

library macro selection, can be implemented in the module

(refer to the Macro Library Guide for more information). I/O

modules contain a tri-state buffer, input and output latches

which can be configured for input, output, or bi-directional

pins (Figure 5).

Horizontal channels are located between the rows of

modules and are composed of several routing tracks. The

horizontal routing tracks within the channel are divided

into one or more segments. The minimum horizontal

segment length is the width of a module pair, and the

maximum horizontal segment length is the full length of the

channel. Any segment that spans more than one-third the

row length is considered a long horizontal segment. A

typical channel is shown in Figure 6. Non-dedicated

horizontal routing tracks are used to route signal nets;

dedicated routing tracks are used for the global clock

networks and for power and ground tie-off tracks.

EN

Q

D

Vertical Routing

PAD

From Array

Another set of routing tracks run vertically through the

module. Vertical tracks are of three types: input, output, and

long, and are divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module; each segment in an output track is

dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

routing. Each output segment spans four channels (two

above and two below), except near the top and bottom of the

array where edge effects occur. Long Vertical Tracks contain

either one or two segments. An example of vertical routing

tracks and segments is shown in Figure 6.

G/CLK*

Q

D

To Array

G/CLK*

* Can be Configured as a Latch or D Flip-Flop

(Using C-Module)

Figure 5 • I/O Module

Segmented

Logic

Horizontal

Modules

The Integrator Series devices contain flexible I/O structures

where each output pin has a dedicated output enable

control. The I/O module can be used to latch input and/or

output data, providing a fast set-up time. In addition, the

Actel Designer Series software tools can build a D-type

flip-flop using a C-module to register input and/or output

signals.

Routing

Tracks

Antifuses

Actel’s Designer Series development tools provide a design

library of I/O macrofunctions which can implement all I/O

configurations supported by the Integrator Series FPGAs.

Vertical Routing Tracks

Routing Structure

Figure 6 • Routing Structure

The Integrator Series architecture uses vertical and

horizontal routing tracks to interconnect the various logic

and I/O modules. These routing tracks are metal

interconnects that may either be of continuous length or

broken into pieces called segments. Varying segment

lengths allows interconnection of over 90% of design tracks

to occur with only two antifuse connections. Segments can

Antifuse Structure

An antifuse is a “normally open” structure as opposed to the

normally closed fuse structure used in PROMs or PALs. The

use of antifuses to implement a programmable logic device

results in highly-testable structures as well as efficient

8

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

programming algorithms. The structure is highly testable

because there are no pre-existing connections; therefore,

temporary connections can be made using pass transistors.

These temporary connections can isolate individual

CLKB

CLKA

CLKINB

CLKINA

antifuses to be programmed and individual circuit

structures to be tested, which can be done before and after

programming. For example, all metal tracks can be tested

for continuity and shorts between adjacent tracks, and the

functionality of all logic modules can be verified.

From

Pads

S0

S1

Internal

Signal

CLKMOD

CLKO(17)

CLKO(16)

CLKO(15)

Clock

Drivers

Clock Networks

Two low-skew, high-fanout clock distribution networks are

provided in each 3200DX device. These networks are

referred to as CLK0 and CLK1. Each network has a clock

module (CLKMOD) that selects the source of the clock

signal and may be driven as follows:

CLKO(2)

CLKO(1)

1. Externally from the CLKA pad

2. Externally from the CLKB pad

3. Internally from the CLKINA input

4. Internally from the CLKINB input

Clock Tracks

The clock modules are located in the top row of I/O

modules. Clock drivers and a dedicated horizontal clock

track are located in each horizontal routing channel.

Figure 7 • Clock Networks

IEEE Standard 1149.1 Boundary Scan Testing (BST)

The user controls the clock module by selecting one of two

clock macros from the macro library. The macro CLKBUF is

used to connect one of the two external clock pins to a clock

network, and the macro CLKINT is used to connect an

internally-generated clock signal to a clock network. Since

both clock networks are identical, the user does not care

whether CLK0 or CLK1 is being used. The clock input pads

may also be used as normal I/Os, bypassing the clock

networks (see Figure 7).

IEEE Standard 1149.1 defines a four-pin Test Access Port

(TAP) interface for testing integrated circuits in a system.

The 3200DX family provides five BST pins: Test Data In

(TDI), Test Data Out (TDO), Test Clock (TCK), and Test

Mode Select Test Reset (TRST) (3200DX24A only). Devices

are configured in a test “chain” where BST data can be

transmitted serially between devices via TDO-to-TDI

interconnections. The TMS and TCK signals are shared

among all devices in the test chain so that all components

operate in the same state.

The 3200DX devices which contain SRAM modules (all

except A3265DX and A32140DX) have four additional

register control resources, called quadrant clock networks

(Figure 8 on page 10). Each quadrant clock provides a local,

high-fanout resource to the contiguous logic modules within

its quadrant of the device. Quadrant clock signals can

originate from specific I/O pins or from the internal array

and can be used as a secondary register clock, register

clear, or output enable.

The 3200DX family implements a subset of the IEEE

Standard 1149.1 BST instruction in addition to a private

instruction, which allows the use of Actel’s ActionProbe

facility with BST. Refer to the IEEE Standard 1149.1

specification for detailed information regarding BST.

Boundary Scan Circuitry

The 3200DX boundary scan circuitry consists of a Test

Access Port (TAP) controller, test instruction register, a

JPROBE register, a bypass register, and a boundary scan

register. Figure 9 on page 10 shows a block diagram of the

3200DX boundary scan circuitry.

Test Circuitry

All devices contain Actel’s ActionProbe test circuitry which

test and debug a design once it is programmed into a device.

Once a device has been programmed, the ActionProbe test

circuitry allows the designer to probe any internal node

during device operation to aid in debugging a design. In

addition, 3200DX devices contain IEEE Standard 1149.1

boundary scan test circuitry.

When a device is operating in BST mode, four I/O pins are

used for the TDI, TDO, TMS, and TCK signals. An active

reset (nTRST) pin is not supported; however, the 3200DX

device contain power-on circuitry that resets the boundary

scan circuitry upon power-up. Table 1 on page 11

summarizes the functions of the IEEE 1149.1 BST signals.

Discontinued – v3.0

9

Integrator Series FPGAs: 1200XL and 3200DX Families

QCLKA

QCLKC

Quad

Clock

Module

Quad

Clock

Module

QCLK1

QCLK3

QCLKB

QCLKD

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Quad

Clock

QCLK2

QCLK4

Module

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 8 • Quadrant Clock Network

JPROBE Register

Boundary Scan Register

Output

MUX

TDO

Bypass

Register

Control Logic

JTAG

TMS

Instruction

Decode

TAP Controller

TCK

JTAG

Instruction

Register

TDI

Figure 9 • 3200DX IEEE 1149.1 Boundary Scan Circuitry

10

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Table 1 • IEEE 1149.1 BST Signals

Table 2 • BST Instructions

Signal

Name

Function

Test Mode

Code

Description

Serial data input for BST instructions and

data. Data is shifted in on the rising edge

of TCK.

Allows the external circuitry and

board-level interconnections to be tested

by forcing a test pattern at the output pins

and capturing test results at the input

pins.

TDI

Test Data In

EXTEST

000

Serial data output for BST instructions

and test data.

TDO

TMS

TCK

Test Data Out

Test Mode Select

Test Clock

Allows a snapshot of the signals at the

device pins to be captured and examined

during device operation.

SAMPLE/

PRELOAD

Serial data input for BST mode. Data is

shifted in on the rising edge of TCK.

001

011

100

Clock signal to shift the BST data into

the device.

A private instruction allowing the user to

connect Actel’s Micro Probe registers to

the test chain.

JPROBE

JTAG

Allows the user to build

application-specific instructions such as

RAM READ and RAM WRITE.

USER

INSTRUCTION

All 3200DX devices are IEEE 1149.1 (JTAG) compliant.

3200DX devices offer superior diagnostic and testing

capabilities by providing JTAG and probing capabilites.

These functions are controlled through the special JTAG

pins in conjunction with the program fuse.

Refer to the IEEE Standard 1149.1

specification.

HIGH Z

CLAMP

101

110

Refer to the IEEE Standard 1149.1

specification.

Enables the bypass register between the

TDI and TDO pins. The test data passes

through the selected device to adjacent

devices in the test chain.

JTAG fuse programmed:

BYPASS

111

• TCK must be terminated—logical high or low doesn’t

matter (to avoid floating input)

JTAG BST Instructions

• TDI, TMS may float or at logical high (internal pull-up is

present)

JTAG BST testing within the 3200DX devices is controlled

by a Test Access Port (TAP) state machine. The TAP

controller drives the three-bit instruction register, a bypass

register, and the boundary scan data registers within the

device. The TAP controller uses the TMS signal to control

the JTAG testing of the device. The JTAG test mode is

determined by the bitstream entered on the TMS pin. The

table in the next column describes the JTAG instructions

supported by the 3200DX.

• TDO may float or connect to TDI of another device (it’s an

output)

JTAG fuse not programmed:

• TCK, TDI, TDO, TMS are user I/O. If not used, they will be

configured as tristated output.

BST Instructions

Boundary scan testing within the 3200DX devices is

controlled by a Test Access Port (TAP) state machine. The

TAP controller drives the three-bit instruction register, a

bypass register, and the boundary scan data registers within

the device. The TAP controller uses the TMS signal to

control the testing of the device. The BST mode is

determined by the bitstream entered on the TMS pin.

Table 2 describes the test instructions supported by the

3200DX devices.

Design Tool Support ActionProbe

If a device has been successfully programmed and the

security fuse has not been programmed, any internal logic

or I/O module output can be observed in real time using the

ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s

Silicon Explorer diagnostic and debug tool kit.

Reset

The TMS pin is equipped with an internal pull-up resistor.

This allows the TAP controller to remain in or return to the

Test-Logic-Reset state when there is no input or when a

logical 1 is on the TMS pin. To reset the controller, TMS

must be HIGH for at least five TCK cycles.

When a device is operating in BST mode, four I/O pins are

used for the TDI, TDO, TMS, and TCLK signals. An active

reset (nTRST) pin is not supported; however, the 3200DX

contains power-on circuitry which automatically resets the

BST circuitry upon power-up. The following table

summarizes the functions of the BST signals.

Discontinued – v3.0

11

Integrator Series FPGAs: 1200XL and 3200DX Families

5.0V Operating Conditions

Recommended Operating Conditions

Parameter

Commercial

Industrial

Military

Units

1

Absolute Maximum Ratings

Temperature

Range

1

0 to +70

±5

–40 to +85

±10

–55 to +125

±10

°C

Free Air Temperature Range

Power Supply

Tolerance

Symbol

Parameter

Limits

Units

%V

CC

V

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

CC

Note:

2

1. Ambient temperature (T_A) is used for commercial and

industrial; case temperature (T_C) is used for military.

V

–0.5 to V +0.5

CC

I

Output Voltage

–0.5 to V +0.5

CC

V

O

T

Storage Temperature

–65 to +150

°C

STG

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Device should not be

operated outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V_CC+ 0.5V or less than GND – 0.5V, the internal protection

diode will be forward biased and can draw excessive current.

Electrical Specifications

Commercial

Commercial –F

Industrial

Max.

Military

Max.

Units

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

1

V

(I = –10 mA)

2.4

V

OH

(I = –6 mA)

3.84

OH

(I = –4 mA)

3.7

V

OH

1

(I = 10 mA)

0.5

0.33

0.8

0.5

0.33

0.8

V

OL

(I = 6 mA)

0.40

0.8

0.40

0.8

V

OL

V

–0.3

2.0

–0.3

2.0

–0.3

2.0

–0.3

2.0

V

IL

V

+ 0.3

V

+ 0.3

V

+ 0.3

V + 0.3

CC

V

IH

CC

Input Transition Time t , t

R

500

10

500

10

500

10

500

10

ns

pF

mA

F

2

C

I/O Capacitance

IO

3

Standby Current, I

(typical = 1 mA)

2.0

20

10

20

CC

I

Dynamic V Supply Current

CC

See the “Power Dissipation” section on page 14.

Can be converted from IBIS model on the web.

CC(D)

4

IV Curve

Notes:

1. Only one output tested at a time. V_CC= min.

2. Includes worst-case 176 CPGA package capacitance. V_OUT= 0 V, f = 1 MHz.

3. All outputs unloaded. All inputs = V_CCor GND, typical I_CC= 1 mA. I_CClimit includes I_PPand I_SVduring normal operation.

4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

12

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

3.3V Operating Conditions

Recommended Operating Conditions

Parameter

Commercial

Units

1

Absolute Maximum Ratings

1

Temperature Range

0 to +70

±5

°C

Free Air Temperature Range

Power Supply Tolerance

%V

Note:

Symbol

Parameter

Limits

Units

1. Ambient temperature (T_A) is used for commercial.

V

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

CC

2

I

–0.5 to V +0.5

CC

Output Voltage

–0.5 to V +0.5

CC

V

O

T

Storage Temperature

–65 to +150

°C

STG

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Device should not be

operated outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V_CC+ 0.5V or less than GND – 0.5V, the internal protection

diodes will forward bias and can draw excessive current.

Electrical Specifications

Commercial

Parameter

Units

Min.

Max.

(I = –4 mA)

2.15

2.4

V

OH

1

V

OH

(I = –3.2 mA)

OH

1

V

(I = 6 mA)

0.4

0.8

V

OL

–0.3

2.0

V

IL

V

+ 0.3

V

IH

CC

2

Input Transition Time t , t

R

500

10

ns

pF

mA

F

2, 3

C

I/O Capacitance

IO

4

Standby Current, I

(typical = 0.3 mA)

0.75

CC

I

Dynamic V Supply Current

CC

See the “Power Dissipation” section on page 14.

Can be converted from IBIS model on the web.

CC(D)

4

IV Curve

Notes:

1. Only one output tested at a time. V_CC= min.

2. Includes worst-case 84-pin PLCC package capacitance. V_OUT= 0 V, f = 1 MHz.

3. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = V_CCor GND.

4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.

Discontinued – v3.0

13

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Thermal Characteristics

Maximum junction temperature is 150°C.

The device junction to case thermal characteristic is θ_jc,

and the junction to ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different

air flow rates.

A sample calculation of the absolute maximum power

dissipation allowed for a PQFP 160-pin package with still air

at commercial temperature is as follows:

Max. junction temp. (°C) – Max. commercial temp.

150°C – 70°C

---------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 2 . 4 W

θ_ja(°C/W)

34°C/W

θ

Maximum Power Dissipation

ja

Pin Count

Package Type

Still Air

300 ft/min

Still Air

300 ft/min

Plastic Quad Flat Pack

Plastic Leaded Chip Carrier

Thin Quad Flat Pack

100

144

160

208

84

42°C/W

36°C/W

34°C/W

25°C/W

37°C/W

32°C/W

16.8°C/W

16.1°C/W

43°C/W

33°C/W

29°C/W

27°C/W

16.2°C/W

28°C/W

25°C/W

11.4°C/W

10.6°C/W

35°C/W

1.9 W

2.2 W

2.4 W

3.2 W

2.2 W

2.5 W

4.8 W

5.0 W

1.9 W

2.4 W

2.8 W

3.0 W

4.9 W

2.9 W

3.2 W

7.0 W

7.5 W

2.3 W

176

208

240

100

Power Quad Flat Pack

Very Thin Quad Flat Pack

Power Dissipation

The power dissipation due to standby current is typically a

small component of the overall power. Standby power is

calculated below for commercial worst case conditions.

General Power Equation

P = [I_CCstandby + I_CCactive] * V_CC+ I_OL* V_OL* N

+ I_OH* (V_CC– V_OH) * M

I_CC

V_CC

Power

2 mA

5.25 V

10.5 mW

where:

The static power dissipation by TTL loads depends on the

number of outputs driving HIGH or LOW and the DC load

current. Again, this number is typically small. For instance,

a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with

all outputs driving LOW and 140 mW with all outputs driving

HIGH. The actual dissipation will average somewhere in

between as I/Os switch states with time.

I_CCstandby is the current flowing when no inputs or

outputs are changing.

I_CCactive is the current flowing due to CMOS switching.

I_OL, I_OHare TTL sink/source currents.

V_OL, V_OHare TTL level output voltages.

N equals the number of outputs driving TTL loads to V_OL

.

Active Power Component

M equals the number of outputs driving TTL loads to V_OH

.

Power dissipation in CMOS devices is usually dominated by

the active (dynamic) power dissipation. This component is

frequency-dependent, a function of the logic and the

external I/O. Active power dissipation results from charging

internal chip capacitances of the interconnect,

unprogrammed antifuses, module inputs, and module

outputs, plus external capacitance due to PC board traces

and load device inputs. An additional component of the

active power dissipation is the totem pole current in the

CMOS transistor pairs. The net effect can be associated with

an equivalent capacitance that can be combined with

frequency and voltage to represent active power dissipation.

An accurate determination of N and M is problematic

because their values depend on the family type, design

details, and on the system I/O. The power can be divided

into two components: static and active.

Static Power Component

Actel FPGAs have small static power components that

result in lower power dissipation than PALs or PLDs. By

integrating multiple PALs/PLDs into one FPGA, an even

greater reduction in board-level power dissipation can

be achieved.

14

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Equivalent Capacitance

f_p

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

= Average second routed array clock rate in MHz

The power dissipated by a CMOS circuit can be expressed by

f_q1

Equation 1

f_q2

Power (µW) = C_EQ* V_CC²* F

(1)

Fixed Capacitance Values for Actel FPGAs

(pF)

where:

C_EQis the equivalent capacitance expressed in picofarads

(pF).

Table 5.

V_CCis power supply in volts (V).

r₁

routed_Clk1

106

r₂

routed_Clk2

106

Device Type

A1225XL

A1240XL

A3265DX

A1280XL

A32100DX

A32140DX

A32200DX

A32300DX

F is the switching frequency in megahertz (MHz).

Equivalent capacitance is calculated by measuring I_CCactive

at a specified frequency and voltage for each circuit

component of interest. Measurements have been made over

a range of frequencies at a fixed value of V_CC. Equivalent

capacitance is frequency-independent, so the results may

be used over a wide range of operating conditions.

Equivalent capacitance values are shown below.

134

158

168

178

190

230

285

134

158

168

178

190

230

285

C

Values for Actel FPGAs

EQ

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

)

5.2

11.6

23.8

3.5

Determining Average Switching Frequency

To determine the switching frequency for a design, the user

must have a detailed understanding of the data input values

to the circuit. The following guidelines represent worst-case

scenarios; they can be generally used to predict the upper

limits of power dissipation.

)

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic

must be known. Equation 2 shows a piece-wise linear

summation over all components.

Logic Modules (m)

=

80% of

Combinatorial

Modules

Power = V_CC²* [(m x C_EQM* f_m)_Modules

(n * C_EQI* f_n)_Inputs+ (p * (C_EQO+ C_L) * f_p)_outputs

0.5 * (q₁* C_EQCR* f_q1)_{routed_Clk1}+ (r₁* f_q1)_{routed_Clk1}

+

Inputs Switching (n)

Outputs Switching (p)

=

# of Inputs/4

# Outputs/4

+

0.5 * (q₂* C_EQCR* f_q2)_{routed_Clk2}+ (r₂* f_q2)_{routed_Clk2}(2)

First Routed Array Clock Loads

(q₁)

40% of Sequential

Modules

where:

m

n

p

= Number of logic modules switching at frequency f_m

= Number of input buffers switching at frequency f_n

= Number of output buffers switching at frequency f_p

Second Routed Array Clock

Loads (q₂)

=

40% of Sequential

Modules

Load Capacitance (C_L)

=

35 pF

F/10

q₁

= Number of clock loads on the first routed array

clock

Average Logic Module Switching

Rate (f_m)

q₂

= Number of clock loads on the second routed array

clock

Average Input Switching Rate

(f_n)

=

F/5

F/10

F

r₁

r₂

= lFixed capacitance due to first routed array clock

= Fixed capacitance due to second routed array

clock

Average Output Switching Rate

(f_p)

Average First Routed Array

Clock Rate (f_q1)

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

C_EQCR= Equivalent capacitance of routed array clock in pF

Average Second Routed Array

Clock Rate (f_q2)

F/2

C_L

f_m

f_n

= Output load capacitance in p

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

Discontinued – v3.0

15

Integrator Series FPGAs: 1200XL and 3200DX Families

1200XL Timing Model*

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

Combinatorial

Logic Module

I/O Module

t

_INYL= 1.3 ns

t_IRD2= 3.2 ns†

t

_DLH= 3.8 ns

t_RD1= 0.8 ns

t_RD2= 1.3 ns

t_RD4= 2.0 ns

D

Q

t

_PD= 2.6 ns

t

_RD8= 3.2 ns

I/O Module

t_DLH= 3.8 ns

G

Sequential

Logic Module

t_INH= 0.0 ns

t_INSU= 0.3 ns

t_INGL= 2.6 ns

Combin-

atorial

D

G

Q

Logic

included

in t_SUD

t_RD1= 0.8 ns

t_ENHZ= 5.4 ns

t_OUTH= 0.0 ns

t_OUTSU= 0.3 ns

t

_CO= 2.6 ns

t_SUD= 0.4 ns

_HD= 0.0 ns

Array

Clocks

t

_GLH= 4.2 ns

t

t_CKH= 5.7 ns

FO = 256

F_MAX= 225 MHz

t_LCO= 10.7 ns (64 loads, pad-pad)

Notes:

1. *Values shown for A1225XL-2 at worst-case commercial conditions.†

2. Input Module Predicted Routing Delay

16

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX Timing Model (Logic Functions using Array Clocks)*

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

_INPY= 1.2 ns

t

t_IRD1= 2.7 ns

Combinatorial

Module

t

_DLH= 3.2 ns

t_RD1= 0.3 ns

t_RD2= 0.7 ns

t_RD4= 1.2 ns

D

Q

t_PD= 2.1 ns

G

Decode

Module

t_INH= 0.0 ns

t_INSU= 0.4 ns

t_INGO= 2.8 ns

t

_RDD= 0.4 ns

I/O Module

t_PDD= 2.1 ns

t_DLH= 3.2 ns

Sequential

Logic Module

t

_RD1= 0.3 ns

Combin-

D

G

Q

atorial

Logic

included

in t_SUD

t_ENHZ= 7.1 ns

t_LH= 0.0 ns

t_LSU= 0.4 ns

t_CO= 2.0 ns

t_SUD= 0.3 ns

_HD= 0.0 ns

t

_GHL= 6.5 ns

t

Array

Clocks

t_CKH= 5.3 ns

F_MAX= 173 MHz

*Values shown for A3265DX-2 at worst-case commercial conditions.

Discontinued – v3.0

17

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX Timing Model (Logic Functions using Quadrant Clocks)*

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

_INPY= 1.4 ns

t

t_IRD1= 1.9 ns

Combinatorial

Module

t

_DLH= 3.7 ns

t_RD1= 1.1 ns

t_RD2= 1.7 ns

t_RD4= 2.6 ns

D

Q

t_PD= 2.0 ns

G

Decode

Module

t_INH= 0.0 ns

t_INSU= 0.45 ns

t_INGO= 3.3 ns

t

_RDD= 0.3 ns

I/O Module

t_PDD= 2.5 ns

t_DLH= 3.7 ns

Sequential

Logic Module

t

_RD1= 1.1 ns

Combin-

D

G

Q

atorial

Logic

included

in t_SUD

t_ENHZ= 8.3 ns

t_LH= 0.0 ns

t_LSU= 0.26 ns

t_CO= 2.3 ns

t_SUD= 0.3 ns

_HD= 0.0 ns

t

_GHL= 8.9 ns

t

Quadrant

Clocks

t

_CKH= 5.3 ns**

F_MAX= 165 MHz

* Preliminary values shown for A32200DX-3 at worst-case commercial conditions.

** Load-dependent.

18

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX Timing Model (SRAM Functions)*

Input Delays

I/O Module

t

_INPY= 1.4 ns

t_IRD1= 1.9 ns

D

Q

G

Predicted

Routing

Delays

I/O Module

_DLH= 3.7 ns

t_INSU= 0.45 ns

t_INH= 0.05 ns

t_INGO= 3.3 ns

t

RD [7:0]

RDAD [5:0]

REN

WD [7:0]

t_RD1= 1.1 ns

WRAD [5:0]

BLKEN

D

G

Q

WEN

WCLK

RCLK

t_ADSU= 1.5 ns

t_ADH= 0.0 ns

t_RENSUA= 0.6 ns

t

_ADSU= 1.5 ns

t_ADH= 0.0 ns

t_GHL= 8.9 ns

_LSU= 0.26 ns

t_LH= 0.0 ns

t

ARRAY

CLOCKS

t_WENSU= 2.6 ns

t_BENS= 2.6 ns

t_RCO= 3.2 ns

F

_MAX= 165 MHz

*Values shown for A32200DX-3 at worst-case commercial conditions.

Discontinued – v3.0

19

Integrator Series FPGAs: 1200XL and 3200DX Families

Parameter Measurement

Output Buffer Delays

E

D

PAD To AC test loads (shown below)

TRIBUFF

In

50%

V_OH

E

50%

E

50%

V_CC

50%

V_OH

50%

1.5V

V_OL

90%

PAD

V_OL

PAD

GND

1.5V

10%

1.5V

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_ENHZ

AC Test Loads

Load 1

Load 2

(Used to measure propagation delay)

(Used to measure rising/falling edges)

V_CC

GND

To the output under test

35 pF

R to V_CCfor t_PLZ/t_PZL

R to GND for t_PHZ/t_PZH

R = 1 k¾

To the output under test

35 pF

Input Buffer Delays

Module Delays

S

A

B

Y

PAD

INBUF

S, A or B

Y

50% 50%

3V

50%

PAD

0V

50%

1.5V

V_CC

1.5V

t_PLH

t_PHL

Y

GND

50%

t_PHL

50%

t_PLH

t_INYH

t_INYL

20

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Sequential Module Timing Characteristics

Flip-Flops and Latches

D

E

CLK

Y

PRE

CLR

(Positive Edge Triggered)

t_HD

D¹

t_A

t_WCLKA

t_SUD

G, CLK

t_SUENA

t_WCLKI

t_HENA

E

t_CO

Q

t_RS

PRE, CLR

t_WASYN

Note:

D represents all data functions involving A, B, and S for multiplexed flip-flops.

Discontinued – v3.0

21

Integrator Series FPGAs: 1200XL and 3200DX Families

Sequential Timing Characteristics (continued)

Input Buffer Latches

PAD

DATA

IBDL

G

CLK

PAD

CLKBUF

DATA

G

t_INH

t_INSU

t_HEXT

CLK

t_SUEXT

Output Buffer Latches

D

G

PAD

OBDLHS

D

G

t_OUTSU

t_OUTH

22

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Decode Module Timing

A

B

C

D

E

Y

H

F

G

V_CC

A–G, H

50%

V_CC

Y

t_PHL

t_PLH

SRAM Timing Characteristics

Read Port

Write Port

WRAD [5:0]

BLKEN

WEN

RDAD [5:0]

LEW

RAM Array

32x8 or 64x4

(256 Bits)

REN

WCLK

RCLK

WD [7:0]

RD [7:0]

Discontinued – v3.0

23

Integrator Series FPGAs: 1200XL and 3200DX Families

Dual-Port SRAM Timing Waveforms

3200DX SRAM Write Operation

t_RCKHL

WCLK

t_ADSU

t_ADH

WD[7:0]

WRAD[5:0]

Valid

t_WENSU

t_WENH

WEN

t_BENSU

Valid

t_BENH

BLKEN

Note: Identical timing for falling-edge clock.

3200DX SRAM Synchronous Read Operation

t_CKHL

t_RCKHL

RCLK

t_RENSU

t_RENH

REN

t_ADSU

Valid

t_ADH

RDAD[5:0]

t_RCO

t_DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling-edge clock.

24

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX SRAM Asynchronous Read Operation—Type 1

(Read Address Controlled)

t_RDADV

RDAD[5:0]

RD[7:0]

ADDR1

t_DOH

Data 1

ADDR2

t_RPD

Data 2

3200DX SRAM Asynchronous Read Operation—Type 2

(Write Address Controlled)

WEN

t_WENSU

t_WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t_ADH

t_ADSU

WCLK

t_RPD

t_DOH

Old Data

New Data

RD[7:0]

Discontinued – v3.0

25

Integrator Series FPGAs: 1200XL and 3200DX Families

Predictable Performance:

Tight Delay Distributions

are not determined until after placement and routing of the

user’s design is complete. Delay values may then be

determined by using the Designer Series utility or

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being driven.

Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of

inputs increase.

performing simulation with post-layout delays.

Critical Nets and Typical Nets

Propagation delays in this data sheet apply to typical nets,

which are used for initial design performance evaluation.

The abundant routing resources in the Integrator Series

architecture allows for deterministic timing. Using

DirectTime, a timing-driven place and route tool in Actel’s

Designer Series development software, the designer may

specify timing-critical nets and system clock frequency.

Using these timing specifications, the place and route

software optimize the design layout to meet the user’s

specifications.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number of

loads) driven by a module. Higher fanout usually requires

some paths to have longer routing tracks.

The Integrator Series delivers a very tight fanout delay

distribution. This tight distribution is achieved in two ways:

by decreasing the delay of the interconnect elements and by

decreasing the number of interconnect elements per path.

Long Tracks

Some nets in the design use long tracks, which are special

routing resources that span multiple rows, columns, or

modules. Long tracks employ three and sometimes four

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, up to 6% of nets in a fully

utilized device require long tracks. Long tracks contribute

approximately 3 ns to 6 ns delay, which is represented

statistically in higher fanout (FO=8) routing delays in the

data sheet specifications section.

Actel’s patented PLICE antifuse offers

a very low

resistive/capacitive interconnect. The antifuses, fabricated

in 0.6 micron lithography, offer nominal levels of 100 ohms

resistance and 7.0 femtofarad (fF) capacitance per antifuse.

The Integrator Series fanout distribution is also tight due to

the low number of antifuses required for each interconnect

path. The proprietary architecture limits the number of

antifuses per path to a maximum of four, with 90% of

interconnects using two antifuses.

Timing Characteristics

Timing Derating

A timing derating factor of 0.45 is used to reflect best-case

processing. Note that this factor is relative to the “standard

speed” timing parameters, and must be multiplied by the

appropriate voltage and temperature derating factors for a

given application.

Timing characteristics for devices fall into three categories:

family-dependent, device-dependent, and design-dependent.

The input and output buffer characteristics are common to

all Integrator Series members. Internal routing delays are

device-dependent. Design dependency means actual delays

Timing Derating Factor (Temperature and Voltage)

Industrial

Military

Min.

Max.

Min.

Max.

(Commercial Specification) x

0.69

1.11

0.67

1.23

Timing Derating Factor for Designs at Typical Temperature (T = 25°C)

J

and Voltage (5.0V)

(Maximum Specification, Worst-Case Condition) x

0.85

Note: This derating factor applies to all routing and propagation

delays.

26

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T = 4.75V, 70°C)

J

–55

–40

0

25

70

85

125

4.50

4.75

5.00

5.25

5.50

0.75

0.71

0.69

0.68

0.67

0.79

0.75

0.72

0.69

0.86

0.82

0.80

0.77

0.76

0.92

0.87

0.85

0.82

0.81

1.06

1.00

0.97

0.95

0.93

1.11

1.05

1.02

0.98

0.97

1.23

1.16

1.13

1.09

1.08

Junction Temperature and Voltage Derating Curves

(Normalized to Worst-Case Commercial, T_J= 4.75V, 70°C)

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

125˚C

85˚C

70˚C

25˚C

0˚C

–40˚C

–55˚C

4.50

4.75

5.00

Voltage (V)

5.25

5.50

Note: This derating factor applies to all routing and propagation delays.

Discontinued – v3.0

27

Integrator Series FPGAs: 1200XL and 3200DX Families

A1225XL Timing Characteristics

(Worst-Case Commercial Conditions, V

= 4.75 V, T = 70°C)

CC

‘–3’ Speed

Min. Max.

J

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max. Units

1

Logic ModulePropagation Delays

t

Single Module

2.6

3.0

3.5

5.0

4.2

ns

PD1

CO

GO

RS

Sequential Clk-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

2

Predicted Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.8

1.3

1.7

2.0

3.2

0.9

1.4

1.8

2.3

3.5

1.1

1.7

2.2

2.7

4.2

1.57

2.43

3.15

3.86

6.00

1.3

2.0

2.6

3.2

5.0

ns

3,4

Sequential Timing Characteristics

t_SUD

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

0.4

0.0

0.8

0.0

3.2

6.5

0.0

0.3

0.0

0.3

0.4

0.0

0.9

0.0

3.6

7.4

0.0

0.4

0.0

0.4

0.5

0.0

1.0

0.0

4.3

8.7

0.0

0.4

0.0

0.4

0.7

0.0

1.4

0.0

6.1

12.4

0.0

0.6

0.0

0.6

0.0

1.2

0.0

5.2

10.4

0.0

0.5

0.0

0.5

ns

t_HD

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

t_INH

Input Buffer Latch Hold

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock

Frequency

225

200

170

120

115

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts

(adds) to the internal set-up (hold) time.

5. V_CC= 3.0V for 3.3V specifications.

28

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A1225XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2’ Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t

Pad-to-Y High

Pad-to-Y Low

G-to-Y High

G-to-Y Low

1.1

1.3

2.0

2.6

1.2

1.4

2.3

3.0

1.4

1.7

2.7

3.5

2.0

2.4

3.9

5.0

1.7

2.0

3.2

4.2

ns

INYH

INYL

INGH

INGL

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.2

3.8

4.1

5.2

3.3

3.6

4.2

4.6

5.9

3.9

4.3

5.0

5.4

6.9

5.6

6.1

7.2

7.7

9.9

4.7

5.2

6.0

6.5

8.3

ns

IRD1

IRD2

IRD3

IRD4

IRD8

Global Clock Network

FO = 32

FO = 256

5.1

5.7

5.8

6.5

6.8

7.6

9.7

10.9

8.2

9.1

t

f

Input Low to High

Input High to Low

CKH

ns

FO = 32

FO = 256

5.0

5.7

6.5

6.7

7.6

9.6

10.9

8.0

9.1

CKL

FO = 32

FO = 256

2.6

2.7

3.0

3.1

3.5

3.6

5.0

5.1

4.2

4.3

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

PWH

PWL

CKSW

SUEXT

HEXT

P

ns

FO = 32

FO = 256

2.6

2.7

3.0

3.1

3.5

3.6

5.0

5.1

4.2

4.3

ns

FO = 32

FO = 256

0.8

0.9

1.0

1.4

1.2

ns

FO = 32

FO = 256

0.0

Input Latch External Set-Up

Input Latch External Hold

Minimum Period

ns

FO = 32

FO = 256

2.6

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.1

5.2

ns

FO = 32

FO = 256

5.4

5.6

6.1

6.3

7.2

7.4

10.3

10.6

8.6

8.9

ns

FO = 32

FO = 256

225

200

180

170

155

120.

105

115

105

Maximum Frequency

MAX

MHz

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

29

Integrator Series FPGAs: 1200XL and 3200DX Families

A1225XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

CC

‘–2’ Speed

Min. Max.

J

3.3V ‘Std”

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

1

TTL Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

3.8

4.1

3.8

4.1

5.4

4.2

4.7

4.3

4.6

4.3

4.7

6.1

4.8

5.4

5.0

5.4

5.0

5.5

7.2

5.6

6.3

7.1

7.7

6.0

6.5

6.0

6.5

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.9

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

9.0

10.0

12.0

17.2

14.4

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

12.8

0.04

0.05

14.4

0.04

0.06

17.0

0.05

0.07

24.3

0.06

0.08

20.4

0.06

0.08

ns

d

Capacitive Loading, Low to High

ns/pF

TLH

THL

Capacitive Loading, High to Low

1

CMOS Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

4.8

3.4

3.8

4.1

5.4

4.2

4.7

5.4

3.8

4.3

4.7

6.1

4.8

5.4

6.4

4.5

5.0

5.5

7.2

5.6

6.3

9.1

6.4

7.7

5.4

6.0

6.6

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.9

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

10.7

11.8

14.2

20.3

17.0

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

15.0

0.05

17.0

0.06

0.05

20.0

0.07

0.06

28.6

0.08

0.07

24.0

0.08

0.07

ns

d

Capacitive Loading, Low to High

Capacitive Loading, High to Low

ns/pF

TLH

THL

Note:

1. Delays based on 35 pF loading.

30

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A1240XL Timing Characteristics

(Worst-Case Commercial Conditions, V

= 4.75 V, T = 70°C)

J

CC

‘–3’ Speed

Min. Max.

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

1

Logic ModulePropagation Delays

t

Single Module

2.6

3.0

3.5

5.0

4.2

ns

PD1

CO

GO

RS

Sequential Clk-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

2

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.1

1.3

1.7

2.3

3.4

1.2

1.4

1.9

2.6

3.8

1.4

1.7

2.2

3.0

4.5

2.0

2.4

3.1

4.3

6.4

1.7

2.0

2.6

3.6

5.4

ns

RD1

RD2

RD3

RD4

RD8

3, 4

Sequential Timing Characteristics

t

f

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

0.4

0.0

0.8

0.0

3.4

6.8

0.0

0.3

0.0

0.3

0.4

0.0

0.9

0.0

3.8

7.7

0.0

0.4

0.0

0.4

0.5

0.0

1.0

0.0

4.5

9.1

0.0

0.4

0.0

0.4

0.7

0.0

1.4

0.0

6.4

13.0

0.0

0.6

0.0

0.6

0.0

1.2

0.0

5.4

10.9

0.0

0.5

0.0

0.5

ns

SUD

HD

ns

SUENA

HENA

WCLKA

WASYN

A

ns

Input Buffer Latch Hold

ns

INH

Input Buffer Latch Set-Up

ns

INSU

OUTH

OUTSU

MAX

Output Buffer Latch Hold

ns

Output Buffer Latch Set-Up

ns

Flip-Flop (Latch) Clock Frequency

215

190

160

110

105

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts

(adds) to the internal set-up (hold) time.

5. V_CC= 3.0V for 3.3V specifications.

Discontinued – v3.0

31

Integrator Series FPGAs: 1200XL and 3200DX Families

A1240XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2’ Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t

Pad-to-Y High

Pad-to-Y Low

G-to-Y High

G-to-Y Low

1.1

1.3

2.0

2.6

1.2

1.4

2.3

3.0

1.4

1.7

2.7

3.5

2.0

2.4

3.9

5.0

1.7

2.0

3.2

4.2

ns

INYH

INYL

INGH

INGL

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.4

3.8

4.1

5.6

3.3

3.8

4.3

4.7

6.3

3.9

4.5

5.1

5.5

7.4

5.6

6.4

4.7

5.4

6.1

6.6

8.9

ns

IRD1

IRD2

IRD3

IRD4

IRD8

7.3

7.9

10.6

Global Clock Network

FO = 32

FO = 256

5.1

5.7

5.8

6.5

6.8

7.6

9.7

10.9

8.2

9.1

ns

t

f

Input Low to High

Input High to Low

CKH

FO = 32

FO = 256

5.0

5.7

6.5

6.7

7.6

9.6

10.9

8.0

9.1

ns

CKL

FO = 32

FO = 256

2.7

2.9

3.1

3.3

3.6

3.9

5.1

5.6

4.3

4.7

ns

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

PWH

PWL

CKSW

SUEXT

HEXT

P

FO = 32

FO = 256

2.7

2.9

3.1

3.3

3.6

3.9

5.1

5.6

4.3

4.7

ns

FO = 32

FO = 256

0.8

0.9

1.0

1.4

1.2

ns

FO = 32

FO = 256

0.0

ns

Input Latch External Set-Up

Input Latch External Hold

Minimum Period

FO = 32

FO = 256

2.6

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.1

5.2

ns

FO = 32

FO = 256

5.6

6.0

6.3

6.8

7.4

8.0

10.6

11.4

8.9

9.6

ns

FO = 32

FO = 256

215

195

190

170

160

144

110

100

105

95

MHz

Maximum Frequency

MAX

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

32

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A1240XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2’ Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

1

TTL Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

3.8

4.1

3.8

4.1

5.4

4.2

4.7

4.3

4.6

4.3

4.7

6.1

4.8

5.4

5.0

5.4

5.0

5.5

7.2

5.6

6.3

7.1

7.7

6.0

6.5

6.0

6.6

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.9

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

9.2

10.5

12.3

17.6

14.8

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

12.9

0.04

0.05

14.6

0.04

0.06

17.2

0.05

0.07

24.6

0.06

0.08

20.6

0.06

0.08

ns

d

Capacity Loading, Low to High

ns/pF

TLH

THL

Capacity Loading, High to Low

1

CMOS Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

4.8

3.4

3.8

4.1

5.4

4.2

4.7

5.4

3.8

4.3

4.7

6.1

4.8

5.4

6.4

4.5

5.0

5.5

7.2

5.6

6.3

9.1

6.4

7.7

5.4

6.0

6.6

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.9

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

10.9

12.4

14.5

20.7

17.4

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

15.2

0.05

17.2

0.06

0.05

20.3

0.07

0.06

29.0

0.08

0.07

24.4

0.08

0.07

ns

d

Capacity Loading, Low to High

Capacity Loading, High to Low

ns/pF

TLH

THL

Note:

1. Delays based on 35 pF loading.

Discontinued – v3.0

33

Integrator Series FPGAs: 1200XL and 3200DX Families

A3265DX Timing Characteristics

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–3’ Speed

Min. Max.

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

1

Logic ModulePropagation Delays

Combinatorial Functions

t

Internal Array Module Delay

2.1

2.5

2.4

2.8

2.9

3.4

3.7

4.4

3.2

3.7

ns

PD

t

Internal Decode Module Delay

2

PDD

Predicted Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.3

0.7

0.4

0.8

1.2

1.6

3.2

0.5

0.9

0.6

1.2

1.8

2.4

4.9

0.8

0.5

1.0

1.6

2.1

4.1

0.7

ns

1.0

1.4

1.9

2.7

3.7

Decode-to-Output Routing Delay

3, 4

0.46

0.62

Sequential Timing Characteristics

t_CO

Flip-Flop Clock-to-Output

2.3

2.1

2.7

2.4

3.1

2.9

4.1

3.7

3.5

3.2

ns

t_GO

Latch Gate-to-Output

t_SUD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

0.35

0.0

0.4

0.0

0.47

0.0

0.6

0.0

0.5

0.0

t_HD

t_RO

Flip-Flop (Latch) Reset to Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

2.3

2.7

3.1

4.1

3.5

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.75

0.0

0.9

0.0

4.2

5.5

1.0

0.0

4.9

6.5

1.3

0.0

6.4

8.4

1.1

0.0

5.5

7.1

3.7

4.9

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts

(adds) to the internal set-up (hold) time.

5. V_CC= 3.0V for 3.3V specifications.

34

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A3265DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2’ Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

3.3

1.6

3.7

1.9

4.4

2.4

5.7

2.1

4.8

ns

INPY

INGO

INH

0.0

0.5

5.1

0.0

0.6

5.9

0.0

0.7

6.9

0.0

0.9

9.0

0.0

0.8

7.7

Input Latch Set-Up

INSU

ILA

Latch Active Pulse Width

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

3.2

3.6

3.7

4.2

4.5

5.2

7.5

0.4

4.3

4.9

5.3

6.1

8.8

0.5

5.6

6.4

6.9

7.9

11.4

0.7

4.8

5.4

5.9

6.7

9.7

0.6

ns

IRD1

IRD2

IRD3

IRD4

IRD5

IRDD

3.9

4.5

6.6

0.37

Global Clock Network

t

f

Input Low to High

Input High to Low

Minimum Pulse Width

Maximum Skew

FO=32

FO=256

6.3

7.4

7.1

8.4

9.9

10.9

12.8

9.2

10.9

ns

CKH

FO=32

FO=256

5.9

6.4

6.6

7.3

7.8

8.6

10.1

11.2

8.6

9.5

ns

CKL

FO=32

FO=256

3.2

3.4

3.7

3.9

4.3

4.6

5.6

6.0

4.8

5.1

ns

PW

FO=32

FO=256

0.75

0.9

1.0

1.3

1.1

ns

CKSW

SUEXT

HEXT

P

FO=32

FO=256

0.0

ns

Input Latch External Set-Up

FO=32

FO=256

2.5

2.9

3.4

4.4

3.8

ns

Input Latch External Hold

Minimum Period (1/fmax)

FO=32

FO=256

5.0

6.0

7.2

8.3

9.5

11.9

13.6

9.2

10.6

ns

FO=32

FO=256

173

151

138

121

120

105

84

74

108

95

MHz

MAX

Maximum Datapath Frequency

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

35

Integrator Series FPGAs: 1200XL and 3200DX Families

A3265DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

1

TTL Output Module Timing

t

Data-to-Pad High

3.8

4.6

4.8

5.2

8.3

7.7

4.3

5.2

5.4

5.9

9.5

9.4

8.7

5.0

6.1

6.5

7.9

5.5

6.7

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

6.4

8.3

7.1

ns

Enable-Pad Z to Low

6.9

9.0

7.6

ns

Enable-Pad High to Z

11.1

10.2

14.5

14.4

13.3

12.3

11.3

ns

Enable-Pad Low to Z

ns

G-to-Pad High

ns

G-to-Pad Low

ns

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

0.8

0.0

ns

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad)32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

9.8

13.9

0.037

0.05

0.3

11.1

15.7

0.04

0.03

0.4

13.1

18.5

0.05

0.07

0.5

17.0

24.1

0.071

0.1

14.5

20.5

0.06

0.08

0.6

ns

LCO

ACO

ns

d

ns/pF

TLH

TLL

t

Hard-Wired Wide-Decode Output

1

0.7

WDO

CMOS Output Module Timing

t

Data-to-Pad High

4.6

3.8

4.8

5.2

8.3

9.0

5.2

4.3

5.5

5.9

9.5

9.4

10.2

6.1

5.0

7.9

6.5

6.7

5.5

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

6.4

8.4

7.1

ns

Enable-Pad Z to Low

6.9

9.0

7.6

ns

Enable-Pad High to Z

11.1

12.0

14.5

14.4

15.6

12.3

13.3

ns

Enable-Pad Low to Z

ns

G-to-Pad High

ns

G-to-Pad Low

ns

I/O Latch Set-Up

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

0.8

0.0

ns

I/O Latch Hold

ns

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

Hard-Wired Wide-Decode Output

11.7

16.4

0.05

0.04

0.3

13.3

18.5

0.06

0.05

0.4

15.6

21.8

0.07

0.06

0.5

20.3

28.3

0.1

17.3

24.1

0.1

ns

LCO

ACO

ns

d

ns/pF

TLH

TLL

0.1

t

0.7

0.6

WDO

Note:

1. Delays based on 35pF loading.

36

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A1280XL Timing Characteristics

(Worst-Case Commercial Conditions, V

= 4.75 V, T = 70°C)

J

CC

‘–3’ Speed

Min. Max.

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

1

Logic ModulePropagation Delays

t

Single Module

2.6

3.0

3.5

5.0

4.2

ns

PD1

CO

GO

RS

Sequential Clk-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

2

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.8

2.2

2.6

5.0

1.4

2.0

2.5

3.0

5.7

1.7

2.4

2.9

3.5

6.7

2.4

3.4

4.1

5.0

9.6

2.0

2.9

3.5

4.2

8.0

ns

RD1

RD2

RD3

RD4

RD8

3,4

Sequential Timing Characteristics

t

f

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

0.4

0.0

0.8

0.0

3.7

8.0

0.0

0.3

0.0

0.3

0.4

0.0

0.9

0.0

4.3

8.7

0.0

0.4

0.0

0.4

0.5

0.0

1.0

0.0

4.9

10.0

0.0

0.4

0.0

0.4

0.7

0.0

1.4

0.0

7.0

14.0

0.0

0.6

0.0

0.6

0.0

1.2

0.0

5.9

12.0

0.0

0.5

0.0

0.5

ns

SUD

HD

ns

SUENA

HENA

WCLKA

WASYN

A

ns

Input Buffer Latch Hold

ns

INH

Input Buffer Latch Set-Up

ns

INSU

OUTH

OUTSU

MAX

Output Buffer Latch Hold

ns

Output Buffer Latch Set-Up

ns

Flip-Flop (Latch) Clock Frequency

200

167

130

90

110

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts

(adds) to the internal set-up (hold) time.

5. V_CC= 3.0V for 3.3V specifications.

Discontinued – v3.0

37

Integrator Series FPGAs: 1200XL and 3200DX Families

A1280XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t

Pad-to-Y High

Pad-to-Y Low

G-to-Y High

G-to-Y Low

1.1

1.3

2.0

2.6

1.2

1.4

2.3

3.0

1.4

1.7

2.7

3.5

2.0

2.4

3.9

5.0

1.7

2.0

3.2

4.2

ns

INYH

INYL

INGH

INGL

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.2

3.7

4.0

4.6

6.6

3.7

4.2

4.5

5.2

7.5

4.3

4.9

5.3

6.1

8.8

6.1

7.0

5.2

5.9

ns

IRD1

IRD2

IRD3

IRD4

IRD8

7.6

6.4

8.7

7.3

12.6

10.6

Global Clock Network

FO = 32

FO = 384

5.1

5.7

5.8

6.5

6.8

7.6

9.7

10.9

8.2

9.1

ns

t

f

Input Low to High

Input High to Low

CKH

FO = 32

FO = 384

5.0

5.7

6.5

6.7

7.6

9.6

10.9

8.0

9.1

ns

CKL

FO = 32

FO = 384

3.2

3.5

3.9

4.3

4.6

6.1

6.6

5.2

5.5

ns

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

PWH

PWL

CKSW

SUEXT

HEXT

P

FO = 32

FO = 384

3.2

3.5

3.9

4.3

4.6

6.1

6.6

5.2

5.5

ns

FO = 32

FO = 384

0.8

0.9

1.0

1.4

1.2

ns

FO = 32

FO = 384

0.0

ns

Input Latch External Set-Up

Input Latch External Hold

Minimum Period

FO = 32

FO = 384

2.6

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.1

5.2

ns

FO = 32

FO = 384

6.5

7.2

7.4

8.0

8.7

9.6

12.4

13.7

10.4

11.5

ns

FO = 32

FO = 384

200

180

167

150

143

130

100

90

120

110

MHz

Maximum Frequency

MAX

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

38

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A1280XL Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

CC

‘–2’ Speed

Min. Max.

J

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter

Description

1

Min.

Max.

Min.

Max.

Units

TTL Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

3.8

4.1

3.8

4.1

5.4

4.2

4.7

4.3

4.6

4.3

4.7

6.1

4.8

5.4

5.0

5.4

5.0

5.5

7.2

5.6

6.3

7.1

7.7

6.0

6.5

6.0

6.6

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.7

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

9.8

11.0

13.1

18.7

15.7

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

13.9

0.04

0.05

15.7

0.04

0.06

18.5

0.05

0.07

26.4

0.06

0.08

22.2

0.06

0.08

ns

d

Capacitive Loading, Low to High

ns/pF

TLH

THL

Capacitive Loading, High to Low

1

CMOS Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

4.8

3.4

3.8

4.1

5.4

4.2

4.7

5.4

3.8

4.3

4.7

6.1

4.8

5.4

6.4

4.5

5.0

5.5

7.2

5.6

6.3

9.1

6.4

7.7

5.4

6.0

6.6

8.6

6.7

7.6

ns

DLH

DHL

7.1

ENZH

ENZL

ENHZ

ENLZ

GLH

7.9

10.3

8.0

G-to-Pad Low

9.0

GHL

I/O Latch Clock-Out (Pad-to-Pad),

64 Clock Loading

LCO

11.6

13.0

15.5

22.2

18.6

ns

t

Array Clock-Out (Pad-to-Pad),

64 Clock Loading

ACO

16.4

0.05

18.5

0.06

0.05

21.8

0.07

0.06

31.2

0.08

0.07

26.2

0.08

0.07

ns

d

Capacitive Loading, Low to High

Capacitive Loading, High to Low

ns/pF

TLH

THL

Note:

1. Delays based on 35 pF loading.

Discontinued – v3.0

39

Integrator Series FPGAs: 1200XL and 3200DX Families

A32100DX Timing Characteristics

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic ModulePropagation Delays

Combinatorial Functions

t

Internal Array Module Delay

Internal Decode Module Delay

2.2

2.4

2.6

2.7

3.0

3.1

3.5

3.7

5.2

5.7

4.1

4.3

ns

PD

PDD

Predicted Module Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.0

1.4

1.8

2.4

4.2

0.3

1.1

1.7

1.3

1.9

2.5

3.1

5.6

0.4

1.5

2.2

2.9

3.7

6.6

0.5

3.3

4.3

1.7

2.5

3.4

4.3

7.7

0.6

ns

2.1

5.2

2.7

6.5

5.0

10.0

0.4

0.37

Sequential Timing Characteristics

t_CO

Flip-Flop Clock-to-Output

2.2

2.6

3.0

3.5

5.0

4.1

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset to Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

0.3

0.0

0.37

0.0

0.4

0.0

0.5

0.0

0.7

0.0

0.6

0.0

t_H

t_RO

2.2

2.6

3.0

3.5

5.0

4.1

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.6

0.0

3.1

0.75

0.0

0.9

0.0

4.2

1.0

0.0

4.9

1.4

0.0

7.0

0.85

0.0

3.7

5.7

Flip-Flop (Latch) Asynchronous Pulse

Width

4.1

4.8

5.4

6.4

7.0

7.5

ns

40

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32100DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Timing

Synchronous SRAM Operations

t_RC

Read Cycle Time

6.4

3.2

7.5

3.8

8.5

4.3

10.0

5.0

14.3

7.1

11.7

5.9

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock High/Low Time

Data Valid After Clock High/Low

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.2

3.8

4.3

5.0

7.1

5.9

1.5

0.0

0.6

3.2

2.6

0.0

2.6

0.0

1.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.3

7.1

5.7

0.0

5.8

0.0

2.8

0.0

1.0

5.9

4.7

0.0

4.8

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

7.7

9.0

10.2

12.0

17.2

14.1

ns

t_RDADV

t_ADSU

t_ADH

8.3

1.5

0.0

0.57

3.2

2.6

0.0

9.8

1.8

0.0

0.7

3.8

3.0

0.0

11.1

2.0

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.6

3.4

0.0

1.3

7.1

5.7

0.0

15.2

2.8

0.0

1.0

5.9

4.7

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.1

1.35

1.5

1.8

2.6

2.1

Discontinued – v3.0

41

Integrator Series FPGAs: 1200XL and 3200DX Families

A32100DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t

Input Data Pad-to-Y

1.4

2.9

1.65

3.4

1.9

3.8

2.2

4.5

3.1

6.4

2.5

5.3

ns

INPY

1

INGO

Input Latch Gate-to-Output

ns

1

t

Input Latch Hold

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

INH

INSU

ILA

1

Input Latch Set-Up

0.45

0.82

1

Latch Active Pulse Width

4.4

4.8

5.9

6.9

9.8

8.1

ns

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.6

2.0

2.6

4.1

1.75

2.4

3.0

4.8

2.1

2.7

3.4

5.4

2.5

3.2

4.0

6.4

3.6

4.6

5.7

9.1

2.9

3.8

4.7

7.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

Global Clock Network

t

f

Input Low to High

FO=32

FO=635

4.7

5.7

5.6

6.75

6.3

7.7

7.4

9.0

10.5

12.8

8.7

10.5

ns

CKH

Input High to Low

FO=32

FO=635

4.8

6.4

5.6

7.5

6.4

8.5

7.5

10.0

10.7

14.2

8.8

11.7

ns

CKL

Minimum Pulse Width

High

FO=32

FO=635

2.5

2.7

2.9

3.2

3.3

3.7

3.9

4.3

5.6

6.1

4.5

5.0

ns

PWH

PWL

CKSW

SUEXT

HEXT

P

Minimum Pulse Width

Low

FO=32

FO=635

2.5

2.7

2.9

3.2

3.3

3.7

3.9

4.3

5.5

6.1

4.5

5.0

ns

Maximum Skew

FO=32

FO=635

0.6

0.75

0.9

1.0

1.4

1.8

ns

Input Latch External

Set-Up

FO=32

FO=635

0.0

ns

Input Latch External

Hold

FO=32

FO=635

2.2

2.7

2.5

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.0

6.1

ns

Minimum Period

(1/fmax)

FO=32

FO=635

5.0

5.5

6.0

6.4

7.4

8.2

7.9

8.6

12.4

13.7

9.3

10.1

ns

Maximum Datapath

Frequency

FO=32

FO=635

183

167

159

145

146

133

127

116

89

81

108

99

MHz

HMAX

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

42

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32100DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min.

Max.

Min. Max. Min. Max. Min. Max. Min. Max. Units

1

TTL Output Module Timing

t

Data-to-Pad High

3.7

4.5

4.8

5.1

8.3

9.0

4.3

5.3

5.6

6.0

9.8

10.5

4.9

6.0

5.8

7.1

8.2

6.8

8.3

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

10.1

10.7

11.4

18.5

20.1

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

6.4

7.5

8.8

6.8

8.0

9.4

11.1

12.0

13.0

14.1

15.2

16.4

G-to-Pad Low

I/O Latch Output Set-Up

I/O Latch Output Hold

0.26

0.0

0.3

0.0

0.34

0.0

0.4

0.0

0.6

0.0

0.6

0.0

LH

LCO

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

8.4

9.8

11.1

13.1

18.7

15.3

21.7

ns

t

ACO

11.8

0.03

0.04

13.8

0.037

0.05

15.7

0.04

0.06

0.05

18.5

0.05

0.07

0.06

26.5

0.07

0.10

0.09

ns

d

Capacitive Loading, Low to High

Capacitive Loading, High to Low

0.06 ns/pF

0.08 ns/pF

TLH

THL

t

Hard-Wired Wide-Decode Output

1

0.045

0.07

ns

WDO

CMOS Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

4.5

3.7

4.8

5.1

8.3

9.0

5.3

4.3

5.6

6.0

9.8

10.5

6.0

4.9

7.1

5.8

10.1

8.2

8.3

6.8

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

6.4

7.5

10.7

11.4

18.5

20.0

8.8

6.8

8.0

9.4

11.1

12.0

13.0

14.1

15.2

16.4

G-to-Pad Low

I/O Latch Set-Up

I/O Latch Hold

0.26

0.0

0.3

0.0

0.3

0.0

0.4

0.0

0.6

0.0

0.6

0.0

LH

LCO

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

9.9

11.0

13.2

15.5

22.3

18.2

25.6

ns

t

ACO

13.9

0.04

16.4

0.052

0.045

18.5

0.05

21.8

0.07

0.06

30.0

0.10

0.09

ns

d

Capacitive Loading, Low to High

Capacitive Loading, High to Low

Hard-Wired Wide-Decode Output

0.08 ns/pF

0.07 ns/pF

TLH

THL

t

0.07

ns

WDO

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

43

Integrator Series FPGAs: 1200XL and 3200DX Families

A32140DX Timing Characteristics

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2 Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

1

Logic Module Propagation Delays

Combinatorial Functions

t

Internal Array Module Delay

1.8

1.9

2.3

2.5

2.8

3.0

3.6

3.8

3.2

3.5

ns

PD

Internal Decode Module Delay

2

PDD

Predicted Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.0

1.4

1.8

2.2

3.8

0.5

1.3

1.9

2.4

2.9

5.0

0.7

1.6

2.2

2.0

2.8

3.7

4.5

7.7

1.0

1.8

2.5

ns

2.8

3.3

3.4

4.0

5.9

7.0

Decode-to-Output Routing Delay

3, 4

0.78

0.91

Sequential Timing Characteristics

t_CO

Flip-Flop Clock-to-Output

2.1

1.8

2.8

2.3

3.3

2.8

4.3

3.6

3.9

3.2

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset to Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

0.3

0.0

0.4

0.0

0.47

0.0

0.6

0.0

0.55

0.0

t_H

t_RO

2.1

2.8

3.3

4.3

3.9

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.6

0.0

2.6

0.9

0.0

3.5

1.0

0.0

4.1

1.3

0.0

5.4

1.17

0.0

4.82

Flip-Flop (Latch) Asynchronous Pulse Width

4.1

5.5

6.5

8.4

7.6

ns

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal set-up (hold) time.

44

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32140DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

‘–2’ Speed

Min. Max.

3.3V ‘Std’

Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.2

2.3

1.6

3.1

1.9

3.7

2.4

4.7

2.2

4.3

ns

INPY

INGO

INH

0.0

0.3

3.1

0.0

0.4

4.2

0.0

0.47

4.9

0.0

0.6

6.4

0.0

0.55

5.7

Input Latch Set-Up

INSU

ILA

Latch Active Pulse Width

1

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.7

3.1

3.4

3.9

5.6

0.3

3.7

4.2

4.5

5.2

7.5

0.4

4.3

4.9

5.3

6.1

8.8

0.5

5.6

6.4

6.9

7.9

11.4

0.7

5.0

5.7

ns

IRD1

IRD2

IRD3

IRD4

IRD5

IRDD

6.2

7.1

10.3

0.6

Decode-to-Output Routing Delay

Global Clock Network

t

f

Input Low to High

Input High to Low

Minimum Pulse Width

Maximum Skew

FO=32

FO=486

6.2

6.8

8.3

9.1

9.7

10.7

12.7

13.9

11.4

12.5

ns

CKH

FO=32

FO=486

6.12

6.7

8.2

8.9

9.6

10.5

12.5

13.6

11.3

12.3

ns

CKL

FO=32

FO=486

2.7

2.9

3.7

3.9

4.3

4.6

5.6

6.0

5.0

5.41

ns

PW

FO=32

FO=486

0.6

0.9

1.0

1.3

1.17

ns

CKSW

SUEXT

HEXT

P

FO=32

FO=486

0.0

ns

Input Latch External Set-Up

Input Latch External Hold

FO=32

FO=486

2.2

2.9

3.4

4.4

4.0

ns

Minimum Period (1/fmax)

FO=32

FO=486

5.7

6.6

7.6

8.3

9.5

11.9

13.6

9.0

11.1

ns

FO=32

FO=486

173

151

138

121

120

105

84

74

102

90

MHz

MAX

Maximum Datapath Frequency

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

45

Integrator Series FPGAs: 1200XL and 3200DX Families

A32140DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–2 Speed

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

1

TTL Output Module Timing

t

Data-to-Pad High

3.3

3.5

4.1

4.4

7.1

6.5

4.4

4.6

5.5

5.9

9.5

8.7

5.1

5.4

6.7

7.1

6.0

6.3

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

6.4

8.4

7.5

ns

Enable-Pad Z to Low

6.9

9.0

8.1

ns

Enable-Pad High to Z

11.1

10.2

14.5

13.3

13.0

12.0

ns

Enable-Pad Low to Z

ns

G-to-Pad High

ns

G-to-Pad Low

ns

I/O Latch Output Set-Up

I/O Latch Output Hold

0.4

0.0

0.6

0.0

0.7

0.0

0.9

0.0

0.82

0.0

ns

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

8.4

11.1

15.7

0.04

0.03

0.04

13.1

18.5

0.05

0.07

0.05

17.0

24.1

0.07

0.1

15.4

21.7

0.06

0.08

0.06

ns

LCO

ACO

11.8

0.03

0.02

0.03

ns

d

ns/pF

TLH

THL

t

Hard-Wired Wide-Decode Output

1

0.07

WDO

CMOS Output Module Timing

t

Data-to-Pad High

3.5

3.3

4.1

4.4

7.1

6.5

4.6

4.4

5.5

5.9

9.5

8.7

5.4

5.1

7.1

6.7

6.0

6.3

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

6.4

8.4

7.5

ns

Enable-Pad Z to Low

6.9

9.0

8.1

ns

Enable-Pad High to Z

11.1

10.2

14.5

13.3

13.0

12.0

ns

Enable-Pad Low to Z

ns

G-to-Pad High

ns

G-to-Pad Low

ns

I/O Latch Set-Up

0.4

0.0

0.6

0.0

0.7

0.0

0.9

0.0

0.82

0.0

ns

I/O Latch Hold

ns

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

Hard-Wired Wide-Decode Output

9.9

13.9

0.04

0.3

13.3

18.5

0.06

0.05

0.4

15.6

21.8

0.07

0.06

0.5

20.3

28.3

0.1

18.3

25.6

0.08

0.07

0.6

ns

LCO

ACO

ns

d

ns/pF

TLH

THL

0.1

t

0.7

WDO

Note:

1. Delays based on 35 pF loading.

46

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32200DX Timing Characteristics

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays

Combinatorial Functions

t

Internal Array Module Delay

Internal Decode Module Delay

2.0

2.5

2.4

2.9

2.7

3.3

3.2

3.9

4.5

5.6

3.7

4.5

ns

PD

PDD

Predicted Module Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.1

1.7

2.1

2.6

4.5

0.6

1.35

2.0

1.5

2.2

2.8

3.4

6.0

0.8

1.8

2.6

3.3

4.0

7.0

0.9

2.6

3.7

4.7

5.7

10.0

1.3

2.1

3.0

3.8

4.7

8.2

1.0

ns

2.4

3.0

5.3

0.67

Sequential Timing Characteristics

t_CO

Flip-Flop Clock-to-Output

2.3

2.0

2.7

2.4

3.1

2.7

3.6

3.2

5.1

4.5

4.2

3.7

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset to Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.35

0.0

0.4

0.0

0.47

0.0

0.7

0.0

0.55

0.0

t_H

t_RO

2.3

2.7

3.1

3.6

5.1

4.2

t_SUENA

t_HENA

t_WCLKA

0.6

0.0

0.75

0.0

0.9

0.0

1.0

0.0

1.4

0.0

1.17

0.0

Flip-Flop (Latch) Clock Active

Pulse Width

3.1

4.1

3.7

4.9

4.2

5.5

4.9

6.5

7.0

9.2

5.7

7.6

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

Discontinued – v3.0

47

Integrator Series FPGAs: 1200XL and 3200DX Families

A32200DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Timing

Synchronous SRAM Operations

t_RC

Read Cycle Time

6.4

3.2

7.5

3.9

8.5

4.3

10.0

5.0

14.3

7.1

11.7

5.8

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock High/Low Time

Data Valid After Clock High/Low

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.2

3.8

4.3

5.0

7.1

5.8

1.5

0.0

0.6

3.2

2.6

0.0

2.6

0.0

1.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.4

7.0

5.4

0.0

5.6

0.0

2.8

0.0

1.0

5.8

4.7

0.0

4.8

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

7.7

9.0

10.2

12.0

17.2

14.1

ns

t_RDADV

t_ADSU

t_ADH

8.3

1.5

0.0

0.57

3.2

2.6

0.0

9.75

1.8

0.0

0.7

3.8

3.0

0.0

11.1

2.0

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.6

3.4

0.0

1.4

7.1

5.4

0.0

15.2

2.8

0.0

1.0

5.8

4.7

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSU

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.1

1.3

1.5

1.8

2.6

2.1

48

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32200DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t

Input Data Pad-to-Y

1.4

3.3

1.65

3.2

1.9

4.3

2.2

5.1

2.9

7.3

2.5

6.0

ns

INPY

1

INGO

Input Latch Gate-to-Output

ns

1

t

Input Latch Hold

0.0

0.45

4.4

0.0

0.52

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.8

0.0

0.8

8.1

INH

INSU

ILA

1

Input Latch Set-Up

1

Latch Active Pulse Width

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Delay

1.9

2.5

3.3

3.9

5.0

0.3

2.2

2.9

3.9

4.5

6.0

0.37

2.6

3.3

4.4

5.2

6.7

0.4

3.0

3.9

5.2

6.1

7.9

0.5

4.2

5.5

7.6

8.7

11.2

0.7

3.5

4.5

6.1

7.1

9.3

0.6

ns

IRD1

IRD2

IRD3

IRD4

IRD5

IRDD

Global Clock Network

t

f

Input Low to High

FO=32

FO=635

5.3

6.1

6.2

7.2

7.1

8.2

8.3

9.6

11.8

13.7

9.7

11.3

ns

CKH

Input High to Low

FO=32

FO=635

5.2

6.8

6.2

8.0

7.0

9.0

8.2

10.6

11.7

15.1

9.6

12.8

ns

CKL

FO=32

FO=635

2.7

2.9

3.2

3.45

3.7

3.9

4.3

4.6

6.1

6.6

5.0

5.4

ns

PWH

PWL

CKSW

SUEXT

HEXT

P

Minimum Pulse Width High

FO=32

FO=635

2.7

2.9

3.2

3.45

3.7

3.9

4.3

4.6

6.1

6.6

5.0

5.4

ns

Minimum Pulse Width Low

Maximum Skew

FO=32

FO=635

0.6

0.75

0.9

1.0

1.4

1.1

ns

FO=32

FO=635

0.0

ns

Input Latch External Set-Up

Input Latch External

Hold

FO=32

FO=635

2.2

2.7

2.6

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.0

5.0

ns

Minimum Period

(1/fmax)

FO=32

FO=635

5.5

6.1

6.5

7.2

7.4

8.2

8.7

9.6

12.4

13.7

10.2

11.2

ns

Maximum Datapath

Frequency

FO=32

FO=635

165

151

153.

140

132

121

115

105

80

73

98

90

MHz

HMAX

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

49

Integrator Series FPGAs: 1200XL and 3200DX Families

A32200DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min.

Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

1

TTL Output Module Timing

t

Data-to-Pad High

3.7

4.5

4.8

5.2

8.3

8.9

4.3

5.3

5.6

6.0

9.7

10.5

4.9

6.0

5.8

7.1

8.3

6.8

8.3

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

10.1

10.7

11.5

18.5

20.0

Enable-Pad Z to High

6.4

7.5

8.8

Enable-Pad Z to Low

6.9

8.1

9.5

Enable-Pad High to Z

11.1

11.9

13.0

14.0

15.2

16.5

Enable-Pad Low to Z

G-to-Pad High

G-to-Pad Low

I/O Latch Output Set-Up

I/O Latch Output Hold

0.26

0.0

0.3

0.0

0.3

0.0

0.4

0.0

0.6

0.0

0.5

0.0

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

8.4

9.8

11.1

15.7

0.04

0.06

0.05

13.1

18.5

0.05

0.07

0.06

18.7

26.5

0.07

0.10

0.09

15.4

21.7

LCO

ACO

11.8

0.03

0.04

13.9

d

0.035

0.05

0.06 ns/pF

0.08 ns/pF

TLH

THL

t

Hard-Wired Wide-Decode Output

1

0.045

0.07

ns

WDO

CMOS Output Module Timing

t

Data-to-Pad High

Data-to-Pad Low

Enable-Pad Z to High

Enable-Pad Z to Low

Enable-Pad High to Z

Enable-Pad Low to Z

G-to-Pad High

4.5

3.7

4.8

5.2

8.3

8.9

5.3

4.3

5.6

6.0

9.7

10.5

6.0

4.9

5.8

7.1

8.3

6.8

8.3

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

10.1

10.7

11.5

18.5

20.0

6.4

7.5

8.8

6.9

8.1

9.5

11.1

11.9

13.0

14.0

15.2

16.5

G-to-Pad Low

I/O Latch Set-Up

I/O Latch Hold

0.26

0.0

0.3

0.0

0.3

0.0

0.4

0.0

0.6

0.0

0.5

0.0

LH

I/O Latch Clock-Out (Pad-to-Pad)

32 I/O

LCO

9.9

11.6

13.2

15.5

22.3

18.2

25.6

ns

t

ACO

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

13.9

0.04

16.3

0.05

18.5

0.06

0.05

21.8

0.07

0.06

31.2

0.10

0.09

d

Capacitive Loading, Low to High

Capacitive Loading, High to Low

Hard-Wired Wide-Decode Output

0.08 ns/pF

0.07 ns/pF

TLH

THL

0.045

t

0.07

ns

WDO

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

50

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32300DX Timing Characteristics

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays

Combinatorial Functions

t

Internal Array Module Delay

Internal Decode Module Delay

2.2

2.5

2.6

2.9

3.3

3.4

3.9

4.8

5.6

4.0

4.5

ns

PD

PDD

Predicted Module Routing Delays

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.1

1.7

2.4

2.9

5.2

0.6

1.4

2.0

2.8

3.6

6.2

0.7

1.5

2.3

3.1

3.9

7.0

0.8

1.8

2.7

3.7

4.6

8.2

0.9

2.5

3.8

5.2

6.5

10.0

1.3

2.1

3.2

4.3

5.4

9.6

1.0

ns

Sequential Timing Characteristics

t_CO

Flip-Flop Clock-to-Output

2.3

2.2

2.7

2.6

3.1

2.9

3.6

3.4

5.0

4.5

4.2

4.0

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset to Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

0.32

0.0

0.4

0.0

0.42

0.0

0.5

0.0

0.7

0.0

0.6

0.0

t_H

t_RO

2.2

2.6

3.0

3.5

5.0

4.1

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.6

0.0

3.1

0.75

0.0

0.9

0.0

4.2

1.0

0.0

4.9

1.4

0.0

7.0

1.1

0.0

5.7

3.7

Flip-Flop (Latch) Asynchronous Pulse

Width

3.5

4.1

4.7

5.5

7.9

6.4

ns

Discontinued – v3.0

51

Integrator Series FPGAs: 1200XL and 3200DX Families

A32300DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3 Speed

‘–2 Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Timing

Synchronous SRAM Operations

t_RC

Read Cycle Time

6.4

3.2

7.5

8.5

4.3

10.0

5.0

14.3

7.1

11.6

5.8

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock High/Low Time

Data Valid After Clock High/Low

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.75

3.2

3.75

4.3

5.0

7.1

5.8

1.5

0.0

0.6

3.2

2.6

0.0

2.6

0.0

1.8

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.3

7.1

5.7

0.0

5.9

0.0

2.82

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

0.68

3.75

3.0

1.05

5.8

Write Enable Set-Up

Write Enable Hold

4.7

0.0

Block Enable Set-Up

Block Enable Hold

2.3

4.8

0.0

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

7.7

9.0

10.2

12.0

17.2

14.1

ns

t_RDADV

t_ADSU

t_ADH

8.3

1.5

0.0

0.57

3.2

2.6

0.0

9.6

1.8

11.1

2.0

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.6

3.4

0.0

1.3

7.1

5.7

0.0

15.2

2.8

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

0.0

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

0.68

3.75

3.0

1.05

5.8

Write Enable Set-Up

4.7

Write Enable Hold

0.0

Data Out Hold Time

1.1

1.35

1.5

1.8

2.6

2.1

52

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

A32300DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t

Input Data Pad-to-Y

Input Latch

1.4

2.9

1.7

3.4

1.9

3.8

2.2

4.5

3.1

6.4

2.5

5.2

ns

INPY

INGO

1

Gate-to-Output

ns

1

t

Input Latch Hold

0.0

0.45

4.4

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.8

0.0

0.82

8.1

INH

INSU

ILA

1

Input Latch Set-Up

1

Latch Active Pulse Width

Input Module Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.9

2.5

3.3

3.9

5.0

0.6

2.3

2.9

2.6

3.3

4.4

5.2

6.7

0.8

3.0

3.9

5.2

6.1

7.9

0.9

4.2

5.5

7.4

8.7

11.2

1.3

3.5

4.6

ns

IRD1

IRD2

IRD3

IRD4

IRD5

RDD

3.9

6.1

4.6

7.2

6.0

9.2

0.67

1.05

Global Clock Network

t

Input Low to High

FO=32

FO=635

6.4

7.3

7.6

8.6

9.7

10.1

11.4

14.4

16.2

11.8

13.4

ns

CKH

FO=32

FO=635

6.6

7.1

7.7

8.4

8.8

9.5

10.3

11.2

14.7

16.0

12.1

13.1

ns

t

Input High to Low

CKL

FO=32

FO=635

3.0

3.3

3.5

3.8

4.0

4.3

4.7

5.1

6.7

7.2

5.5

6.0

ns

PWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

t

FO=32

FO=635

3.0

3.3

3.8

4.0

4.3

4.7

5.1

6.7

7.2

5.5

6.0

ns

PWL

FO=32

FO=635

0.6

0.75

0.9

1.0

1.4

1.17

ns

t

CKSW

Input Latch External

Set-Up

FO=32

FO=635

0.0

ns

SUEXT

t

f

FO=32

FO=635

2.2

2.7

2.6

3.2

2.9

3.7

3.4

4.3

4.9

6.1

4.0

5.0

ns

HEXT

P

Input Latch External Hold

Minimum Period (1/fmax)

FO=32

FO=635

5.5

6.1

6.9

7.7

7.4

8.2

9.3

10.2

13.2

14.5

10.9

12.0

ns

Maximum Datapath

Frequency

FO=32

FO=635

154

141

142

130

123

113

107

98

75

69

91

83

MHz

HMAX

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Discontinued – v3.0

53

Integrator Series FPGAs: 1200XL and 3200DX Families

A32300DX Timing Characteristics (continued)

(Worst-Case Commercial Conditions V

= 4.75 V, T = 70°C)

J

CC

3.3V ‘Std’

Speed

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

1

TTL Output Module Timing

t

Data-to-Pad High

3.7

4.4

4.8

5.1

8.3

4.3

5.4

4.3

5.2

4.9

5.9

5.8

6.9

7.7

8.1

8.2

9.8

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

5.6

6.4

7.5

8.8

10.7

11.4

18.5

9.6

ns

Enable-Pad Z to Low

6.0

6.8

8.0

9.4

ns

Enable-Pad High to Z

9.75

5.0

11.1

5.7

13.0

6.7

15.2

7.9

ns

Enable-Pad Low to Z

ns

G-to-Pad High

ns

G-to-Pad Low

6.3

7.1

8.4

7.9

12.0

ns

I/O Latch Output Set-Up

I/O Latch Output Hold

0.26

0.0

0.3

0.0

0.34

0.0

0.4

0.0

0.47

0.0

0.6

0.0

ns

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

8.4

9.7

13.9

0.3

11.1

15.7

0.34

0.4

13.1

18.5

0.4

15.4

21.8

0.47

0.58

0.058

18.7

26.5

0.6

ns

LCO

ACO

11.8

0.26

0.32

0.03

ns

d

ns/pF

ns

TLH

THL

0.37

0.037

0.5

0.7

t

Hard-Wired Wide-Decode Output

1

0.04

0.05

0.07

WDO

CMOS Output Module Timing

t

Data-to-Pad High

4.4

3.7

4.8

5.1

8.3

4.3

5.4

5.2

4.3

5.9

4.9

6.9

5.8

8.1

7.7

8.2

9.8

ns

DLH

DHL

ENZH

ENZL

ENHZ

ENLZ

GLH

GHL

LSU

Data-to-Pad Low

Enable-Pad Z to High

5.6

6.4

7.5

8.8

10.7

11.4

18.5

9.6

Enable-Pad Z to Low

6.0

6.8

8.0

9.4

Enable-Pad High to Z

9.75

5.0

11.1

5.7

13.0

6.7

15.2

7.9

Enable-Pad Low to Z

G-to-Pad High

G-to-Pad Low

6.3

7.1

8.4

9.9

12.0

I/O Latch Set-Up

0.26

0.0

0.3

0.0

0.34

0.0

0.4

0.0

0.47

0.0

0.6

0.0

I/O Latch Hold

LH

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

Capacitive Loading, Low to High

Capacitive Loading, High to Low

Hard-Wired Wide-Decode Output

9.9

11.6

16.4

0.37

0.3

13.2

18.5

0.4

15.5

21.8

0.5

17.6

25.6

0.6

22.3

31.2

LCO

ACO

13.9

0.32

0.26

0.03

d

0.10 ns/pF

0.09 ns/pF

TLH

THL

0.3

0.4

0.5

t

0.037

0.04

0.05

0.06

0.09

ns

WDO

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

54

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Pin Descriptions

CLKA, CLKB Clock A and Clock B (Input)

TTL clock inputs for clock distribution networks. The clock

input is buffered prior to clocking the logic modules. This

pin can also be used as an I/O.

PRB, I/O

Probe B (Output)

The Probe B pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin is used in conjunction with the

Probe A pin to allow real-time diagnostic output of any

signal path within the device. The Probe B pin can be used

as a user-defined I/O when debugging has been completed.

The pin’s probe capabilities can be permanently disabled to

protect programmed design confidentiality. PRB is active

when the MODE pin is HIGH. This pin functions as an I/O

when the MODE pin is LOW.

DCLK

Diagnostic Clock (Input)

TTL clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

GND

Ground (Input)

Input LOW supply voltage.

I/O

Input/Output (Input, Output)

QCLKA,B,C,D Quadrant Clock (Input/Output)

These four pins are the quadrant clock inputs. When not

used as a register control signal, these pins can function as

general purpose I/O.

I/O pin functions as an input, output, three-state or

bidirectional buffer. Input and output levels are compatible

with standard TTL and CMOS specifications. Unused I/O

pins are automatically driven LOW by the Designer Series

software for XL devices and are automatically tristated for

DX devices.

SDO

Serial Data (Output)

Serial data output for diagnostic probe and device

programming. SDO is active when the MODE pin is HIGH.

This pin functions as an I/O when MODE pin is LOW.

MODE

Mode (Input)

The MODE pin controls the use of multi-function pins

(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is HIGH,

the special functions are active. To provide ActionProbe

capability, the MODE pin should be terminated to GND

through a 10K resistor so the MODE pin can be pulled HIGH

when required.

SDI

Serial Data Input (Input)

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

TCK

Test Clock

Clock signal to shift the JTAG data into the device. This pin

functions as an I/O when the JTAG fuse is not programmed.

NC

No Connection

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

TDI

Test Data In

Serial data input for JTAG instructions and data. Data is

shifted in on the rising edge of TCLK. This pin functions as

an I/O when the JTAG fuse is not programmed.

PRA, I/O

Probe A (Output)

The Probe A pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin is used in conjunction with the

Probe B pin to allow real-time diagnostic output of any

signal path within the device. The Probe A pin can be used

as a user-defined I/O when debugging has been completed.

The pin's probe capabilities can be permanently disabled to

protect programmed design confidentiality. PRA is active

when the MODE pin is HIGH. This pin functions as an I/O

when the MODE pin is LOW.

TDO

Test Data Out

Serial data output for JTAG instructions and test data. This

pin functions as an I/O when the JTAG fuse is not

programmed.

TMS

Test Mode Select

Serial data input for JTAG test mode. Data is shifted in on

the rising edge of TCLK. This pin functions as an I/O when

the JTAG fuse is not programmed.

V

Supply Voltage (Input)

CC

Input HIGH supply voltage.

Note: TCK, TDI, TDO, TMS are only available on devices

containing JTAG circuitry.

Discontinued – v3.0

55

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments

84-Pin PLCC Package (Top View)

1

84

84-Pin

PLCC

56

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

84-Pin PLCC Package

A1240XL

Function

A3265DX

Function

Number

A1225XL

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

2

CLKB, I/O

PRB, I/O

I/O

CLKB, I/O

PRB, I/O

I/O

CLKB, I/O

PRB, I/O

I/O (WD)

GND

CLKB, I/O

PRB, I/O

I/O

CLKB, I/O

PRB, I/O

CLKB, I/O

PRB, I/O

I/O (WD)

GND

4

5

I/O (WD)

6

GND

7

I/O

QCLKC, I/O

I/O (WD)

I/O

8

I/O

I/O (WD)

DCLK, I/O

MODE (GND)

I/O

I/O (WD)

DCLK, I/O

MODE (GND)

9

I/O

I/O (WD)

10

12

22

23

28

34

35

36

37

38

39

43

44

45

46

47

49

50

51

52

62

63

64

65

70

76

78

79

80

81

83

84

DCLK, I/O

MODE (GND)

DCLK, I/O

MODE (GND)

DCLK, I/O

MODE (GND)

DCLK, I/O

MODE (GND)

V

CC

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

TMS, I/O

TDI, I/O

GND

TMS, I/O

TDI, I/O

I/O (WD)

I/O

I/O (WD)

QCLKA, I/O

I/O (WD)

I/O

I/O (WD)

V

CC

I/O

I/O (WD)

I/O

I/O (WD)

QCLKB, I/O

I/O (WD)

GND

I/O (WD)

GND

I/O

I/O (WD)

GND

I/O

GND

I/O

GND

I/O

GND

I/O

I/O (WD)

SDO, TDO, I/O

TCK, I/O

GND

I/O (WD)

SDO, TDO, I/O

TCK, I/O

GND

I/O

GND

V

CC

GND

SDI, I/O

I/O

GND

SDI, I/O

I/O

GND

SDI, I/O

I/O

GND

SDI, I/O

GND

SDI, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

SDI, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

I/O (WD)

QCLKD, I/O

PRA, I/O

CLKA, I/O

I/O

PRA, I/O

CLKA, I/O

PRA, I/O

CLKA, I/O

PRA, I/O

CLKA, I/O

V

CC

Notes:

1. I/O (WD): Denotes I/O pin with an associated wide-decode module

2. Wide-decode I/O (WD) can also be general purpose user I/O.

3. NC: Denotes ‘No Connection’.

4. All unlisted pin numbers are user I/O’s.

5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

Discontinued – v3.0

57

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

100-Pin PQFP Package, 100-Pin VQFP Package (Top View)

100-Pin

PQFP

100

1

100

1

100-Pin

VQFP

58

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

100-Pin PQFP Package, 100-Pin VQFP Package

A1225XL-

PQ100

Function

A1225XL-

VQ100

Function

A1240XL-

PQ100

Function

A3265DX

PQ100

Function

Pin Number

2

DCLK, I/O

MODE (GND)

DCLK, I/O

3

I/O

4

MODE (GND)

7

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

9

14

15

16

17

20

22

32

33

34

35

36

37

38

39

40

41

42

44

45

46

47

48

49

50

52

55

57

62

63

64

65

66

67

70

72

77

81

82

83

V

CC

I/O

V

I/O

V

CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

I/O (WD)

I/O

V

I/O

CC

I/O

V

CC

I/O

I/O (WD)

GND

I/O

GND

I/O

GND

I/O

GND

I/O

I/O (WD)

I/O

SDO, I/O

I/O

SDO, I/O

I/O

SDO, I/O

I/O

SDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V

I/O

CC

GND

V

CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

SDI, I/O

I/O

I/O (WD)

I/O

GND

I/O

Discontinued – v3.0

59

Integrator Series FPGAs: 1200XL and 3200DX Families

100-Pin PQFP Package, 100-Pin VQFP Package

A1225XL-

PQ100

Function

A1225XL-

VQ100

Function

A1240XL-

PQ100

Function

A3265DX

PQ100

Function

Pin Number

84

85

86

87

88

89

90

92

94

95

96

99

100

GND

I/O

PRA, I/O

I/O

GND

I/O

GND

I/O (WD)

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

PRA, I/O

I/O

V

CC

CLKA, I/O

I/O

CLKB, I/O

PRB, I/O

GND

CLKA, I/O

V

CC

CLKB, I/O

PRB, I/O

I/O

CLKB, I/O

PRB, I/O

I/O

CLKB, I/O

PRB, I/O

I/O (WD)

GND

I/O

GND

I/O

GND

I/O

I/O (WD)

I/O

DCLK, I/O

I/O

Notes:

1. NC: Denotes ‘No Connection’.

2. All unlisted pin numbers are user I/O’s.

3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

4. I/O (WD): Denotes I/O pin with an associated Wide-Decode Module

60

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

144-Pin PQFP Package (Top View)

144

1

144-Pin

PQFP

Discontinued – v3.0

61

Integrator Series FPGAs: 1200XL and 3200DX Families

144-Pin PQFP Package

Pin Number

A1240XL Function

Pin Number

A1240XL Function

2

9

MODE (GND)

GND

125

126

127

128

130

132

136

137

138

144

CLKA, I/O

V

CC

10

11

GND

18

19

20

21

28

29

30

44

45

46

54

55

64

65

79

80

81

88

89

90

91

92

100

101

102

110

116

117

118

123

V

CLKB, I/O

PRB, I/O

GND

CC

GND

DCLK, I/O

V

CC

GND

V

CC

GND

SDI, I/O

GND

PRA, I/O

Notes:

1. NC: Denotes ‘No Connection’.

2. All unlisted pin numbers are user I/O’s.

3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

62

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

160-Pin PQFP Package (Top View)

160

1

160-Pin

PQFP

Notes:

1.

I/O (WD): Denotes I/O pin with an associated wide-decode module

2. Wide-Decode I/O (WD) can also be general-purpose user I/O.

3. NC Denotes ‘No Connection’.

4. All unlisted pin numbers are user I/O’s.

5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

Discontinued – v3.0

63

Integrator Series FPGAs: 1200XL and 3200DX Families

160-Pin PQFP Package

Number

A3265DX

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

2

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK

DCLK, I/O

I/O (WD)

4

I/O (WD)

5

I/O (WD)

I/O

6

V

CC

7

I/O (WD)

GND

I/O

GND

I/O

11

12

13

14

16

18

20

21

23

24

25

26

28

29

30

31

33

34

35

36

37

38

40

44

49

54

57

58

59

60

61

62

64

69

80

82

83

84

86

87

88

89

90

GND

I/O

QCLKC, I/O

I/O (WD)

PRB, I/O

CLKB, I/O

I/O

I/O (WD)

PRB, I/O

CLKB, I/O

I/O

I/O (WD)

PRB, I/O

CLKB, I/O

I/O

PRB, I/O

CLKB, I/O

V

CC

CLKA, I/O

PRA, I/O

I/O

CLKA, I/O

PRA, I/O

I/O

CLKA, I/O

PRA, I/O

I/O (WD)

I/O

CLKA, I/O

PRA, I/O

I/O (WD)

I/O

I/O (WD)

I/O

QCLKD

I/O (WD)

GND

I/O

I/O (WD)

GND

I/O

I/O (WD)

GND

I/O

I/O (WD)

I/O

I/O (WD)

NC

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

V

CC

I/O (WD)

I/O

I/O (WD)

SDI, I/O

GND

I/O (WD)

SDI, I/O

GND

SDI, I/O

GND

SDI, I/O

GND

V

CC

GND

V

CC

GND

I/O

GND

I/O

GND

TCK, I/O

GND

TCK, I/O

GND

I/O

GND

I/O

GND

SDO, I/O

I/O (WD)

SDO, TDO, I/O

I/O (WD)

I/O

V

CC

I/O (WD)

GND

I/O

I/O (WD)

GND

I/O (WD)

GND

I/O

I/O (WD)

I/O

64

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

160-Pin PQFP Package (Continued)

Number

A3265DX

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

91

92

I/O

QCLKB, I/O

I/O

I/O (WD)

I/O

93

I/O

95

I/O (WD)

I/O

96

I/O (WD)

I/O

97

98

V

CC

99

GND

I/O (WD)

GND

I/O

GND

I/O (WD)

GND

I/O (WD)

GND

106

107

109

110

111

112

114

115

116

118

119

120

125

130

135

138

139

140

145

150

155

159

160

I/O

GND

I/O

QCLKA, I/O

I/O

I/O (WD)

I/O

I/O (WD)

I/O

V

CC

I/O

I/O (WD)

TDI, I/O

TMS, I/O

GND

I/O (WD)

TDI, I/O

TMS, I/O

GND

I/O

GND

V

CC

GND

V

CC

GND

MODE (GND)

GND

MODE (GND)

GND

MODE (GND)

GND

MODE (GND)

GND

Discontinued – v3.0

65

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

208-Pin PQFP Package, 208-Pin RQFP Package (Top View)

208

1

208-Pin PQFP

208-Pin RQFP

Notes:

1.

I/O (WD): Denotes I/O pin with an associated wide-decode module.

2. Wide-Decode I/O (WD) can also be general purpose user I/O.

3. NC: Denotes ‘No Connection’.

4. All unlisted pin numbers are user I/O’s.

5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

6. RQFP has an exposed circular metal heat sink on the top surface.

66

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

208-Pin PQFP Package, 208-Pin RQFP Package

A1280XL

Function

A32100DX

Function

A32200DX-

PQ208 Function

A32200DX-

RQ208 Function

A32300DX

Function

Pin Number

A32140DX Function

1

GND

I/O

2

NC

V

CC

DCLK, I/O

I/O

DCLK, I/O

I/O

CC

3

MODE (GND)

5

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

I/O (WD)

6

7

V

CC

9

I/O

10

11

13

15

16

17

19

20

22

24

26

27

28

29

30

32

33

38

40

41

42

43

45

47

48

50

51

52

53

54

55

57

58

59

60

61

62

65

66

67

68

70

71

74

77

78

I/O

QCLKC, I/O

I/O (WD)

I/O

QCLKC, I/O

I/O (WD)

I/O

V

CC

I/O

I/O (WD)

PRB, I/O

CLKB, I/O

GND

I/O (WD)

PRB, I/O

CLKB, I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

V

CC

V

I/O

CLKA, I/O

PRA, I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

I/O

CLKA, I/O

PRA, I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

I/O

CC

I/O

V

CC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V

CC

I/O

I/O (WD)

SDI, I/O

I/O

I/O (WD)

SDI, I/O

I/O

NC

GND

I/O

NC

I/O

NC

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

TMS, I/O

TDI, I/O

I/O (WD)

I/O

GND

TMS, I/O

TDI, I/O

I/O (WD)

I/O

GND

I/O

GND

I/O

I/O (WD)

I/O

GND

I/O

GND

I/O

V

CC

NC

I/O

QCLKA, I/O

I/O

QCLKA, I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

NC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

V

CC

I/O

GND

Discontinued – v3.0

67

Integrator Series FPGAs: 1200XL and 3200DX Families

208-Pin PQFP Package, 208-Pin RQFP Package (Continued)

A1280XL

Function

A32100DX

Function

A32200DX-

PQ208 Function

A32200DX-

RQ208 Function

A32300DX

Function

Pin Number

A32140DX Function

79

80

V

CC

NC

I/O

NC

I/O

NC

GND

TCK, I/O

GND

I/O

GND

TCK, I/O

GND

I/O

CC

81

I/O

83

85

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

86

I/O

89

I/O

90

I/O

91

QCLKB, I/O

I/O (WD)

I/O

QCLKB, I/O

I/O (WD)

I/O

93

I/O (WD)

I/O

94

I/O

95

I/O

96

NC

I/O

97

NC

I/O

98

V

CC

I/O

CC

100

101

103

104

105

106

107

108

110

112

113

114

115

117

121

122

126

127

128

129

130

131

132

133

136

137

138

141

142

144

146

147

148

149

150

151

152

154

I/O

I/O (WD)

SDO, I/O

I/O

I/O (WD)

SDO, TDO, I/O

I/O

I/O (WD)

SDO, TDO, I/O

I/O

V

CC

I/O

GND

I/O

GND

I/O

GND

NC

I/O

GND

V

CC

SDO, TDO, I/O

I/O (WD)

SDO, TDO, I/O

I/O (WD)

CC

I/O

V

CC

NC

I/O

NC

I/O

NC

I/O

NC

I/O

I/O (WD)

QCLKB, I/O

I/O (WD)

I/O

I/O (WD)

QCLKB, I/O

I/O (WD)

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

TCK, I/O

GND

TCK, I/O

GND

TCK, I/O

GND

I/O

GND

V

CC

V

CC

GND

I/O

GND

I/O

CC

GND

V

I/O

CC

I/O

GND

I/O

GND

I/O

I/O (WD)

QCLKA, I/O

I/O

I/O (WD)

QCLKA, I/O

I/O

NC

I/O

NC

GND

I/O

NC

GND

I/O

V

CC

I/O

I/O (WD)

TDI, I/O

I/O (WD)

TDI, I/O

I/O

68

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

208-Pin PQFP Package, 208-Pin RQFP Package (Continued)

A1280XL

Function

A32100DX

Function

A32200DX-

PQ208 Function

A32200DX-

RQ208 Function

A32300DX

Function

Pin Number

A32140DX Function

155

156

157

159

161

162

164

165

166

168

169

171

176

177

178

180

181

182

183

184

186

187

188

190

191

193

194

195

196

197

201

202

203

204

206

207

208

I/O

TMS, I/O

GND

TMS, I/O

GND

I/O

GND

SDI, I/O

I/O

GND

V

CC

SDI, I/O

I/O (WD)

SDI, I/O

I/O (WD)

SDI, I/O

I/O (WD)

I/O

V

CC

NC

I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

I/O

I/O (WD)

I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

I/O

NC

I/O

I/O (WD)

PRA, I/O

CLKA, I/O

I/O

PRA, I/O

CLKA, I/O

NC

V

CC

I/O

V

CC

NC

V

CC

V

I/O

CC

GND

CLKB, I/O

I/O

GND

CLKB

I/O

GND

CLKB, I/O

I/O

GND

CLKB, I/O

I/O

GND

I/O

GND

PRB, I/O

I/O

PRB, I/O

I/O (WD)

I/O

PRB, I/O

I/O (WD)

I/O

PRB, I/O

I/O (WD)

I/O

NC

I/O

NC

I/O (WD)

I/O

I/O (WD)

QCLKC, I/O

I/O

NC

I/O

QCLKC, I/O

NC

I/O

NC

I/O

NC

I/O

V

CC

I/O

CC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

MODE

MODE (GND)

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

V

CC

GND

Discontinued – v3.0

69

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

240-Pin RQFP Package (Top View)

Exposed

Heatsink

240

1

•

240-Pin

RQFP

•

Notes:

1. I/O (WD): Denotes I/O pin with an associated wide-decode module.

2. Wide-Decode I/O (WD) can also be general purpose user I/O.

3. NC: Denotes ‘No Connection.’

4. All unlisted pin numbers are user I/O’s.

5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

6. RQFP has an exposed circular metal heat sink on the top surface.

70

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

240-Pin RQFP Package

A32300DX

Function

A32300DX

Function

A32200DX Function

Pin Number

A32200DX Function

2

DCLK, I/O

I/O (WD)

DCLK, I/O

I/O (WD)

120

121

123

125

126

128

132

133

135

142

143

147

148

150

151

152

159

160

163

164

166

172

174

175

178

179

180

181

182

192

206

209

210

219

227

237

238

239

240

GND

6

GND

SDO, TDO, I/O

I/O (WD)

7

SDO, TDO, I/O

I/O (WD)

8

V

CC

15

17

18

21

22

24

26

28

29

30

32

33

34

37

38

45

47

48

52

54

55

57

59

60

61

71

85

88

89

90

91

92

94

108

118

119

QCLKC, I/O

I/O (WD)

PRB, I/O

CLKB, I/O

GND

QCLKC, I/O

I/O (WD)

PRB, I/O

CLKB, I/O

GND

I/O (WD)

V

CC

I/O (WD)

QCLKB, I/O

I/O (WD)

I/O

I/O (WD)

QCLKB, I/O

I/O (WD)

V

I/O

CC

V

CC

CLKA, I/O

I/O

CLKA, I/O

I/O (WD)

PRA, I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

GND

PRA, I/O

I/O (WD)

QCLKD, I/O

I/O (WD)

QCLKA, I/O

I/O (WD)

QCLKA, I/O

V

CC

V

I/O (WD)

TDI, I/O

TMS, I/O

GND

I/O (WD)

TDI, I/O

TMS, I/O

GND

CC

I/O (WD)

SDI, I/O

I/O (WD)

SDI, I/O

V

CC

GND

V

CC

GND

V

CC

GND

TCK, I/O

GND

TCK, I/O

GND

MODE (GND)

V

CC

GND

Discontinued – v3.0

71

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

176-Pin TQFP Package (Top View)

176

1

176-Pin

TQFP

Notes:

1. I/O (WD): Denotes I/O pin with an associated wide-decode module.

2. Wide-Decode I/O (WD) can also be general-purpose user I/O.

3. NC: Denotes ‘No Connection.’

4. All unlisted pin numbers are user I/O’s.

5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise it can be terminated directly to GND.

72

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

176-pin TQFP Package

A1240XL

Function

A3265DX

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

Pin Number

1

GND

MODE

NC

GND

MODE

NC

GND

MODE

NC

GND

MODE

NC

GND

MODE

I/O

2

8

10

11

13

18

19

20

22

23

24

25

26

27

28

29

33

37

38

45

46

47

48

49

50

51

52

54

55

56

57

59

60

61

64

66

67

68

69

70

72

73

74

75

76

77

78

79

80

NC

I/O

NC

I/O

NC

V

CC

GND

NC

GND

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

GND

NC

GND

V

CC

V

CC

NC

I/O

V

CC

NC

I/O

NC

GND

I/O

NC

GND

I/O

NC

I/O

NC

I/O

NC

GND

I/O

NC

I/O

GND

TMS, I/O

TDI, I/O

I/O

TMS, I/O

TDI, I/O

I/O

NC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

V

CC

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

NC

I/O

QCLKA, I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

GND

I/O

GND

V

CC

I/O

NC

I/O

NC

I/O

NC

I/O (WD)

I/O

NC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

NC

I/O

I/O (WD)

I/O

QCLKB, I/O

I/O

NC

I/O (WD)

I/O

NC

I/O (WD)

NC

I/O

I/O (WD)

I/O

Discontinued – v3.0

73

Integrator Series FPGAs: 1200XL and 3200DX Families

176-pin TQFP Package (Continued)

A1240XL

Pin Number

A3265DX

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

81

I/O

NC

I/O (WD)

I/O

82

V

CC

84

I/O

I/O (WD)

I/O

I/O (WD)

I/O

85

I/O

86

NC

I/O

87

I/O

SDO, TDO, I/O

GND

SDO, TDO, I/O

GND

89

GND

NC

GND

NC

GND

I/O

96

I/O

97

NC

I/O

101

103

106

107

108

109

110

111

112

113

114

115

116

117

121

124

125

126

133

135

136

137

138

139

140

141

142

143

144

145

146

147

149

150

151

152

154

155

156

158

160

NC

I/O

NC

I/O

NC

I/O

GND

NC

GND

I/O

GND

I/O

GND

I/O

NC

I/O

TCK, I/O

GND

TCK, I/O

GND

V

CC

GND

V

CC

V

NC

I/O

NC

V

CC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

SDI, I/O

NC

GND

SDI, I/O

NC

GND

SDI, I/O

I/O

GND

SDI, I/O

I/O

GND

SDI, I/O

I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

V

CC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

NC

I/O (WD)

NC

I/O

I/O (WD)

I/O

NC

I/O

I/O (WD)

I/O

QCLKD, I/O

I/O

NC

I/O

I/O (WD)

I/O

I/O (WD)

PRA, I/O

CLKA, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

NC

I/O

PRA, I/O

CLKA, I/O

PRA, I/O

CLKA, I/O

PRA, I/O

CLKA, I/O

V

CC

GND

CLKB, I/O

PRB, I/O

CLKB, I/O

PRB, I/O

CLKB, I/O

PRB, I/O

CLKB, I/O

PRB, I/O

CLKB, I/O

PRB, I/O

74

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

176-pin TQFP Package (Continued)

A1240XL

Function

A3265DX

Function

A1280XL

Function

A32100DX

Function

A32140DX

Function

Pin Number

161

162

163

164

165

166

168

169

170

171

172

173

175

NC

I/O

I/O (WD)

I/O

NC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

QCLKC, I/O

NC

I/O

NC

I/O (WD)

I/O

NC

I/O

NC

I/O

I/O (WD)

I/O

NC

V

CC

I/O

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

DCLK, I/O

Discontinued – v3.0

75

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

100-Pin CPGA (Top View)

1

2

3

4

5

6

7

8

9

10 11

A

B

C

D

E

F

G

H

J

A

B

C

D

E

F

G

H

J

100-Pin

CPGA

K

L

K

L

1

2

3

4

5

6

7

8

9

10 11

Orientation Pin

Signal

Pad Number

Location

PRA or I/O

PRB or I/O

MODE

85

92

2

A7

A4

C2

C8

C3

C6

D6

SDI or I/O

DCLK or I/O

CLKA or I/O

CLKB or I/O

GND

77

100

87

90

7, 20, 32, 44, 55, 70, 82, 94

15, 38, 64, 88

E3, G3, J5, J7, G9, F11, D10, C7, C5

F3, G1, K6, F9, F10, E11, B6

V

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE = GND, except during device programming or debugging.

76

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

132-Pin CPGA (Top View)

1

2

3

4

5

6

7

8

9

10 11 12 13

A

B

C

D

E

F

A

B

C

D

E

F

132-Pin

CPGA

G

H

J

G

H

J

K

L

K

L

M

N

M

N

1

2

3

4

5

6

7

8

9

10 11 12 13

Orientation Pin

Signal

Pad Number

Location

PRA or I/O

PRB or I/O

MODE

113

121

2

B8

C6

A1

SDI or I/O

DCLK or I/O

CLKA or I/O

CLKB or I/O

GND

101

132

115

119

B12

C3

B7

B6

9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, 107, 108, 125, 126

18, 19, 49, 50, 83, 84, 116, 117

E3, F4, J2, J3, L5, L9, M9, K12, J11, H13, E12, E11, C9, B9, B5, C5

G3, G2, G4, L7, K7, G10, G11, G12, G13, D7, C7

V

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE = GND, except during device programming or debugging.

Discontinued – v3.0

77

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

176-Pin CPGA (Top View)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

176-Pin

CPGA

K

L

K

L

M

N

P

R

M

N

P

R

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Signal

Pad Number

Location

PRA or I/O

PRB or I/O

MODE

152

160

2

C9

D7

C3

B14

B3

SDI or I/O

DCLK or I/O

CLKA or I/O

CLKB or I/O

GND

135

175

154

158

A9

B8

1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89

101, 106, 111, 121, 126, 133, 145, 156, 165

D4, E4, G4, H4, K4, L4, M4, M6, M8, M10, M12

K12, J12, J13, H12, F12, E12, D12, D10, C8, D6

V

CC

13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170

F4, H2, H3, J4, M5, N8, M11, J14, H13, H14, G12, D11, D8, D5

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE = GND, except during device programming or debugging.

78

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

84-Pin CQFP

84

Pin #1

Index

1

84-Pin

CQFP

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE = GND, except during device programming or debugging.

Discontinued – v3.0

79

Integrator Series FPGAs: 1200XL and 3200DX Families

84-pin CQFP Package

Pin Number

A32100DX Function

Pin Number

A32100DX Function

1

GND

74

76

77

78

79

80

81

82

83

84

V

CC

2

MODE (GND)

CLKB, I/O

PRB, I/O

I/O (WD)

QCLKC, I/O

GND

7

V

CC

10

11

12

17

22

23

24

25

26

28

30

32

33

34

35

36

37

38

39

40

41

42

43

50

51

52

53

55

56

59

63

64

65

66

67

68

69

70

71

72

73

GND

V

CC

V

(V

)

CC

SV

GND

I/O (WD)

DCLK, I/O

TMS, I/O

TDI, I/O

I/O (WD)

QCLKA, I/O

I/O (WD)

GND

V

CC

I/O (WD)

QCLKB, I/O

I/O (WD)

GND

I/O (WD)

SDO, I/O

GND

TCK, I/O

VKS (GND)

V

(V

)

PP

SV

CC

)

V

CC

GND

SDI

I/O (WD)

QCLKD, I/O

I/O (WD)

PRA, I/O

CLKA, I/O

80

Discontinued – v3.0

Integrator Series FPGAs: 1200XL and 3200DX Families

Package Pin Assignments (continued)

172-Pin CQFP

172

Pin #1

Index

1

172-Pin

CQFP

Signal

Pad Number

CLKA or I/O

CLKB or I/O

DCLK or I/O

150

154

171

GND

7, 17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 118, 123, 141, 152, 161

MODE

1

PRA or I/O

PRB or I/O

SDI or I/O

148

156

131

V

12, 23, 24, 27, 50, 66, 80, 107, 109, 110, 113, 136, 151, 166

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven LOW.

2. All unassigned pins are available for use as I/Os.

3. MODE = GND, except during device programming or debugging.

Discontinued – v3.0

81

Integrator Series FPGAs: 1200XL and 3200DX Families

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous version

Changes in current version (v3.0)

Page

Because the changes in this data sheet are extensive and technical in nature—due to the elimination of 32400DX

product—this should be viewed as a new document. Please read it as you would a data sheet that is published for

the first time. Note that the “Package and Mechanical Drawings” section has been eliminated from the data sheet

and can now be found on the Actel web site.

ALL

Unspecified

Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated from the data sheet.

The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical

Drawings,” available on the Actel web site.

Data Sheet Categories

In order to provide the latest information to designers, some data sheets are published before data has been fully

characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories

are as follows:

Advanced

The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This

information can be used as estimates, but not for production.

Preliminary

The data sheet contains information based on simulation and/or initial characterization. The information is believed to be

correct, but changes are possible.

Unmarked (production)

The data sheet contains information that is considered to be final.

82

Discontinued – v3.0

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Europe Ltd.

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

USA

Actel Asia-Pacific

Daneshill House, Lutyens Close

Basingstoke, Hampshire RG24 8AG

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: +44 (0)1256 305600

Fax: +44 (0)1256 355420

Tel: (408) 739-1010

Fax: (408) 739-1540

Tel: +81 03-3445-7671

Fax: +81 03-3445-7668

5172135-1/2.01

Integrator Series FPGAs: 1200XL and 3200DX Families

84

Discontinued – v3.0


型号：	A32100XLV-FPQB
厂家：	Actel Corporation
描述：	Integrator Series FPGAs: 1200XL and 3200DX Families 集成系列FPGA ： 1200XL和3200DX家庭
文件：	总84页 (文件大小：3116K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A32100XLV-FPQB [ACTEL]

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