A3P1000-1FGG144T_技术文档

1 – Automotive ProASIC3 Device Family Overview

General Description

Automotive ProASIC3 nonvolatile flash technology gives automotive system designers the

advantage of a secure, low-power, single-chip solution that is live at power-up (LAPU). Automotive

ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These

features enable designers to create high-density systems using existing ASIC or FPGA design flows

and tools.

Automotive ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM

storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL).

Automotive ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of

SRAM and up to 300 user I/Os.

Automotive ProASIC3 devices are the only firm-error-immune automotive grade FPGAs. Firm-error

immunity makes them ideally suited for demanding applications in powertrain, safety, and

telematics-based subsystems, where firm-error failure is not an option.

Firm errors in SRAM-based FPGAs can result in high defect levels in field-deployed systems. These

unavoidable defects must be considered separately from standard defects and failure mechanisms

when looking at overall system quality and reliability.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based Automotive ProASIC3 devices allow all functionality to be live at

power-up; no external boot PROM is required. On-board security mechanisms prevent access to all

the programming information and enable secure remote updates of the FPGA logic. Flash-based

FPGAs are LAPU Class 0 devices, offering the lowest available power in a single-chip device and

providing firm-error immunity. The Automotive ProASIC3 family device architecture mitigates the

need for ASIC migration at high user volumes. This makes the Automotive ProASIC3 family a cost-

effective ASIC replacement solution, especially for automotive applications.

Security

The nonvolatile, flash-based Automotive ProASIC3 devices do not require a boot PROM, so there is

no vulnerable external bitstream that can be easily copied. Automotive ProASIC3 devices

incorporate FlashLock, which provides a unique combination of reprogrammability and design

security without external overhead, advantages that only an FPGA with nonvolatile flash

programming can offer.

Automotive ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in

Automotive ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-

128 (FIPS192) bit block cipher encryption standard. The AES was adopted by the National Institute

of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Automotive

ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them

the most comprehensive programmable logic device security solution available today. Automotive

ProASIC3 devices with AES-based security allow for secure, remote field updates over public

networks such as the Internet, and ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves. The contents of a programmed Automotive ProASIC3

device cannot be read back, although secure design verification is possible. Additionally, security

features of Automotive ProASIC3 devices provide anti-tampering protection.

Security, built into the FPGA fabric, is an inherent component of the Automotive ProASIC3 family.

The flash cells are located beneath seven metal layers, and many device design and layout

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1-1

Automotive ProASIC3 Device Family Overview

techniques have been used to make invasive attacks extremely difficult. The Automotive ProASIC3

family, with FlashLock and AES security, is unique in being highly resistant to both invasive and

noninvasive attacks. Your valuable IP is protected and secure. An Automotive ProASIC3 device

provides the most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

Automotive ProASIC3 FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based Automotive ProASIC3 devices support Level 0 of the LAPU classification

standard. This feature helps in system component initialization, execution of critical tasks before

the processor wakes up, setup and configuration of memory blocks, clock generation, and bus

activity management. The LAPU feature of flash-based Automotive ProASIC3 devices greatly

simplifies total system design and reduces total system cost, often eliminating the need for CPLDs

and external clock generation PLLs. In addition, glitches and brownouts in system power will not

corrupt the Automotive ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the

device will not have to be reloaded when system power is restored. This enables the reduction or

complete removal of the configuration PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-based Automotive ProASIC3 devices

simplify total system design and reduce cost and design risk while increasing system reliability and

improving system initialization time.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of Automotive

ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of

Automotive ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune

to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can

easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA

fabric.

Low Power

Flash-based Automotive ProASIC3 devices exhibit very low power characteristics, similar to those of

an ASIC, making them an ideal choice for power-sensitive applications. Automotive ProASIC3

devices have only a very limited power-on current surge and no high-current transition period,

both of which occur on many FPGAs.

Automotive ProASIC3 devices also have low dynamic power consumption to further maximize

power savings.

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Automotive ProASIC3 Flash FPGAs

Advanced Flash Technology

The Automotive ProASIC3 family offers many benefits, including nonvolatility and

reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of

metal. Standard CMOS design techniques are used to implement logic and control functions. The

combination of fine granularity, enhanced flexible routing resources, and abundant flash switches

allows for very high logic utilization without compromising device routability or performance.

Logic functions within the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary Automotive ProASIC3 architecture provides granularity comparable to standard-

cell ASICs. The Automotive ProASIC3 device consists of five distinct and programmable architectural

features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM memory

Extensive CCCs and PLLs

Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the Automotive ProASIC3 core tile as either a three-

input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of Automotive ProASIC3 devices via an IEEE 1532 JTAG interface.

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Automotive ProASIC3 Device Family Overview

Bank 0

CCC

RAM Block

4,608-Bit SRAM

or FIFO Block

I/Os

VersaTile

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Bank 1

Figure 1-1 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125)

Bank 0

CCC

RAM Block

4,608-Bit SRAM

or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit SRAM

or FIFO Block

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

(A3P600 and A3P1000)

Bank 2

Figure 1-2 • Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P600 and A3P1000)

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Automotive ProASIC3 Flash FPGAs

VersaTiles

The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the

ProASIC^PLUS®core tiles. The Automotive ProASIC3 VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

User Nonvolatile FlashROM

Actel Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM.

The FlashROM can be used in diverse system applications:

•

Unique protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, infotainment systems)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard Automotive ProASIC3 IEEE 1532 JTAG programming

interface.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel Automotive ProASIC3 development software solutions, Libero^®Integrated Design

Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is

auto-generation of sequential programming files for applications requiring a unique serial number

in each part. Another feature allows the inclusion of static data for system version control. Data for

the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software

tools. Comprehensive programming file support is also included to allow for easy programming of

large numbers of parts with differing FlashROM contents.

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Automotive ProASIC3 Device Family Overview

SRAM

Automotive ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each

variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that

can be configured with different bit widths on each port. For example, data can be sent through a

4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the

device JTAG port (ROM emulation mode) using the UJTAG macro.

PLL and CCC

Automotive ProASIC3 devices provide designers with very flexible clock conditioning circuit (CCC)

capabilities. Each member of the Automotive ProASIC3 family contains six CCCs. One CCC (center

west side) has a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One

CCC (center west side) has a PLL.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

2 programmable delay types for clock skew minimization

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

•

Output duty cycle = 50% 1.5% or better (for PLL only)

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

•

Maximum acquisition time is 300 µs (for PLL only)

Low power consumption of 5 mW

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL

only)

•

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 350 MHz /

f_{OUT_CCC}(for PLL only)

Global Clocking

Automotive ProASIC3 devices have extensive support for multiple clocking domains. In addition to

the CCC and PLL support described above, there is a comprehensive global clock distribution

network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The Automotive ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of

voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3 FPGAs support many different I/O

standards—single-ended and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these

banks determines the I/O standards supported.

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Automotive ProASIC3 Flash FPGAs

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications

Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

Automotive ProASIC3 banks for the A3P250 and A3P1000 devices support LVPECL, LVDS, B-LVDS,

and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads.

Part Number and Revision Date

Part Number 51700099-001-0

Revised January 2008

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Automotive ProASIC3 Device Family Overview

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

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Automotive ProASIC3 DC and Switching Characteristics

2 – Automotive ProASIC3 DC and Switching

Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximums are stress ratings only; functional operation of the device at these or any other

conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-

2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

V_CC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

V

V_JTAG

–0.3 to 3.75

V_PUMPProgramming voltage

–0.3 to 3.75

V_CCPLLAnalog power supply (PLL)

–0.3 to 1.65

V_CCI

VMV

VI

DC I/O output buffer supply voltage

–0.3 to 3.75

DC I/O input buffer supply voltage

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (V_CCI+ 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

2

T_STG

Storage temperature

Junction temperature

–65 to +150

+150

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-3 on page 2-3.

2. For flash programming and retention maximum limits, refer to Figure 2-1 on page 2-2. For recommended

operating limits, refer to Table 2-2 on page 2-2.

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Automotive ProASIC3 DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions

Symbol

T_J

Parameter

Junction temperature

Automotive Grade 1 Automotive Grade 2 Units

–40 to +135

1.425 to 1.575

1.4 to 3.6

–40 to +115

1.425 to 1.575

1.4 to 3.6

°C

V

V_CC

1.5 V DC core supply voltage

JTAG DC voltage

V_JTAG

V_PUMP

Programming voltage Programming Mode

Operation³

3.0 to 3.6

0 to 3.6

V_CCPLL

Analog power supply (PLL)

1.4 to 1.6

V_CCIand VMV 1.5 V DC supply voltage

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS/B-LVDS/M-LVDS differential I/O

LVPECL differential I/O

2.3 to 2.7

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-14 on page 2-16. VMV and V_CCIshould be at the same voltage within a

given I/O bank.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. V_PUMPcan be left floating during operation (not programming mode).

110

100

HTR

Lifetime

Tj (°C)

(yrs)

90

80

70

60

50

40

30

20

10

0

70

85

102.7

43.8

20.0

15.6

100

105

110

115

120

125

130

12.3

9.7

7.7

6.2

5.0

135

140

145

150

4.0

3.3

2.7

2.2

70 85 100 105 110 115 120 125 130 135 140 145 150

Temperature (ºC)

Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.

Figure 2-1 • High-Temperature Data Retention (HTR)

2-2

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Automotive ProASIC3 DC and Switching Characteristics

Table 2-3 • Overshoot and Undershoot Limits (as measured on quiet I/Os)

Average V_CCI–GND Overshoot or Undershoot Maximum Overshoot/ Maximum Overshoot/

V_CCIand VMV

Duration as a Percentage of Clock Cycle

Undershoot (115°C)

Undershoot (135°C)

2.7 V or less

10%

5%

0.81 V

0.72 V

0.90 V

0.82 V

3 V

10%

5%

0.80 V

0.72 V

0.90 V

0.81 V

3.3 V

10%

5%

0.79 V

0.69 V

0.88 V

0.79 V

3.6 V

10%

5%

N/A

Notes:

1. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the

overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be

reduced by 0.15 V.

2. This table refers only to overshoot/undershoot limits for simultaneously switching I/Os and does not

provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-2 on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. V_CCand V_CCIare above the minimum specified trip points (Figure 2-2 on page 2-4).

2. V_CCI> V_CC– 0.75 V (typical)

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

V_CCTrip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

V_CCand V_CCIramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

•

During programming, I/Os become tristated and weakly pulled up to V_CCI.

JTAG supply, PLL power supplies, and charge pump V_PUMPsupply have no influence on I/O

behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

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Automotive ProASIC3 DC and Switching Characteristics

V

= V + VT

CCI

CC

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V

CC

V

= 1.575 V

CC

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

V

= 1.425 V

CC

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

= 0.85 V 0.25 V

V

a

Deactivation trip point:

= 0.75 V 0.25 V

Region 1: I/O buffers are OFF

V

d

V

Activation trip point:

= 0.9 V 0.3 V

CCI

Min V datasheet specification

CCI

V

voltage at a selected I/O

a

Deactivation trip point:

= 0.8 V 0.3 V

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

V

d

Figure 2-2 • I/O State as a Function of V_CCIand V_CCVoltage Levels

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

T_J= Junction Temperature = ΔT + T_A

EQ 2-1

where:

T_A= Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ_ja* P

θ_ja= Junction-to-ambient of the package. θ_janumbers are located in Table 2-4 on

page 2-5.

P = Power dissipation

2-4

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Automotive ProASIC3 DC and Switching Characteristics

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ_jcand the junction-to-ambient air thermal

resistivity is θ_ja. The thermal characteristics for θ_jaare shown for two air flow rates. The absolute

maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

Max. junction temp. (°C) – Max. ambient temp. (°C)

110°C – 70°C

20.5°C/W

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1. 95 1 W

θ_ja(°C/W)

EQ 2-2

Table 2-4 • Package Thermal Resistivities

θ_ja

Still

200

500

Package Type

Device

Count θ_jc

Air ft./min. ft./min. Units

Very Thin Quad Flat Pack (VQFP)

Fine Pitch Ball Grid Array (FBGA)

All devices

See note*

A3P1000

100

144

256

484

144

256

484

10.0 35.3

29.4

22.9

22.8

17.0

26.2

24.4

19.0

27.1

21.5

15.9

24.2

22.7

16.7

°C/W

3.8 26.9

3.8 26.6

3.2 20.5

6.3 31.6

6.6 28.1

8.0 23.3

* This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package

thermal information will be available in future revisions of the datasheet.

Temperature and Voltage Derating Factors

Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 115°C, V_CC= 1.425 V)

Array Voltage V_CC(V)

–40°C

0.83

0.79

0.76

0°C

0.88

0.83

0.80

25°C

0.90

0.85

0.82

70°C

0.95

0.90

0.87

85°C

0.97

0.92

0.88

115°C

1.00

0.95

0.91

125°C

1.01

0.96

0.93

135°C

1.02

0.97

0.94

1.425

1.5

1.575

v1.0

2-5

Automotive ProASIC3 DC and Switching Characteristics

Calculating Power Dissipation

Quiescent Supply Current

Table 2-6 • Quiescent Supply Current Characteristics

A3P060

2 mA

A3P125

2 mA

A3P250

3 mA

A3P1000

8 mA

Typical (25°C)

Maximum (Automotive Grade 1) – 135°C

Maximum (Automotive Grade 2) – 115°C

53 mA

26 mA

53 mA

26 mA

106 mA

53 mA

265 mA

131 mA

Note: I_DDIncludes V_CC, V_PUMP, V_CCI, and VMV currents. Values do not include I/O static

contribution, which is shown in Table 2-7 and Table 2-10 on page 2-8.

Power per I/O Pin

Table 2-7 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

P

Dynamic Power

P_AC9(µW/MHz)²

VMV (V)

_DC2(mW)¹

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.69

5.12

2.13

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Notes:

1. P_DC2is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on V_CCand VMV.

2-6

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

P

Dynamic Power

P

_AC9(µW/MHz)²

VMV (V)

_DC2(mW)¹

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.72

5.14

2.13

1.48

18.13

3.3 V PCI-X

Notes:

1. P_DC2is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on V_CCand VMV.

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

P_DC3(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C

_LOAD(pF)

V_CCI(V)

Single-Ended

3.3 V LVTTL /

35

3.3

–

468.67

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

35

2.5

1.8

1.5

–

267.48

149.46

103.12

1.5 V LVCMOS

(JESD8-11)

3.3 V PCI

3.3 V PCI-X

Differential

LVDS

10

3.3

–

201.02

–

2.5

3.3

7.74

88.92

LVPECL

19.54

166.52

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. P_DC3is the static power (where applicable) measured on VMV.

3. P_AC10is the total dynamic power measured on V_CCIand VMV.

v1.0

2-7

Automotive ProASIC3 DC and Switching Characteristics

Table 2-10 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

P_DC3(mW)²

Dynamic Power

P

C_LOAD(pF)

V_CCI(V)

_AC10(µW/MHz)³

Single-Ended

3.3 V LVTTL /

35

3.3

–

452.67

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

35

2.5

1.8

1.5

–

258.32

133.59

92.84

1.5 V LVCMOS

(JESD8-11)

3.3 V PCI

3.3 V PCI-X

Notes:

10

3.3

–

184.92

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. P_DC3is the static power (where applicable) measured on VMV.

3. P_AC10is the total dynamic power measured on V_CCIand VMV.

2-8

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Device Specific Dynamic Power

(µW/MHz)

Parameter

P_AC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3P1000 A3P250 A3P125 A3P060

14.50

2.48

11.00

1.58

11.00

0.81

9.30

0.81

P_AC2

P_AC3

0.81

P_AC4

Clock contribution of a VersaTile used as a sequential

module

0.12

P_AC5

P_AC6

First contribution of a VersaTile used as a sequential module

0.07

0.29

Second contribution of a VersaTile used as a sequential

module

P_AC7

P_AC8

P_AC9

P_AC10

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.29

0.70

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

See Table 2-7 on page 2-6.

See Table 2-7 and Table 2-10 on

page 2-8.

P_AC11

P_AC12

Average contribution of a RAM block during a read

operation

25.00

Average contribution of a RAM block during a write

operation

30.00

P_AC13

P_AC14

Static PLL contribution

2.55 mW

2.60

Dynamic contribution for PLL

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero^®Integrated Design Environment (IDE).

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on

page 2-11.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-

13 on page 2-12.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-13 on page 2-12. The calculation should be repeated for each clock domain defined

in the design.

v1.0

2-9

Automotive ProASIC3 DC and Switching Characteristics

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= P_DC1+ N_INPUTS* P_DC2+ N_OUTPUTS* P_DC3

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE*P_AC2+ N_ROW* P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in Table 2-12

on page 2-11.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in Table 2-12 on

page 2-11.

F_CLKis the global clock signal frequency.

N

_S-CELLis the number of VersaTiles used as sequential modules in the design.

P_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ α₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

F

_CLKis the global clock signal frequency.

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* α₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

F

_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * α₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.

F

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* α₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.

F_CLKis the global clock signal frequency.

2-10

v1.0

Automotive ProASIC3 DC and Switching Characteristics

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* α₂/ 2 * β₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-12.

β₁is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-12.

F_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* β₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* β₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

β₃is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on

page 2-12.

PLL Contribution—P

PLL

P_PLL= P_AC13+ P_AC14* F_CLKOUT

F_CLKINis the input clock frequency.

F

_CLKOUTis the output clock frequency.¹

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated

by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include

each output clock in the formula by adding its corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL

contribution.

v1.0

2-11

Automotive ProASIC3 DC and Switching Characteristics

Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

β₁

β₂

β₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

User I/O Characteristics

Timing Model

I/O Module

(non-registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL (applicable to

Advanced I/O banks only)

t

= 0.67 ns

t

= 0.58 ns

PD

t

= 1.66 ns

DP

I/O Module

(non-registered)

Combinational Cell

Y

Output Drive Strength = 12 mA

High Slew Rate

LVTTL

t

= 3.25 ns (Advanced I/O banks)

DP

t

= 1.04 ns

PD

I/O Module

(non-registered)

Combinational Cell

Y

I/O Module

(registered)

Output drive Strength = 8 mA

LVTTL

t

= 1.29 ns

High Slew Rate

= 4.52 ns (Advanced I/O banks)

PY

t

DP

LVPECL

(applicable

to Advanced

I/O banks only)

t

= 0.60 ns

PD

I/O Module

(non-registered)

D

Q

Combinational Cell

Y

Output Drive Strength = 4 mA

High Slew Rate

LVCMOS 1.5 V

t

= 0.29 ns

ICLKQ

ISUD

t

= 4.89 ns (Advanced I/O banks)

t

= 0.56 ns

DP

= 0.31 ns

PD

Input LVTTL

Clock

I/O Module

(registered)

Register Cell

Combinational Cell

Y

t

= 0.94 ns (Advanced I/O banks)

PY

LVTTL 3.3 V Output Drive

Strength = 12 mA

High Slew Rate

= 3.25 ns

D

Q

D

Q

D

t

Q

I/O Module

t

= 0.56 ns

PD

t

(non-registered)

DP

(Advanced I/O banks)

t

= 0.66 ns

= 0.51 ns

CLKQ

SUD

= 0.70 ns

= 0.37 ns

t

= 0.66 ns

= 0.51 ns

OCLKQ

CLKQ

SUD

LVDS,

BLVDS,

M-LVDS

t

OSUD

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t

= 1.47 ns

PY

t

= 0.94 ns

t

= 0.94 ns

PY

(Advanced I/O banks)

Figure 2-3 • Timing Model

Operating Conditions: –1 Speed, Automotive Grade 2 Temp. Range (T_J= 115°C), Worst Case

V_CC= 1.425 V

2-12

v1.0

Automotive ProASIC3 DC and Switching Characteristics

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

V_IH

V_trip

V_CC

V_IL

PAD

Y

50%

GND

t_PY

(R)

t_PY

(F)

V_CC

50%

DIN

t_DOUT

(R)

GND

t_DOUT

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

v1.0

2-13

Automotive ProASIC3 DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(F)

V_CC

(R)

50%

V_CC

D

0 V

50%

0 V

DOUT

PAD

V_OH

V_trip

V_OL

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

2-14

v1.0

Automotive ProASIC3 DC and Switching Characteristics

t

EOUT

D

Q

CLK

t , t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

t

CLK

D

= MAX(t

(r), t

(f))

V

I/O Interface

EOUT

V

CC

D

E

CC

50%

t

50%

t

EOUT (F)

EOUT (R)

V

CC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

V

HZ

CCI

90% V

CCI

V

trip

V

10% V

OL

CCI

V

CC

D

E

V

CC

50%

t

EOUT (F)

EOUT (R)

V

CC

50%

EOUT

PAD

50%

t

ZHS

t

V

ZLS

OH

V

trip

V

OL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

v1.0

2-15

Automotive ProASIC3 DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

12 12

Drive

Slew

I/O Standard

Strength Rate Min, V

Max, V

3.3 V LVTTL /

12 mA High –0.3

0.8

2

3.6

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA High –0.3

0.7

1.7

3.6

0.7

1.7

12 12

12 mA High –0.3 0.35 * V_CCI0.65 * V_CCI

12 mA High –0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45 12 12

0.25 * V_CCI0.75 * V_CCI12 12

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Note: Currents are measured at 125°C junction temperature.

Table 2-15 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

12 12

Drive

Slew

I/O Standard Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

High

–0.3

0.8

2

3.6

2.5 V LVCMOS 12 mA

High

0.7

1.7

3.6

0.7

1.7

12 12

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

8 mA

4 mA

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45

8

4

8

4

0.25 * V_CCI0.75 * V_CCI

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Note: Currents are measured at 125°C junction temperature.

Table 2-16 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard

Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

High –0.3

0.8

2

3.6

8

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

8 mA

4 mA

2 mA

0.7

1.7

3.6

0.7

1.7

8

4

2

8

4

2

High –0.3 0.35 * V_CCI0.65 * V_CCI

High –0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45

0.25 * V_CCI0.75 * V_CCI

Note: Currents are measured at 125°C junction temperature.

2-16

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Automotive

Grade 1 and Grade 2

Automotive Grade 1¹

Automotive Grade 2²

I_IL

µA

10

I_IH

µA

10

I_IL

µA

15

I_IH

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

Notes:

1. Automotive range Grade 1 (–40°C < T_J< 135°C)

2. Automotive range Grade 2 (–40°C < T_J< 115°C)

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-18 • Summary of AC Measuring Points

Standard

Measuring Trip Point (V_trip

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

3.3 V PCI-X

Table 2-19 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data-to-Pad delay through the Output Buffer

Pad-to-Data delay through the Input Buffer

t_DP

t_PY

t_DOUT

t_EOUT

t_DIN

t_HZ

Data–to–Output Buffer delay through the I/O interface

Enable–to–Output Buffer Tristate Control delay through the I/O interface

Input Buffer–to–Data delay through the I/O interface

Enable-to-Pad delay through the Output Buffer—HIGH to Z

Enable-to-Pad delay through the Output Buffer—Z to HIGH

Enable-to-Pad delay through the Output Buffer—LOW to Z

Enable-to-Pad delay through the Output Buffer—Z to LOW

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable-to-Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable-to-Pad delay through the Output Buffer with delayed enable—Z to LOW

v1.0

2-17

Automotive ProASIC3 DC and Switching Characteristics

Table 2-20 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Automotive-Case Conditions: T_J= 115°C, Worst Case V_CC= 1.425 V, Worst Case

V_CCI= 3.0 V

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

12 mA High 35 pF

–

0.53 3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37 2.71 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 35 pF

1.8 V LVCMOS 12 mA High 35 pF

1.5 V LVCMOS 12 mA High 35 pF

–

0.53 3.28 0.04 1.19 0.38 3.34 3.16 1.77 1.80 5.39 5.22 ns

0.53 3.25 0.04 1.12 0.38 1.89 1.63 3.41 3.75 3.06 2.82 ns

0.53 3.75 0.04 1.32 0.38 2.18 1.91 3.63 3.87 3.35 3.11 ns

3.3 V PCI

Per PCI High 10 pF 25 ²0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns

spec

3.3 V PCI-X

Per PCI-X High 10 pF 25 ²0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns

spec

LVDS

24 mA High

–

0.53 1.68 0.04 1.47

0.53 1.66 0.04 1.29

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on

page 2-47 for connectivity. This resistor is not required during normal operation.

2-18

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-21 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Automotive-Case Conditions: T_J= 115°C, Worst Case V_CC= 1.425 V, Worst Case

_CCI= 3.0 V

V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

12 mA High 35 pF

–

0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 35 pF

–

0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns

0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns

0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

8 mA

4 mA

High 35 pF

Per PCI High 10 pF 25 ²0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns

spec

3.3 V PCI-X

Per PCI-X High 10 pF 25 ²0.55 2.19 0.04 0.79 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns

spec

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on

page 2-47 for connectivity. This resistor is not required during normal operation.

v1.0

2-19

Automotive ProASIC3 DC and Switching Characteristics

Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Automotive-Case Conditions: T_J= 135°C, Worst Case V_CC= 1.425 V, Worst Case

V_CCI= 3.0 V

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

12 mA High 35 pF

–

0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 35 pF

1.8 V LVCMOS 12 mA High 35 pF

1.5 V LVCMOS 12 mA High 35 pF

–

0.55 3.39 0.04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.39 ns

0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.92 ns

0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.21 ns

3.3 V PCI

Per PCI High 10 pF 25 ²0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns

spec

3.3 V PCI-X

Per PCI-X High 10 pF 25 ²0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns

spec

LVDS

24 mA High

–

0.55 1.74 0.04 1.52

0.55 1.71 0.04 1.34

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on

page 2-47 for connectivity. This resistor is not required during normal operation.

2-20

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Automotive-Case Conditions: T_J= 115°C, Worst Case V_CC= 1.425 V, Worst Case

_CCI= 3.0 V

V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

12 mA High 35 pF

–

0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 35 pF

–

0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns

0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns

0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

8 mA

4 mA

High 35 pF

Per PCI High 10 pF 25 ²0.55 2.55 0.04 0.82 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns

spec

3.3 V PCI-X

Per PCI-X High 10 pF 25 ²0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns

spec

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on

page 2-47 for connectivity. This resistor is not required during normal operation.

v1.0

2-21

Automotive ProASIC3 DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-24 • Input Capacitance

Symbol

C_IN

Definition

Input capacitance

Input capacitance on the clock pin

Conditions

Min. Max. Units

V_IN= 0, f = 1.0 MHz

8

pF

C_INCLK

Table 2-25 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω)²

100

50

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

300

150

75

6 mA

8 mA

50

12 mA

16 mA

24 mA

2 mA

25

17

50

11

33

2.5 V LVCMOS

1.8 V LVCMOS

100

50

200

100

50

6 mA

12 mA

16 mA

24 mA

2 mA

25

20

40

11

22

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

16 mA

2 mA

20

22

20

22

1.5 V LVCMOS

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

Per PCI/PCI-X specification

33

37

3.3 V PCI/PCI-X

25

75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on V_CCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-22

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-26 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard Plus I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

25

16 mA

25

75

2.5 V LVCMOS

1.8 V LVCMOS

2 mA

100

50

200

100

50

6 mA

12 mA

25

2 mA

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

1.5 V LVCMOS

2 mA

4 mA

200

100

0

224

112

0

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on V_CCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Table 2-27 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

(Ω)

V_CCI

Min.

10 k

11 k

18 k

19 k

Max.

45 k

55 k

70 k

90 k

Min.

10 k

12 k

17 k

19 k

Max.

45 k

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

74 k

110 k

140 k

1. R_{(WEAK PULL-UP-MAX)}= (V_OLspec) / I_{(WEAK PULL-UP-MIN)}

2. R_{(WEAK PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_{(WEAK PULL-UP-MIN)}

v1.0

2-23

Automotive ProASIC3 DC and Switching Characteristics

Table 2-28 • I/O Short Currents I_OSH/I_OSL

Applicable to Advanced I/O Banks

Drive Strength

I

_OSL(mA)*

I_OSH(mA)*

25

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

27

25

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

2 mA

109

127

181

27

103

132

268

25

3.3 V LVCMOS

4 mA

27

25

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

2 mA

109

127

181

18

103

132

268

16

2.5 V LVCMOS

1.8 V LVCMOS

6 mA

37

32

12 mA

16 mA

24 mA

2 mA

74

65

87

83

124

11

169

9

4 mA

22

17

6 mA

44

35

8 mA

51

45

12 mA

16 mA

2 mA

74

91

74

91

1.5 V LVCMOS

16

13

4 mA

33

25

6 mA

39

32

8 mA

55

66

12 mA

Per PCI/PCI-X specification

55

66

3.3 V PCI/PCI-X

109

103

* T_J= 100°C

2-24

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-29 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard Plus I/O Banks

Drive Strength

I_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

27

25

51

103

16

32

65

9

4 mA

27

6 mA

54

8 mA

54

12 mA

109

18

16 mA

2.5 V LVCMOS

1.8 V LVCMOS

2 mA

6 mA

37

12 mA

74

2 mA

11

4 mA

22

17

35

13

25

103

6 mA

44

8 mA

44

1.5 V LVCMOS

2 mA

4 mA

16

33

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

109

* T_J= 100°C

The length of time an I/O can withstand I_OSH/I_OSLevents depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-30 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

125°C

135°

6 months

3 months

25 days

12 days

v1.0

2-25

Automotive ProASIC3 DC and Switching Characteristics

Table 2-31 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Rise/Fall Time

(min.)

Input Rise/Fall Time

Input Buffer

(max.)

10 ns *

Reliability

LVTTL/LVCMOS

No requirement

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/M-LVDS/LVPECL

* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals.

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-32 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

25

10 10

4 mA

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

109

127

181

103

132

268

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-26

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-33 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

25

10 10

54

51

54

51

12 12

16 16

109

103

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-7 • AC Loading

Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

3.3

1.4

35

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

v1.0

2-27

Automotive ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

8.56 0.05 1.14

7.28 0.04 0.97

5.49 0.05 1.14

4.67 0.04 0.97

5.49 0.05 1.14

4.67 0.04 0.97

3.95 0.05 1.14

3.36 0.04 0.97

3.73 0.05 1.14

3.17 0.04 0.97

3.44 0.05 1.14

2.92 0.04 0.97

8.72 7.37 1.46 1.42 11.22 9.866

7.42 6.27 1.46 1.42

5.59 4.55 1.65 1.74

4.75 3.87 1.65 1.74

5.59 4.55 1.65 1.74

4.75 3.87 1.65 1.74

4.02 1.56 3.59 1.94

3.42 1.56 3.05 1.94

1.84 1.42 3.65 4.11

1.84 1.42 3.10 3.50

1.70 1.17 3.72 4.54

1.70 1.17 3.16 3.86

9.54

8.09

6.88

8.09

6.88

6.52

5.55

3.05

2.91

8.393

7.05

ns

6 mA

STD

-1

ns

5.997

7.05

ns

8 mA

STD

-1

ns

5.997

2.795

2.797

2.651

2.653

2.405

2.407

ns

12 mA

16 mA

24 mA

Notes:

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

11.47 0.05 1.14 0.46

9.75 0.04 0.97 0.39

8.13 0.05 1.14 0.46

6.92 0.04 0.97 0.39

8.13 0.05 1.14 0.46

6.92 0.04 0.97 0.39

6.24 0.05 1.14 0.46

5.31 0.04 0.97 0.39

5.82 0.05 1.14 0.46

4.95 0.04 0.97 0.39

5.42 0.05 1.14 0.46

4.61 0.04 0.97 0.39

11.68 9.95 1.46 1.33 14.18 12.449

9.94 8.46 1.46 1.33 12.06

8.28 7.03 1.65 1.65 10.79

7.05 5.98 1.65 1.65 9.17

8.28 7.03 1.65 1.65 10.79

7.05 5.98 1.65 1.65 9.17

6.36 5.45 1.77 1.85 8.86

5.41 4.63 1.77 1.85 7.53

5.93 5.10 1.80 1.90 8.43

5.04 4.34 1.80 1.90 7.17

5.52 5.08 1.83 2.10 8.02

4.70 4.32 1.83 2.11 6.82

10.59

9.526

8.103

9.526

8.103

7.946

6.76

ns

6 mA

STD

-1

ns

8 mA

STD

-1

ns

12 mA

16 mA

24 mA

STD

-1

ns

STD

-1

7.604

6.468

7.581

6.449

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-28

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

8.06 0.05 1.12

6.85 0.04 .095

5.03 0.05 1.12

4.28 0.04 0.95

5.03 0.05 1.12

4.28 0.04 0.95

3.53 0.05 1.12

3.01 0.04 0.95

3.53 0.05 1.12

3.01 0.04 0.95

8.20 7.03 1.26 1.27 8.20 7.027

6.98 5.98 1.26 1.27 6.98 5.978

5.13 4.27 1.42 1.56 5.13 4.267

ns

6 mA

STD

-1

ns

4.36 3.63 1.42 1.56 4.36

5.13 4.27 1.42 1.56 5.13 4.267

4.36 3.63 1.42 1.56 4.36 3.63

3.63

ns

8 mA

STD

-1

ns

12 mA

16 mA

Notes:

STD

-1

1.74 1.43 3.12 3.60 1.74 1.427

1.74 1.43 2.65 3.06 1.74 1.428

1.74 1.43 3.12 3.60 1.74 1.427

1.74 1.43 2.65 3.06 1.74 1.428

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

6 mA

8 mA

12 mA

16 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

10.82 0.05 1.12

11.02 9.42 1.26 1.20 11.02 9.419

9.21

7.49

6.37

7.49

6.37

5.64

4.80

5.64

4.80

0.04 0.95

0.05 1.12

0.04 0.95

0.05 1.12

0.04 0.95

0.05 1.12

0.04 0.95

0.05 1.12

0.04 0.95

9.38

7.63

6.49

7.63

6.49

5.75

4.89

5.75

4.89

8.01 1.26 1.20

6.58 1.43 1.48

5.60 1.43 1.49

6.58 1.43 1.48

5.60 1.43 1.49

5.04 1.54 1.67

4.29 1.54 1.67

5.04 1.54 1.67

4.29 1.54 1.67

9.38

7.63

6.49

7.63

6.49

5.75

4.89

5.75

4.89

8.012

6.58

ns

STD

-1

ns

5.598

6.58

ns

STD

-1

ns

5.598

5.042

4.289

5.042

4.289

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-29

Automotive ProASIC3 DC and Switching Characteristics

Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

8.28 0.05 1.10

7.05 0.04 0.94

5.31 0.05 1.10

4.52 0.04 0.94

5.31 0.05 1.10

4.52 0.04 0.94

3.82 0.05 1.10

3.25 0.04 0.94

3.60 0.05 1.10

3.07 0.04 0.94

3.33 0.05 1.10

2.83 0.04 0.94

8.44 7.13 1.42 1.37 10.85 9.55

ns

7.18 6.06 1.42 1.37

5.41 4.40 1.60 1.68

4.60 3.74 1.60 1.68

5.41 4.40 1.60 1.68

4.60 3.74 1.60 1.68

3.89 1.51 3.47 1.88

3.31 1.51 2.96 1.88

1.78 1.37 3.53 3.98

1.78 1.37 3.00 3.38

1.64 1.13 3.60 4.39

1.64 1.13 3.06 3.74

9.23

7.83

6.66

7.83

6.66

6.31

5.37

2.95

2.81

2.82

8.12

6.82

5.80

6.82

5.80

2.70

2.71

2.57

2.33

6 mA

STD

-1

8 mA

STD

-1

12 mA

16 mA

24 mA

Notes:

STD

-1

STD

-1

STD

-1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

4 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

11.09 0.05 1.10

11.30 9.63 1.41 1.29 13.72 12.04

9.44

7.87

6.69

7.87

6.69

6.04

5.14

5.63

4.79

5.25

4.46

0.04 0.94

0.05 1.10

0.04 0.94

0.05 1.10

0.04 0.94

0.05 1.10

0.04 0.94

0.05 1.10

0.04 0.94

0.05 1.10

0.04 0.94

9.61

8.02

6.82

8.02

6.82

6.15

5.23

5.74

4.88

5.34

4.55

8.19 1.41 1.29 11.67 10.25

ns

6 mA

STD

-1

6.80 1.59 1.59 10.43

5.78 1.59 1.60 8.88

6.80 1.59 1.59 10.43

9.22

7.84

9.22

7.84

7.69

6.54

7.36

6.26

7.34

6.24

ns

8 mA

STD

-1

ns

5.78 1.59 1.60

5.27 1.71 1.79

4.48 1.71 1.79

4.94 1.74 1.84

4.20 1.74 1.84

4.92 1.77 2.04

4.18 1.77 2.04

8.88

8.57

7.29

8.16

6.94

7.76

6.60

ns

12 mA

16 mA

24 mA

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-30

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade

STD

-1

t_DOUT

0.63

0.55

0.63

0.55

0.63

0.55

0.63

0.55

0.63

0.55

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

7.79 0.05 1.08

6.85 0.04 0.95

4.87 0.05 1.08

4.28 0.04 0.95

4.87 0.05 1.08

4.28 0.04 0.95

3.42 0.05 1.08

3.01 0.04 0.95

3.42 0.05 1.08

3.01 0.04 0.95

7.94 6.80 1.22 1.23 7.94 6.80

6.98 5.98 1.26 1.27 6.98 5.98

4.96 4.13 1.38 1.51 4.96 4.13

4.36 3.63 1.42 1.56 4.36 3.63

4.96 4.13 1.38 1.51 4.96 4.13

4.36 3.63 1.42 1.56 4.36 3.63

1.69 1.38 3.02 3.48 1.69 1.38

1.74 1.43 2.65 3.06 1.74 1.43

1.69 1.38 3.02 3.48 1.69 1.38

1.74 1.43 2.65 3.06 1.74 1.43

ns

6 mA

STD

-1

8 mA

STD

-1

12 mA

16 mA

Notes:

STD

-1

STD

-1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

STD

-1

0.63

0.55

0.63

0.55

0.63

0.55

0.63

0.55

0.63

0.55

10.47 0.05 1.08

10.66 9.11 1.22 1.16 10.66 9.11

ns

9.21

7.25

6.37

7.25

6.37

5.46

4.80

5.46

4.80

0.04 0.95

0.05 1.08

0.04 0.95

0.05 1.08

0.04 0.95

0.05 1.08

0.04 0.95

0.05 1.08

0.04 0.95

9.38

7.38

6.49

7.38

6.49

5.56

4.89

5.56

4.89

8.01 1.26 1.20

6.37 1.38 1.44

5.60 1.43 1.49

6.37 1.38 1.44

5.60 1.43 1.49

4.88 1.49 1.61

4.29 1.54 1.67

4.88 1.49 1.61

4.29 1.54 1.67

9.38

7.38

6.49

7.38

6.49

5.56

4.89

5.56

4.89

8.01

6.37

5.60

6.37

5.60

4.88

4.29

4.88

4.29

STD

-1

STD

-1

STD

-1

STD

-1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-31

Automotive ProASIC3 DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-43 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.7

1.7

3.6

0.7

1.7

2

6

2

6

18

37

16

32

10 10

6 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

74

65

87

83

124

169

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-44 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.7

1.7

3.6

0.7

1.7

2

6

2

6

18

37

74

16

32

65

10 10

6 mA

12 mA

Notes:

12 12

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-8 • AC Loading

Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

2.5

1.2

35

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

2-32

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-46 • 2.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

9.69 0.05 1.45

8.24 0.04 1.23

5.78 0.05 1.45

4.91 0.04 1.23

3.98 0.05 1.45

3.39 0.04 1.23

3.75 0.05 1.45

3.19 0.04 1.23

3.45 0.05 1.45

2.94 0.04 1.23

8.76 9.69 1.48 1.25 11.26 12.187

7.45 8.24 1.48 1.25

5.63 5.78 1.68 1.62

4.79 4.91 1.69 1.63

4.05 3.84 1.82 1.86

3.45 3.27 1.83 1.86

1.85 1.69 3.76 3.97

1.85 1.69 3.20 3.38

1.70 1.35 3.84 4.47

1.71 1.35 3.27 3.80

9.58

8.13

6.92

6.55

5.58

3.06

2.92

10.367

8.277

7.04

ns

6 mA

STD

-1

ns

12 mA

16 mA

24 mA

Notes:

STD

-1

6.338

5.392

2.926

2.929

2.585

2.586

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-47 • 2.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

12.12 0.05 1.45 0.46 12.54 12.74 1.48 1.19 15.04 15.243

10.31 0.04 1.23 0.39 10.67 10.84 1.48 1.20 12.80 12.966

ns

6 mA

STD

-1

8.24 0.05 1.45 0.46

7.01 0.04 1.23 0.39

6.91 0.05 1.45 0.46

5.88 0.04 1.23 0.39

6.44 0.05 1.45 0.46

5.48 0.04 1.23 0.39

6.16 0.05 1.45 0.46

5.24 0.04 1.23 0.39

9.07

7.71

7.04

5.99

6.56

5.58

6.15

5.23

8.74 1.68 1.57 11.57 11.237

ns

7.43 1.69 1.57 9.84

6.62 1.82 1.80 9.54

5.63 1.83 1.80 8.11

6.18 1.86 1.86 9.06

5.26 1.86 1.86 7.71

6.16 1.90 2.10 8.65

5.24 1.90 2.10 7.36

9.559

9.117

7.756

8.678

7.382

8.657

7.364

ns

12 mA

16 mA

24 mA

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-33

Automotive ProASIC3 DC and Switching Characteristics

Table 2-48 • 2.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

9.26 0.05 1.45

7.87 0.04 1.23

5.43 0.05 1.45

4.62 0.04 1.23

3.59 0.05 1.45

3.05 0.04 1.23

8.28 9.26 1.24 1.12 10.78 11.756

7.05 7.87 1.24 1.13

5.19 5.43 1.43 1.47

4.42 4.62 1.43 1.47

3.65 3.51 1.56 1.69

3.11 2.99 1.56 1.69

9.17

7.69

6.55

6.15

5.23

10

ns

6 mA

STD

-1

7.926

6.743

6.012

5.114

ns

12 mA

Notes:

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-49 • 2.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

6 mA

12 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

12.12 0.05 1.45 0.46 11.89 12.12 1.25 1.08 14.39 14.622

10.31 0.04 1.23 0.39 10.12 10.31 1.25 1.08 12.24 12.438

ns

STD

-1

8.24 0.05 1.45 0.46

7.01 0.04 1.23 0.39

6.30 0.05 1.45 0.46

5.35 0.04 1.23 0.39

8.39

7.14

6.41

5.45

8.23 1.43 1.42 10.89

7.00 1.43 1.42 9.26

6.16 1.56 1.63 8.91

5.24 1.56 1.63 7.58

10.73

9.128

8.656

7.364

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-34

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-50 • 2.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

9.37 0.05 1.40

7.97 0.04 1.19

5.59 0.05 1.40

4.75 0.04 1.19

3.85 0.05 1.40

3.28 0.04 1.19

3.63 0.05 1.40

3.08 0.04 1.19

3.34 0.05 1.40

2.84 0.04 1.19

8.47 9.37 1.43 1.21 10.89 11.79

7.21 7.97 1.43 1.21

5.45 5.59 1.63 1.57

4.63 4.75 1.63 1.57

3.92 3.71 1.77 1.80

3.34 3.16 1.77 1.80

1.79 1.64 3.64 3.84

1.79 1.64 3.09 3.27

1.65 1.31 3.72 4.32

1.65 1.31 3.16 3.68

9.27

7.87

6.69

6.34

5.39

2.96

2.82

10.03

8.01

6.81

6.13

5.22

2.83

2.50

ns

6 mA

STD

-1

ns

12 mA

16 mA

24 mA

Notes:

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-51 • 2.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

11.73 0.05 1.40 0.45

9.98 0.04 1.19 0.38

7.97 0.05 1.40 0.45

6.78 0.04 1.19 0.38

6.68 0.05 1.40 0.45

5.69 0.04 1.19 0.38

6.24 0.05 1.40 0.45

5.30 0.04 1.19 0.38

5.96 0.05 1.40 0.45

5.07 0.04 1.19 0.38

12.14 12.33 1.43 1.16 14.55 14.75

10.32 10.49 1.43 1.16 12.38 12.55

ns

6 mA

STD

-1

8.77

7.46

6.81

5.79

6.35

5.40

5.95

5.06

8.45 1.63 1.51 11.19 10.87

ns

7.19 1.63 1.52 9.52

6.40 1.77 1.74 9.23

5.45 1.77 1.74 7.85

5.98 1.80 1.80 8.77

5.08 1.80 1.80 7.46

5.96 1.84 2.03 8.37

5.07 1.84 2.03 7.12

9.25

8.82

7.50

8.40

7.14

8.38

7.12

ns

12 mA

16 mA

24 mA

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-35

Automotive ProASIC3 DC and Switching Characteristics

Table 2-52 • 2.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

8.95 0.05 1.40

7.62 0.04 1.19

5.25 0.05 1.40

4.47 0.04 1.19

3.47 0.05 1.40

2.95 0.04 1.19

8.01 8.95 1.20 1.09 10.43 11.37

6.82 7.62 1.20 1.09

5.03 5.25 1.38 1.42

4.27 4.47 1.38 1.42

3.53 3.40 1.51 1.63

3.01 2.89 1.51 1.63

8.87

7.44

6.33

5.95

5.06

9.68

7.67

6.52

5.82

4.95

ns

6 mA

STD

-1

ns

12 mA

Notes:

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-53 • 2.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

6 mA

12 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

11.73 0.05 1.40 0.45

9.98 0.04 1.19 0.38

7.97 0.05 1.40 0.45

6.78 0.04 1.19 0.38

6.09 0.05 1.40 0.45

5.18 0.04 1.19 0.38

11.51 11.73 1.21 1.04 13.93 14.15

9.79

8.12

6.91

6.20

5.28

9.98 1.21 1.04 11.85 12.03

7.96 1.38 1.37 10.54 10.38

ns

STD

-1

ns

6.77 1.39 1.37 8.96

5.96 1.51 1.58 8.62

5.07 1.51 1.58 7.33

8.83

8.38

7.12

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-36

v1.0

Automotive ProASIC3 DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-54 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

3.6

0.45 V_CCI– 0.45

2

4

6

8

2

4

6

8

11

22

44

51

74

9

10 10

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

45

91

0.45 V_CCI– 0.45 12 12

0.45 V_CCI– 0.45 16 16

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-55 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

3.6

0.45 V_CCI– 0.45

2

4

6

8

2

4

6

8

11

22

44

9

10 10

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-9 • AC Loading

v1.0

2-37

Automotive ProASIC3 DC and Switching Characteristics

Table 2-56 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

35

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

Timing Characteristics

Table 2-57 • 1.8 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

13.26 0.05 1.36 0.46 10.22 13.26 1.53 0.90 12.72 15.764

11.28 0.04 1.16 0.39

7.73 0.05 1.36 0.46

6.58 0.04 1.16 0.39

4.97 0.05 1.36 0.46

4.23 0.04 1.16 0.39

4.39 0.05 1.36 0.46

3.73 0.04 1.16 0.39

3.95 0.05 1.36 0.46

3.36 0.04 1.16 0.39

3.95 0.05 1.36 0.46

3.36 0.04 1.16 0.39

8.69 11.28 1.53 0.90 10.82

13.41

10.232

8.704

7.472

6.356

6.888

5.859

2.915

2.918

2.915

2.918

ns

STD

-1

6.55

5.58

4.67

3.98

4.39

3.74

1.95

7.73 1.78 1.54 9.05

6.58 1.78 1.54 7.70

4.97 1.95 1.83 7.17

4.23 1.95 1.83 6.10

4.39 1.99 1.91 6.89

3.73 1.99 1.91 5.86

1.68 4.14 4.56 3.16

1.68 3.52 3.88 3.16

1.68 4.14 4.56 3.16

1.68 3.52 3.88 3.16

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-38

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-58 • 1.8 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

17.36 0.05 1.45 0.46 15.78 17.36 1.53 0.87 18.28 19.864

14.77 0.04 1.23 0.39 13.42 14.77 1.54 0.87 15.55 16.897

11.71 0.05 1.45 0.46 11.64 11.71 1.78 1.48 14.14 14.214

ns

STD

-1

ns

9.96 0.04 1.23 0.39

9.00 0.05 1.45 0.46

7.66 0.04 1.23 0.39

8.39 0.05 1.45 0.46

7.14 0.04 1.23 0.39

8.15 0.05 1.45 0.46

6.94 0.04 1.23 0.39

8.15 0.05 1.45 0.46

6.94 0.04 1.23 0.39

9.90

9.17

7.80

8.54

7.27

8.09

6.88

8.09

6.88

9.96 1.78 1.48 12.03 12.091

8.77 1.95 1.77 11.67 11.267

ns

STD

-1

ns

7.46 1.95 1.77 9.92

8.16 1.99 1.85 11.04

6.94 1.99 1.85 9.40

9.585

10.66

9.068

ns

STD

-1

ns

STD

-1

8.15 2.05 2.14 10.59 10.654

6.94 2.05 2.14 9.01 9.063

8.15 2.05 2.14 10.59 10.654

6.94 2.05 2.14 9.01 9.063

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-59 • 1.8 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

13.26 0.05 1.36 0.46 9.75 12.67 1.24 0.82 12.26

15.17

11.28 0.04 1.16 0.39 8.30 10.78 1.24 0.83 10.43 12.905

ns

STD

-1

7.73 0.05 1.36 0.46 6.13 7.25 1.46 1.41 8.63

6.58 0.04 1.16 0.39 5.21 6.17 1.46 1.41 7.34

4.97 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79

4.23 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78

4.39 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79

3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78

9.749

8.293

7.039

5.987

7.039

5.987

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-39

Automotive ProASIC3 DC and Switching Characteristics

Table 2-60 • 1.8 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

17.36 0.05 1.45 0.46 15.09 16.55 1.24 0.79 17.59 19.052

14.77 0.04 1.23 0.39 12.84 14.08 1.24 0.79 14.96 16.207

11.71 0.05 1.45 0.46 10.88 11.07 1.47 1.35 13.38 13.567

ns

STD

-1

ns

9.96 0.04 1.23 0.39

9.00 0.05 1.45 0.46

7.66 0.04 1.23 0.39

8.39 0.05 1.45 0.46

7.14 0.04 1.23 0.39

9.26

8.47

7.21

8.47

7.21

9.41 1.47 1.35 11.38 11.541

8.18 1.62 1.62 10.97 10.685

ns

STD

-1

ns

6.96 1.62 1.62 9.33

8.18 1.62 1.62 10.97 10.685

6.96 1.62 1.62 9.33 9.089

9.089

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-61 • 1.8 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

12.83 0.05 1.32

10.92 0.04 1.12

9.88 12.83 1.48 0.87 12.30 15.25

8.41 10.92 1.48 0.87 10.46 12.97

ns

STD

-1

7.48

6.36

4.81

4.09

4.25

3.61

3.82

3.25

3.82

3.25

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

6.34

5.39

4.52

3.85

4.25

3.61

1.89

7.48

6.36

4.81

4.09

4.25

3.61

1.63

1.72 1.49

1.89 1.77

1.92 1.85

1.93 1.85

4.00 4.41

3.41 3.75

4.00 4.41

3.41 3.75

8.76

7.45

6.94

5.90

6.67

5.67

3.06

9.90

8.42

7.23

6.15

6.66

5.67

2.82

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-40

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-62 • 1.8 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

16.80 0.05 1.40 0.45

14.29 0.04 1.19 0.38

11.33 0.05 1.40 0.45

9.64 0.04 1.19 0.38

8.71 0.05 1.40 0.45

7.41 0.04 1.19 0.38

8.12 0.05 1.40 0.45

6.90 0.04 1.19 0.38

7.89 0.05 1.40 0.45

6.71 0.04 1.19 0.38

7.89 0.05 1.40 0.45

6.71 0.04 1.19 0.38

15.27 16.80 1.48 0.84 17.69 19.22

12.99 14.29 1.49 0.84 15.05 16.35

11.26 11.33 1.73 1.43 13.68 13.75

ns

STD

-1

ns

9.58

8.87

7.54

8.27

7.03

7.83

6.66

7.83

6.66

9.64 1.73 1.43 11.64 11.70

8.48 1.89 1.72 11.29 10.90

ns

STD

-1

ns

7.22 1.89 1.72 9.60

7.89 1.93 1.79 10.69 10.31

6.72 1.93 1.79 9.09 8.77

7.89 1.98 2.07 10.25 10.31

6.71 1.98 2.07 8.72 8.77

7.89 1.98 2.07 10.25 10.31

6.71 1.98 2.07 8.72 8.77

9.27

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-63 • 1.8 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

12.83 0.05 1.32

10.92 0.04 1.12

9.44 12.26 1.20 0.80 11.86 14.68

8.03 10.43 1.20 0.80 10.09 12.49

ns

STD

-1

7.48

6.36

4.81

4.09

4.25

3.61

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

0.05 1.32

0.04 1.12

5.93

5.04

4.15

3.53

4.15

3.53

7.01

5.97

4.39

3.74

4.39

3.74

1.41 1.36

1.42 1.37

1.57 1.63

8.35

7.10

6.57

5.59

6.57

5.59

9.43

8.02

6.81

5.79

6.81

5.79

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-41

Automotive ProASIC3 DC and Switching Characteristics

Table 2-64 • 1.8 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

16.80 0.05 1.40 0.45

14.29 0.04 1.19 0.38

11.33 0.05 1.40 0.45

9.64 0.04 1.19 0.38

8.71 0.05 1.40 0.45

7.41 0.04 1.19 0.38

8.12 0.05 1.40 0.45

6.90 0.04 1.19 0.38

14.60 16.01 1.20 0.77 17.02 18.43

12.42 13.62 1.20 0.77 14.48 15.68

10.53 10.71 1.42 1.31 12.95 13.13

ns

STD

-1

ns

8.96

8.19

6.97

8.19

6.97

9.11 1.42 1.31 11.01 11.17

7.92 1.57 1.57 10.61 10.34

ns

STD

-1

ns

6.74 1.57 1.57 9.03

7.92 1.57 1.57 10.61 10.34

6.74 1.57 1.57 9.03 8.79

8.79

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-65 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.30 * V_CCI0.7 * V_CCI

3.6

0.25 * V_CCI0.75 * V_CCI

2

4

6

8

2

4

6

8

16

33

39

55

13

25

32

66

10 10

–0.3 0.30 * V_CCI0.7 * V_CCI

0.25 * V_CCI0.75 * V_CCI

0.25 * V_CCI0.75 * V_CCI12 12

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-42

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-66 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

–0.3 0.30 * V_CCI0.7 * V_CCI3.6 0.25 * V_CCI0.75 * V_CCI

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

Notes:

2

4

2

4

0

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-10 • AC Loading

Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

35

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

v1.0

2-43

Automotive ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-68 • 1.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

9.35 0.05 1.61

7.95 0.04 1.37

5.94 0.05 1.61

5.05 0.04 1.37

5.22 0.05 1.61

4.44 0.04 1.37

4.56 0.05 1.61

3.88 0.04 1.37

4.56 0.05 1.61

3.88 0.04 1.37

7.63 9.35 1.87 1.50 10.13 11.851

6.49 7.95 1.87 1.50

5.42 5.94 2.07 1.84

4.61 5.05 2.07 1.85

5.09 5.22 2.11 1.93

4.33 4.44 2.11 1.93

2.25 1.98 4.41 4.70

2.25 1.98 3.75 4.00

2.25 1.98 4.41 4.70

2.25 1.98 3.75 4.00

8.62

7.92

6.74

7.59

6.45

3.46

10.081

8.442

7.181

7.718

6.566

3.211

3.213

3.211

3.213

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-69 • 1.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

STD

-1

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

0.64

0.55

14.29 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794

12.16 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286

11.19 0.05 1.45 0.46 11.40 10.67 2.07 1.77 13.90 13.175

ns

STD

-1

ns

9.52 0.04 1.23 0.39

10.44 0.05 1.45 0.46 10.63 9.94 2.12 1.86 13.13 12.442

8.88 0.04 1.23 0.39 9.04 8.46 2.12 1.86 11.17 10.584

9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445

8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586

9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445

8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586

9.70

9.08 2.07 1.77 11.82 11.207

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-44

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-70 • 1.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

Notes:

STD

-1

0.64

0.55

0.64

0.55

8.76 0.05 1.59

7.45 0.04 1.35

5.41 0.05 1.59

4.60 0.04 1.35

7.63 9.35 1.87 1.50 10.13 11.851

6.49 7.95 1.87 1.50

5.42 5.94 2.07 1.84

4.61 5.05 2.07 1.85

8.62

7.92

6.74

10.081

8.442

7.181

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-71 • 1.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

STD

-1

0.64

0.55

0.64

0.55

13.51 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794

11.49 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286

10.38 0.05 1.45 0.46 11.40 10.67 2.07 1.77 13.90 13.175

ns

STD

-1

ns

8.83 0.04 1.23 0.39

9.70

9.08 2.07 1.77 11.82 11.207

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-72 • 1.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

9.05 0.05 1.56

7.70 0.04 1.32

5.75 0.05 1.56

4.89 0.04 1.32

5.05 0.05 1.56

4.29 0.04 1.32

4.41 0.05 1.56

3.75 0.04 1.32

4.41 0.05 1.56

3.75 0.04 1.32

7.38 9.05 1.81 1.45 9.80 11.47

6.28 7.70 1.81 1.45 8.34

5.25 5.75 2.00 1.78 7.67

4.46 4.89 2.00 1.78 6.52

4.92 5.05 2.04 1.87 7.34

4.19 4.29 2.04 1.87 6.24

2.18 1.91 4.27 4.55 3.35

2.18 1.91 3.63 3.87 3.35

2.18 1.91 4.27 4.55 3.35

2.18 1.91 3.63 3.87 3.35

9.75

8.17

6.95

7.47

6.35

3.11

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-45

Automotive ProASIC3 DC and Switching Characteristics

Table 2-73 • 1.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

STD

-1

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

0.63

0.53

13.83 0.05 1.40 0.45

11.76 0.04 1.19 0.38

10.83 0.05 1.40 0.45

9.21 0.04 1.19 0.38

10.10 0.05 1.40 0.45

8.59 0.04 1.19 0.38

9.64 0.05 1.40 0.45

8.20 0.04 1.19 0.38

9.64 0.05 1.40 0.45

8.20 0.04 1.19 0.38

13.86 13.83 1.82 1.39 16.28 16.25

11.79 11.76 1.82 1.39 13.85 13.82

11.03 10.33 2.00 1.71 13.45 12.75

ns

STD

-1

ns

9.38

10.28

8.75

9.82

8.35

9.82

8.35

8.79 2.01 1.72 11.44 10.84

9.62 2.05 1.80 12.70 12.04

8.18 2.05 1.80 10.81 10.24

9.62 2.11 2.12 12.23 12.04

8.18 2.11 2.12 10.41 10.24

9.62 2.11 2.12 12.23 12.04

8.18 2.11 2.12 10.41 10.24

ns

STD

-1

ns

STD

-1

ns

STD

-1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-74 • 1.5 V LVCMOS High Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

Notes:

STD

-1

0.63

0.53

0.63

0.53

8.47 0.05 1.54

7.21 0.04 1.31

5.24 0.05 1.54

4.45 0.04 1.31

7.38 9.05 1.81 1.45 9.80 11.47

6.28 7.70 1.81 1.45 8.34

5.25 5.75 2.00 1.78 7.67

4.46 4.89 2.00 1.78 6.52

9.75

8.17

6.95

ns

STD

-1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-75 • 1.5 V LVCMOS Low Slew

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

STD

-1

0.63

0.53

0.63

0.53

13.07 0.05 1.40 0.45

11.12 0.04 1.19 0.38

10.04 0.05 1.40 0.45

8.54 0.04 1.19 0.38

13.86 13.83 1.82 1.39 16.28 16.25

11.79 11.76 1.82 1.39 13.85 13.82

11.03 10.33 2.00 1.71 13.45 12.75

ns

STD

-1

ns

9.38

8.79 2.01 1.72 11.44 10.84

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-46

v1.0

Automotive ProASIC3 DC and Switching Characteristics

3.3 V PCI, 3.3 V PCI-X

The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz

PCI Bus applications.

Table 2-76 • Minimum and Maximum DC Input and Output Levels

3.3 V

PCI/PCI-X

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA¹Max, mA¹µA²µA²

Per PCI curves 10 10

Per PCI

specification

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 125°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-11.

R to V_CCIfor t_DP(F)

R to GND for t_DP(R)

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-11 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-77.

Table 2-77 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

0.285 * V_CCIfor t_DP(R)

0.615 * V_CCIfor t_DP(F)

C_LOAD(pF)

0

3.3

10

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

Timing Characteristics

Table 2-78 • 3.3 V PCI/PCI-X

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.64

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

Std.

–1

2.58 0.05 0.95

2.19 0.04 0.81

1.27 0.94 3.12 3.60 2.49 2.18

1.27 0.94 2.65 3.06 2.49 2.18

0.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-47

Automotive ProASIC3 DC and Switching Characteristics

Table 2-79 • 3.3 V PCI/PCI-X

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

0.64

t_DP

t_DIN

t_PY

t_EOUT

0.46

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

Std.

–1

3.00 0.05 0.93

2.55 0.04 0.79

1.27 0.94 3.12 3.60 2.49 2.18

1.27 0.94 2.65 3.06 2.49 2.18

0.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-80 • 3.3 V PCI/PCI-X

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

0.628

0.53

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

Std.

–1

2.50 0.05 0.92

2.12 0.04 0.78

1.23 0.91 3.02 3.48 2.40 2.11

1.23 0.91 2.57 2.96 2.41 2.11

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-81 • 3.3 V PCI/PCI-X

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

0.628

0.53

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.38

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

Std.

–1

2.90 0.05 0.90

2.47 0.04 0.77

1.23 0.91 3.02 3.48 2.40 2.11

1.23 0.91 2.57 2.96 2.41 2.11

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-12

on page 2-49. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

2-48

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

165 Ω

Z = 50 Ω

0

INBUF_LVDS

+

–

140 Ω

Z = 50 Ω

100 Ω

0

N

Figure 2-12 • LVDS Circuit Diagram and Board-Level Implementation

Table 2-82 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Min.

Typ.

Max.

Units

V

Supply Voltage

2.375

0.9

2.5

1.075

1.425

–

2.625

1.25

1.6

V_OL

Output LOW Voltage

V

V_OH

Output HIGH Voltage

1.25

0

V

V_I

Input Voltage

2.925

450

V

V_ODIFF

V_OCM

V_ICM

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

250

1.125

0.05

100

350

mV

V

1.25

350

1.375

2.35

–

V

V_IDIFF

mV

Notes:

1.

5%

2. Differential input voltage = 350 mV

Table 2-83 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.075

1.325

Cross point

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

Timing Characteristics

Table 2-84 • LVDS

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Speed Grade

t_DOUT

0.64

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

2.05

1.74

1.79

1.52

0.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-49

Automotive ProASIC3 DC and Switching Characteristics

Table 2-85 • LVDS

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Speed Grade

t_DOUT

0.63

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

1.98

1.68

1.73

1.47

0.53

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-13. The input and output

buffer delays are available in the LVDS section in Table 2-84 on page 2-49.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

R_S= 60 Ω and R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-13 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-14

on page 2-51. The building blocks of the LVPECL transmitter-receiver are one transmitter macro,

one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver

end. The values for the three driver resistors are different from those used in the LVDS

implementation because the output standard specifications are different.

2-50

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Bourns Part Number: CAT16-PC4F12

FPGA

P

OUTBUF_LVPECL

100 Ω

Z₀= 50 Ω

187 W

Z₀= 50 Ω

INBUF_LVPECL

+

–

100 Ω

N

Figure 2-14 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-86 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Supply Voltage

Min. Max. Min. Max. Min. Max. Units

3.0

3.3

3.6

V

V_OL

Output LOW Voltage

0.96

1.8

0

1.27

2.11

3.3

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.9

V_OH

Output HIGH Voltage

V

V_IL, V_IH

V_ODIFF

V_OCM

Input LOW, Input HIGH Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

V

0.625 0.97 0.625 0.97 0.625 0.97

1.762 1.98 1.762 1.98 1.762 1.98

V

V_ICM

1.01

300

2.57

1.01

300

2.57

1.01

300

2.57

V

V_IDIFF

mV

Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.64

1.94

Cross point

* Measuring point = V_trip.See Table 2-18 on page 2-17 for a complete table of trip points.

Timing Characteristics

Table 2-88 • LVPECL

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Speed Grade

t_DOUT

0.64

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

2.01

1.71

1.57

1.34

0.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-89 • LVPECL

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Speed Grade

t_DOUT

0.63

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

1.95

1.66

1.52

1.29

0.53

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

v1.0

2-51

Automotive ProASIC3 DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

L

D

DOUT

EOUT

Data_out

PRE

DFN1E1P1

F

PRE

DFN1E1P1

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

G

E

B

H

I

A

PRE

DFN1E1P1

J

D

Q

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-15 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-52

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-90 • Parameter Definition and Measuring Nodes

Measuring Nodes

Parameter Name

Parameter Definition

(from, to)*

H, DOUT

F, H

t_OCLKQ

t_OSUD

Clock-to-Q of the Output Data Register

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

J, H

t_OESUE

t_OEHE

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-15 on page 2-52 for more information.

v1.0

2-53

Automotive ProASIC3 DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

CLR

LL

HH

AA

DD

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-16 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-54

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-91 • Parameter Definitions and Measuring Nodes

Measuring Nodes

Parameter Name

Parameter Definition

(from, to)*

HH, DOUT

FF, HH

t_OCLKQ

t_OSUD

Clock-to-Q of the Output Data Register

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

* See Figure 2-16 on page 2-54 for more information.

v1.0

2-55

Automotive ProASIC3 DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

1

CLK

t_IHD

t_ISUD

50%

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-17 • Input Register Timing Diagram

Timing Characteristics

Table 2-92 • Input Data Register Propagation Delays

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V

Parameter

t_ICLKQ

Description

–1 Std. Units

Clock-to-Q of the Input Data Register

0.29 0.34

0.32 0.38

0.00 0.00

0.45 0.53

0.00 0.00

0.55 0.65

0.00 0.00

0.27 0.32

0.00 0.00

0.27 0.32

0.25 0.30

0.41 0.48

0.37 0.43

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

Enable Hold Time for the Input Data Register

t_IHE

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

2-56

v1.0

Automotive ProASIC3 DC and Switching Characteristics

Table 2-93 • Input Data Register Propagation Delays

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V

Parameter

t_ICLKQ

Description

–1 Std. Units

Clock-to-Q of the Input Data Register

0.29 0.34

0.31 0.37

0.00 0.00

0.44 0.52

0.00 0.00

0.54 0.64

0.00 0.00

0.27 0.31

0.00 0.00

0.27 0.31

0.25 0.30

0.41 0.48

0.37 0.43

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Output Register

t

OCKMPWH OCKMPWL

50%

t

50%

1

CLK

t

OSUD OHD

50%

0

Data_out

t

OREMPRE

Enable

Preset

50%

t

OWPRE

ORECPRE

50%

t

OHE

50%

t

OSUE

t

OREMCLR

50%

t

ORECCLR

OWCLR

50%

Clear

t

OPRE2Q

50%

DOUT

t

OCLR2Q

t

OCLKQ

Figure 2-18 • Output Register Timing Diagram

v1.0

2-57

Automotive ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-94 • Output Data Register Propagation Delays

Automotive-Case Conditions: T_J= 135°C, Worst-Case V_CC= 1.425 V

Parameter

t_OCLKQ

t_OSUD

Description

–1 Std. Units

Clock-to-Q of the Output Data Register

0.72 0.84

0.38 0.45

0.00 0.00

0.53 0.63

0.00 0.00

0.98 1.15

0.00 0.00

0.27 0.32

0.00 0.00

0.27 0.32

0.25 0.30

0.41 0.48

0.37 0.43

ns

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width HIGH for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating

values.

Table 2-95 • Output Data Register Propagation Delays

Automotive-Case Conditions: T_J= 115°C, Worst-Case V_CC= 1.425 V

Parameter

t_OCLKQ

t_OSUD

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.70 0.82

0.37 0.44

0.00 0.00

0.52 0.61

0.00 0.00

0.96 1.12