A42MX24-3TQ176IX39_技术文档

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40MX and 42MX FPGA Families

F e a t u r e s

H ig h C a p a c i t y

• Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

• Single-Chip ASIC Alternative

• 3,000 to 54,000 System Gates

• QML Certification

• Up to 2.5 kbits Configurable Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Ceramic Devices Available to DSCC SMD

E a s e o f I n t e g r a t io n

• Up to 202 User-Programmable I/O Pins

• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os),

with PCI-Compliant I/Os

H ig h P e r f o r m a n c e

• 5.6 ns Clock-to-Out

• Up to 100% Resource Utilization and 100% Pin Locking

• Deterministic, User-Controllable Timing

• 250 MHz Performance

• 5 ns Dual-Port SRAM Access

• 100 MHz FIFOs

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• 7.5 ns 35-Bit Address Decode

• Low Power Consumption

H iR e l F e a t u r e s

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

• Commercial, Industrial, Automotive, and Military

Temperature Plastic Packages

P r o d u c t P r o f i l e

Device

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

Capacity

System Gates

SRAM Bits

3,000

–

6,000

–

14,000

–

24,000

–

36,000

–

54,000

2,560

Logic Modules

Sequential

Combinatorial

Decode

–

295

–

547

–

348

336

–

624

608

–

954

912

24

1,230

1,184

24

Clock-to-Out

9.5 ns

5.6 ns

6.1 ns

6.3 ns

SRAM Modules

(64x4 or 32x8)

–

348

516

2

–

624

928

2

–

954

1,410

2

10

1,230

1,822

6

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

147

1

273

1

User I/O (maximum)

PCI

57

–

69

–

104

–

140

–

176

Yes

202

Yes

Boundary Scan Test (BST)

–

Packages (by pin count))

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

44, 68

44, 68, 84

84

100, 160

100

176

–

84

160, 208

–

208, 240

–

100

80

–

100

80

–

100, 160, 208

100

176

–

176

–

208, 256

272

–

J a n u a r y 2 0 0 4

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

O r d e r i n g I n f o r m a t i o n

A42MX16

PQ

100

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

A = Automotive (–40 to +125°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

BG = Plastic Ball Grid Array

CQ = Ceramic Quad Flat Pack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

–F = Approximately 40% Slower than Standard

Part Number

A40MX02 = 3,000 System Gates

A40MX04 = 6,000 System Gates

A42MX09 = 14,000 System Gates

A42MX16 = 24,000 System Gates

A42MX24 = 36,000 System Gates

A42MX36 = 54,000 System Gates

P l a s t i c D e v i c e R e s o u r c e s

User I/Os

PLCC

44-Pin

PLCC

PQFP

VQFP

TQFP

PBGA

Device

68-Pin 84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

34

–

57

–

57

69

83

–

57

69

–

69

72

–

101

125

–

83

–

104

140

150

–

140

176

–

202

–

202

Package Definitions

PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,

PBGA = Plastic Ball Grid Array

C e r a m i c D e v i c e R e s o u r c e s

User I/Os

CQFP

208-Pin

CQFP

256-Pin

Device

A42MX36

Package Definitions

CQFP = Ceramic Quad Flat Pack

176

202

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T e m p e r a t u r e G r a d e O f f e r i n g s

Package

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

PLCC 44

C, I, M

PLCC 68

C, I, A, M

PLCC 84

C, I, A, M

C, I, M

PQFP 100

PQFP 160

PQFP 208

PQFP 240

VQFP 80

VQFP 100

TQFP 176

PBGA 272

CQFP 208

CQFP 256

C, I, A, M

C, I, M

C, I, A, M

C, I, M

C, M, B

Notes:

C = Commercial

I = Industrial

A = Automotive

M = Military

B = MIL-STD-883 Class B

S p e e d G r a d e O f f e r i n g s

– F

Std

–1

✓

–2

✓

–3

✓

C

I

✓

A

M

B

✓

Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.

C o n t a c t y o u r lo c a l Ac t e l r e p r e s e n t a t iv e fo r d e v ic e a v a ila b ilit y .

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G e n e r a l D e s c r i p t i o n

M X A r c h i t e c t u r a l O v e r v i e w

Actel’s 40MX and 42MX families offer a cost-effective design

solution at 5V. The MX devices are single-chip solutions and

provide high performance while shortening the system

design and development cycle. MX devices can integrate and

consolidate logic implemented in multiple PALs, CPLDs,

and FPGAs. Example applications include high-speed

controllers and address decoding, peripheral bus interfaces,

DSP, and co-processor functions.

The MX devices are composed of fine-grained building

blocks that enable fast, efficient logic designs. All devices

within these families are composed of logic modules, I/O

modules, routing resources and clock networks, which are

the building blocks for fast logic designs. In addition, the

A42MX36 device contains embedded dual-port SRAM

modules, which are optimized for high-speed datapath

functions such as FIFOs, LIFOs and scratchpad memory.

A42MX24 and A42MX36 also contain wide-decode modules.

The MX device architecture is based on Actel’s patented

antifuse technology implemented in a 0.45µm triple-metal

CMOS process. With capacities ranging from 3,000 to 54,000

system gates, the MX devices provide performance up to

250 MHz, are live on power-up and have one-fifth the

standby power consumption of comparable FPGAs. Actel’s

MX FPGAs provide up to 202 user I/Os and are available in a

wide variety of packages and speed grades.

L o g ic M o d u le s

The 40MX logic module is an eight-input, one-output logic

circuit designed to implement a wide range of logic

functions with efficient use of interconnect routing

resources (Figure 1).

The logic module can implement the four basic logic

functions (NAND, AND, OR and NOR) in gates of two, three,

or four inputs. The logic module can also implement a

variety of D-latches, exclusivity functions, AND-ORs and

OR-ANDs. No dedicated hard-wired latches or flip-flops are

required in the array; latches and flip-flops can be

constructed from logic modules whenever required in the

application.

Actel’s A42MX24 and A42MX36 devices also feature

MultiPlex I/Os, which support mixed-voltage systems,

enable programmable PCI, deliver high-performance

operation at both 5.0V and 3.3V, and provide a low-power

mode. The devices are fully compliant with the PCI Local

Bus Specification (version 2.1). They deliver 200 MHz

on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level

features such as IEEE Standard 1149.1 (JTAG) Boundary

Scan Testing and fast wide-decode modules. In addition, the

A42MX36 device offers dual-port SRAM for implementing

fast FIFOs, LIFOs, and temporary data storage. The storage

elements can efficiently address applications requiring wide

datapath manipulation and can perform transformation

functions such as those required for telecommunications,

networking, and DSP.

All MX devices are fully tested over automotive and military

temperature ranges. In addition, the largest member of the

family, the A42MX36, is available in both CQ208 and CQ256

ceramic packages screened to MIL-STD-883 levels. For easy

prototyping and conversion from plastic to ceramic, the

CQ208 and PQ208 devices are pin-compatible.

Figure 1 • 40MX Logic Module

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The 42MX devices contain three types of logic modules:

combinatorial (C-modules), sequential (S-modules) and

decode (D-modules). Figure 2 illustrates the combinatorial

logic module. The S-module, shown in Figure 3, implements

the same combinatorial logic function as the C-module

while adding a sequential element. The sequential element

can be configured as either a D-flip-flop or a transparent

latch. The S-module register can be bypassed so that it

implements purely combinatorial logic.

A0

B0

S0

D00

D01

D10

D11

Y

S1

A1

B1

Figure 2 • 42MX C-Module Implementation

D00

D01

D00

D01

OUT

Y

D

Q

Y

D

Q

D10

S0

D11

S1

D11

S1

S0

GATE

CLR

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D00

D01

D0

Y

OUT

Y

D

Q

D10

S0

D1

D11

S1

GATE

S

CLR

Up to 8-Input Function (Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 3 • 42MX S-Module Implementation

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A42MX24 and A42MX36 devices contain D-modules, which

are arranged around the periphery of the device. D-modules

contain wide-decode circuitry, providing a fast, wide-input

AND function similar to that found in CPLD architectures

(Figure 4). The D-module allows A42MX24 and A42MX36

devices to perform wide-decode functions at speeds

comparable to CPLDs and PALs. The output of the D-module

has a programmable inverter for active HIGH or LOW

assertion. The D-module output is hardwired to an output

pin, and can also be fed back into the array to be

incorporated into other logic.

offering active HIGH or LOW implementation. The SRAM

block contains eight data inputs (WD[7:0]), and eight

outputs (RD[7:0]), which are connected to segmented

vertical routing tracks.

The A42MX36 dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring FIFO

and LIFO queues. The ACTgen Macro Builder within Actel’s

Designer software provides capability to quickly design

memory functions with the SRAM blocks. Unused SRAM

blocks can be used to implement registers for other user

logic within the design.

D u a l-P o r t S R A M M o d u le s

The A42MX36 device contains dual-port SRAM modules that

have been optimized for synchronous or asynchronous

applications. The SRAM modules are arranged in 256-bit

blocks that can be configured as 32x8 or 64x4. SRAM

modules can be cascaded together to form memory spaces of

user-definable width and depth. A block diagram of the

A42MX36 dual-port SRAM block is shown in Figure 5.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

The A42MX36 SRAM modules are true dual-port structures

containing independent read and write ports. Each SRAM

module contains six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM block contain independent

clocks (RCLK and WCLK) with programmable polarities

Feedback to Array

Figure 4 • A42MX24 and A42MX36 D-Module

Implementation

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 Bits)

WRAD[5:0]

[5:0]

Read

Logic

Latches

REN

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 5 • A42MX36 Dual-Port SRAM Block

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R o u t i n g S t r u c t u r e

Segmented

Horizontal

Routing

The MX architecture uses vertical and horizontal routing

tracks to interconnect the various logic and I/O modules.

These routing tracks are metal interconnects that may be

continuous or split into segments. Varying segment lengths

allow the interconnect of over 90% of design tracks to occur

with only two antifuse connections. Segments can be joined

together at the ends using antifuses to increase their

lengths up to the full length of the track. All interconnects

can be accomplished with a maximum of four antifuses.

Logic

Modules

Tracks

Antifuses

Horizontal Routing

Horizontal routing tracks span the whole row length or are

divided into multiple segments and are located in between

the rows of modules. Any segment that spans more than

one-third of the row length is considered a long horizontal

segment. A typical channel is shown in Figure 6. Within

horizontal routing, dedicated routing tracks are used for

global clock networks and for power and ground tie-off

tracks. Non-dedicated tracks are used for signal nets.

Vertical Routing Tracks

Figure 6 • MX Routing Structure

C l o c k N e t w o r k s

The 40MX devices have one global clock distribution

network (CLK). A signal can be put on the CLK network by

being routed through the CLKBUF buffer.

In 42MX devices, there are two low-skew, high-fanout clock

distribution networks, referred to as CLKA and CLKB. Each

network has a clock module (CLKMOD) that can select the

source of the clock signal from any of the following

(Figure 7 on page 8):

Vertical Routing

Another set of routing tracks run vertically through the

module. There are three types of vertical tracks: input,

output, and long. Long tracks span the column length of the

module, and can be divided into multiple segments. Each

segment in an input track is dedicated to the input of a

particular module; each segment in an output track is

dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

routing. Each output segment spans four channels (two

above and two below), except near the top and bottom of

the array, where edge effects occur. Long vertical tracks

contain either one or two segments. An example of vertical

routing tracks and segments is shown in Figure 6.

• Externally from the CLKA pad, using CLKBUF buffer

• Externally from the CLKB pad, using CLKBUF buffer

• Internally from the CLKINTA input, using CLKINT buffer

• Internally from the CLKINTB input, using CLKINT buffer

The clock modules are located in the top row of I/O

modules. Clock drivers and a dedicated horizontal clock

track are located in each horizontal routing channel.

Clock input pads in both 40MX and 42MX devices can also

be used as normal I/Os, bypassing the clock networks.

Antifuse Structures

The A42MX36 device has four additional register control

resources, called quadrant clock networks (Figure 8 on

page 8). Each quadrant clock provides a local, high-fanout

resource to the contiguous logic modules within its

quadrant of the device. Quadrant clock signals can originate

from specific I/O pins or from the internal array and can be

used as a secondary register clock, register clear, or output

enable.

An antifuse is a "normally open" structure. The use of

antifuses to implement a programmable logic device results

in highly testable structures as well as efficient

programming algorithms. There are no pre-existing

connections; temporary connections can be made using

pass transistors. These temporary connections can isolate

individual antifuses to be programmed and individual

circuit structures to be tested, which can be done before

and after programming. For instance, all metal tracks can

be tested for continuity and shorts between adjacent tracks,

and the functionality of all logic modules can be verified.

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CLKB

CLKA

CLKINB

CLKINA

From

Pads

S0

S1

Internal

Signal

CLKMOD

CLKO(17)

Clock

Drivers

CLKO(16)

CLKO(15)

CLKO(2)

CLKO(1)

Clock Tracks

Figure 7 • Clock Networks of 42MX Devices

QCLKA

QCLKC

Quad

Clock

Quad

Clock

QCLK1

QCLK3

QCLKB

QCLKD

Module

*QCLK1IN

*QCLK3IN

S1 S0

S0 S1

Quad

Clock

Module

Quad

Clock

Module

QCLK2

QCLK4

*QCLK2IN

*QCLK4IN

S1 S0

S0 S1

*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 8 • Quadrant Clock Network of A42MX36 Devices

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M u l t i P le x I /O M o d u l e s

42MX devices feature Multiplex I/Os and support 5.0V, 3.3V,

and mixed 3.3V/5.0V operations.

STD

The MultiPlex I/O modules provide the interface between

the device pins and the logic array. Figure 9 is a block

diagram of the 42MX I/O module. A variety of user functions,

determined by a library macro selection, can be

implemented in the module. (Refer to the Antifuse Macro

Library Guide for more information.) All 42MX I/O modules

contain tristate buffers, with input and output latches that

can be configured for input, output, or bidirectional

operation.

Signal

Output

PCI

Drive

PCI Enable

Fuse

Figure 10 • PCI Output Structure of A42MX24 and

All 42MX devices contain flexible I/O structures, where

each output pin has a dedicated output-enable control

(Figure 9). The I/O module can be used to latch input or

output data, or both, providing fast set-up time. In addition,

the Actel Designer software tools can build a D-type flip-flop

using a C-module combined with an I/O module to register

input and output signals. Refer to the Antifuse Macro

Library Guide for more details.

A42MX36 Devices

O t h e r A r c h i t e c t u r a l F e a t u r e s

P e r f o r m a n c e

MX devices can operate with internal clock frequencies of

250 MHz, enabling fast execution of complex logic

functions. MX devices are live on power-up and do not

require auxiliary configuration devices and thus are an

optimal platform to integrate the functionality contained in

multiple programmable logic devices. In addition, designs

that previously would have required a gate array to meet

performance can be integrated into an MX device with

improvements in cost and time-to-market. Using

timing-driven place-and-route (TDPR) tools, designers can

achieve highly deterministic device performance.

A42MX24 and A42MX36 devices also offer selectable PCI

output drives, enabling 100% compliance with version 2.1 of

the PCI specification. For low-power systems, all inputs and

outputs are turned off to reduce current consumption to

below 500µA.

To achieve 5.0V or 3.3V PCI-compliant output drives on

A42MX24 and A42MX36 devices, a chip-wide PCI fuse is

programmed via the Device Selection Wizard in the

Designer software (Figure 10). When the PCI fuse is not

programmed, the output drive is standard.

U s e r S e c u r it y

The Actel FuseLock provides robust security against design

theft. Special security fuses are hidden in the fabric of the

device and prevent unauthorized users from accessing the

programming and/or probe interfaces. It is virtually

impossible to identify or bypass these fuses without

damaging the device, making Actel antifuse FPGAs immune

to both invasive and noninvasive attacks.

Actel’s Designer software development tools provide a

design library of I/O macro functions that can implement all

I/O configurations supported by the MX FPGAs.

EN

Special security fuses in 40MX devices include the Probe

Fuse and Program Fuse. The former disables the probing

circuitry while the latter prohibits further programming of

all fuses, including the Probe Fuse. In 42MX devices, there

is the Security Fuse which, when programmed, both

disables the probing circuitry and prohibits further

programming of the device.

Q

D

PAD

From Array

To Array

G/CLK*

Look for this symbol to ensure your valuable IP is secure.

Q

D

For more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

G/CLK*

* Can be Configured as a Latch or D Flip-Flop

(Using C-Module)

Figure 9 • 42MX I/O Module

FuseLock

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P r o g r a m m i n g

1. Load the .AFM file

Device programming is supported through the Silicon

Sculptor series of programmers. Silicon Sculptor II is a

compact, robust, single-site and multi-site device

programmer for the PC. With standalone software, Silicon

Sculptor II is designed to allow concurrent programming of

multiple units from the same PC.

2. Select the device to be programmed

3. Begin programming

When the design is ready to go to production, Actel offers

device volume-programming services either through

distribution partners or via In-House Programming from the

factory.

Silicon Sculptor II programs devices independently to

achieve the fastest programming times possible. After being

programmed, each fuse is verified to insure that it has been

programmed correctly. Furthermore, at the end of

programming, there are integrity tests that are run to

ensure no extra fuses have been programmed. Not only does

it test fuses (both programmed and nonprogrammed),

Silicon Sculptor II also allows self-test to verify its own

hardware extensively.

For more details on programming MX devices, please refer

to the Programming Actel Devices and the Silicon Sculptor

II user’s guides.

P o w e r S u p p l y

MX devices are designed to operate in both 5.0V and 3.3V

environments. In particular, 42MX devices can operate in

mixed 5.0V/3.3V systems. Table 1 describes the voltage

support of MX devices.

The procedure for programming an MX device using Silicon

Sculptor II is as follows:

Table 1 • Voltage Support of MX Devices

Device

V_CC

V_CCA

V_CCI

Maximum Input Tolerance

Nominal Output Voltage

5.0V

3.3V

–

5.5V

3.6V

5.5V

3.6V

5.5V

5.0V

3.3V

5.0V

3.3V

40MX

–

5.0V

3.3V

5.0V

3.3V

42MX

–

P o w e r -U p /D o w n i n M ix e d -V o lt a g e M o d e

L o w P o w e r M o d e

When powering up 42MX in mixed voltage mode

(V_CCA= 5.0V and V_CCI= 3.3V), V_CCAmust be greater than or

42MX devices have been designed with a Low Power Mode.

This feature, activated with setting the special LP pin to

HIGH for a period longer than 800 ns, is particularly useful

for battery-operated systems where battery life is a primary

concern. In this mode, the core of the device is turned off

and the device consumes minimal power with low standby

current. In addition, all input buffers are turned off, and all

outputs and bidirectional buffers are tristated. Since the

core of the device is turned off, the states of the registers

are lost. The device must be re-initialized when exiting Low

Power Mode. I/Os can be driven during LP mode, and clock

pins should be driven HIGH or LOW and should not float to

avoid drawing current. To exit LP mode, the LP pin must be

pulled LOW for over 200 µs to allow for charge pumps to

power up, and device initialization will begin.

equal to V throughout the power-up sequence. If V

CCI

exceeds V

during power up, either the I/Os’ input

CCA

protection junction on the I/Os will be forward-biased or the

I/Os will be at logical HIGH, and I_CCrises to high levels. For

power-down, any sequence with V

and V can be

CCA

CCI

implemented.

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P o w e r D i s s i p a t i o n

V

= Power supply in volts (V)

CCA

The general power consumption of MX devices is made up of

static and dynamic power and can be expressed with the

following equation:

F

= Switching frequency in megahertz (MHz)

E q u i v a l e n t C a p a c it a n c e

Equivalent capacitance is calculated by measuring

I_CCactive at a specified frequency and voltage for each

circuit component of interest. Measurements have been

G e n e r a l P o w e r E q u a t i o n

P = [I_CCstandby + I_CCactive] * V_CCI+ I_OL* V * N

OL

+ I_OH* (V_CCI– V ) * M

made over a range of frequencies at a fixed value of V

.

OH

CC

Equivalent capacitance is frequency-independent, so the

results can be used over a wide range of operating

conditions. Equivalent capacitance values are shown below.

where:

I_CCstandby is the current flowing when no inputs or

outputs are changing.

C _{E Q}Va lu e s f o r A c t e l M X F P G A s

I_CCactive is the current flowing due to CMOS switching.

I_OL, I_OHare TTL sink/source currents.

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

)

3.5

6.9

)

V , V_OHare TTL level output voltages.

OL

)

18.2

1.4

N equals the number of outputs driving TTL loads to V .

OL

)

M equals the number of outputs driving TTL loads to V .

OH

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic

must be known. The equation below shows a piece-wise

linear summation over all components.

Accurate values for N and M are difficult to determine

because they depend on the family type, on design details,

and on the system I/O. The power can be divided into two

components: static and active.

Power = V ²* [(m x C_EQM* f_m)_Modules

+

CCA

S t a t i c P o w e r C o m p o n e n t

(n * C_EQI* f_n)_Inputs+ (p * (C_EQO+ C_L) * f_p)_outputs

+

The static power due to standby current is typically a small

component of the overall power consumption. Standby

power is calculated for commercial, worst-case conditions.

The static power dissipation by TTL loads depends on the

number of outputs driving, and on the DC load current. For

instance, a 32-bit bus sinking 4mA at 0.33V will generate

42mW with all outputs driving LOW, and 140mW with all

outputs driving HIGH. The actual dissipation will average

somewhere in between, as I/Os switch states with time.

0.5 * (q₁* C_EQCR* f_q1)_{routed_Clk1}+ (r₁* f_q1)_{routed_Clk1}

0.5 * (q₂* C_EQCR* f_q2)_{routed_Clk2}+ (r₂* f_q2)_{routed_Clk2}

+

(2)

where:

m

n

= Number of logic modules switching at frequency f_m

= Number of input buffers switching at frequency f_n

= Number of output buffers switching at frequency f_p

p

q₁

= Number of clock loads on the first routed array

clock

A c t i v e P o w e r C o m p o n e n t

q₂

= Number of clock loads on the second routed array

clock

Power dissipation in CMOS devices is usually dominated by

the dynamic power dissipation. Dynamic power

consumption is frequency-dependent and is a function of

the logic and the external I/O. Active power dissipation

results from charging internal chip capacitances of the

interconnect, unprogrammed antifuses, module inputs, and

module outputs, plus external capacitances due to PC board

traces and load device inputs. An additional component of

the active power dissipation is the totem pole current in the

CMOS transistor pairs. The net effect can be associated

with an equivalent capacitance that can be combined with

frequency and voltage to represent active power dissipation.

r₁

r₂

= Fixed capacitance due to first routed array clock

= Fixed capacitance due to second routed array

clock

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

C_EQCR= Equivalent capacitance of routed array clock in pF

C_L

f_m

f_n

= Output load capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

= Average second routed array clock rate in MHz

The power dissipated by a CMOS circuit can be expressed by

the equation:

f_p

Power (µW) = C_EQ* V ²* F

(1)

CCA

f_q1

f_q2

where:

C_EQ= Equivalent capacitance expressed in picofarads

(pF)

v6 .0

1 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

F i x e d C a p a c i t a n c e Va l u e s fo r MX F P G A s ( p F )

functional 18-channel logic analyzer. Silicon Explorer II

allows designers to complete the design verification process

at their desks and reduces verification time from several

hours per cycle to a few seconds.

r₁

r₂

Device Type

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

routed_Clk1 routed_Clk2

41.4

68.6

118

165

185

220

N/A

118

165

185

220

Silicon Explorer II is used to control the MODE, DCLK, SDI

and SDO pins in MX devices to select the desired nets for

debugging. The user simply assigns the selected internal

nets in the Silicon Explorer II software to the PRA/PRB

output pins for observation. Probing functionality is

activated when the MODE pin is held HIGH.

Figure 11 illustrates the interconnection between Silicon

Explorer II and 40MX devices, while Figure 12 on page 13

illustrates the interconnection between Silicon Explorer II

and 42MX devices

T e s t C ir c u it r y a n d S i li c o n E x p lo r e r I I P r o b e

MX devices contain probing circuitry that provides built-in

access to every node in a design, via the use of Silicon

Explorer II. Silicon Explorer II is an integrated hardware

and software solution that, in conjunction with the Designer

software, allow users to examine any of the internal nets of

the device while it is operating in a prototyping or a

production system. The user can probe into an MX device

without changing the placement and routing of the design

and without using any additional resources. Silicon

Explorer II’s noninvasive method does not alter timing or

loading effects, thus shortening the debug cycle and

providing a true representation of the device under actual

functional situations.

To allow for probing capabilities, the security fuses must not

be programmed. (Refer to “User Security” section on page 9

for the security fuses of 40MX and 42MX devices). Table 2 on

page 13 summarizes the possible device configurations for

probing.

PRA and PRB pins are dual-purpose pins. When the

"Reserve

Probe

Pin"

is

checked

in

the

Designer software, PRA and PRB pins are reserved as

dedicated outputs for probing. If PRA and PRB pins are

required as user I/Os to achieve successful layout and

"Reserve Probe Pin" is checked, the layout tool will override

the option and place user I/Os on PRA and PRB pins.

Silicon Explorer II samples data at 100 MHz (asynchronous)

or 66 MHz (synchronous). Silicon Explorer II attaches to a

PC’s standard COM port, turning the PC into a fully

16 Logic Analyzer Channels

40MX

Serial Connection

to Windows PC

MODE

SDI

Silicon

Explorer II

DCLK

SDO

PRA

PRB

Figure 11 • Silicon Explorer II Setup with 40MX

1 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

16 Logic Analyzer Channels

42MX

Serial Connection

to Windows PC

MODE

SDI

Silicon

Explorer II

DCLK

SDO

PRA

PRB

Figure 12 • Silicon Explorer II Setup with 42MX

Table 2 • Device Configuration Options for Probe Capability

Security Fuse(s)

Programmed

MODE

PRA, PRB¹

User I/Os²

SDI, SDO, DCLK¹

No

LOW

HIGH

–

User I/Os²

No

Probe Circuit Outputs

Probe Circuit Secured

Probe Circuit Inputs

Probe Circuit Secured

Yes

Notes:

1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals

will not pass through these pins and may cause contention.

2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the “Pin Descriptions” section on page 80 for

information on unused I/O pins.

D e s ig n C o n s id e r a t i o n

rising edge of TCK for the given state transition to occur. IR

It is recommended to use a series 70Ω termination resistor

on every probe connector (SDI, SDO, MODE, DCLK, PRA

and PRB). The 70Ω series termination is used to prevent

data transmission corruption during probing and reading

back the checksum.

and DR indicate that the instruction register or the data

register is operating in that state.

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest of

the test logic architecture. On power-up, the TAP controller

enters the Test-Logic-Reset state. To guarantee a reset of

the controller from any of the possible states, TMS must

remain high for five TCK cycles.

I E E E S t a n d a r d 1 1 4 9 . 1 B o u n d a r y S c a n T e s t

( B S T ) C ir c u it r y

42MX24 and 42MX36 devices are compatible with IEEE

Standard 1149.1 (informally known as Joint Testing Action

Group Standard or JTAG), which defines a set of hardware

architecture and mechanisms for cost-effective board-level

testing. The basic MX boundary-scan logic circuit is

composed of the TAP (test access port), TAP controller, test

data registers and instruction register (Figure 13 on

page 14). This circuit supports all mandatory IEEE 1149.1

instructions (EXTEST, SAMPLE/PRELOAD and BYPASS)

and some optional instructions. Table 3 on page 14

describes the ports that control JTAG testing, while Table 4

on page 14 describes the test instructions supported by

these MX devices.

42MX24 and 42MX36 devices support three types of test

data registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other register

needs to be accessed in a device. This speeds up test data

transfer to other devices in a test data path. The 32-bit

device identification register is a shift register with four

fields (lowest significant byte (LSB), ID number, part

number and version). The boundary-scan register observes

and controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out pin.

The serial pins are used to serially connect all the

Each test section is accessed through the TAP, which has

four associated pins: TCK (test clock input), TDI and TDO

(test data input and output), and TMS (test mode selector).

boundary-scan register cells in

a

device into a

boundary-scan register chain, which starts at the TDI pin

and ends at the TDO pin. The parallel ports are connected

to the internal core logic tile and the input, output and

control ports of an I/O buffer to capture and load data into

the register to control or observe the logic state of each I/O.

The TAP controller is a four-bit state machine. The ’1’s and

’0’s represent the values that must be present at TMS at a

v6 .0

1 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

Boundary Scan Register

Output

TDO

MUX

Bypass

Register

Control Logic

JTAG

TMS

TCK

JTAG

TDI

Instruction

Decode

TAP Controller

Instruction

Register

Figure 13 • 42MX IEEE 1149.1 Boundary Scan Circuitry

Table 3 • Test Access Port Descriptions

Port

Description

Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock

(TCK).

TMS (Test Mode Select)

TCK (Test Clock Input)

Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the

rising edge of the clock, and serially to shift the output data on the falling edge of the clock. The

maximum clock frequency for TCK is 20 MHz.

Serial input for instruction and test data. Data is captured on the rising edge of the test logic

clock.

TDI (Test Data Input)

Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state

(high impedance) when data scanning is not in progress.

TDO (Test Data Output)

Table 4 • Supported BST Public Instructions

Instruction

IR Code (IR2.IR0)

Instruction Type

Description

Allows the external circuitry and board-level

EXTEST

000

Mandatory

interconnections to be tested by forcing a test pattern at

the output pins and capturing test results at the input pins.

Allows a snapshot of the signals at the device pins to be

captured and examined during operation

SAMPLE/PRELOAD

HIGH Z

001

101

Mandatory

Optional

Tristates all I/Os to allow external signals to drive pins.

Please refer to the IEEE Standard 1149.1 specification.

Allows state of signals driven from component pins to be

determined from the Boundary-Scan Register. Please

refer to the IEEE Standard 1149.1 specification for details.

CLAMP

110

111

Optional

Enables the bypass register between the TDI and TDO

pins. The test data passes through the selected device to

adjacent devices in the test chain.

BYPASS

Mandatory

1 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

J T A G M o d e A c t iv a t i o n

The JTAG test logic circuit is activated in the Designer

software by selecting Tools -> Device Selection. This brings

up the Device Selection dialog box as shown in Figure 14.

The JTAG test logic circuit can be enabled by clicking the

"Reserve JTAG Pins" check box. Table 5 explains the pins’

behavior in either mode.

Figure 14 • Device Selection Wizard

Table 5 • Boundary Scan Pin Configuration and Functionality

Reserve JTAG

Checked

Unchecked

TCK

TDI, TMS

TDO

BST input; must be terminated to logical HIGH or LOW to avoid floating

BST input; may float or be tied to HIGH

BST output; may float or be connected to TDI of another device

User I/O

T R S T P in a n d T A P C o n t r o l le r R e s e t

and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment. Libero IDE

includes Synplify® for Actel from Synplicity®, ViewDraw

for Actel from Mentor Graphics, ModelSim™ HDL

Simulator from Mentor Graphics®, WaveFormer Lite™

from SynaptiCAD™, and Designer software from Actel.

Refer to the Libero IDE flow (located on Actel’s website)

diagram for more information.

An active reset (TRST) pin is not supported; however, MX

devices contain power-on circuitry that resets the boundary

scan circuitry upon power-up. Also, the TMS pin is equipped

with an internal pull-up resistor. This allows the TAP

controller to remain in or return to the Test-Logic-Reset

state when there is no input or when a logical 1 is on the

TMS pin. To reset the controller, TMS must be HIGH for at

least five TCK cycles.

B o u n d a r y S c a n D e s c r i p t i o n L a n g u a g e

( B S D L ) F ile

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools for

FPGA development. The Designer software includes

timing-driven place-and-route, and a world-class integrated

static timing analyzer and constraints editor. With the

Designer software, a user can lock his/her design pins

before layout while minimally impacting the results of

place-and-route. Additionally, the back-annotation flow is

compatible with all the major simulators and the simulation

results can be cross-probed with Silicon Explorer II, Actel’s

integrated verification and logic analysis tool. Another tool

included in the Designer software is the ACTgen macro

builder, which easily creates popular and commonly used

logic functions for implementation into your schematic or

HDL design. Actel's Designer software is compatible with

the most popular FPGA design entry and verification tools

from companies such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

Conforming to the IEEE Standard 1149.1 requires that the

operation of the various JTAG components be documented.

The BSDL file provides the standard format to describe the

JTAG components that can be used by automatic test

equipment software. The file includes the instructions that

are supported, instruction bit pattern, and the

boundary-scan chain order. For an in-depth discussion on

BSDL files, please refer to Actel BSDL Files Format

Description application note.

Actel BSDL files are grouped into two categories - generic

and device-specific. The generic files assign all user I/Os as

inouts. Device-specific files assign user I/Os as inputs,

outputs or inouts.

Generic files for MX devices are available on Actel’s website

at http://www.actel.com/techdocs/models/bsdl.html.

D e v e l o p m e n t T o o l S u p p o r t

The MX family of FPGAs is fully supported by both Actel’s

Libero™ Integrated Design Environment and Designer

FPGA Development software. Actel Libero IDE is a design

management environment that streamlines the design flow.

Libero IDE provides an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log files,

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

companies such as Mentor Graphics, Synplicity, Synopsys,

and Cadence Design Systems. The Designer software is

available for both the Windows and UNIX operating systems.

v6 .0

1 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

R e l a t e d D o c u m e n t s

A p p li c a t io n N o t e s

Actel BSDL Files Format Description

http://www.actel.com/documents/BSDLformat.pdf

Programming Actel Devices

http://www.actel.com/documents/ProgrammingGuide.pdf

U s e r ’s G u i d e s a n d M a n u a ls

Antifuse Macro Library Guide

http://www.actel.com/documents/libguide.pdf

Actel’s Implementation of Security in Actel Antifuse FPGAs

http://www.actel.com/documents/AntifuseSecurityAN.pdf

Silicon Sculptor II

http://www.actel.com/techdocs/manuals/default.asp#programmers

M i s c e lla n e o u s

Libero IDE Flow Diagram

http://www.actel.com/products/tools/libero/flow.html

1 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

5 . 0 V O p e r a t i n g C o n d i t i o n s

A b s o l u t e M a x im u m R a t i n g s f o r 4 0 M X D e v ic e s *

Symbol

Parameter

Limits

Units

V_CC

V_I

DC Supply Voltage

Input Voltage

–0.5 to +7.0

–0.5 to V_CC+0.5

–65 to +150

V

V_O

Output Voltage

V

t_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended

Operating Conditions.

A b s o l u t e M a x im u m R a t i n g s f o r 4 2 M X D e v ic e s *

Symbol

Parameter

DC Supply Voltage for I/Os

Limits

Units

V_CCI

V_CCA

V_I

–0.5 to +7.0

V

DC Supply Voltage for Array

Input Voltage

–0.5 to V_CCI+0.5

–65 to +150

V

V_O

Output Voltage

V

t_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended

Operating Conditions.

R e c o m m e n d e d O p e r a t i n g C o n d it io n s

Parameter

Commercial

Industrial

Military

Units

Temperature Range*

V_CC(40MX)

0 to +70

-40 to +85

4.5 to 5.5

–55 to +125

4.5 to 5.5

°C

V

4.75 to 5.25

V

_CCA(42MX)

_CCI(42MX)

V

Note: *Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used for military grades.

v6 .0

1 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

5 V T T L E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Commercial -F

’Industrial

Military

Min

.

Symbol

Parameter

Min.

Max

Min.

Max

Min.

Max

Units

I_OH= -10mA

I_OH= -4mA

I_OL= 10mA

I_OL= 6mA

2.4

V

1

V_OH

3.7

0.5

0.8

0.5

0.8

V

1

V_OL

0.4

0.8

0.4

0.8

V

V_IL

-0.3

V

V_IH(40MX)

2.0 V_CC+0.3 2.0 V_CC+0.3

V

V_IH(42MX)

2.0 V_CCI+0.3 2.0 V_CCI+0.3 2.0 V_CCI+0.3 2.0 V_CCI+0.3

V

I_IL

V_IN= 0.5V

V_IN= 2.7V

-10

µA

I_IH

Input Transition Time, T_R

and T_F

500

10

3

500

10

500

10

500

10

ns

pF

C_IOI/O Capacitance

A40MX02,

A40MX04

25

10

25

mA

A42MX09

A42MX16

5

6

25

mA

2

Standby Current, I_CC

A42MX24,

A42MX36

20

25

mA

Low-Power Mode Standby 42MX devices

Current only

0.5

I

_CC- 5.0

I_CC- 5.0

I_IO, I/O source sink current Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)

Notes:

1. Only one output tested at a time. V /V_CCI= min.

CC

2. All outputs unloaded. All inputs = V /V_CCIor GND.

CC

1 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

3 . 3 V O p e r a t i n g C o n d i t i o n s

A b s o l u t e M a x im u m R a t i n g s f o r 4 0 M X D e v ic e s *

Symbol

Parameter

DC Supply Voltage

Limits

Units

V_CC

V_I

–0.5 to +7.0

–0.5 to V_CC+0.5

–65 to +150

V

Input Voltage

V_O

Output Voltage

V

t_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended

Operating Conditions.

A b s o l u t e M a x im u m R a t i n g s f o r 4 2 M X D e v ic e s *

Symbol

Parameter

Limits

Units

V_CCI

V_CCA

V_I

DC Supply Voltage for I/Os

DC Supply Voltage for Array

Input Voltage

–0.5 to +7.0

V

–0.5 to V_CCI+0.5

–65 to +150

V

V_O

Output Voltage

V

t_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended

Operating Conditions.

R e c o m m e n d e d O p e r a t i n g C o n d it io n s

Parameter

Commercial

Industrial

Military

Units

Temperature Range*

V_CC(40MX)

0 to +70

3.0 to 3.6

–40 to +85

3.0 to 3.6

–55 to +125

3.0 to 3.6

°C

V

_CCA(42MX)

_CCI(42MX)

V

Note: *Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used for military grades.

v6 .0

1 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

3 . 3 V L V T T L E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Commercial -F

Industrial

Military

Max

Symbol

Parameter

Min.

Max

Min.

Max

Min.

Max

Min.

Units

1

V_OH

I_OH= –4mA 2.15

I_OL= 6mA

2.15

2.4

V

1

V_OL

0.4

0.8

0.4

0.8

0.48

0.8

0.48

0.8

V_IL

–0.3

2.0

–0.3

V

V_IH(40MX)

2.0 V_CC+0.3

2.0 V_CCI+0.3

–10

V_CC+0.3 2.0 V_CC+0.3 2.0 V_CC+0.3

V_CCI+0.3 2.0 V_CCI+0.3 2.0 V_CCI+0.3

V

V_IH(42MX)

2.0

V

I_IL

–10

µA

I_IH

–10

Input Transition Time,

T_Rand T_F

500

10

3

500

10

500

10

500

10

ns

pF

C_IOI/O Capacitance

A40MX02,

A40MX04

25

10

25

mA

A42MX09

A42MX16

5

6

25

mA

2

Standby Current, I_CC

A42MX24,

A42MX36

15

25

mA

Low-Power Mode

Standby Current

42MX devices

only

0.5

I

_CC- 5.0

I_CC- 5.0

I_IO, I/O source sink

current

Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)

Notes:

1. Only one output tested at a time. V /V_CCI= min.

CC

2. All outputs unloaded. All inputs = V /V_CCIor GND.

CC

2 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

M i x e d 5 . 0 V /3 . 3 V O p e r a t i n g C o n d i t i o n s ( f o r 4 2 M X d e v i c e s o n l y )

A b s o l u t e M a x im u m R a t i n g s *

Symbol

Parameter

Limits

Units

V_CCI

V_CCA

V_I

DC Supply Voltage for I/Os

DC Supply Voltage for Array

Input Voltage

–0.5 to +7.0

V

–0.5 to V_CCI+0.5

–65 to +150

V

V_O

Output Voltage

V

t_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended

Operating Conditions.

R e c o m m e n d e d O p e r a t i n g C o n d it io n s

Parameter

Commercial

Industrial

Military

Units

Temperature Range*

0 to +70

-40 to +85

4.5 to 5.5

3.0 to 3.6

–55 to +125

4.5 to 5.5

3.0 to 3.6

°C

V

V_CCA

V_CCI

4.75 to 5.25

3.14 to 3.47

V

Note: *Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used for military grades.

M i x e d 5 . 0 V /3 . 3 V E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Commercial ’-F

’Industrial

Military

Symbol

Parameter

Min.

Max

Min.

Max

Min.

Max

Min.

Max

Units

I_OH= –10mA

I_OH= –4mA

I_OL= 10mA

I_OL= 6mA

2.4

V

1

V_OH

3.7

0.5

0.8

0.5

0.8

V

1

V_OL

0.4

0.8

0.4

0.8

V

V_IL

V_IH

I_L

–0.3

V

2.0 V_CCI+0.3 2.0 V_CCI+0.3 2.0 V_CCI+0.3 2.0 V_CCI+0.3

V

V_IN= 0.5V

V_IN= 2.7V

–10

µA

I_H

Input Transition Time,

T_Rand T_F

500

ns

C_IOI/O Capacitance

10

5

10

25

10

25

10

25

pF

mA

A42MX09

A42MX16

6

2

Standby Current, I_CC

A42MX24,

A42MX36

20

25

mA

Low-Power Mode

Standby Current

0.5

I_CC- 5.0

I_IOI/O source sink

current

Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)

Notes:

1. Only one output tested at a time. V_CCI= min.

2. All outputs unloaded. All inputs = V_CCIor GND.

v6 .0

2 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

O u t p u t D r i v e C h a r a c t e r i s t i c s f o r 5 . 0 V P C I S i g n a l i n g

MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 15 on page 24 shows the

typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus

Specification.

D C S p e c if i c a t io n ( 5 . 0 V P C I S ig n a li n g ) ¹

PCI

MX

Symbol Parameter

Condition

Min.

Max

Min.

Max

Units

V_CCI

V_IH

V_IL

I_IH

Supply Voltage for I/Os

4.75

2.0

5.25

V_CC+ 0.5

0.8

4.75

2.0

–0.3

—

5.25²

V_CCI+ 0.3

0.8

V

Input High Voltage

Input Low Voltage

–0.5

V

Input High Leakage Current

Input Low Leakage Current

V_IN= 2.7V

V_IN=0.5V

70

10

µA

I_IL

–70

—

–10

I_OUT= –2 mA

2.4

V_OH

Output High Voltage

Output Low Voltage

V

I

_OUT= –6 mA

3.84

—

I_OUT= 3 mA,

6 mA

V_OL

0.55

0.33

C_IN

Input Pin Capacitance

CLK Pin Capacitance

Pin Inductance

10

12

20

—

10

pF

nH

C_CLK

L_PIN

Notes:

5

< 8 nH³

1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.

2. Maximum rating for V –0.5V to 7.0V.

CCI

3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

A C S p e c if i c a t io n s ( 5 . 0 V P C I S i g n a l in g ) *

PCI

MX

Symbol Parameter

Condition

Min.

Max

Min.

Max

Units

I_CL

Low Clamp Current

–5 < V_IN≤ –1

–25 + (V_IN+1)

/0.015

–60

–10

mA

Slew (r) Output Rise Slew Rate

Slew (f) Output Fall Slew Rate

0.4V to 2.4V load

2.4V to 0.4V load

1

5

1.8

2.8

4.3

V/ns

Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.

2 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

O u t p u t D r i v e C h a r a c t e r i s t i c s f o r 3 . 3 V P C I S i g n a l i n g

D C S p e c if i c a t io n ( 3 . 3 V P C I S ig n a li n g ) ¹

PCI

MX

Symbol Parameter

Condition

Min.

Max

Min.

Max

Units

V_CCI

V_IH

V_IL

Supply Voltage for I/Os

3.0

0.5

3.6

V_CC+ 0.5

0.8

3.0

0.5

3.6

V_CCI+ 0.3

0.8

V

Input High Voltage

Input Low Voltage

–0.5

–0.3

V

I_IH

Input High Leakage Current

Input Leakage Current

Output High Voltage

Output Low Voltage

V_IN= 2.7V

70

10

µA

V

I_IL

–70

–10

V_OH

V_OL

I_OUT= –2 mA

0.9

5

3.3

I_OUT= 3 mA,

6 mA

0.1

0.1 V_CCI

V

C_IN

Input Pin Capacitance

CLK Pin Capacitance

Pin Inductance

10

12

20

10

pF

nH

C_CLK

L_PIN

Notes:

< 8 nH³

1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.

2. Maximum rating for V –0.5V to 7.0V.

CCI

3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

A C S p e c if i c a t io n s f o r ( 3 . 3 V P C I S ig n a li n g ) *

PCI

MX

Symbol Parameter

Condition

Min.

Max

Min.

Max

Units

I_CL

Low Clamp Current

–5 < V_IN≤ –1

–25 + (V_IN+1)

/0.015

–60

–10

mA

Slew (r) Output Rise Slew Rate

Slew (f) Output Fall Slew Rate

0.2V to 0.6V load

0.6V to 0.2V load

1

4

1.8

2.8

4.0

V/ns

Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.

v6 .0

2 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

–0.05

–0.10

–0.15

–0.20

PCI I_OLMaximum

MX PCI I_OL

PCI I_OLMinimum

0

1

2

3

4

5

6

PCI I_OHMaximum

MX PCI I_OH

PCI I_OHMinimum

Voltage Out (V)

Figure 15 • Typical Output Drive Characteristics (based upon measured data)

2 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

J u n c t i o n T e m p e r a t u r e ( T _J)

θ

= Junction to ambient of package. θ numbers are

ja

The temperature variable in the Designer software refers to

the junction temperature, not the ambient temperature.

This is an important distinction because the heat generated

from dynamic power consumption is usually hotter than the

ambient temperature. Equation 1, shown below, can be

used to calculate junction temperature.

located in the Package Thermal Characteristics table

below.

P a c k a g e T h e r m a l C h a r a c t e r i s t i c s

The device junction-to-case thermal characteristic is θ_jc,

and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different

air flow rates.

Junction Temperature = ∆T + T

(1)

a

Where:

T = Ambient Temperature

The maximum junction temperature is 150°C.

a

Maximum power dissipation for commercial- and

∆T = Temperature gradient between junction (silicon) and

ambient

industrial-grade devices is a function of θ .

ja

A sample calculation of the absolute maximum power

dissipation allowed for a TQFP 176-pin package at

commercial temperature and still air is as follows:

∆T = θ * P

(2)

ja

P = Power

Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C

--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------

= 2.86W

Maximum Power Allowed =

=

θ_ja(°C/W)

28°C/W

The maximum power dissipation for military-grade devices is a function of θ . A sample calculation of the absolute maximum

jc

power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows:

Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C

--------------------------------------------------------------------------------------------------------------------------------- -------------------------------------

= 3.97W

Maximum Power Allowed =

=

θ_jc(°C/W)

6.3°C/W

θ_ja

1.0 m/s

2.5 m/s

Still Air

Plastic Packages

Pin Count

θ_jc

200 ft/min 500 ft/min

Units

Plastic Quad Flat Pack

100

160

208

240

44

12.0

10.0

8.0

27.8

26.2

26.1

25.6

20.0

25.0

22.5

24.7

38.2

35.3

18.3

23.4

22.8

22.5

22.3

24.5

21.0

18.9

19.9

31.9

29.4

14.9

21.2

21.1

20.8

22.0

19.4

17.6

18.0

29.4

27.1

13.9

°C/W

Plastic Quad Flat Pack

8.5

Plastic Leaded Chip Carrier

Thin Plastic Quad Flat Pack

Very Thin Plastic Quad Flat Pack

Plastic Ball Grid Array

16.0

13.0

12.0

11.0

12.0

10.0

3.0

68

84

176

80

100

272

θ_ja

1.0 m/s

2.5 m/s

Still Air

Ceramic Packages

Pin Count

θ_jc

200 ft/min 500 ft/min

Units

Ceramic Quad Flat Pack

208

256

2.0

22.0

20.0

19.8

16.5

18.0

15.0

°C/W

v6 .0

2 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 0 M X T i m i n g M o d e l *

Input Delay

Internal Delays

Predicted

Routing

Delays

Output Delay

I/O Module

t_INYL= 0.62 ns

t_IRD2= 2.59 ns

Logic Module

t_DLH= 3.32 ns

t

_IRD1= 2.09 ns

t_IRD4= 3.64 ns

t_IRD8= 5.73 ns

t_RD1= 1.28 ns

_RD2= 1.80 ns

t_RD4= 2.33 ns

t_RD8= 4.93 ns

t_PD= 1.24 ns

t_CO= 1.24 ns

t_ENHZ= 7.92 ns

t

Array

Clock

t_CKH= 4.55 ns

FO = 128

F_MAX= 180 MHz

Note:

* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.

2 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t_IRD1= 2.0 ns†

t_INYL= 0.8 ns

Combinatorial

Logic Module

t_DLH= 2.5 ns

t_RD1= 0.7 ns

t_RD2= 1.9 ns

t_RD4= 1.4 ns

t_RD8= 2.3 ns

D

Q

t

_PD= 1.2 ns

I/O Module

t_DLH= 2.5 ns

G

Sequential

Logic Module

t_INH= 0.0 ns

_INSU= 0.3 ns

t

_INGL= 1.3 ns

Combin-

atorial

Logic

included

in t_SUD

D

G

Q

t_RD1= 0.70 ns

t_ENHZ= 4.9 ns

t_OUTH= 0.00 ns

t_OUTSU= 0.3 ns

t_GLH= 2.6 ns

t_CO= 1.3 ns

t

_SUD= 0.3 ns

t_HD= 0.00 ns

Array

Clocks

t_CKH= 2.70 ns

FO = 32

F_MAX= 296 MHz

t_LCO= 5.2 ns (light loads, pad-to-pad)

Notes:

*Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.

† Input module predicted routing delay.

v6 .0

2 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l ( L o g i c F u n c t i o n s u s i n g Q u a d r a n t C l o c k s ) *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t_INPY= 1.0 ns

t

_IRD1= 2.0 ns

Combinatorial

Module

t_DLH= 2.6 ns

t_RD1= 0.9 ns

t_RD2= 1.3 ns

t_RD4= 2.0 ns

D

G

Q

t

_PD= 1.3 ns

Decode

Module

t_INH= 0.0 ns

_INSU= 0.5 ns

t_RDD= 0.3 ns

t

_INGO= 1.4 ns

t_PDD= 1.6 ns

I/O Module

t_DLH= 2.6 ns

Sequential

Logic Module

t_RD1= 0.9 ns

Combin-

atorial

Logic

included

in t_SUD

D

G

Q

t_ENHZ= 5.3 ns

t_LH= 0.00 ns

t

_LSU= 0.5 ns

t

_CO= 1.3 ns

t_SUD= 0.3 ns

_HD= 0.0 ns

t_GHL= 2.9 ns

t

Quadrant

Clocks

t

_CKH= 3.03 ns**

F_MAX= 180 MHz

Notes:

* Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions.

** Load-dependent

2 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l ( S R A M F u n c t i o n s ) *

Input Delays

I/O Module

t_INPY= 1.0 ns

t

_IRD1= 2.0 ns

D

G

Q

Predicted

Routing

Delays

I/O Module

t_INSU= 0.5 ns

t_INH= 0.0 ns

t_INGO= 1.4 ns

t_DLH= 2.6 ns

RD [7:0]

RDAD [5:0]

REN

WD [7:0]

t_RD1= 0.9 ns

WRAD [5:0]

BLKEN

D

G

Q

WEN

WCLK

RCLK

t_ADSU= 1.6 ns

t_GHL= 2.9 ns

t_LSU= 0.5 ns

t_LH= 0.0 ns

t

_ADH= 0.0 ns

t

_ADH= 0.0 ns

t_WENSU= 2.7 ns

_BENS= 2.8 ns

t_RENSU= 0.6 ns

t_RCO= 3.4 ns

Array

Clocks

t

F

_MAX= 167 MHz

Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.

P a r a m e t e r M e a s u r e m e n t

O u t p u t B u f f e r D e l a y s

E

D

PAD To AC test loads (shown below)

TRIBUFF

In

50%

V_OH

E

50%

E

50%

V_CCI

50%

V_OH

50%

1.5V

V_OL

90%

PAD

V_OL

PAD

GND

1.5V

10%

1.5V

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_ENHZ

v6 .0

2 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A C Te s t L o a d s

Load 1

Load 2

(Used to measure propagation delay)

(Used to measure rising/falling edges)

V_CCI

GND

To the output under test

35 pF

R to V_CCIfor t_PLZ/t_PZL

R to GND for t_{PHZ PZH}

/t

R = 1 kΩ

To the output under test

35 pF

I n p u t B u ff e r D e la y s

M o d u le D e l a y s

S

A

B

Y

PAD

INBUF

S, A or B

Y

50% 50%

3V

50%

PAD

0V

50%

1.5V

V_CCI

1.5V

t_PLH

t_PHL

Y

GND

50%

t_PHL

50%

t_PLH

t_INYH

t_INYL

3 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

S e q u e n t i a l M o d u l e T i m i n g C h a r a c t e r i s t i c s

F l ip -F l o p s a n d L a t c h e s

D

E

CLK

Y

PRE

CLR

(Positive Edge-Triggered)

t_HD

D*

t_A

t_WCLKA

t_SUD

G, CLK

t_SUENA

t_WCLKI

t_HENA

E

t_CO

Q

t_RS

PRE, CLR

t_WASYN

Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.

v6 .0

3 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

I n p u t B u f f e r L a t c h e s

PAD

DATA

IBDL

G

PAD

CLK

CLKBUF

DATA

G

t_INH

t_INSU

t_HEXT

CLK

t_SUEXT

O u t p u t B u f f e r L a t c h e s

D

G

PAD

OBDLHS

D

G

t_OUTSU

t_OUTH

3 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D e c o d e M o d u l e T i m i n g

A

B

C

D

E

F

Y

H

G

A–G, H

50%

Y

t_PHL

t_PLH

S R A M T i m i n g C h a r a c t e r i s t i c s

Read Port

Write Port

WRAD [5:0]

BLKEN

WEN

RDAD [5:0]

LEW

RAM Array

32x8 or 64x4

(256 Bits)

REN

WCLK

RCLK

WD [7:0]

RD [7:0]

v6 .0

3 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D u a l -P o r t S R A M T i m i n g W a v e f o r m s

4 2 M X S R A M Wr it e O p e r a t io n

t_RCKHL

WCLK

t_ADSU

t_ADH

WD[7:0]

WRAD[5:0]

Valid

t_WENSU

t_WENH

WEN

t_BENSU

Valid

t_BENH

BLKEN

Note: Identical timing for falling edge clock.

4 2 M X S R A M S y n c h r o n o u s R e a d O p e r a t i o n

t_CKHL

t_RCKHL

RCLK

t_RENSU

t_RENH

REN

t_ADSU

Valid

t_ADH

RDAD[5:0]

t_RCO

t_DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling edge clock.

3 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X S R A M A s y n c h r o n o u s R e a d O p e r a t i o n —Ty p e

1

(Read Address Controlled)

t_RDADV

RDAD[5:0]

RD[7:0]

ADDR1

t_DOH

ADDR2

t_RPD

Data 1

Data 2

4 2 M X S R A M A s y n c h r o n o u s R e a d O p e r a t i o n —Ty p e

2

(Write Address Controlled)

WEN

t_WENSU

t_WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t_ADH

t_ADSU

WCLK

t_RPD

t_DOH

Old Data

New Data

RD[7:0]

v6 .0

3 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P r e d i c t a b l e P e r f o r m a n c e :

T i g h t D e l a y D i s t r i b u t i o n s

T i m i n g C h a r a c t e r i s t i c s

Device timing characteristics fall into three categories:

family-dependent, device-dependent, and design-dependent.

The input and output buffer characteristics are common to

all MX devices. Internal routing delays are device-dependent;

actual delays are not determined until after place-and-route

of the user’s design is complete. Delay values may then be

determined by using the Designer software utility or by

performing simulation with post-layout delays.

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being driven.

Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of

inputs increases.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number of

loads) driven by a module. Higher fanout usually requires

some paths to have longer routing tracks.

C r i t i c a l N e t s a n d Ty p ic a l N e t s

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most timing

critical paths. Critical nets are determined by net property

assignment in Actel's Designer software prior to placement

and routing. Up to 6% of the nets in a design may be

designated as critical.

The MX FPGAs deliver a tight fanout delay distribution,

which is achieved in two ways: by decreasing the delay of the

interconnect elements and by decreasing the number of

interconnect elements per path.

Actel’s patented antifuse offers

a

very low

resistive/capacitive interconnect. The antifuses, fabricated

in 0.45 µm lithography, offer nominal levels of 100Ω

resistance and 7.0fF capacitance per antifuse.

L o n g T r a c k s

Some nets in the design use long tracks, which are special

routing resources that span multiple rows, columns, or

modules. Long tracks employ three and sometimes four

antifuse connections, which increase capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, up to 6 percent of

nets in a fully utilized device require long tracks. Long

tracks add approximately a 3 ns to a 6 ns delay, which is

represented statistically in higher fanout (FO=8) routing

delays in the data sheet specifications section, beginning on

page 42.

MX fanout distribution is also tight due to the low number of

antifuses required for each interconnect path. The

proprietary architecture limits the number of antifuses per

path to a maximum of four, with 90 percent of interconnects

using only two antifuses.

T im i n g D e r a t in g

MX devices are manufactured with a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum timing

parameters reflect maximum operating voltage, minimum

operating temperature and best-case processing. Maximum

timing parameters reflect minimum operating voltage,

maximum operating temperature and worst-case

processing.

3 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C A}= 5 . 0 V)

Temperature

42MX Voltage

–55°C

0.93

0.88

0.85

0.84

0.83

–40°C

0.95

0.90

0.87

0.86

0.85

0°C

1.05

1.00

0.96

0.95

0.94

25°C

1.09

1.03

1.00

0.97

0.96

70°C

1.25

1.18

1.15

1.12

1.10

85°C

1.29

1.22

1.18

1.14

1.13

125°C

1.41

1.34

1.29

1.28

1.26

4.50

4.75

5.00

5.25

5.50

42MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 25°C, V_CCA= 5.0V)

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

–55˚C

–40˚C

0˚C

25˚C

70˚C

85˚C

125˚C

4.50

4.75

5.00

5.25

5.50

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

v6 .0

3 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 0 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C}= 5 . 0 V)

Temperature

40MX Voltage

–55°C

0.89

0.84

0.82

0.80

0.79

–40°C

0.93

0.88

0.85

0.82

0°C

1.02

0.97

0.94

0.91

0.90

25°C

1.09

1.03

1.00

0.97

0.96

70°C

1.25

1.18

1.15

1.12

1.10

85°C

1.31

1.24

1.20

1.16

1.15

125°C

1.45

1.37

1.33

1.29

1.28

4.50

4.75

5.00

5.25

5.50

40MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 25°C, V_CC= 5.0V)

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

–55˚C

–40˚C

0˚C

25˚C

70˚C

85˚C

125˚C

4.50

4.75

5.00

5.25

5.50

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

3 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C A}= 3 . 3 V)

Temperature

42MX Voltage

–55°C

–40°C

0°C

25°C

70°C

85°C

125°C

3.00

3.30

3.60

0.97

0.84

0.81

1.00

0.87

0.84

1.10

0.96

0.92

1.15

1.00

0.96

1.32

1.15

1.10

1.36

1.18

1.13

1.45

1.26

1.21

42MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 25°C, V_CCA= 3.3V)

1.60

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

55˚C

40˚C

0˚C

25˚C

70˚C

85˚C

125˚C

3.00

3.30

3.60

Volta ge

(V)

Note: This derating factor applies to all routing and propagation delays.

v6 .0

3 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 0 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C}= 3 . 3 V)

Temperature

40MX Voltage

–55°C

–40°C

0°C

25°C

70°C

85°C

125°C

3.00

3.30

3.60

1.08

0.86

0.83

1.12

0.89

0.85

1.21

0.96

0.92

1.26

1.00

0.96

1.50

1.19

1.14

1.64

1.30

1.25

2.00

1.59

1.53

40MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 25°C, V_CC= 3.3V)

2.20

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

55˚C

-55˚C

40˚C

-40C

0˚C

˚0˚C

25˚C

70˚C

85˚C

125˚C

125˚

3.00

3.30

3.60

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

4 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P C I S y s t e m T i m i n g S p e c i f i c a t i o n

P C I M o d e l s

Table 6 and Table 7 list the critical PCI timing parameters

and the corresponding timing parameters for the MX

PCI-compliant devices.

Actel provides synthesizable VHDL and Verilog-HDL models

for a PCI Target interface, a PCI Target and Target+DMA

Master interface. Contact your Actel sales representative

for more details.

Table 6 • Clock Specification for 33 MHz PCI

PCI

A42MX24

A42MX36

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

t_CYC

t_HIGH

t_LOW

CLK Cycle Time

CLK High Time

CLK Low Time

30

11

–

4.0

1.9

–

4.0

1.9

–

ns

Table 7 • Timing Parameters for 33 MHz PCI

PCI

A42MX24

A42MX36

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

t_VAL

CLK to Signal Valid—Bused Signals

CLK to Signal Valid—Point-to-Point

Float to Active

2

2 ²

2

11

12

–

2.0

–

9.0

4.0

8.3¹

–

2.0

–

9.0

4.0

8.3¹

–

ns

t_VAL(PTP)

t_ON

t_OFF

Active to Float

–

28

–

t_SU

Input Set-Up Time to CLK—Bused Signals

Input Set-Up Time to CLK—Point-to-Point

Input Hold to CLK

7

1.5

0

1.5

0

t_SU(PTP)

t_H

10, 12 ²

–

0

–

Notes:

1. T_OFFis system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.

2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals. GNT# has a

setup of 10; REW# has a setup of 12.

v6 .0

4 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.2

2.7

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.8

2.3

2.9

4.9

1.5

2.1

2.7

3.3

5.7

1.7

2.4

3.0

3.7

6.5

2.0

2.8

3.6

4.4

7.6

2.8

3.9

ns

5.0

6.1

10.6

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

3.1

0.0

3.1

0.0

3.5

0.0

3.5

0.0

4.0

0.0

4.0

0.0

4.7

0.0

4.7

0.0

6.6

0.0

6.6

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

3.3

4.8

3.8

5.6

4.3

6.3

5.0

7.5

7.0

ns

t_A

Flip-Flop Clock Input Period

10.4

f_MAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

181

168

154

134

80

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this

macro.

4 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

ns

6.7

7.8

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to HIGH

FO = 16

FO = 128

4.6

5.3

6.0

7.0

9.8

ns

Input High to LOW

FO = 16

FO = 128

4.8

5.6

6.3

7.4

10.4

Minimum Pulse Width HIGH FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Minimum Pulse Width LOW FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.01

3.4

3.6

4.8

5.1

ns

Maximum Skew

FO = 16

FO = 128

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

4.7

4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.0

10.4

ns

f_MAX

Note:

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v6 .0

4 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.3

4.0

3.8

4.6

4.3

5.2

5.1

6.1

7.2

8.6

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.7

4.3

4.9

5.8

8.0

4.7

5.4

6.1

7.2

10.1

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.02

0.03

0.02

0.03

0.04

0.04 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.9

3.4

4.5

3.9

5.1

4.4

6.05

5.2

8.5

7.3

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.4

3.9

4.4

5.2

7.3

4.9

5.6

6.4

7.5

10.5

17.0

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.03

0.02

0.04

0.02

0.04

0.03

0.05

0.03

0.07 ns/pF

0.04 ns/pF

1. Delays based on 35 pF loading.

4 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.7

3.7

1.7

2.0

4.3

2.0

2.3

4.9

2.3

2.7

5.7

2.7

3.7

8.0

3.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.7

3.4

4.2

7.1

2.2

3.1

3.9

4.8

8.2

2.5

3.5

4.4

5.4

9.2

3.0

4.1

4.2

5.7

ns

5.2

7.3

6.3

8.9

10.9

15.2

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

4.3

0.0

4.3

0.0

4.9

0.0

4.9

0.0

5.6

0.0

5.6

0.0

6.6

0.0

6.6

0.0

9.2

0.0

9.2

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

5.3

6.0

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.6

6.8

5.3

7.8

6.0

8.9

7.0

9.8

ns

t_A

Flip-Flop Clock Input Period

10.4

14.6

f_MAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

109

101

92

80

48

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this

macro.

v6 .0

4 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1

1.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.4

4.2

3.8

4.8

4.5

5.6

6.3

7.8

ns

5.0

5.7

6.7

9.4

5.9

6.7

7.8

11.0

17.3

9.26

10.5

12.6

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

6.4

7.4

8.3

9.8

13.7

ns

Input HIGH to LOW

FO = 16

FO = 128

6.7

7.8

8.8

10.4

14.5

Minimum Pulse Width

HIGH

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Minimum Pulse Width

LOW

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Maximum Skew

FO = 16

FO = 128

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

6.5

6.8

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

f_MAX

Note:

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

4 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

4.7

5.6

5.4

6.4

6.1

7.3

7.2

8.6

10.0

12.0

11.3

14.1

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

5.2

6.0

6.8

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

0.06

11.1

8.2

12.8

9.5

14.5

10.7

0.04

0.05

0.03

0.04

0.03

0.04

0.06 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

5.5

4.8

6.4

5.5

7.2

6.2

8.5

7.3

11.9

10.2

14.7

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.06

0.04

0.05

0.03

0.05

0.03

0.10 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

v6 .0

4 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.2

2.3

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.2

1.9

2.4

2.9

5.0

1.6

2.2

2.8

3.4

5.8

1.8

2.5

3.2

3.9

6.6

2.1

2.9

3.7

4.5

7.8

3.0

4.1

ns

5.2

6.3

10.9

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

3.1

0.0

3.1

0.0

3.5

0.0

3.5

0.0

4.0

0.0

4.0

0.0

4.7

0.0

4.7

0.0

6.6

0.0

6.6

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

3.3

4.8

3.8

5.6

4.3

6.3

5.0

7.5

7.0

ns

t_A

Flip-Flop Clock Input Period

10.4

f_MAX

Flip-Flop (Latch) Clock Frequency

(FO = 128)

181

167

154

134

80

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold time for

this macro.

4 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

ns

6.7

7.8

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

4.6

5.3

6.0

7.1

9.9

ns

Input HIGH to LOW

FO = 16

FO = 128

4.8

5.6

6.3

7.5

10.4

Minimum Pulse Width HIGH FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Minimum Pulse Width LOW FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Maximum Skew

FO = 16

FO = 128

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

4.7

4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.1

10.4

ns

f_MAX

Note:

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v6 .0

4 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.3

4.0

3.8

4.6

4.3

5.2

5.1

6.1

7.2

8.6

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.7

4.3

4.9

5.8

8.1

4.7

5.4

6.1

7.2

10.1

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.02

0.03

0.04

0.04 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.9

3.4

4.5

3.9

5.1

4.4

6.1

5.2

8.5

7.3

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.4

3.9

4.4

5.2

7.3

4.9

5.6

6.4

7.5

10.5

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.0

6.8

0.03

0.02

0.04

0.02

0.04

0.03

0.05

0.03

0.07 ns/pF

0.04 ns/pF

1. Delays based on 35 pF loading.

5 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.7

3.7

1.7

2.0

4.3

2.0

2.3

4.9

2.3

2.7

5.7

2.7

3.7

8.0

3.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.9

2.7

3.4

4.1

7.1

2.2

3.1

3.9

4.8

8.1

2.5

3.5

4.4

5.4

9.2

3.0

4.1

4.2

5.7

ns

5.2

7.3

6.3

8.9

10.9

15.2

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

4.3

0.0

4.3

0.0

5.0

0.0

5.0

0.0

5.6

0.0

5.6

0.0

6.6

0.0

6.6

0.0

9.2

0.0

9.2

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

5.3

5.6

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.6

6.8

5.3

7.8

5.6

8.9

7.0

9.8

ns

t_A

Flip-Flop Clock Input Period

10.4

14.6

f_MAX

Flip-Flop (Latch) Clock Frequency

(FO = 128)

109

101

92

80

48

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold time for this

macro.

v6 .0

5 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1

1.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.3

4.2

5.0

5.9

9.3

3.8

4.8

4.5

5.6

6.3

7.8

ns

5.7

6.7

9.4

6.7

7.8

11.0

17.2

10.5

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

6.4

7.4

8.4

9.9

13.8

ns

Input HIGH to LOW

FO = 16

FO = 128

6.8

7.8

8.9

10.4

14.6

Minimum Pulse Width

HIGH

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Minimum Pulse Width

LOW

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Maximum Skew

FO = 16

FO = 128

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

6.5

6.8

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

f_MAX

Note:

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

5 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

4.7

5.6

5.4

6.4

6.1

7.3

7.2

8.6

10.0

12.0

11.3

14.1

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

5.2

6.0

6.9

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

0.06

11.1

8.2

12.8

9.5

14.5

10.7

0.04

0.05

0.03

0.04

0.03

0.04

0.06 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

5.5

4.8

6.4

5.5

7.2

6.2

8.5

7.3

11.9

10.2

14.7

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.06

0.04

0.05

0.03

0.05

0.03

0.10 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

v6 .0

5 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.2

1.3

1.2

1.3

1.4

1.6

1.5

1.6

1.8

1.9

1.8

2.1

2.5

2.7

2.6

2.9

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.7

0.9

1.2

1.4

2.3

0.8

1.0

1.3

1.5

2.6

0.9

1.2

1.5

1.7

2.9

1.0

1.4

1.7

2.0

3.4

1.4

1.9

2.4

2.9

4.8

ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.3

0.0

0.4

0.0

0.4

0.0

0.5

0.0

0.4

0.0

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.8

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.4

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

4.5

3.5

0.0

0.3

0.0

0.3

4.9

3.8

0.0

0.3

0.0

0.3

5.6

4.3

0.0

0.4

0.0

0.4

6.6

5.1

0.0

0.4

0.0

0.4

9.2

7.1

0.0

0.6

0.0

0.6

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock

Frequency

268

244

224

195

117

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

5 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.0

0.8

1.3

1.2

0.9

1.4

1.3

1.0

1.6

1.2

1.9

2.2

1.7

2.7

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.3

2.5

2.8

3.7

2.2

2.5

2.8

3.1

4.1

2.5

2.9

3.2

3.5

4.7

3.0

3.4

3.7

4.1

5.5

4.2

4.7

5.2

5.7

7.7

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 256

2.4

2.7

3.0

3.4

3.6

4.0

5.0

5.5

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 256

3.5

3.9

4.3

4.4

4.9

5.2

5.7

7.3

8.0

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 256

1.2

1.3

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Minimum Pulse Width

LOW

FO = 32

FO = 256

1.2

1.3

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Maximum Skew

FO = 32

FO = 256

0.3

0.4

0.5

0.6

ns

Input Latch External

Set-Up

FO = 32

FO = 256

0.0

ns

Input Latch External Hold FO = 32

FO = 256

2.3

2.2

2.6

2.4

3.0

3.3

3.5

3.9

4.9

5.5

ns

Minimum Period

FO = 32

FO = 256

3.4

3.7

4.1

4.0

4.5

4.7

5.2

7.8

8.6

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 256

296

268

269

244

247

224

215

195

129

117

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v6 .0

5 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

2.9

2.6

2.9

4.9

5.3

2.6

2.7

3.2

2.9

3.2

5.4

5.9

2.9

3.1

3.6

3.3

3.7

6.2

6.7

3.3

3.6

4.3

3.9

4.3

7.3

7.9

3.8

5.1

6.0

ns

5.5

6.1

10.2

11.1

5.3

G-to-Pad LOW

5.3

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.2

5.8

6.6

7.7

10.8

15.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

7.4

8.2

9.3

10.9

0.04

0.05

d_TLH

d_THL

Capacity Loading, LOW to HIGH

0.03

0.04

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

Capacity Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.4

2.9

2.7

2.9

4.9

5.3

4.2

2.7

3.2

2.9

3.2

5.4

5.9

4.6

3.1

3.6

3.3

3.7

6.2

6.7

5.2

3.6

4.3

3.9

4.3

7.3

7.9

6.1

5.1

6.0

ns

5.5

6.1

10.2

11.1

8.6

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.2

5.8

6.6

7.7

10.8

15.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

7.4

8.2

9.3

10.9

0.04

0.05

d_TLH

d_THL

Note:

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

1. Delays based on 35 pF loading.

5 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.6

1.8

1.7

2.0

1.8

2.0

1.9

2.2

2.1

2.3

2.1

2.5

2.7

2.5

2.9

3.5

3.8

3.5

4.1

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.0

1.3

1.6

1.9

3.2

1.1

1.4

1.8

2.1

3.6

1.2

1.6

2.0

2.4

4.1

1.4

1.9

2.4

2.9

4.8

2.0

2.7

3.3

4.0

6.7

ns

Logic Module Sequential Timing ^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.5

0.0

0.6

0.0

0.5

0.0

0.6

0.0

0.6

0.0

0.7

0.0

0.7

0.0

0.8

0.0

0.9

0.0

1.2

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.7

5.3

6.0

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

6.2

5.0

0.0

0.3

0.0

0.3

6.9

5.6

0.0

0.3

0.0

0.3

7.8

6.2

0.0

0.3

0.0

0.3

9.2

7.1

0.0

0.4

0.0

0.4

12.9

9.9

0.0

0.6

0.0

0.6

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock

Frequency

161

146

135

117

70

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v6 .0

5 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.2

1.8

1.6

1.3

2.0

1.8

1.4

2.3

2.17

1.7

3.0

2.4

3.7

ns

2.7

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.8

3.2

3.5

3.9

5.2

3.2

3.5

3.9

4.3

5.8

3.6

4.0

4.4

4.9

6.6

4.2

4.7

5.2

5.7

7.7

5.9

6.6

ns

7.3

8.0

10.8

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 256

4.1

4.5

5.0

5.1

5.6

6.0

6.7

8.4

9.3

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 256

5.0

5.4

5.5

6.0

6.2

6.8

7.3

8.0

10.2

11.2

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 256

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

Minimum Pulse Width

LOW

FO = 32

FO = 256

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

Maximum Skew

FO = 32

FO = 256

0.4

0.5

0.6

0.9

ns

Input Latch External

Set-Up

FO = 32

FO = 256

0.0

ns

Input Latch External Hold FO = 32

FO = 256

3.3

3.7

4.1

4.2

4.6

4.9

5.5

6.9

7.6

ns

Minimum Period

FO = 32

FO = 256

5.6

6.1

6.2

6.8

6.7

7.4

7.8

8.5

12.9

14.2

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 256

177

161

146

148

135

129

117

77

70

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

5 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.0

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

4.3

5.1

4.6

5.1

8.6

9.4

7.3

5.1

6.1

7.1

8.3

ns

5.5

7.6

6.1

8.5

10.2

11.1

8.6

14.2

15.5

12.0

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.7

9.7

10.9

12.9

18.0

25.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

12.2

0.00

0.09

13.5

0.00

0.10

15.4

0.00

0.10

18.1

0.10

d_TLH

d_THL

Capacity Loading, LOW to HIGH

0.01 ns/pF

0.10 ns/pF

Capacity Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.1

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

5.5

4.2

4.6

5.1

8.6

9.4

7.3

6.4

5.0

9.0

7.0

ns

5.5

7.6

6.1

8.5

10.2

11.1

8.6

14.2

15.5

12.0

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.7

9.7

10.9

12.9

18.0

25.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

12.2

0.04

0.05

13.5

0.04

0.05

15.4

0.05

0.06

18.1

0.06

0.07

d_TLH

d_THL

Note:

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

1. Delays based on 35 pF loading.

v6 .0

5 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.4

1.6

1.5

1.6

1.5

1.7

1.8

1.7

2.0

2.1

2.0

2.3

2.8

3.0

2.8

3.3

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.8

1.0

1.3

1.6

2.6

0.9

1.2

1.4

1.7

2.9

1.0

1.3

1.6

2.0

3.2

1.2

1.5

1.9

2.3

3.8

1.6

2.1

2.7

3.2

5.3

ns

Logic Module Sequential Timing^3,4

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.3

0.0

0.7

0.0

0.4

0.0

0.8

0.0

0.4

0.0

0.9

0.0

0.5

0.0

1.0

0.0

0.7

0.0

1.4

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.4

3.8

4.3

5.0

7.1

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

4.5

6.8

0.0

0.5

0.0

0.5

5.0

7.6

0.0

0.5

0.0

0.5

5.6

8.6

0.0

0.6

0.0

0.6

6.6

10.1

0.0

9.2

14.1

0.0

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

0.7

1.0

0.0

0.7

1.0

Flip-Flop (Latch) Clock

Frequency

215

195

179

156

94

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

6 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.1

0.8

1.4

1.2

0.9

1.6

1.3

1.0

1.8

1.6

1.2

2.1

2.2

1.7

2.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.8

2.1

2.3

2.6

3.6

2.0

2.3

2.6

3.0

4.0

2.3

2.6

3.0

3.3

4.6

2.7

3.1

3.5

3.9

5.4

4.0

4.3

4.9

5.4

7.5

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 384

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

6.0

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 384

3.8

4.5

4.2

5.0

4.8

5.6

6.6

7.8

9.2

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 384 3.7

3.2

3.5

4.1

4.0

4.6

4.7

5.4

6.6

7.6

ns

Minimum Pulse Width LOW FO = 32

3.2

3.5

4.1

4.0

4.6

4.7

5.4

6.6

7.6

ns

FO = 384 3.7

Maximum Skew

FO = 32

FO = 384

0.3

0.4

0.5

0.7

ns

Input Latch External Set-Up FO = 32

0.0

ns

FO = 384 0.0

Input Latch External Hold FO = 32

2.8

3.1

3.5

5.5

4.0

4.1

4.7

5.7

6.6

ns

FO = 384 3.2

Minimum Period

FO = 32

FO = 384 4.6

4.2

4.67

5.1

5.6

5.8

6.4

9.7

10.7

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 384

237

215

195

198

179

172

156

103

94

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v6 .0

6 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

3.0

2.7

3.0

5.4

5.0

2.9

2.8

3.3

3.0

3.3

6.0

5.6

3.2

3.7

3.4

3.8

6.8

6.3

3.6

3.7

4.4

4.0

4.4

8.0

7.4

4.3

5.2

6.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

6.2

11.2

10.4

6.0

G-to-Pad LOW

6.0

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.7

6.3

7.1

8.4

11.9

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

0.03

0.04

11.9

0.04

0.05

16.7

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.2

2.5

2.7

3.0

5.4

5.0

5.1

3.6

2.7

3.0

3.3

6.0

5.6

4.0

3.1

3.4

3.8

6.8

6.3

6.4

4.7

3.6

4.0

4.4

8.0

7.4

7.5

6.6

5.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

6.2

11.2

10.4

10.5

G-to-Pad LOW

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.7

6.3

7.1

8.4

11.9

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

0.03

0.04

11.9

0.04

0.05

16.7

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

1. Delays based on 35 pF loading.

6 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.9

2.0

1.9

2.2

2.1

2.2

2.1

2.4

2.5

2.4

2.8

3.0

2.8

3.3

4.0

4.2

4.0

4.6

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.1

1.5

1.8

2.2

3.6

1.2

1.6

2.0

2.4

4.0

1.4

1.8

2.3

2.7

4.5

1.6

2.1

2.7

3.2

5.3

2.3

3.0

3.8

4.5

7.5

ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.5

0.0

1.0

0.0

0.5

0.0

1.1

0.0

0.6

0.0

1.2

0.0

0.7

0.0

1.4

0.0

0.9

0.0

2.0

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.8

5.3

6.0

7.1

9.9

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

6.2

9.5

0.0

0.7

0.0

0.7

6.9

10.6

0.0

0.8

0.0

0.8

7.9

12.0

0.0

9.2

14.1

0.0

12.9

19.8

0.0

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Notes:

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock Frequency

0.9

1.01

0.0

1.4

ns

0.0

ns

0.89

1.01

1.4

ns

129

117

108

94

56

MHz

1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v6 .0

6 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.1

2.0

1.6

1.3

2.2

1.9

1.4

2.5

2.2

1.7

2.9

3.1

2.4

4.1

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.6

2.9

3.3

3.6

5.1

2.9

3.2

3.6

4.0

5.6

3.2

3.7

4.1

4.6

6.4

3.8

4.3

4.9

5.4

7.5

5.3

6.1

ns

6.8

7.6

10.5

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 384

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.0

9.9

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 384

5.7

6.6

6.3

7.4

7.1

8.3

8.4

9.8

11.8

13.7

ns

Minimum Pulse Width

LOW

FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

Maximum Skew

FO = 32

FO = 384

0.5

2.2

0.5

2.4

0.6

2.7

0.7

3.2

1.0

4.5

ns

Input Latch External

Set-Up

FO = 32

FO = 384

0.0

ns

Input Latch External Hold FO = 32

FO = 384

3.9

4.5

4.3

4.9

5.6

5.7

6.6

8.0

9.2

ns

Minimum Period

FO = 32

FO = 384

7.0

7.7

7.8

8.6

8.4

9.3

9.7

10.7

16.2

17.8

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 384

142

129

117

119

108

103

94

62

56

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

6 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.5

4.1

3.8

4.2

7.6

7.0

4.8

3.9

4.6

4.2

4.6

8.4

7.8

5.3

4.4

5.2

4.8

5.3

9.5

8.8

6.0

5.2

6.1

7.3

8.6

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

7.8

6.2

8.7

11.2

10.4

7.2

15.7

14.5

10.0

G-to-Pad LOW

7.2

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

11.9

16.7

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.5

3.4

3.8

4.2

7.6

7.0

7.1

5.0

3.8

4.2

4.6

8.4

7.8

7.9

5.6

4.3

4.8

5.3

9.5

8.8

8.9

6.6

5.1

9.3

7.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

7.8

6.2

8.7

11.2

10.4

10.5

15.7

14.5

14.7

G-to-Pad LOW

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

11.9

16.7

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

1. Delays based on 35 pF loading.

v6 .0

6 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 2 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.2

1.4

1.3

1.6

1.5

1.8

2.1

2.5

3.0

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.8

1.0

1.3

1.5

2.4

0.9

1.2

1.4

1.7

2.7

1.0

1.3

1.6

1.9

3.0

1.2

1.5

1.9

2.2

3.6

1.7

2.1

2.6

3.1

5.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.3

1.2

1.4

1.3

1.6

1.5

1.9

1.8

2.7

2.5

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.4

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_RO

1.4

1.6

1.8

2.1

2.9

t_SUENA

t_HENA

t_WCLKA

0.4

0.0

0.5

0.0

0.5

0.0

0.6

0.0

0.8

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

4.4

3.7

4.8

4.2

5.3

4.9

6.5

6.9

9.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

6 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 5 . 0 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.3

1.1

1.4

1.3

1.6

1.5

1.9

2.1

2.6

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.8

2.1

2.3

2.5

3.4

2.0

2.3

2.5

2.8

3.8

2.3

2.6

2.9

3.2

4.3

2.7

3.1

3.4

3.7

5.1

3.8

4.3

4.8

5.2

7.1

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=486

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

5.9

ns

t_CKL

Input HIGH to LOW

FO=32

FO=486

3.7

4.3

4.1

4.7

4.6

5.4

6.3

7.6

8.8

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=486

2.2

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Minimum Pulse Width LOW FO=32

FO=486

2.2

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Maximum Skew

FO=32

0.5

0.6

0.7

0.8

1.1

ns

FO=486

Input Latch External Set-Up FO=32

FO=486

0.0

ns

Input Latch External Hold

FO=32

2.8

3.3

3.1

3.7

3.5

4.2

4.1

4.9

5.7

6.9

ns

FO=486

Minimum Period (1/f_MAX

)

FO=32

4.7

5.1

5.2

5.7

6.2

6.5

7.1

10.9

11.9

ns

FO=486

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=486

210

193

191

175

176

161

153

140

92

84

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v6 .0

6 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 5 . 0 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

2.4

2.8

2.5

2.8

5.2

4.8

2.9

2.7

3.2

2.8

3.1

5.7

5.3

3.2

3.1

3.6

3.2

3.5

6.5

6.0

3.6

4.2

3.8

4.2

7.6

7.1

4.3

5.1

5.9

5.3

5.9

10.7

9.9

6.0

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

t_LCO

5.6

6.1

6.9

8.1

11.4

22.0

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

32 I/O

t_ACO

10.6

0.04

0.03

11.8

0.04

0.03

13.4

0.04

0.03

15.7

0.05

0.04

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.1

2.4

2.5

2.8

5.2

4.8

4.9

3.5

2.6

2.8

3.1

5.7

5.3

5.4

3.9

3.0

3.2

3.5

6.5

6.0

6.2

4.6

3.5

3.8

4.2

7.6

7.1

7.2

6.4

4.9

ns

5.3

5.8

10.7

9.9

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Hold

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

t_LCO

5.5

6.1

6.9

8.1

11.3

22.0

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

32 I/O

t_ACO

10.6

0.04

0.03

11.8

0.04

0.03

13.4

0.04

0.03

15.7

0.05

0.04

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

6 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 2 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

2.0

1.1

1.8

2.2

2.1

2.5

3.0

3.4

4.2

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.7

2.0

1.1

1.5

1.8

1.3

1.6

2.0

2.3

3.7

1.4

1.8

2.2

2.6

4.2

1.7

2.1

2.6

3.1

5.0

2.3

3.0

3.7

4.3

7.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

2.1

3.4

2.0

1.9

2.3

2.1

2.7

2.5

3.7

3.4

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

t_RO

2.0

2.2

2.5

2.9

4.1

t_SUENA

t_HENA

t_WCLKA

0.6

0.0

0.6

0.0

0.7

0.0

0.8

0.0

1.2

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

6.1

5.2

6.8

5.8

7.7

6.9

9.0

9.6

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

12.6

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v6 .0

6 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX 2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 3 . 3 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

1.8

1.6

1.9

1.8

2.2

2.6

3.0

3.6

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

1.4

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

13.5

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.6

2.9

3.2

3.5

4.8

2.9

3.2

3.6

3.9

5.3

3.2

3.6

4.0

4.4

6.1

3.8

4.3

4.8

5.2

7.1

5.3

6.0

ns

6.6

7.3

10.0

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=486

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.1

10.0

ns

t_CKL

Input HIGH to LOW

FO=32

FO=486

5.1

6.0

5.7

6.6

6.4

7.5

7.6

8.8

10.6

12.4

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=486

3.0

3.3

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Minimum Pulse Width LOW FO=32

FO=486

3.0

3.3

3.4

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Maximum Skew

FO=32

0.8

1.0

1.1

1.6

ns

FO=486

Input Latch External Set-Up FO=32

FO=486

0.0

ns

Input Latch External Hold

FO=32

3.9

4.6

4.3

5.2

4.9

5.8

5.7

6.9

8.1

9.6

ns

FO=486

Minimum Period (1/f_MAX

)

FO=32

7.8

8.6

8.7

9.5

10.4

10.8

11.9

18.2

19.9

ns

FO=486

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=486

126

116

115

105

106

97

92

84

55

50

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX 2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 3 . 3 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3 Speed

Min. Max.

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

3.4

4.0

3.6

3.9

7.2

6.7

4.8

3.8

4.4

4.0

4.4

8.0

7.5

5.3

4.3

5.0

4.5

5.0

9.1

8.5

6.0

5.0

5.9

5.3

5.8

10.7

9.9

7.2

7.1

8.3

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

7.4

8.2

14.9

13.9

10.0

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.7

8.5

9.6

11.3

15.9

30.8

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

14.8

0.05

0.04

16.5

0.05

0.04

18.7

0.06

0.05

22.0

0.07

0.06

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.10 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.8

3.5

3.6

3.4

7.2

6.7

6.8

5.3

3.9

4.0

8.0

7.5

7.6

5.5

4.1

4.5

5.0

9.0

8.5

8.6

6.4

4.9

9.0

6.8

ns

5.3

7.4

5.8

8.2

10.7

9.9

14.9

13.9

14.2

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.7

8.5

9.6

11.3

15.9

30.8

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

14.8

0.05

0.04

16.5

0.05

0.04

18.7

0.06

0.05

22.0

0.07

0.06

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.10 ns/pF

0.08 ns/pF

1. Delays based on 35 pF loading.

v6 .0

7 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.3

1.6

1.5

1.8

1.7

2.0

2.4

2.7

3.3

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

0.9

1.3

1.6

2.0

3.3

0.3

1.0

1.4

1.8

2.2

3.7

0.4

1.2

1.6

2.0

2.5

4.2

0.4

1.4

1.9

2.4

2.9

4.9

0.5

2.0

2.7

3.4

4.1

6.9

0.7

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.3

1.4

1.6

1.9

2.7

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.3

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_RO

1.6

1.7

2.0

2.3

3.2

t_SUENA

t_HENA

t_WCLKA

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

4.4

3.7

4.8

4.2

5.5

4.9

6.4

6.9

9.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

7 2

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

Logic Module Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

t_RC

Read Cycle Time

6.8

3.4

7.5

3.8

8.5

4.3

10.0

5.0

14.0

7.0

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.4

3.8

4.3

5.0

7.0

1.6

0.0

0.6

3.4

2.7

0.0

2.8

0.0

1.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.3

7.0

5.6

0.0

5.7

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

8.1

9.0

10.2

12.0

16.8

ns

t_RDADV

t_ADSU

t_ADH

8.8

1.6

0.0

0.6

3.4

2.7

0.0

9.8

1.8

0.0

0.7

3.8

3.0

0.0

11.1

2.0

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.2

3.4

0.0

1.3

7.0

5.6

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.2

1.3

1.5

1.8

2.5

v6 .0

7 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.4

1.1

1.6

1.3

1.8

1.5

2.1

2.9

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.3

2.6

3.0

4.3

2.2

2.6

2.9

3.3

4.8

2.5

2.9

3.3

3.8

5.5

2.9

3.4

3.9

4.4

6.4

4.1

4.8

5.5

6.2

9.0

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

2.7

3.0

3.3

3.4

3.8

4.0

4.4

5.6

6.2

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

3.8

4.9

4.2

5.4

4.8

6.1

5.6

7.2

7.8

10.1

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

1.8

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

FO=635 2.0

Minimum Pulse Width LOW FO=32

1.8

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

FO=635 2.0

Maximum Skew

FO=32

0.8

0.9

1.0

1.4

ns

FO=635

Input Latch External Set-Up FO=32

0.0

ns

FO=635 0.0

Input Latch External Hold

FO=32 2.8

3.2

3.7

3.6

4.2

4.9

5.9

6.9

ns

FO=635 3.3

Minimum Period (1/f_MAX

)

FO=32 5.5

6.1

6.6

7.2

7.6

8.3

12.7

13.8

ns

FO=635 6.0

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=635

180

166

164

151

139

131

121

79

73

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 4

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

2.6

3.0

2.7

3.0

5.3

4.9

2.9

2.8

3.3

3.0

3.3

5.8

5.5

3.3

3.2

3.7

3.3

3.7

6.6

6.2

3.7

3.8

4.4

3.9

4.3

7.8

7.3

4.4

5.3

6.2

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.5

6.1

10.9

10.2

6.1

G-to-Pad LOW

6.1

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

5.7

6.3

7.1

8.4

11.8

16.1

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

7.8

8.6

9.8

11.5

0.10

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07

0.08

0.09

0.14 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.5

2.5

2.7

2.9

5.3

4.9

5.0

3.9

2.7

3.0

3.3

5.8

5.5

5.6

4.5

3.1

3.3

3.7

6.6

6.2

6.3

5.2

3.6

3.9

4.3

7.8

7.3

7.5

7.3

5.1

ns

5.5

6.1

10.9

10.2

10.4

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

5.7

6.3

7.1

8.4

11.8

16.1

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

7.8

8.6

9.8

11.5

0.10

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07

0.08

0.09

0.14 ns/pF

1. Delays based on 35 pF loading.

v6 .0

7 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.9

2.2

2.1

2.5

2.3

2.8

2.7

3.3

3.8

4.7

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.3

1.8

2.3

2.8

4.6

0.5

1.5

2.0

2.5

3.1

5.2

0.5

1.7

2.3

2.8

3.5

5.8

0.6

2.0

2.7

3.4

4.1

6.9

0.7

2.7

3.7

4.7

5.7

9.6

1.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.8

2.0

2.3

2.7

3.7

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

t_RO

2.2

2.4

2.7

3.2

4.5

t_SUENA

t_HENA

t_WCLKA

1.0

0.0

1.1

0.0

1.2

0.0

1.4

0.0

2.0

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

6.1

5.2

6.8

5.8

7.7

6.9

9.0

9.6

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

12.6

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

7 6

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

Logic Module Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

t_RC

Read Cycle Time

9.5

4.8

10.5

5.3

11.9

6.0

14.0

7.0

19.6

9.8

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

4.8

5.3

6.0

7.0

9.8

2.3

0.0

0.9

4.8

3.8

0.0

3.9

0.0

2.5

0.0

1.0

5.3

4.2

0.0

4.3

0.0

2.8

0.0

1.1

6.0

4.8

0.0

4.9

0.0

3.4

0.0

1.3

7.0

5.6

0.0

5.7

0.0

4.8

0.0

1.8

9.8

7.8

0.0

8.0

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

11.3

12.6

14.3

16.8

23.5

ns

t_RDADV

t_ADSU

t_ADH

12.3

2.3

0.0

0.9

4.8

3.8

0.0

13.7

2.5

0.0

1.0

5.3

4.2

0.0

15.5

2.8

0.0

1.1

6.0

4.8

0.0

18.2

3.4

0.0

1.3

7.0

5.6

0.0

25.5

4.8

0.0

1.8

9.8

7.8

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.8

2.0

2.1

2.5

3.5

v6 .0

7 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

2.0

1.6

2.2

1.8

2.5

2.1

2.9

3.0

4.1

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

1.4

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

13.5

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.8

3.2

3.7

4.2

6.1

3.1

3.5

4.1

4.6

6.8

3.5

4.1

4.7

5.3

7.7

4.1

4.8

5.5

6.2

9.0

5.7

6.7

ns

7.7

8.7

12.6

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

4.6

5.0

5.1

5.6

5.7

6.3

6.7

7.4

9.3

10.3

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

5.3

6.8

5.9

7.6

6.7

8.6

7.8

10.1

11.0

14.1

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=635

2.5

2.8

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Minimum Pulse Width LOW FO=32

FO=635

2.5

2.8

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Maximum Skew

FO=32

1.0

1.2

1.3

1.5

2.2

ns

FO=635

Input Latch External Set-Up FO=32

FO=635

0.0

ns

Input Latch External Hold

FO=32

4.0

4.6

4.4

5.2

5.0

5.9

6.9

8.2

9.6

ns

FO=635

Minimum Period (1/f_MAX

)

FO=32

9.2

9.9

10.2

11.0

11.1

12.0

12.7

13.8

21.2

23.0

ns

FO=635

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=635

108

100

98

91

90

83

79

73

47

44

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 8

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C A}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

3.6

4.2

3.7

4.1

7.34

6.9

4.9

4.0

4.6

4.2

4.6

8.2

7.6

5.5

4.5

5.2

4.7

5.2

9.3

8.7

6.2

5.3

6.2

7.4

8.6

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.5

7.7

6.1

8.5

10.9

10.2

7.3

15.3

14.3

10.2

G-to-Pad LOW

7.3

I/O Latch Output Set-Up

I/O Latch Output Hold

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.9

8.8

10.0

11.8

16.5

22.5

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

10.9

0.10

12.1

0.11

13.7

0.12

16.1

0.14

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.20 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.9

3.4

3.7

4.1

7.4

6.9

7.0

5.5

3.8

4.1

4.6

8.2

7.6

7.8

6.2

4.3

4.7

5.2

9.3

8.7

8.9

7.3

5.1

10.3

7.1

ns

5.5

7.7

6.1

8.5

10.9

10.2

10.4

15.3

14.3

14.6

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.9

8.8

10.0

11.8

16.5

22.5

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

10.9

0.10

12.1

0.11

13.7

0.12

16.1

0.14

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.20 ns/pF

1. Delays based on 35 pF loading.

v6 .0

7 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P i n D e s c r i p t i o n s

C LK /A/B , I/O G lo b a l C lo c k

P R A, I/O

P R B , I/O

P r o b e A/B

Clock inputs for clock distribution networks. CLK is for

40MX while CLKA and CLKB are for 42MX devices. The

clock input is buffered prior to clocking the logic modules.

This pin can also be used as an I/O.

The Probe pin is used to output data from any user-defined

design node within the device. Each diagnostic pin can be

used in conjunction with the other probe pin to allow

real-time diagnostic output of any signal path within the

device. The Probe pin can be used as a user-defined I/O

when verification has been completed. The pin's probe

capabilities can be permanently disabled to protect

programmed design confidentiality. The Probe pin is

accessible when the MODE pin is HIGH. This pin functions

as an I/O when the MODE pin is LOW.

DC LK , I/O

Dia g n o s t ic C lo c k

Clock input for diagnostic probe and device programming.

DCLK is active when the MODE pin is HIGH. This pin

functions as an I/O when the MODE pin is LOW.

G N D

G r o u n d

Input LOW supply voltage.

I/O

In p u t /O u t p u t

Q C LK A/B /C /D, I/O Q u a d r a n t C lo c k

Quadrant clock inputs for A42MX36 devices. When not used

as a register control signal, these pins can function as user

I/Os.

Input, output, tristate or bi-directional buffer. Input and

output levels are compatible with standard TTL and CMOS

specifications. Unused I/Os pins are configured by the

Designer software as shown in Table 8.

S DI, I/O

S e r ia l D a t a In p u t

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

Table 8 • Configuration of Unused I/Os

Device

Configuration

A40MX02, A40MX04

A42MX09, A42MX16

A42MX24, A42MX36

Pulled LOW

Tristated

S DO , I/O

S e r ia l Da t a O u t p u t

Serial data output for diagnostic probe and device

programming. SDO is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

SDO is available for 42MX devices only.

In all cases, it is recommended to tie all unused MX I/O pins

to LOW on the board. This applies to all dual-purpose pins

when configured as I/Os as well.

When Silicon Explorer II is being used, SDO will act as an

output while the "checksum" command is run. It will return

to user I/O when "checksum" is complete.

LP

Lo w P o w e r Mo d e

Controls the low power mode of all 42MX devices. The

device is placed in the low power mode by connecting the

LP pin to logic HIGH. In low power mode, all I/Os are

tristated, all input buffers are turned OFF, and the core of

the device is turned OFF. To exit the low power mode, the

LP pin must be set LOW. The device enters the low power

mode 800ns after the LP pin is driven to a logic HIGH. It will

resume normal operation in 200µs after the LP pin is driven

to a logic LOW.

T C K , I/O

Te s t C lo c k

Clock signal to shift the Boundary Scan Test (BST) data into

the device. This pin functions as an I/O when "Reserve

JTAG" is not checked in the Designer Software. BST pins are

only available in A42MX24 and A42MX36 devices.

T DI, I/O

Te s t Da t a In

Serial data input for BST instructions and data. Data is

shifted in on the rising edge of TCK. This pin functions as an

I/O when "Reserve JTAG" is not checked in the Designer

Software. BST pins are only available in A42MX24 and

A42MX36 devices.

MO DE

Mo d e

Controls the use of multifunction pins (DCLK, PRA, PRB,

SDI, TDO). The MODE pin is held HIGH to provide

verification capability. The MODE pin should be terminated

to GND through a 10kΩ resistor so that the MODE pin can

be pulled HIGH when required.

T DO , I/O

Te s t Da t a O u t

Serial data output for BST instructions and test data. This

pin functions as an I/O when "Reserve JTAG" is not checked

in the Designer Software. BST pins are only available in

A42MX24 and A42MX36 devices.

N C

N o C o n n e c t io n

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

8 0

v6 .0

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

T M S , I/O

Te s t M o d e S e le c t

V_{C C I}

S u p p ly Vo lt a g e

The TMS pin controls the use of the IEEE 1149.1 Boundary

Scan pins (TCK, TDI, TDO). In flexible mode when the TMS

pin is set LOW, the TCK, TDI and TDO pins are boundary

scan pins. Once the boundary scan pins are in test mode,

they will remain in that mode until the internal boundary

scan state machine reaches the "logic reset" state. At this

point, the boundary scan pins will be released and will

function as regular I/O pins. The "logic reset" state is

reached 5 TCK cycles after the TMS pin is set HIGH. In

dedicated test mode, TMS functions as specified in the

IEEE 1149.1 specifications. IEEE JTAG specification

recommends a 10kΩ pull-up resistor on the pin. BST pins

are only available in A42MX24 and A42MX36 devices.

Supply voltage for I/Os in 42MX devices

WD, I/O

Wid e D e c o d e O u t p u t

When a wide decode module is used in a 42MX device this

pin can be used as a dedicated output from the wide decode

module. This direct connection eliminates additional

interconnect delays associated with regular logic modules.

To implement the direct I/O connection, connect an output

buffer of any type to the output of the wide decode macro

and place this output on one of the reserved WD pins.

V_{C C}

S u p p ly Vo lt a g e

Input supply voltage for 40MX devices

V_{C C A}

S u p p ly Vo lt a g e

Supply voltage for array in 42MX devices

v6 .0

8 1

P a c k a g e P i n A s s i g n m e n t s

4 4 -P in P LC C

1 44

44-Pin

PLCC

4 4 -p in P L C C

A40MX02

Function

A40MX04

Function

A40MX02

Function

A40MX04

Function

Pin Number

1

2

I/O

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

I/O

3

V_CC

I/O

V_CC

I/O

V_CC

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

GND

I/O

GND

I/O

GND

CLK, I/O

MODE

V_CC

GND

CLK, I/O

MODE

V_CC

I/O

V_CC

I/O

V_CC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

8 2

v6 .0

P a c k a g e P i n A s s i g n m e n t s

6 8 -P in P LC C

1 68

68-Pin

PLCC

6 8 -P i n P L C C

Number

A40MX02 A40MX04

Number

A40MX02 A40MX04

Number

A40MX02 A40MX04

Function

1

2

I/O

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

I/O

3

I/O

GND

I/O

GND

I/O

4

V_CC

I/O

V_CC

I/O

5

I/O

6

I/O

CLK, I/O

I/O

CLK, I/O

I/O

7

I/O

8

I/O

MODE

V_CC

MODE

V_CC

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

SDI, I/O

I/O

DCLK, I/O DCLK, I/O

I/O

PRA, I/O

PRB, I/O

I/O

PRA, I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

v6 .0

8 3

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

8 4 -P in P LC C

1

84

84-Pin

PLCC

8 4

v6 .0

8 4 -P i n P L C C

A40MX04 A42MX09 A42MX16 A42MX24

A40MX04 A42MX09 A42MX16

A42MX24

Function

Number Function Function Function Function

Number Function Function Function

1

I/O

V_CC

I/O

NC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

CLKB, I/O CLKB, I/O CLKB, I/O

I/O I/O I/O

PRB, I/O PRB, I/O PRB, I/O

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

WD, I/O

I/O

2

3

I/O

4

V_CC

I/O

5

I/O

GND

I/O

GND

I/O

WD, I/O

GND

I/O

6

I/O

7

I/O

GND

I/O

GND

I/O

GND

8

I/O

WD, I/O

I/O

WD, I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

DCLK, I/O DCLK, I/O DCLK, I/O

I/O

SDO, I/O SDO, I/O SDO, TDO, I/O

I/O

MODE

I/O

MODE

I/O

MODE

I/O

GND

I/O

TCK, I/O

LP

I/O

LP

V_CCA

V_CCI

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

CLK, I/O

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

MODE

V_CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

TMS, I/O

TDI, I/O

WD, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

WD, I/O

PRA, I/O

I/O

WD, I/O

I/O

PRA, I/O PRA, I/O

I/O I/O

CLKA, I/O CLKA, I/O

V_CCAV_CCA

I/O

GND

I/O

CLKA, I/O

V_CCA

I/O

v6 .0

8 5

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in P Q F P P a c k a g e (T o p Vie w )

100-Pin

PQFP

100

1

8 6

v6 .0

1 0 0 -P in P Q F P

A40MX02 A40MX04 A42MX09 A42MX16

Number Function Function Function Function

1

NC

I/O

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

NC

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

NC

V_CCA

I/O

V_CCA

I/O

2

DCLK, I/O DCLK, I/O

3

I/O

MODE

I/O

MODE

I/O

4

I/O

5

I/O

6

PRB, I/O PRB, I/O

I/O

7

I/O

GND

I/O

V_CC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

8

I/O

9

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

I/O

GND

I/O

V_CC

I/O

NC

I/O

GND

I/O

SDO, I/O SDO, I/O

I/O

V_CCA

V_CCI

I/O

V_CCA

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

LP

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

v6 .0

8 7

1 0 0 -P in P Q F P ( C o n t in u e d )

A40MX02 A40MX04 A42MX09 A42MX16

Number Function Function Function Function

79

80

81

82

83

84

85

86

87

88

89

NC

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

90

91

92

93

94

95

96

97

98

99

100

CLK, I/O CLK, I/O

V_CCA

I/O

V_CCA

I/O

MODE

V_CC

I/O

MODE

V_CC

I/O

CLKB, I/O CLKB, I/O

I/O I/O

PRB, I/O PRB, I/O

I/O

V_CC

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

PRA, I/O PRA, I/O

I/O I/O

CLKA, I/O CLKA, I/O

SDI, I/O

I/O

DCLK, I/O DCLK, I/O

PRA, I/O PRA, I/O

I/O

8 8

v6 .0

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 6 0 -P in P Q F P P a c k a g e (T o p Vie w )

160

1

160-Pin

PQFP

v6 .0

8 9

1 6 0 -P in P Q F P

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

1

I/O

DCLK, I/O

NC

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

2

3

I/O

4

I/O

WD, I/O

V_CCI

GND

I/O

GND

I/O

GND

I/O

5

I/O

6

NC

V_CCI

I/O

7

I/O

8

I/O

9

I/O

GND

I/O

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

NC

I/O

GND

NC

GND

I/O

GND

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

V_CCI

GND

V_CCA

LP

V_CCA

V_CCI

GND

V_CCA

LP

V_CCA

V_CCI

GND

V_CCA

LP

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

V_CCA

CLKA, I/O

I/O

V_CCA

CLKA, I/O

I/O

V_CCA

CLKA, I/O

I/O

TCK, I/O

I/O

PRA, I/O

NC

PRA, I/O

I/O

PRA, I/O

WD, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

WD, I/O

GND

NC

I/O

GND

I/O

GND

I/O

GND

NC

GND

I/O

WD, I/O

I/O

NC

V_CCI

I/O

V_CCI

NC

I/O

WD, I/O

SDI, I/O

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

NC

GND

I/O

GND

9 0

v6 .0

1 6 0 -P in P Q F P ( C o n t in u e d )

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

81

82

I/O

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

WD, I/O

I/O

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

I/O

83

I/O

84

I/O

NC

GND

I/O

85

I/O

GND

I/O

GND

I/O

86

NC

I/O

V_CCI

I/O

V_CCI

87

I/O

88

I/O

WD, I/O

GND

I/O

89

GND

NC

I/O

GND

I/O

NC

GND

I/O

90

GND

I/O

GND

I/O

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

96

I/O

WD, I/O

I/O

97

I/O

98

V_CCA

GND

NC

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

NC

V_CCI

GND

NC

I/O

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

NC

I/O

GND

NC

I/O

GND

I/O

GND

I/O

WD, I/O

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

GND

I/O

V_CCA

I/O

V_CCA

I/O

WD, I/O

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

GND

I/O

GND

I/O

NC

I/O

TDI, I/O

TMS, I/O

GND

I/O

MODE

GND

MODE

GND

MODE

GND

v6 .0

9 1

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 0 8 -P in P Q F P P a c k a g e (T o p Vie w )

208

1

208-Pin PQFP

9 2

v6 .0

2 0 8 -P in P Q F P

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

1

GND

NC

MODE

I/O

GND

V_CCA

MODE

I/O

GND

V_CCA

MODE

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

NC

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

NC

GND

I/O

9

NC

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

TMS, I/O

TDI, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

V_CCI

NC

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

QCLKA, I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

WD, I/O

I/O

WD, I/O

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

GND

V_CCA

NC

I/O

GND

V_CCA

V_CCI

I/O

GND

V_CCA

V_CCI

I/O

NC

I/O

v6 .0

9 3

2 0 8 -P in P Q F P ( C o n t in u e d )

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

85

86

I/O

WD, I/O

I/O

WD, I/O

I/O

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

I/O

TCK, I/O

LP

I/O

TCK, I/O

LP

87

I/O

LP

88

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

89

NC

I/O

90

I/O

91

I/O

QCLKB, I/O

I/O

92

I/O

93

I/O

WD, I/O

I/O

WD, I/O

I/O

94

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

95

NC

V_CCI

I/O

96

I/O

97

I/O

98

V_CCI

I/O

V_CCI

I/O

99

I/O

NC

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

I/O

WD, I/O

I/O

WD, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O SDO, TDO, I/O

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

NC

I/O

GND

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

V_CCI

NC

V_CCI

I/O

V_CCI

I/O

NC

I/O

GND

I/O

WD, I/O

9 4

v6 .0

2 0 8 -P in P Q F P ( C o n t in u e d )

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

I/O

WD, I/O

I/O

WD, I/O

I/O

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

QCLKD, I/O

I/O

NC

I/O

NC

WD, I/O

I/O

WD, I/O

QCLKC, I/O

I/O

NC

I/O

WD, I/O

PRA, I/O

I/O

WD, I/O

PRA, I/O

I/O

NC

I/O

PRA, I/O

I/O

CLKA, I/O

NC

CLKA, I/O

I/O

CLKA, I/O

I/O

NC

I/O

NC

V_CCI

I/O

V_CCI

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

WD, I/O

I/O

WD, I/O

I/O

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

PRB, I/O

v6 .0

9 5

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 4 0 -P in P Q F P P a c k a g e (T o p Vie w )

240

1

•

240-Pin

PQFP

9 6

v6 .0

2 4 0 -P in P Q F P

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

1

I/O

DCLK, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

81

82

I/O

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

GND

I/O

2

3

I/O

83

I/O

SDO, TDO, I/O

I/O

4

I/O

84

I/O

5

I/O

QCLKD, I/O

I/O

85

V_CCA

I/O

WD, I/O

I/O

6

WD, I/O

V_CCI

86

7

WD, I/O

I/O

87

I/O

8

88

V_CCA

V_CCI

V_CCA

LP

V_CCI

I/O

9

I/O

89

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I/O

90

I/O

91

I/O

V_CCI

I/O

92

TCK, I/O

I/O

WD, I/O

I/O

93

I/O

WD, I/O

I/O

94

GND

I/O

QCLKC, I/O

I/O

95

QCLKB, I/O

I/O

96

I/O

WD, I/O

I/O

SDI, I/O

I/O

97

I/O

98

I/O

V_CCA

GND

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

WD, I/O

I/O

WD, I/O

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

GND

V_CCA

V_CCI

I/O

V_CCI

I/O

V_CCI

V_CCA

GND

I/O

V_CCI

I/O

CLKA, I/O

I/O

PRA, I/O

I/O

WD, I/O

I/O

V_CCA

GND

I/O

WD, I/O

I/O

v6 .0

9 7

2 4 0 -P in P Q F P ( C o n t in u e d )

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

I/O

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

V_CCA

GND

I/O

V_CCI

I/O

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

I/O

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

I/O

WD, I/O

I/O

QCLKA, I/O

I/O

V_CCA

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

GND

MODE

V_CCA

GND

TDI, I/O

TMS, I/O

GND

I/O

V_CCA

I/O

9 8

v6 .0

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

8 0 -P in VQ F P

80

1

80-Pin

VQFP

v6 .0

9 9

8 0 -P i n V Q F P

A40MX02

Function

A40MX04

Function

A40MX02

Function

A40MX04

Function

Pin Number

1

I/O

NC

I/O

GND

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

NC

I/O

2

3

NC

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

GND

I/O

8

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

CLK, I/O

I/O

CLK, I/O

I/O

MODE

V_CC

NC

MODE

V_CC

I/O

NC

I/O

NC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

NC

SDI, I/O

DCLK, I/O

PRA, I/O

NC

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

1 0 0

v6 .0

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in V Q F P P a c k a g e ( T o p V ie w )

100

1

100-Pin

VQFP

v6 .0

1 0 1

1 0 0 -P in VQ F P P a c k a g e

A42MX09

Function

A42MX16

Function

A42MX09

Function

A42MX16

Function

Pin Number

1

I/O

MODE

I/O

MODE

I/O

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

2

3

4

I/O

5

I/O

GND

I/O

GND

I/O

6

I/O

7

GND

I/O

GND

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

I/O

LP

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

I/O

NC

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

V_CCA

I/O

CLKA, I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDO, I/O

DCLK, I/O

1 0 2

v6 .0

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 7 6 -P in T Q F P P a c k a g e (T o p Vie w )

176

1

176-Pin

TQFP

v6 .0

1 0 3

1 7 6 -P in T Q F P

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

1

GND

MODE

I/O

GND

MODE

I/O

GND

MODE

I/O

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

GND

I/O

GND

I/O

GND

TMS, I/O

TDI, I/O

I/O

2

3

I/O

4

I/O

5

I/O

WD, I/O

I/O

6

I/O

7

I/O

8

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

NC

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

I/O

NC

GND

NC

V_CCA

NC

V_CCI

NC

I/O

NC

GND

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCA

I/O

GND

V_CCA

WD, I/O

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

NC

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

I/O

1 0 4

v6 .0

1 7 6 -P in T Q F P ( C o n t in u e d )

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

89

90

GND

I/O

GND

I/O

GND

I/O

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

GND

I/O

GND

I/O

GND

I/O

91

I/O

SDI, I/O

NC

SDI, I/O

I/O

SDI, I/O

I/O

92

I/O

93

I/O

WD, I/O

I/O

94

I/O

95

I/O

96

NC

I/O

NC

V_CCI

I/O

V_CCI

97

I/O

98

I/O

99

I/O

NC

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

NC

LP

GND

I/O

GND

I/O

WD, I/O

PRA, I/O

I/O

NC

I/O

TCK, I/O

LP

PRA, I/O

I/O

PRA, I/O

I/O

LP

V_CCA

GND

V_CCI

V_CCA

NC

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

V_CCA

I/O

V_CCA

I/O

PRB, I/O

NC

PRB, I/O

I/O

PRB, I/O

WD, I/O

I/O

NC

I/O

NC

I/O

NC

WD, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

NC

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

v6 .0

1 0 5

P a c k a g e P i n A s s i g n m e n t s

2 0 8 -P in C Q F P (T o p Vie w )

208 207 206 205 204 203 202 201 200

164 163 162 161 160 159 158 157

Pin #1

Index

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

A42MX36

208-Pin

CQFP

44

45

46

47

48

49

50

51

52

113

112

111

110

109

108

107

106

105

53 54 55 56 57 58 59 60 61

97 98 99 100 101 102 103 104

1 0 6

v6 .0

2 0 8 -P in C Q F P

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

1

GND

V_CCA

MODE

I/O

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

I/O

79

80

V_CCA

V_CCI

I/O

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

I/O

2

3

I/O

81

I/O

4

I/O

82

I/O

5

I/O

83

I/O

6

I/O

84

I/O

7

I/O

85

WD, I/O

I/O

8

I/O

86

I/O

9

I/O

87

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

I/O

88

I/O

89

I/O

TCK, I/O

LP

I/O

90

I/O

GND

TMS, I/O

TDI, I/O

I/O

91

QCLKB, I/O

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

92

I/O

93

WD, I/O

I/O

94

V_CCA

I/O

95

WD, I/O

I/O

96

I/O

97

I/O

V_CCA

I/O

98

V_CCI

I/O

V_CCI

I/O

99

I/O

GND

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

WD, I/O

I/O

TDO, I/O

I/O

QCLKA, I/O

WD, I/O

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCA

I/O

WD, I/O

I/O

V_CCA

I/O

GND

I/O

GND

I/O

v6 .0

1 0 7

2 0 8 -P in C Q F P (C o n t in u e d )

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

157

158

159

160

161

162

163

164

165

166

167

168

169

GND

I/O

170

171

172

173

174

175

176

177

178

179

180

181

182

I/O

QCLKD, I/O

I/O

183

184

185

186

187

188

189

190

191

192

193

194

195

V_CCA

GND

196

197

198

199

200

201

202

203

204

205

206

207

208

QCLKC, I/O

I/O

SDI, I/O

I/O

CLKB, I/O

I/O

WD, I/O

I/O

PRB, I/O

I/O

WD, I/O

PRA, I/O

I/O

V_CCI

WD, I/O

I/O

WD, I/O

I/O

CLKA, I/O

I/O

WD, I/O

DCLK, I/O

I/O

V_CCI

1 0 8

v6 .0

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 5 6 -P in C Q F P (T o p Vie w )

256 255 254 253 252 251 250 249 248

200 199 198 197 196 195 194 193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

A42MX36

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121 122 123 124 125 126 127 128

v6 .0

1 0 9

2 5 6 -P in C Q F P

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

1

NC

GND

I/O

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

I/O

87

88

WD, I/O

I/O

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

NC

GND

I/O

2

3

I/O

89

4

I/O

90

I/O

5

I/O

GND

I/O

91

I/O

6

I/O

92

I/O

7

I/O

93

I/O

8

I/O

94

I/O

9

I/O

95

V_CCI

V_CCA

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

GND

I/O

96

GND

I/O

97

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

I/O

V_CCA

GND

NC

I/O

WD, I/O

I/O

NC

I/O

NC

I/O

WD, I/O

I/O

SDO, TDO, I/O

I/O

V_CCA

I/O

WD, I/O

I/O

QCLKA, I/O

I/O

V_CCA

I/O

GND

I/O

V_CCA

V_CCI

GND

V_CCA

LP

V_CCI

I/O

V_CCA

V_CCI

GND

I/O

WD, I/O

GND

WD, I/O

I/O

V_CCI

I/O

TCK, I/O

I/O

WD, I/O

I/O

GND

I/O

GND

I/O

QCLKB, I/O

I/O

GND

NC

V_CCA

I/O

NC

I/O

1 1 0

v6 .0

2 5 6 -P in C Q F P (C o n t in u e d )

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

I/O

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

I/O

DCLK, I/O

I/O

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

WD, I/O

I/O

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

I/O

PRB, I/O

I/O

QCLKD, I/O

I/O

WD, I/O

V_CCI

CLKB, I/O

I/O

WD, I/O

GND

WD, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCA

V_CCI

I/O

GND

I/O

CLKA, I/O

I/O

V_CCI

I/O

PRA, I/O

I/O

WD, I/O

I/O

MODE

V_CCA

GND

NC

QCLKC, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

SDI, I/O

I/O

NC

GND

NC

I/O

v6 .0

1 1 1

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 7 2 -P in B G A P a c k a g e ( T o p V ie w )

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

A

B

C

D

E

F

G

H

J

272-Pin PBGA

K

L

M

N

P

R

T

U

V

W

Y

1 1 2

v6 .0

2 7 2 -P in P B G A

Number

A42MX36

Function

A42MX36

Function

A42MX36

Function

A42MX36

Function

Ball

A1

A2

GND

I/O

C4

C5

I/O

WD, I/O

I/O

E19

E20

F1

I/O

K10

K11

K12

K17

K18

K19

K20

L1

GND

I/O

A3

C6

I/O

A4

WD, I/O

I/O

C7

QCLKC, I/O

I/O

F2

I/O

A5

C8

F3

I/O

V_CCA

LP

A6

I/O

C9

I/O

F4

V_CCI

I/O

A7

WD, I/O

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

CLKB

PRA, I/O

WD, I/O

I/O

F17

F18

F19

F20

G1

A8

I/O

A9

I/O

L2

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

I/O

L3

V_CCA

GND

V_CCI

I/O

CLKA

I/O

QCLKD, I/O

I/O

L4

G2

I/O

L9

I/O

WD, I/O

SDI, I/O

I/O

G3

I/O

L10

L11

L12

L17

L18

L19

L20

M1

I/O

G4

V_CCI

I/O

G17

G18

G19

G20

H1

WD, I/O

I/O

GND

DCLK, I/O

I/O

D2

I/O

TCK, I/O

I/O

D3

I/O

H2

I/O

D4

I/O

H3

I/O

M2

I/O

B2

D5

V_CCI

I/O

H4

V_CCA

I/O

M3

I/O

B3

D6

H17

H18

H19

H20

J1

M4

V_CCI

GND

I/O

B4

D7

I/O

M9

B5

I/O

D8

V_CCA

WD, I/O

V_CCI

I/O

M10

M11

M12

M17

M18

M19

M20

N1

B6

I/O

D9

I/O

B7

WD, I/O

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E1

I/O

B8

J2

I/O

B9

PRB, I/O

I/O

V_CCI

I/O

J3

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

J4

V_CCI

GND

V_CCA

I/O

V_CCI

I/O

J9

I/O

WD, I/O

I/O

J10

J11

J12

J17

J18

J19

J20

K1

I/O

V_CCA

GND

I/O

N2

I/O

N3

I/O

WD, I/O

I/O

N4

V_CCI

I/O

N17

N18

N19

N20

P1

WD, I/O

I/O

GND

I/O

E2

I/O

E3

I/O

K2

I/O

E4

V_CCA

V_CCI

I/O

K3

I/O

P2

I/O

C2

MODE

GND

E17

E18

K4

V_CCI

GND

P3

I/O

C3

K9

P4

V_CCA

v6 .0

1 1 3

2 7 2 -P in P B G A (C o n t in u e d )

Number

A42MX36

Function

A42MX36

Function

A42MX36

Function

A42MX36

Function

Ball

P17

P18

P19

P20

R1

I/O

U6

U7

WD, I/O

I/O

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W1

I/O

W16

W17

W18

W19

W20

Y1

WD, I/O

I/O

U8

I/O

WD, I/O

I/O

WD, I/O

GND

I/O

U9

WD, I/O

V_CCA

V_CCI

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

WD, I/O

I/O

R2

I/O

R3

I/O

Y2

R4

V_CCI

I/O

SDO, TDO, I/O

I/O

Y3

R17

R18

R19

R20

T1

QCLKB, I/O

I/O

Y4

TDI, I/O

WD, I/O

I/O

Y5

I/O

V_CCI

I/O

GND

I/O

Y6

I/O

W2

Y7

QCLKA, I/O

I/O

GND

I/O

W3

Y8

T2

I/O

W4

TMS, I/O

I/O

Y9

I/O

T3

I/O

W5

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

I/O

T4

I/O

W6

I/O

T17

T18

T19

T20

U1

V_CCA

I/O

V2

I/O

W7

I/O

V3

GND

I/O

W8

WD, I/O

I/O

V4

W9

I/O

V5

W10

W11

W12

W13

W14

W15

I/O

V6

I/O

U2

I/O

V7

I/O

U3

I/O

V8

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

GND

U4

I/O

V9

U5

V_CCI

V10

I/O

1 1 4

v6 .0

L i s t o f C h a n g e s

The following table lists critical changes that were made in the current version of the document.

Previous version Changes in current version (v6.0)

Page

The “Ease of Integration” section on page 1 was updated.

The “Temperature Grade Offerings” table on page 3 is new.

The “Speed Grade Offerings” table on page 3 is new.

The “General Description” section on page 4 was updated.

The “MultiPlex I/O Modules” section on page 9 was updated.

The “User Security” section on page 9 was updated.

Table 1 on page 10 was updated.

page 1

page 3

page 4

page 9

page 10

page 11

page 14

page 15

The “Power Dissipation” section on page 11 was updated.

The “Static Power Component” section on page 11 was updated.

The “Equivalent Capacitance” section on page 11 was updated.

Figure 13 on page 14 was updated.

Table 4 on page 14 was updated.

Figure 14 on page 15 was updated.

Table 5 on page 15 was updated.

The “Development Tool Support” section on page 15 was updated.

The “Absolute Maximum Ratings for 42MX Devices*” table on page 17 and the “Absolute page 17

Maximum Ratings for 40MX Devices*” table on page 19 were updated.

The “5V TTL Electrical Specifications” table on page 18 was updated.

The “3.3V LVTTL Electrical Specifications” table on page 20 was updated.

page 18

page 20

page 21

In the “Mixed 5.0V/3.3V Operating Conditions (for 42MX devices only)” section on

page 21, the “Absolute Maximum Ratings*” table , “Recommended Operating Conditions”

table , and “Mixed 5.0V/3.3V Electrical Specifications” table were updated.

The “DC Specification (5.0V PCI Signaling)1” table on page 22 was updated.

The “DC Specification (3.3V PCI Signaling)1” table on page 23 was updated.

page 22

page 23

page 25

v5.1

The Junction Temperature (TJ) section, “Package Thermal Characteristics” section on

page 25, and the tables were updated.

The “40MX Timing Model*” on page 26 was updated.

page 26

page 28

page 29

page 32

page 39

page 40

page 80

page 87

The “42MX Timing Model (Logic Functions using Quadrant Clocks)*” on page 28

The “42MX Timing Model (SRAM Functions)*” on page 29 was updated.

The “Output Buffer Latches” figure on page 32 was updated.

The “42MX Temperature and Voltage Derating Factors” section on page 39 is new.

The “40MX Temperature and Voltage Derating Factors” section on page 40 is new.

The “Pin Descriptions” section on page 80 was updated.

In the “100-Pin PQFP” table on page 87, the following pins changed:

Pin 64 (42MX09 and 42MX16) has changed to LP

In the “160-Pin PQFP” table on page 90, the following pins changed:

Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP

page 90

page 93

In the “208-Pin PQFP” table on page 93, the following pins changed:

Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP

Pin 198 (42MX09) has changed to I/O

The n the “240-Pin PQFP” table on page 97, the following pins changed:

Pin 91 (42MX36) has changed to LP

page 97

In the “100-Pin VQFP Package” table on page 102, the following pins changed:

Pin 62 (42MX09 and 42MX16) has changed to LP

page 102

page 104

page 113

In the “176-Pin TQFP” table on page 104, the following pins changed:

Pin 109 (42MX09 and 42MX16) has changed to LP

In the “272-Pin PBGA” table on page 113, the following pins changed:

Pin K20 (42MX36) has changed to LP

v6 .0

1 1 5

The “Low Power Mode” on page 5 was updated.

page 5

v5.0

Footnote 8 in the “Electrical Specifications” table on page 13 was updated.

Footnote 8 in the “Electrical Specifications” table on page 14 was updated.

page 13

page 14

Because the changes in this data sheet are extensive and technical in nature, this should ALL

be viewed as a new document. Please read it as you would a data sheet that is published

for the first time.

v4.0.1

Note that the “Package Characteristics and Mechanical Drawings” section has been

eliminated from the data sheet. The mechanical drawings are now contained in a separate

document, “Package Characteristics and Mechanical Drawings,” available on the Actel

web site.

D a t a S h e e t C a t e g o r i e s

In order to provide the latest information to designers, some datasheets are published before data has been fully characterized.

Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definition of these

categories are as follows:

P r o d u c t B r ie f

The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This

brief gives an overview of specific device and family information.

Ad v a n c e d

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This

information can be used as estimates, but not for production.

U n m a r k e d (p r o d u c t io n )

This datasheet version contains information that is considered to be final.

Da t a s h e e t S u p p le m e n t

The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet.

The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that

do not differ between the two families.

1 1 6

v6 .0

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

2061 Stierlin Court

Mountain View, CA 94043-4655

USA

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

39th Floor

One Pacific Place

88 Queensway

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: (650) 318-4200

Fax: (650) 318-4600

Tel: +44 (0)1276 401450

Fax: +44 (0)1276 401490

Tel: +81 03-3445-7671

Fax: +81 03-3445-7668

Admiralty, Hong Kong

Tel: 852-22735712

5172136-8/1.04


型号：	A42MX24-3TQ176IX39
厂家：	Actel Corporation
描述：	Field Programmable Gate Array, 1890-Cell, CMOS, PQFP176, 栅可编程逻辑
文件：	总117页 (文件大小：2763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A42MX24-3TQ176IX39 [ACTEL]

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A42MX24-3TQ176M

A42MX24-3TQ176MX39

A42MX24-3TQ176MX79

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A42MX24-3TQ176YC

A42MX24-3TQ176YI

A42MX24-3TQ208

A42MX24-3TQ208A

A42MX24-3TQ208B

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A42MX24-3TQ208M