APA075-CQI_技术文档

PLUS

ProASIC

Flash Family FPGAs

General Description

The ProASIC^PLUSfamily of devices, Actel’s second-

generation Flash FPGAs, offers enhanced performance

over Actel’s ProASIC family. It combines the advantages

of ASICs with the benefits of programmable devices

through nonvolatile Flash technology. This enables

engineers to create high-density systems using existing

ASIC or FPGA design flows and tools. In addition, the

ProASIC^PLUSfamily offers a unique clock conditioning

circuit based on two on-board phase-locked loops (PLLs).

The family offers up to one million system gates,

supported with up to 198 kbits of two-port SRAM and up

to 712 user I/Os, all providing 50 MHz PCI performance.

combination of fine granularity, flexible routing

resources, and abundant Flash switches allow 100%

utilization and over 95% routability for highly congested

designs. Tiles and larger functions are interconnected

through a four-level routing hierarchy.

Embedded two-port SRAM blocks with built-in FIFO/RAM

control logic can have user-defined depths and widths.

Users can also select programming for synchronous or

asynchronous operation, as well as parity generations or

checking.

The unique clock conditioning circuitry in each device

includes two clock conditioning blocks. Each block

provides a PLL core, delay lines, phase shifts (0° and

180°), and clock multipliers/dividers, as well as the

circuitry needed to provide bidirectional access to the

PLL. The PLL block contains four programmable

frequency dividers which allow the incoming clock signal

to be divided by a wide range of factors from 1 to 64.

The clock conditioning circuit also delays or advances the

incoming reference clock up to 8 ns (in increments of

0.25 ns). The PLL can be configured internally or

externally during operation without redesigning or

reprogramming the part. In addition to the PLL, there

are two LVPECL differential input pairs to accommodate

high-speed clock and data inputs.

Advantages

to

the

designer

extend

beyond

performance. Unlike SRAM-based FPGAs, four levels of

routing hierarchy simplify routing, while the use of Flash

technology allows all functionality to be live at power-

up. No external boot PROM is required to support device

programming. While on-board security mechanisms

prevent

access

to

the

program

information,

reprogramming can be performed in-system to support

future design iterations and field upgrades. The device’s

architecture mitigates the complexity of ASIC migration

at higher user volume. This makes ProASIC^PLUSa cost-

effective solution for applications in the networking,

communications, computing, and avionics markets.

The ProASIC^PLUSfamily achieves its nonvolatility and

reprogrammability through an advanced Flash-based

0.22 μm LVCMOS process with four layers of metal.

Standard CMOS design techniques are used to

implement logic and control functions, including the

PLLs and LVPECL inputs. This results in predictable

performance compatible with gate arrays.

The ProASIC^PLUSarchitecture provides granularity

comparable to gate arrays. The device core consists of a

Sea-of-Tiles™. Each tile can be configured as a flip-flop,

latch, or three-input/one-output logic function by

programming the appropriate Flash switches. The

To support customer needs for more comprehensive,

lower-cost, board-level testing, Actel’s ProASIC^PLUS

devices are fully compatible with IEEE Standard 1149.1

for test access port and boundary-scan test architecture.

For more information concerning the Flash FPGA

implementation, please refer to the "Boundary Scan

(JTAG)" section on page 1-11.

ProASIC^PLUSdevices are available in a variety of high-

performance plastic packages. Those packages and the

performance features discussed above are described in

more detail in the following sections.

v5.7

1-1

PLUS

ProASIC

Flash Family FPGAs

PLUS

the appropriate logic cell inputs and outputs. Dedicated

high-performance lines are connected as needed for fast,

low-skew global signal distribution throughout the core.

Maximum core utilization is possible for virtually any

design.

ProASIC^PLUSdevices also contain embedded, two-port

SRAM blocks with built-in FIFO/RAM control logic.

ProASIC

Architecture

The proprietary ProASIC^PLUSarchitecture provides

granularity comparable to gate arrays.

The ProASIC^PLUSdevice core consists of a Sea-of-Tiles

(Figure 1-1). Each tile can be configured as a three-input

logic function (e.g., NAND gate, D-Flip-Flop, etc.) by

programming

the

appropriate

Flash

switch

Programming

options

include

synchronous

or

interconnections (Figure 1-2 and Figure 1-3 on page 1-3).

Tiles and larger functions are connected with any of the

four levels of routing hierarchy. Flash switches are

distributed throughout the device to provide

nonvolatile, reconfigurable interconnect programming.

Flash switches are programmed to connect signal lines to

asynchronous operation, two-port RAM configurations,

user defined depth and width, and parity generation or

checking. Please see the "Embedded Memory

Configurations" section on page 1-22 for more

information.

RAM Block

256x9 Two-Port SRAM

or FIFO Block

I/Os

Logic Tile

RAM Block

256x9 Two Port SRAM

or FIFO Block

Figure 1-1 • The ProASIC^PLUSDevice Architecture

Switch In

Floating Gate

Sensing

Switching

Word

Switch Out

Figure 1-2 • Flash Switch

1-2

v5.7

PLUS

ProASIC

Flash Family FPGAs

Local Routing

In 1

Efficient Long-Line Routing

In 2 (CLK)

In 3 (Reset)

Figure 1-3 • Core Logic Tile

Live at Power-Up

Flash Switch

The Actel Flash-based ProASIC^PLUSdevices support

Level 0 of the live at power-up (LAPU) classification

standard. This feature helps in system component

initialization, executing critical tasks before the

processor wakes up, setting up and configuring memory

blocks, clock generation, and bus activity management.

The LAPU feature of Flash-based ProASIC^PLUSdevices

greatly simplifies total system design and reduces total

system cost, often eliminating the need for Complex

Programmable Logic Device (CPLD) and clock generation

PLLs that are used for this purpose in a system. In

addition, glitches and brownouts in system power will

not corrupt the ProASIC^PLUSdevice's Flash configuration,

and unlike SRAM-based FPGAs, the device will not have

to be reloaded when system power is restored. This

enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from

the PCB design. Flash-based ProASIC^PLUSdevices simplify

total system design, and reduce cost and design risk,

while increasing system reliability and improving system

initialization time.

Unlike SRAM FPGAs, ProASIC^PLUSuses a live-on-power-up

ISP Flash switch as its programming element.

In the ProASIC^PLUSFlash switch, two transistors share the

floating gate, which stores the programming

information. One is the sensing transistor, which is only

used for writing and verification of the floating gate

voltage. The other is the switching transistor. It can be

used in the architecture to connect/separate routing nets

or to configure logic. It is also used to erase the floating

gate (Figure 1-2 on page 1-2).

Logic Tile

The logic tile cell (Figure 1-3) has three inputs (any or all

of which can be inverted) and one output (which can

connect to both ultra-fast local and efficient long-line

routing resources). Any three-input, one-output logic

function (except a three-input XOR) can be configured as

one tile. The tile can be configured as a latch with clear

or set or as a flip-flop with clear or set. Thus, the tiles can

flexibly map logic and sequential gates of a design.

v5.7

1-3

PLUS

ProASIC

Flash Family FPGAs

Routing Resources

The routing structure of ProASIC^PLUSdevices is designed

to provide high performance through a flexible four-

level hierarchy of routing resources: ultra-fast local

resources, efficient long-line resources, high-speed, very

long-line resources, and high performance global

networks.

can in turn access every input of every tile. Active buffers

are inserted automatically by routing software to limit

the loading effects due to distance and fanout.

The high-speed, very long-line resources, which span the

entire device with minimal delay, are used to route very

long or very high fanout nets. (Figure 1-6 on page 1-6).

The ultra-fast local resources are dedicated lines that

allow the output of each tile to connect directly to every

input of the eight surrounding tiles (Figure 1-4).

The high-performance global networks are low-skew,

high fanout nets that are accessible from external pins or

from internal logic (Figure 1-7 on page 1-7). These nets

are typically used to distribute clocks, resets, and other

high fanout nets requiring a minimum skew. The global

networks are implemented as clock trees, and signals can

be introduced at any junction. These can be employed

hierarchically with signals accessing every input on all

tiles.

The efficient long-line resources provide routing for

longer distances and higher fanout connections. These

resources vary in length (spanning 1, 2, or 4 tiles), run

both vertically and horizontally, and cover the entire

ProASIC^PLUSdevice (Figure 1-5 on page 1-5). Each tile can

drive signals onto the efficient long-line resources, which

L

Inputs

L

Ultra-Fast

Local Lines

(connects a tile to the

adjacent tile, I/O buffer,

or memory block)

L

Figure 1-4 • Ultra-Fast Local Resources

1-4

v5.7

PLUS

ProASIC

Flash Family FPGAs

Spans 4 Tiles

L

Spans 2 Tiles

L

Spans 1 Tile

Logic Tile

L

Spans 1 Tile

Spans 2 Tiles

Spans 4 Tiles

L

Logic Cell

Figure 1-5 • Efficient Long-Line Resources

v5.7

1-5

PLUS

ProASIC

Flash Family FPGAs

High Speed Very Long-Line Resouces

PAD RING

SRAM

PAD RING

Figure 1-6 • High-Speed, Very Long-Line Resources

Clock Resources

Clock Trees

The ProASIC^PLUSfamily offers powerful and flexible

control of circuit timing through the use of analog

circuitry. Each chip has two clock conditioning blocks

containing a phase-locked loop (PLL) core, delay lines,

phase shifter (0° and 180°), clock multiplier/dividers, and

all the circuitry needed for the selection and

interconnection of inputs to the global network (thus

providing bidirectional access to the PLL). This permits

the PLL block to drive inputs and/or outputs via the two

global lines on each side of the chip (four total lines).

This circuitry is discussed in more detail in the

"ProASICPLUS Clock Management System" section on

page 1-13.

One of the main architectural benefits of ProASIC^PLUSis

the set of power- and delay-friendly global networks.

ProASIC^PLUSoffers four global trees. Each of these trees

is based on a network of spines and ribs that reach all

the tiles in their regions (Figure 1-7 on page 1-7). This

flexible clock tree architecture allows users to map up to

88 different internal/external clocks in an APA1000

device. Details on the clock spines and various numbers

of the family are given in Table 1-1 on page 1-7.

The flexible use of the ProASIC^PLUSclock spine allows the

designer to cope with several design requirements. Users

implementing clock-resource intensive applications can

easily route external or gated internal clocks using global

routing spines. Users can also drastically reduce delay

penalties and save buffering resources by mapping

critical high fanout nets to spines. For design hints on

using these features, refer to Actel’s Efficient Use of

ProASIC Clock Trees application note.

1-6

v5.7

PLUS

ProASIC

Flash Family FPGAs

High-Performance

Global Network

PAD RING

Top Spine

Global Networks

Global

Pads

Global

Pads

Global Spine

Global Ribs

Bottom Spine

Scope of Spine

(Shaded area

plus local RAMs

and I/Os)

PAD RING

Note: This figure shows routing for only one global path.

Figure 1-7 • High-Performance Global Network

Table 1-1 • Clock Spines

APA075

APA150

APA300

APA450

4

APA600

4

APA750 APA1000

Global Clock Networks (Trees)

Clock Spines/Tree

4

6

4

8

4

8

4

16

4

22

12

14

Total Spines

24

32

48

56

64

88

Top or Bottom Spine Height (Tiles)

Tiles in Each Top or Bottom Spine

Total Tiles

16

24

32

48

64

80

512

3,072

768

6,144

1,024

8,192

1,024

12,288

1,536

21,504

2,048

32,768

2,560

56,320

v5.7

1-7

PLUS

ProASIC

Flash Family FPGAs

Array Coordinates

During many place-and-route operations in Actel’s

Designer software tool, it is possible to set constraints

that require array coordinates.

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination.

Core cell coordinates start at the lower left corner

(represented as (1,1)) or at (1,5) if memory blocks are

present at the bottom. Memory coordinates use the

same system and are indicated in Table 1-2. The memory

coordinates for an APA1000 are illustrated in Figure 1-8.

For more information on how to use constraints, see the

Designer User’s Guide or online help for ProASIC^PLUS

software tools.

Table 1-2 is provided as a reference. The array coordinates

are measured from the lower left (0,0). They can be used in

region constraints for specific groups of core cells, I/Os, and

RAM blocks. Wild cards are also allowed.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

Table 1-2 • Array Coordinates

Logic Tile

Memory Rows

Min.

Max.

Bottom

y

Top

All

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

x

1

y

1

5

x

y

Min.

0,0

Max.

97, 37

96

32

–

(33,33) or (33, 35)

(49,49) or (49, 51)

(69,69) or (69, 71)

(101,101) or (101, 103)

(133,133) or (133, 135)

(165,165) or (165, 167)

128

192

224

256

352

48

–

129, 53

129, 73

193, 73

68

(1,1) or (1,3)

68

100

132

164

225, 105

257, 137

353, 169

Memory

Blocks

(1,169)

(1,167)

(1,165)

(1,164)

(353,169)

(352,167)

(352,165)

(352,164)

Core

(1,5)

(1,3)

(1,1)

(352,5)

(352,3)

(352,1)

(0,0)

(353,0)

Memory

Blocks

Figure 1-8 • Core Cell Coordinates for the APA1000

1-8

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-3 • ProASIC^PLUSI/O Power Supply Voltages

Input/Output Blocks

V_DDP

To meet complex system demands, the ProASIC^PLUS

family offers devices with a large number of user I/O

pins, up to 712 on the APA1000. Table 1-3 shows the

available supply voltage configurations (the PLL block

uses an independent 2.5 V supply on the AVDD and

AGND pins). All I/Os include ESD protection circuits. Each

I/O has been tested to 2000 V to the human body model

(per JESD22 (HBM)).

2.5 V

3.3 V

Input Compatibility

Output Drive

3.3V/2.5V

Signal Control

Six or seven standard I/O pads are grouped with a GND

pad and either a V_DD(core power) or V_DDP(I/O power)

pad. Two reference bias signals circle the chip. One

protects the cascaded output drivers, while the other

creates a virtual V_DDsupply for the I/O ring.

Pull-up

Control

Y

EN

Pad

I/O pads are fully configurable to provide the maximum

flexibility and speed. Each pad can be configured as an

input, an output, a tristate driver, or a bidirectional

buffer (Figure 1-9 and Table 1-4).

A

3.3 V/2.5 V Signal Control Drive

Strength and Slew-Rate Control

Figure 1-9 • I/O Block Schematic Representation

Table 1-4 • I/O Features

Function

Description

I/O pads configured as inputs

•

Selectable 2.5 V or 3.3 V threshold levels

Optional pull-up resistor

Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be

configured as an input only, not a bidirectional buffer. This input type may be slower than

a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros

with an “S” in the standard I/O library have added Schmitt capabilities.

•

3.3 V PCI Compliant (except Schmitt trigger inputs)

Selectable 2.5 V or 3.3 V compliant output signals

2.5 V – JEDEC JESD 8-5

I/O pads configured as outputs

3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3 V PCI compliant

Ability to drive LVTTL and LVCMOS levels

Selectable drive strengths

Selectable slew rates

Tristate

I/O pads configured as bidirectional • Selectable 2.5 V or 3.3 V compliant output signals

buffers

•

2.5 V – JEDEC JESD 8-5

3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3 V PCI compliant

Optional pull-up resistor

Selectable drive strengths

Selectable slew rates

Tristate

v5.7

1-9

PLUS

ProASIC

Flash Family FPGAs

low voltage differential amplifier) and a signal and its

complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).

The LVPECL input pad cell differs from the standard I/O

cell in that it is operated from V_DDonly.

Power-Up Sequencing

While ProASIC^PLUSdevices are live at power-up, the order

of V_DDand V_DDPpower-up is important during system

start-up. V_DDshould be powered up simultaneously with

V_DDPon ProASIC^PLUSdevices. Failure to follow these

guidelines may result in undesirable pin behavior during

system start-up. For more information, refer to Actel’s

Power-Up Behavior of ProASIC^PLUSDevices application

note.

Since it is exclusively an input, it requires no output

signal, output enable signal, or output configuration

bits. As a special high-speed differential input, it also

does not require pull ups. Recommended termination for

LVPECL inputs is shown in Figure 1-10. The LVPECL pad

cell compares voltages on the PPECL (I/P) pad (as

illustrated in Figure 1-11) and the NPECL pad and sends

the results to the global MUX (Figure 1-14 on page 1-14).

This high-speed, low-skew output essentially controls the

clock conditioning circuit.

LVPECL Input Pads

In addition to standard I/O pads and power pads,

ProASIC^PLUSdevices have a single LVPECL input pad on

both the east and west sides of the device, along with

AVDD and AGND pins to power the PLL block. The

LVPECL pad cell consists of an input buffer (containing a

LVPECLs are designed to meet LVPECL JEDEC receiver

standard levels (Table 1-5).

Z ₀= 50 Ω

PPECL

+

From LVPECL Driver

R = 100 Ω

Data

_

Z ₀= 50 Ω

NPECL

Figure 1-10 • Recommended Termination for LVPECL Inputs

Voltage

2.72

2.125

1.49

0.86

Figure 1-11 • LVPECL High and Low Threshold Values

Table 1-5 • LVPECL Receiver Specifications

Symbol

V_IH

Parameter

Input High Voltage

Min.

Max

2.72

2.125

V_DD

Units

1.49

0.86

0.3

V

V_IL

Input Low Voltage

V_ID

Differential Input Voltage

1-10

v5.7

PLUS

ProASIC

Flash Family FPGAs

pins are dedicated for boundary-scan test usage. Actel

recommends that a nominal 20 kΩ pull-up resistor is

added to TDO and TCK pins.

Boundary Scan (JTAG)

ProASIC^PLUSdevices are compatible with IEEE Standard

1149.1, which defines a set of hardware architecture and

mechanisms for cost-effective, board-level testing. The

basic ProASIC^PLUSboundary-scan logic circuit is composed

of the TAP (test access port), TAP controller, test data

registers, and instruction register (Figure 1-12). This

circuit supports all mandatory IEEE 1149.1 instructions

(EXTEST, SAMPLE/PRELOAD and BYPASS) and the

optional IDCODE instruction (Table 1-6).

The TAP controller is a four-bit state machine (16 states)

that operates as shown in Figure 1-13 on page 1-12. The

’1’s and ‘0’s represent the values that must be present at

TMS at a rising edge of TCK for the given state transition

to occur. IR and DR indicate that the instruction register

or the data register is operating in that state.

ProASIC^PLUSdevices have to be programmed at least

once for complete boundary-scan functionality to be

available. Prior to being programmed, EXTEST is not

available. If boundary-scan functionality is required prior

to programming, refer to online technical support on the

Actel website and search for ProASIC^PLUSBSDL.

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI and TDO

(test data input and output), TMS (test mode selector)

and TRST (test reset input). TMS, TDI and TRST are

equipped with pull-up resistors to ensure proper

operation when no input data is supplied to them. These

I/O

Test Data

Registers

Bypass Register

Instruction

Register

TAP

Controller

Device

Logic

I/O

Figure 1-12 • ProASIC^PLUSJTAG Boundary Scan Test Logic Circuit

Table 1-6 • Boundary-Scan Opcodes

Hex Opcode

EXTEST

00

01

0F

CLAMP

BYPASS

05

FF

SAMPLE/PRELOAD

IDCODE

v5.7

1-11

PLUS

ProASIC

Flash Family FPGAs

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain high for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASIC^PLUSdevices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

register needs to be accessed in a device. This speeds up

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (lowest significant byte (LSB), ID number,

part number and version). The boundary-scan register

observes and controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output, and control

ports of an I/O buffer to capture and load data into the

register to control or observe the logic state of each I/O.

Test-Logic

1

Reset

0

1

0

1

0

1

Run-Test/

Idle

Select-DR-

Scan

Select-IR-

Scan

0

Capture-DR

0

Capture-IR

0

1

Shift-IR

1

Shift-DR

1

Exit-DR

Exit-IR

0

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

0

1

Figure 1-13 • TAP Controller State Diagram

1-12

v5.7

PLUS

ProASIC

Flash Family FPGAs

follows (Figure 1-15 on page 1-15, Table 1-7 on page 1-

15, and Table 1-8 on page 1-16):

Timing Control and

Characteristics

Global A (secondary clock)

•

Output from Global MUX A

PLUS

ProASIC

Clock Management System

•

Conditioned version of PLL output (f_OUT) – delayed

or advanced

ProASIC^PLUSdevices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASIC^PLUSfamily contains two phase-locked loop (PLL)

blocks which perform the following functions:

•

Divided version of either of the above

Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)¹

•

Clock Phase Adjustment via Programmable Delay

(250 ps steps from –7 ns to +8 ns)

Global B

•

Output from Global MUX B

Delayed or advanced version of f_OUT

Divided version of either of the above

Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)²

•

Clock Skew Minimization

Clock Frequency Synthesis

Each PLL has the following key features:

•

Input Frequency Range (f_IN) = 1.5 to 180 MHz

Feedback Frequency Range (f_VCO) = 24 to 180 MHz

Output Frequency Range (f_OUT) = 8 to 180 MHz

Output Phase Shift = 0 ° and 180 °

Functional Description

Each PLL block contains four programmable dividers as

shown in Figure 1-14 on page 1-14. These allow

frequency scaling of the input clock signal as follows:

Output Duty Cycle = 50%

Low Output Jitter (max at 25°C)

•

The n divider divides the input clock by integer

factors from 1 to 32.

–

f

_VCO<10 MHz. Jitter 1% or better

10 MHz < f_VCO< 60 MHz. Jitter 2% or better

_VCO> 60 MHz. Jitter 1% or better

•

The m divider in the feedback path allows

multiplication of the input clock by integer factors

ranging from 1 to 64.

f

Note: Jitter(ps) = Jitter(%)* period

•

The two dividers together can implement any

combination of multiplication and division

resulting in a clock frequency between 24 and 180

MHz exiting the PLL core. This clock has a fixed

50% duty cycle.

The output frequency of the PLL core is given by

the formula EQ 1-1 (f_REFis the reference clock

frequency):

For Example:

Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps

•

Maximum Acquisition = 80 µs for f_VCO> 40 MHz

Time

= 30 µs for f_VCO< 40 MHz

Low Power Consumption – 6.9 mW (max – analog

f

_OUT= f_REF* m/n

supply) + 7.0μW/MHz (max – digital supply)

EQ 1-1

Physical Implementation

•

The third and fourth dividers (u and v) permit the

signals applied to the global network to each be

further divided by integer factors ranging from 1

to 4.

Each side of the chip contains a clock conditioning circuit

based on a 180 MHz PLL block (Figure 1-14 on page 1-

14). Two global multiplexed lines extend along each side

of the chip to provide bidirectional access to the PLL on

that side (neither MUX can be connected to the opposite

side's PLL). Each global line has optional LVPECL input

pads (described below). The global lines may be driven

by either the LVPECL global input pad or the outputs

from the PLL block, or both. Each global line can be

driven by a different output from the PLL. Unused global

pins can be configured as regular I/Os or left

unconnected. They default to an input with pull-up. The

two signals available to drive the global networks are as

The implementations shown in EQ2 and EQ3 enable the

user to define a wide range of frequency multiplier and

divisors.

f_GLB= m/(n*u)

EQ 1-2

f_GLA= m/(n*v)

EQ 1-3

1. This mode is available through the delay feature of the Global MUX driver.

v5.7

1-13

PLUS

ProASIC

Flash Family FPGAs

enable the user to define a wide range of frequency

multipliers and divisors. The clock conditioning circuit can

advance or delay the clock up to 8 ns (in increments of

0.25 ns) relative to the positive edge of the incoming

reference clock. The system also allows for the selection of

output frequency clock phases of 0° and 180°.

signals relative to other signals to assist in the control of

input set-up times. Not all possible combinations of input

and output modes can be used. The degrees of freedom

available in the bidirectional global pad system and in

the clock conditioning circuit have been restricted. This

avoids unnecessary and unwieldy design kit and software

work.

Prior to the application of signals to the rib drivers, they

pass through programmable delay units, one per global

network. These units permit the delaying of global

V

AVDD AGND

GND

DD

GLA

GLB

Global MUX B OUT

Input Pins to the PLL

See Figure 1-15

Clock Conditioning

Circuitry

(Top level view)

External Feedback Signal

Global MUX A OUT

27

Flash

Configuration Bits

Dynamic

+

on page 1-14

4

-

Configuration Bits

8

Clock Conditioning Circuitry Detailed Block Diagram

CLK

Bypass Primary

OBMUX[2:0]

1

P+

P-

FIVDIV[4:0]

7

DLYB[1:0]

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

0

÷n

6

5

4

GLB

180˚

0˚

PLL Core

÷u

÷m

OBDIV[1:0]

FBDIV[5:0]

2

Clock from Core

(GLINT mode)

1

2

Delay Line

0.25 ns to

4.00 ns,

16 steps,

0.25 ns

increments

0

3

Deskew

Delay

2.95 ns

1

OADIV[1:0]

3

DLYA[1:0]

Delay Line 0.0 ns, 0.25 ns,

0.50 ns and 4.00 ns

XDLYSEL

2

1

÷v

EXTFB

FBDLY[3:0]

GLA

FBSEL[1:0]

OAMUX[1:0]

CLKA

Bypass Secondary

Clock from Core

(GLINT mode)

Notes:

1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.

2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.

3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.

Figure 1-14 • PLL Block – Top-Level View and Detailed PLL Block Diagram

1-14

v5.7

PLUS

ProASIC

Flash Family FPGAs

Package Pins

Physical I/O

Buffers

Global MUX

Configuration Tile

GL

Std. Pad Cell

PECL Pad Cell

Global MUX B

OUT

NPECL

PPECL

External

Feedback

Global MUX A

OUT

GLMX

GL

Std. Pad Cell

Configuration Tile

CORE

Legend

Physical Pin

DATA Signals to the Global MUX

DATA Signals to the Core

Control Signals to the Global MUX

DATA Signals to the PLL Block

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.

Figure 1-15 • Input Connectors to ProASIC^PLUSClock Conditioning Circuitry

Table 1-7 • Clock-Conditioning Circuitry MUX Settings

MUX

Datapath

Comments

FBSEL

1

Internal Feedback

2

Internal Feedback and Advance Clock Using FBDLY

External Feedback (EXTFB)

–0.25 to –4 ns in 0.25 ns increments

3

XDLYSEL

0

Feedback Unchanged

Deskew feedback by advancing clock by system delay

GLB

1

Fixed delay of -2.95 ns

OBMUX

0

Primary bypass, no divider

Primary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

Reserved

1

2

+0.25 to +4 ns in 0.25 ns increments

4

5

6

Phase Shift Clock by +180°

Reserved

7

OAMUX

GLA

0

1

2

3

Secondary bypass, no divider

Secondary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

+0.25 to +4 ns in 0.25 ns increments

v5.7

1-15

PLUS

ProASIC

Flash Family FPGAs

Table 1-8 • Clock-Conditioning Circuitry Delay-Line

Sample Implementations

Settings

Delay Line

Delay Value (ns)

Frequency Synthesis

DLYB

0

Figure 1-16 on page 1-17 illustrates an example where

the PLL is used to multiply a 33 MHz external clock up to

133 MHz. Figure 1-17 on page 1-17 uses two dividers to

synthesize a 50 MHz output clock from a 40 MHz input

reference clock. The input frequency of 40 MHz is

multiplied by five and divided by four, giving an output

clock (GLB) frequency of 50 MHz. When dividers are

used, a given ratio can be generated in multiple ways,

allowing the user to stay within the operating frequency

ranges of the PLL. For example, in this case the input

divider could have been two and the output divider also

two, giving us a division of the input frequency by four

to go with the feedback loop division (effective

multiplication) by five.

1

+0.25

+0.50

+4.0

2

3

DLYA

0

1

2

3

0

+0.25

+0.50

+4.0

Lock Signal

An active-high Lock signal (added via the SmartGen PLL

development tool) indicates that the PLL has locked to

the incoming clock signal. The PLL will acquire and

maintain lock even when there is jitter on the incoming

clock signal. The PLL will maintain lock with an input

jitter up to 5% of the input period, with a maximum of

5 ns. Users can employ the Lock signal as a soft reset of

the logic driven by GLB and/or GLA. Note if F_INis not

within specified frequencies, then both the F_OUTand lock

signal are indeterminate.

Adjustable Clock Delay

Figure 1-18 on page 1-18 illustrates the delay of the

input clock by employing one of the adjustable delay

lines. This is easily done in ProASIC^PLUSby bypassing the

PLL core entirely and using the output delay line. Notice

also that the output clock can be effectively advanced

relative to the input clock by using the delay line in the

feedback path. This is shown in Figure 1-19 on page 1-18.

PLL Configuration Options

Clock Skew Minimization

The PLL can be configured during design (via Flash-

configuration bits set in the programming bitstream) or

dynamically during device operation, thus eliminating

the need to reprogram the device. The dynamic

configuration bits are loaded into a serial-in/parallel-out

shift register provided in the clock conditioning circuit.

The shift register can be accessed either from user logic

within the device or via the JTAG port. Another option is

internal dynamic configuration via user-designed

hardware. Refer to Actel's ProASIC^PLUSPLL Dynamic

Reconfiguration Using JTAG application note for more

information.

Figure 1-20 on page 1-19 indicates how feedback from

the clock network can be used to create minimal skew

between the distributed clock network and the input

clock. The input clock is fed to the reference clock input

of the PLL. The output clock (GLA) feeds a clock network.

The feedback input to the PLL uses a clock input delayed

by a routing network. The PLL then adjusts the phase of

the input clock to match the delayed clock, thus

providing nearly zero effective skew between the two

clocks. Refer to Actel's Using ProASIC^PLUSClock

Conditioning Circuits application note for more

information.

For information on the clock conditioning circuit, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note.

1-16

v5.7

PLUS

ProASIC

Flash Family FPGAs

÷1

÷n

Global MUX B OUT

33 MHz

180

˚

GLB

D

PLL Core

÷u

÷1

0

˚

133 MHz

÷m

÷4

D

External Feedback

Global MUX A OUT

÷v

D

GLA

Figure 1-16 • Using the PLL 33 MHz In, 133 MHz Out

÷4

÷n

180

˚

Global MUX B OUT

40 MHz

GLB

D

PLL Core

÷u

÷1

0

50 MHz

˚

÷m

÷5

D

External Feedback

Global MUX A OUT

÷v

D

GLA

Figure 1-17 • Using the PLL 40 MHz In, 50 MHz Out

v5.7

1-17

PLUS

ProASIC

Flash Family FPGAs

÷1

÷n

Global MUX B OUT

180

˚

GLB

D

133 MHz

PLL Core

÷u

÷1

133 MHz

÷m

÷1

0

˚

D

External Feedback

Global MUX A OUT

÷v

D

GLA

Figure 1-18 • Using the PLL to Delay the Input Clock

÷1

÷n

180

˚

Global MUX B OUT

133 MHz

GLB

D

PLL Core

÷u

÷1

0

133 MHz

˚

÷m

÷1

D

External Feedback

Global MUX A OUT

÷v

D

GLA

Figure 1-19 • Using the PLL to Advance the Input Clock

1-18

v5.7

PLUS

ProASIC

Flash Family FPGAs

On chip

Off chip

/1

÷n

180˚

0˚

Global MUX B

OUT

GL

B

D

PLL Core

133 MHz

÷u

÷m

/1

D

External

Feedback

D

133 MHz

GL

A

÷v

D

Global MUX A

OUT

Q

^SETD

Reference

clock

CLR

Figure 1-20 • Using the PLL for Clock Deskewing

v5.7

1-19

PLUS

ProASIC

Flash Family FPGAs

Logic Tile Timing Characteristics

Timing Derating

Timing characteristics for ProASIC^PLUSdevices fall into

three categories: family dependent, device dependent,

and design dependent. The input and output buffer

characteristics are common to all ProASIC^PLUSfamily

members. Internal routing delays are device dependent.

Design dependency means that actual delays are not

determined until after placement and routing of the

user’s design are complete. Delay values may then be

determined by using the Timer utility or by performing

simulation with post-layout delays.

Since ProASIC^PLUSdevices are manufactured with a

CMOS process, device performance will vary with

temperature, voltage, and process. Minimum timing

parameters reflect maximum operating voltage,

minimum operating temperature, and optimal process

variations. Maximum timing parameters reflect minimum

operating voltage, maximum operating temperature,

and worst-case process variations (within process

specifications). The derating factors shown in Table 1-9

should be applied to all timing data contained within

this datasheet.

All timing numbers listed in this datasheet represent

sample timing characteristics of ProASIC^PLUSdevices.

Actual timing delay values are design-specific and can be

derived from the Timer tool in Actel’s Designer software

after place-and-route.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most

timing-critical paths. Critical nets are determined by net

property assignment prior to place-and-route. Refer to

the Actel Designer User’s Guide or online help for details

on using constraints.

Table 1-9 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_DD= 2.3 V)

–55°C

0.84

–40°C

0.86

0°C

0.91

0.87

0.83

25°C

0.94

0.90

0.86

70°C

1.00

0.95

0.91

85°C

1.02

0.98

0.93

110°C

1.05

125°C

1.13

135°C

1.18

150°C

1.27

2.3 V

2.5 V

2.7 V

Notes:

0.81

0.82

1.01

1.09

1.13

1.21

0.77

0.79

0.96

1.04

1.08

1.16

1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 175°C.

2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.

1-20

v5.7

PLUS

ProASIC

Flash Family FPGAs

PLL Electrical Specifications

Parameter

Value

Notes

Frequency Ranges

Reference Frequency f_IN(min.)

Reference Frequency f_IN(max.)

OSC Frequency f_VCO(min.)

OSC Frequency f_VCO(max.)

Clock Conditioning Circuitry f_OUT(min.)

Clock Conditioning Circuitry f_OUT(max.)

Long Term Jitter Peak-to-Peak Max.*

Temperature

1.5 MHz

180 MHz

24 MHz

180 MHz

6 MHz

Clock conditioning circuitry (min.) lowest input frequency

Clockconditioning circuitry (max.) highest input frequency

Lowest output frequency voltage controlled oscillator

Highest output frequencyvoltage controlledoscillator

Lowest output frequency clock conditioning circuitry

Highest output frequency clock conditioning circuitry

180 MHz

Frequency MHz

f

_VCO<10

10<f_VCO<60 f_VCO>60

25°C (or higher)

1ꢀ

2ꢀ

1ꢀ

Jitter(ps) = Jitter(ꢀ)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

1.5ꢀ

2.5ꢀ

3.5ꢀ

1ꢀ

–40°C

–55°C

Acquisition Time from Cold Start

Acquisition Time (max.)

Power Consumption

Analog Supply Power (max.*)

Digital Supply Current (max.)

Duty Cycle

30 μs

80 μs

f_VCO≤ 40 MHz

f_VCO> 40 MHz

6.9 mW per PLL

7 μW/MHz

50ꢀ 0.5ꢀ

5ꢀ input period (max. 5 ns)

Maximum jitter allowable on an input clock to

acquire and maintain lock.

Input Jitter Tolerance

Note: *High clock frequencies (>60 MHz) under typical setup conditions

v5.7

1-21

PLUS

ProASIC

Flash Family FPGAs

®

User Security

Embedded Memory Configurations

ProASIC^PLUSdevices have FlashLock protection bits that,

once programmed, block the entire programmed

contents from being read externally. Please refer to

Table 1-10 for details on the number of bits in the key for

each device. If locked, the user can only reprogram the

device employing the user-defined security key. This

protects the device from being read back and duplicated.

Since programmed data is stored in nonvolatile memory

cells (actually very small capacitors) rather than in the

wiring, physical deconstruction cannot be used to

compromise data. This type of security breach is further

discouraged by the placement of the memory cells

beneath the four metal layers (whose removal cannot be

accomplished without disturbing the charge in the

capacitor). This is the highest security provided in the

industry. For more information, refer to Actel’s Design

Security in Nonvolatile Flash and Antifuse FPGAs white

paper.

The embedded memory in the ProASIC^PLUSfamily

provides great configuration flexibility (Table 1-11). Each

ProASIC^PLUSblock is designed and optimized as a two-

port memory (one read, one write). This provides 198

kbits of two-port and/or single port memory in the

APA1000 device.

Each memory block can be configured as FIFO or SRAM,

with independent selection of synchronous or

asynchronous read and write ports (Table 1-12).

Additional characteristics include programmable flags as

well as parity checking and generation. Figure 1-21 on

page 1-24 and Figure 1-22 on page 1-25 show the block

diagrams of the basic SRAM and FIFO blocks. Table 1-13

on page 1-24 and Table 1-14 on page 1-25 describe

memory block SRAM and FIFO interface signals,

respectively. A single memory block is designed to

operate at up to 150 MHz (standard speed grade typical

conditions). Each block is comprised of 256 9-bit words

(one read port, one write port). The memory blocks may

be cascaded in width and/or depth to create the desired

memory organization. (Figure 1-23 on page 1-26). This

provides optimal bit widths of 9 (one block), 18, 36, and

72, and optimal depths of 256, 512, 768, and 1,024. Refer

to Actel’s SmartGen User’s Guide for more information.

Table 1-10 • Flashlock Key Size by Device

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Key Size

79 bits

Figure 1-24 on page 1-26 gives an example of optimal

memory usage. Ten blocks with 23,040 bits have been

used to generate three arrays of various widths and

depths. Figure 1-25 on page 1-26 shows how RAM blocks

can be used in parallel to create extra read ports. In this

example, using only 10 of the 88 available blocks of the

APA1000 yields an effective 6,912 bits of multiple port

RAM. The Actel SmartGen software facilitates building

wider and deeper memory configurations for optimal

memory usage.

119 bits

167 bits

191 bits

263 bits

Embedded Memory Floorplan

The embedded memory is located across the top and

bottom of the device in 256x9 blocks (Figure 1-1 on page

1-2). Depending on the device, up to 88 blocks are

available to support a variety of memory configurations.

Each block can be programmed as an independent

memory array or combined (using dedicated memory

routing resources) to form larger, more complex memory

configurations. A single memory configuration could

include blocks from both the top and bottom memory

locations.

Table 1-11 • ProASIC^PLUSMemory Configurations by Device

Maximum Width

Maximum Depth

Device

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Bottom

Top

12

16

24

28

32

44

D

W

D

W

0

256

108

144

216

252

288

396

1,536

2,048

3,072

3,584

4,096

5,632

9

0

16

24

28

32

44

1-22

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-12 • Basic Memory Configurations

Write Access

Asynchronous

Type

RAM

FIFO

Read Access

Asynchronous

Parity

Library Cell Name

RAM256x9AA

Checked

Asynchronous

Synchronous

Asynchronous

Synchronous

Asynchronous

Generated

Checked

RAM256x9AAP

RAM256x9AST

RAM256x9ASTP

RAM256x9ASR

RAM256x9ASRP

RAM256x9SA

RAM256xSAP

RAM256x9SST

RAM256x9SSTP

RAM256x9SSR

RAM256x9SSRP

FIFO256x9AA

FIFO256x9AAP

FIFO256x9AST

FIFO256x9ASTP

FIFO256x9ASR

FIFO256x9ASRP

FIFO256x9SA

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

FIFO256x9SAP

FIFO256x9SST

FIFO256x9SSTP

FIFO256x9SSR

FIFO256x9SSRP

Synchronous Transparent

Synchronous Pipelined

Generated

Checked

Generated

v5.7

1-23

PLUS

ProASIC

Flash Family FPGAs

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

SRAM

(256x9)

SRAM

(256x9)

WRB

WBLKB

RDB

RBLKB

RCLKS

RDB

RBLKB

RCLKS

WRB

Sync Write

and

Sync Read

Ports

Async Write

and

Async Read

Ports

WCLKS

WBLKB

WPE

RPE

WPE

PARODD

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

SRAM

(256x9)

SRAM

(256x9)

WRB

WBLKB

WRB

WBLKB

RDB

RBLKB

RDB

RBLKB

Sync Write

and

Async Read

Ports

Async Write

and

Sync Read

Ports

WCLKS

WPE

RCLKS

RPE

WPE

PARODD

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not

consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when

RAM blocks are cascaded and are automatically inserted by the software tools.

Figure 1-21 • Example SRAM Block Diagrams

Table 1-13 • Memory Block SRAM Interface Signals

Description

Write clock used on synchronization on write side

Read clock used on synchronization on read side

Read address

SRAM Signal

WCLKS

RCLKS

Bits

1

In/Out

In

1

In

RADDR<0:7>

RBLKB

8

In

1

In

Read block select (active Low)

RDB

1

In

Read pulse (active Low)

WADDR<0:7>

WBLKB

8

In

Write address

1

In

Write block select (active Low)

DI<0:8>

WRB

9

In

Input data bits <0:8>, <8> can be used for parity In

Write pulse (active Low)

1

In

DO<0:8>

RPE

9

Out

In

Output data bits <0:8>, <8> can be used for parity Out

Read parity error (active High)

1

WPE

1

Write parity error (active High)

PARODD

1

Selects Odd parity generation/detect when High, Even parity when Low

Note: Not all signals shown are used in all modes.

1-24

v5.7

PLUS

ProASIC

Flash Family FPGAs

DI<0:8>

LEVEL<0:7>

LGDEP<0:2>

DI<0:8>

LEVEL<0:7>

LGDEP<0:2>

DO <0:8>

WPE

FIFO

(256x9)

FIFO

(256x9)

WPE

RPE

WRB

WBLKB

WRB

WBLKB

RPE

FULL

EMPTY

FULL

EMPTY

Sync Write

and

Sync Read

Ports

Sync Write

and

Async Read

Ports

RDB

RBLKB

RDB

RBLKB

EQTH

PARODD

GEQTH

WCLKS

RESET

RCLKS

RESET

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DO <0:8>

WPE

DO <0:8>

FIFO

(256x9)

FIFO

(256x9)

WRB

WBLKB

WRB

WBLKB

WPE

RPE

FULL

EMPTY

Async Write

and

Sync Read

Ports

Async Write

and

Async Read

Ports

RDB

RBLKB

EMPTY

EQTH

RDB

PARODD

RBLKB

GEQTH

RESET

RCLKS

GEQTH

PARODD

RESET

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not

consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when

RAM blocks are cascaded and are automatically inserted by the software tools.

Figure 1-22 • Basic FIFO Block Diagrams

Table 1-14 • Memory Block FIFO Interface Signals

FIFO Signal

WCLKS

Bits

1

In/Out

In

Description

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active Low)

RCLKS

1

In

LEVEL <0:7>

RBLKB

8

In

1

In

RDB

1

In

Read pulse (active Low)

RESET

1

In

Reset for FIFO pointers (active Low)

WBLKB

1

In

Write block select (active Low)

DI<0:8>

WRB

9

In

Input data bits <0:8>, <8> will be generated parity if PARGEN is true

Write pulse (active Low)

1

In

FULL, EMPTY

EQTH, GEQTH

2

Out

FIFO flags. FULL prevents write and EMPTY prevents read

2

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

9

1

3

1

Out

In

Output data bits <0:8>. <8> will be parity output if PARGEN is true.

Read parity error (active High)

WPE

Write parity error (active High)

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

LGDEP <0:2>

PARODD

In

Parity generation/detect – Even when Low, Odd when High

v5.7

1-25

PLUS

ProASIC

Flash Family FPGAs

9

Word Width

9

256

9

256

9

256

9

256

9

256

Word

Depth

256

88 blocks

Figure 1-23 • APA1000 Memory Block Architecture

Word Width

9

Word

256

256 256

Depth

256 words x 18 bits, 1 read, 1 write

256

512 words x 18 bits, 1 read, 1 write

256

1,024 words x 9 bits, 1 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 23,040

Figure 1-24 • Example Showing Memory Arrays with Different Widths and Depths

Word Width

9

Write Port

9

99

9

Word

Depth

256 256

256 256 256 256

Read Ports

256 words x 9 bits, 2 read, 1 write

Read Ports

512 words x 9 bits, 4 read, 1 write

Total Memory Blocks Used = 10

Total Memory Bits = 6,912

Figure 1-25 • Multi-Port Memory Usage

1-26

v5.7

PLUS

ProASIC

Flash Family FPGAs

Design Environment

The ProASIC^PLUSfamily of FPGAs is fully supported by

both Actel's Libero^®Integrated Design Environment

(IDE) and Designer FPGA Development software. Actel

Libero IDE is an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log

files, and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment (see Actel’s

website for more information about Libero IDE). Libero

IDE includes Synplify^®AE from Synplicity®, ViewDraw^®

AE from Mentor Graphics^®, ModelSim^®HDL Simulator

from Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, PALACE™ AE Physical Synthesis from

Magma, and Designer software from Actel.

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel’s back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the SmartGen

macro builder, which easily creates popular and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

PALACE is an effective tool when designing with

ProASIC^PLUS. PALACE AE Physical Synthesis from Magma

takes an EDIF netlist and optimizes the performance of

ProASIC^PLUSdevices through a physical placement-driven

process, ensuring that timing closure is easily achieved.

ISP

The user can generate *.bit or *.stp programming files

from the Designer software and can use these files to

program a device.

ProASIC^PLUSdevices can be programmed in-system. For

more information on ISP of ProASIC^PLUSdevices, refer to

the In-System Programming ProASIC^PLUSDevices and

Performing Internal In-System Programming Using Actel’s

ProASIC^PLUSDevices application notes. Prior to being

programmed for the first time, the ProASIC^PLUSdevice I/Os

are in a tristate condition with the pull-up resistor option

enabled.

Actel's Designer software is a place-and-route tool that

provides a comprehensive suite of back-end support

tools for FPGA development. The Designer software

includes the following:

•

Timer – a world-class integrated static timing

analyzer and constraints editor that support

timing-driven place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and

editor

•

SmartPower – allows the designer to quickly

estimate the power consumption of a design

PinEditor – a graphical application for editing pin

assignments and I/O attributes

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

v5.7

1-27

PLUS

ProASIC

Flash Family FPGAs

Related Documents

Application Notes

Efficient Use of ProASIC Clock Trees

http://www.actel.com/documents/A500K_Clocktree_AN.pdf

I/O Features in ProASIC^PLUSFlash FPGAs

http://www.actel.com/documents/APA_LVPECL_AN.pdf

Power-Up Behavior of ProASIC^PLUSDevices

http://www.actel.com/documents/APA_PowerUp_AN.pdf

ProASIC^PLUSPLL Dynamic Reconfiguration Using JTAG

http://www.actel.com/documents/APA_PLLdynamic_AN.pdf

Using ProASIC^PLUSClock Conditioning Circuits

http://www.actel.com/documents/APA_PLL_AN.pdf

In-System Programming ProASIC^PLUSDevices

http://www.actel.com/documents/APA_External_ISP_AN.pdf

Performing Internal In-System Programming Using Actel’s ProASIC^PLUSDevices

http://www.actel.com/documents/APA_Microprocessor_AN.pdf

ProASIC^PLUSRAM and FIFO Blocks

http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity_WP.pdf

User’s Guide

Designer User’s Guide

http://www.actel.com/documents/designer_UG.pdf

SmartGen Cores Reference Guide

http://www.actel.com/documents/gen_refguide_ug.pdf

ProASIC and ProASIC^PLUSMacro Library Guide

http://www.actel.com/documents/pa_libguide_UG.pdf

Additional Information

The following link contains additional information on ProASIC^PLUSdevices.

http://www.actel.com/products/proasicplus/default.aspx

1-28

v5.7

PLUS

ProASIC

Flash Family FPGAs

the maximum allowable temperature on the active

surface of the IC and is 110° C. P is defined as:

Package Thermal Characteristics

The ProASIC^PLUSfamily is available in several package

types with a range of pin counts. Actel has selected

packages based on high pin count, reliability factors, and

superior thermal characteristics.

T_J– T_A

P = ------------------

Θ_ja

EQ 1-4

Thermal resistance defines the ability of a package to

conduct heat away from the silicon, through the

package to the surrounding air. Junction-to-ambient

thermal resistance is measured in degrees Celsius/Watt

Θ

is a function of the rate (in linear feet per minute

ja

(lfpm)) of airflow in contact with the package. When the

estimated power consumption exceeds the maximum

allowed power, other means of cooling, such as

increasing the airflow rate, must be used. The maximum

power dissipation allowed for a Military temperature

and is represented as Theta ja (Θ ). The lower the

ja

thermal resistance, the more efficiently a package will

dissipate heat.

device is specified as a function of Θ . The absolute

maximum junction temperature is 150°C.

jc

A package’s maximum allowed power (P) is a function of

maximum junction temperature (T_J), maximum ambient

operating temperature (T_A), and junction-to-ambient

The calculation of the absolute maximum power

dissipation allowed for

application is illustrated in the following example for a

456-pin PBGA package:

a

Military temperature

thermal resistance Θ . Maximum junction temperature is

ja

Max. junction temp. (°C) – Max. case temp. (°C) 150°C – 125°C

------------------------------------------------------------------------------------------------------------------------ -------------------------------------

Maximum Power Allowed =

=

= 8.333W

θ_jc(°C/W)

3.0°C/W

EQ 1-5

Table 1-15 • Package Thermal Characteristics

θ_ja

1.0 m/s

2.5 m/s

Plastic Packages

Pin Count

θ_jc

14.0

11.0

8.0

3.8

3.0

3.8

3.2

2.4

1.8

2.0

6.5

Still Air

33.5

26.1

16.2

15.6

26.9

26.6

18.0

20.5

16.4

13.6

12.0

22.0

17.9

8.9

200 ft./min.

500 ft./min.

Units

Thin Quad Flat Pack (TQFP)

Plastic Quad Flat Pack (PQFP)¹

PQFP with Heat spreader²

100

144

208

456

144

256

484

676

896

1152

208

352

624

27.4

28.0

22.5

13.3

12.5

22.9

22.8

14.7

17.0

13.0

10.4

8.9

25.0

25.7

20.8

11.9

11.6

21.5

13.6

15.9

12.0

9.4

°C/W

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

Fine Pitch Ball Grid Array (FBGA)³

Fine Pitch Ball Grid Array (FBGA)⁴

Fine Pitch Ball Grid Array (FBGA)

Ceramic Quad Flat Pack (CQFP)

Ceramic Column Grid Array (CCGA/LGA)

Notes:

7.9

19.8

16.1

8.5

18.0

14.7

8.0

1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300

2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000

3. Depopulated Array

4. Full array

v5.7

1-29

PLUS

ProASIC

Flash Family FPGAs

Calculating Typical Power Dissipation

ProASIC^PLUSdevice power is calculated with both a static and an active component. The active component is a function

of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following

formula:

Total Power Consumption—P

total

P_total= P_dc+ P_ac

where:

P_dc

=

7 mW for the APA075

8 mW for the APA150

11 mW for the APA300

12 mW for the APA450

12 mW for the APA600

13 mW for the APA750

19 mW for the APA1000

P

_dcincludes the static components of P_VDDP+ P_VDD+ P_AVDD

P_clock+ P_storage+ P_logic+ P_outputs+ P_inputs+ P_pll+ P_memory

Global Clock Contribution—P

P_ac

=

clock

P_clock, the clock component of power dissipation, is given by the piece-wise model:

for R < 15000 the model is: (P1 + (P2*R) - (P7*R2)) * Fs (lightly-loaded clock trees)

for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)

where:

100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

P1

P2

=

1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the

clock

0.00003 µW/MHz is a correction factor for partially-loaded clock trees

P7

=

6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

=

P10

P11

0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of

the clock

=

the number of storage tiles clocked by this clock

the clock frequency

R

=

Fs

Storage-Tile Contribution—P

storage

P_storage, the storage-tile (Register) component of AC power dissipation, is given by

P_storage= P5 * ms * Fs

where:

P5

=

1.1 μW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate. The

maximum output toggling rate is Fs/2.

ms

Fs

=

the number of storage tiles (Register) switching during each Fs cycle

the clock frequency

1-30

v5.7

PLUS

ProASIC

Flash Family FPGAs

Logic-Tile Contribution—P

logic

P_logic, the logic-tile component of AC power dissipation, is given by

P_logic= P3 * mc * Fs

where:

P3

=

1.4 μW/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The

maximum output toggling rate is Fs/2.

mc

Fs

=

the number of logic tiles switching during each Fs cycle

the clock frequency

I/O Output Buffer Contribution—P

outputs

P_outputs, the I/O component of AC power dissipation, is given by

P_outputs= (P4 + (C_load* V_DDP²)) * p * Fp

where:

P4

=

326 μW/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output

frequency. This is the total I/O current V_DDP

.

C_load

p

Fp

=

the output load

the number of outputs

the average output frequency

I/O Input Buffer's Buffer Contribution—P

inputs

The input’s component of AC power dissipation is given by

P_inputs= P8 * q * Fq

where:

P8

=

29 μW/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input

frequency.

q

=

the number of inputs

Fq

the average input frequency

PLL Contribution—P

pll

P_pll= P9 * N_pll

where:

P9

=

7.5 mW. This value has been estimated at maximum PLL clock frequency.

number of PLLs used

N_Pll

RAM Contribution—P

memory

Finally, P_memory, the memory component of AC power consumption, is given by

P_memory= P6 * N_memory* F_memory* E_memory

where:

P6

N_memory

=

175 μW/MHz is the average power consumption of a memory block per MHz of the clock

the number of RAM/FIFO blocks

(1 block = 256 words * 9 bits)

F_memory

E_memory

=

the clock frequency of the memory

the average number of active blocks divided by the total number of blocks (N) of the memory.

•

Typical values for E_memorywould be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8,

9, 16, and 32 memory configuration

•

In addition, an application-dependent component to E_memorycan be considered. For

example, for a 1kx8 memory configuration using only 1 cycle out of 2, E_memory= 1/4*1/2 = 1/8

v5.7

1-31

PLUS

ProASIC

Flash Family FPGAs

The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.

This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as

follows:

P

clock

Fs = 10 MHz

= 13,440

=> P_clock= (P1 + (P2*R) - (P7*R²)) * Fs = 121.5 mW

R

P

storage

ms

= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)

=> P_storage= P5 * ms * Fs = 147.8 mW

P

logic

mc = 0 (no logic tiles in this shift register)

=> P_logic= 0 mW

P

outputs

C_load

=

40 pF

3.3 V

24

V_DDP

p

Fp

5 MHz

=> P_outputs= (P4 + (C_load* V_DDP²)) * p * Fp = 91.4 mW

P

inputs

q

=

1

Fq

10 MHz

=> P_inputs= P8 * q * Fq = 0.3 mW

P

memory

N_memory

=

0 (no RAM/FIFO blocks in this shift register)

=> P_memory= 0 mW

P_ac

=> 361 mW

P_total

P_dc+ P_ac= 374 mW (typical)

1-32

v5.7

PLUS

ProASIC

Flash Family FPGAs

Operating Conditions

Standard and –F parts are the same unless otherwise noted. All –F parts are only available as commercial.

Table 1-16 • Absolute Maximum Ratings*

Parameter

Condition

Minimum

–0.3

–1.0

10

Maximum

3.0

Units

Supply Voltage Core (V_DD

)

V

Supply Voltage I/O Ring (V_DDP

)

4.0

DC Input Voltage

V_DDP+ 0.3

V_DDP+ 1.0

V

PCI DC Input Voltage

V

PCI DC Input Clamp Current (absolute)

LVPECL Input Voltage

GND

V_IN< –1 or V_IN= V_DDP+ 1 V

mA

V

–0.3

0

V_DDP+ 0.5

0

V

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

Recommended Operating Conditions.

Table 1-17 • Programming, Storage, and Operating Limits

Storage Temperature Operating

T_JMax.

Junction

Product Grade

Commercial

Industrial

Programming Cycles (min.)

Program Retention (min.)

20 years

Min.

–55°C

–65°C

Max.

110°C

150°C

Temperature

500

100

110°C

20 years

110°C

Military

Refer to Table 1-18 on page 1-34

150°C

MIL-STD-883

150°C

Example – the ambient temperature of a system cycles

between 100°C (25% of the time) and 50°C (75% of the

time). No forced ventilation cooling system is in use. An

APA600-PQ208M FPGA operates in the system,

dissipating 1 W. The package thermal resistance

Performance Retention

For devices operated and stored at 110°C or less, the

performance retention period is 20 years after

programming. For devices operated and stored at

temperatures greater than 110°C, refer to Table 1-18 on

page 1-34 to determine the performance retention

period. Actel does not guarantee performance if the

performance retention period is exceeded. Designers can

determine the performance retention period from the

following table.

(junction-to-ambient) in still air Θ is 20°C/W, indicating

ja

that the junction temperature of the FPGA will be 120°C

(25% of the time) and 70°C (75% of the time). The entry

in Table 1-18 on page 1-34, which most closely matches

the application, is 25% at 125°C with 75% at 110°C.

Performance retention in this example is at least 16.0

years.

Evaluate the percentage of time spent at the highest

temperature, then determine the next highest

temperature to which the device will be exposed. In

Table 1-18 on page 1-34, find the temperature profile

that most closely matches the application.

Note that exceeding the stated retention period may

result in a performance degradation in the FPGA below

the worst-case performance indicated in the Actel Timer.

To ensure that performance does not degrade below the

worst-case values in the Actel Timer, the FPGA must be

reprogrammed within the performance retention

period. In addition, note that performance retention is

independent of whether or not the FPGA is operating.

The retention period of a device in storage at a given

temperature will be the same as the retention period of

a device operating at that junction temperature.

v5.7

1-33

PLUS

ProASIC

Flash Family FPGAs

Table 1-18 • Military Temperature Grade Product Performance Retention

Minimum

Performance

Minimum Time at T_JMinimum Time at T_JMinimum Time at T_JMinimum Time at T_J

110°C or below

100ꢀ

90ꢀ

125°C or below

135°C or below

150°C or below

Retention (Years)

20.0

18.2

16

10ꢀ

25ꢀ

75ꢀ

90ꢀ

10ꢀ

25ꢀ

15.4

13.3

11.8

11.4

10

50ꢀ

90ꢀ

10ꢀ

75ꢀ

100ꢀ

90ꢀ

10ꢀ

50ꢀ

25ꢀ

9.1

8

50ꢀ

75ꢀ

90ꢀ

8

10ꢀ

25ꢀ

7.7

7.3

6.7

5.7

5

50ꢀ

75ꢀ

50ꢀ

25ꢀ

100ꢀ

90ꢀ

10ꢀ

50ꢀ

25ꢀ

50ꢀ

100ꢀ

4.5

4.4

4

50ꢀ

75ꢀ

50ꢀ

4

3.3

2.5

1-34

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-19 • Recommended Maximum Operating Conditions Programming and PLL Supplies

Commercial/Industrial/Military/MIL-STD-883

Parameter

Condition

During Programming

Normal Operation¹

During Programming

Normal Operation²

During Programming

Minimum

15.8

Maximum

16.5

–13.2

0.5

Units

V

V_PP

0

V

V_PN

–13.8

V

I_PP

25

mA

V

I_PN

10

AVDD

V_DD

AGND

GND

V

Notes:

1. Please refer to the "V_PPProgramming Supply Pin" section on page 1-74 for more information.

2. Please refer to the "V_PNProgramming Supply Pin" section on page 1-74 for more information.

Table 1-20 • Recommended Operating Conditions

Limits

Parameter

Symbol

Commercial

Industrial

Military/MIL-STD-883

DC Supply Voltage (2.5 V I/Os)

DC Supply Voltage (3.3 V I/Os)

V_DDand V_DDP

2.5 V ± 0.2 V

V_DDP

V_DD

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

Operating Ambient Temperature Range

Maximum Operating Junction Temperature

T_A, T_C

T_J

0°C to 70°C

–40°C to 85°C

–55°C (T_A) to 125°C (T_C)

110°C

150°C

Note: For I/O long-term reliability, external pull-up resistors cannot be used to increase output voltage above V_DDP

.

v5.7

1-35

PLUS

ProASIC

Flash Family FPGAs

Table 1-21 • DC Electrical Specifications (V_DDP= 2.5 V ±0.2V)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_OH

Output High Voltage

High Drive (OB25LPH)

I_OH= –6 mA

I_OH= –12 mA

I_OH= –24 mA

2.1

2.0

1.7

V

I

_OH= –3 mA

2.1

1.9

1.7

Low Drive (OB25LPL)

I_OH= –6 mA

I_OH= –8 mA

V_OL

Output Low Voltage

High Drive (OB25LPH)

I_OL= 8 mA

I_OL= 15 mA

I_OL= 24 mA

0.2

0.4

0.7

V

Low Drive (OB25LPL)

I_OL= 4 mA

I_OL= 8 mA

I_OL= 15 mA

0.2

0.4

0.7

6

V_IH

Input High Voltage

Input Low Voltage

1.7

–0.3

6

V_DDP+ 0.3

V

7

V_IL

0.7

56

R_WEAKPULLUPWeak Pull-up Resistance

(OTB25LPU)

V_IN≥ 1.25 V

kΩ

HYST

I_IN

Input Hysteresis Schmitt

Input Current

See Table 1-4 on page 1-9

with pull up (V_IN= GND)

without pull up (V_IN= GND or V_DD

V_IN= GND⁴or V_DD

0.3

–240

–10

0.35

0.45

– 20

10

V

µA

mA

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

Std.

–F³

5.0

15

25

Quiescent Supply Current

(standby)

Industrial

V_IN= GND⁴or V_DD

Std.

5.0

20

mA

Quiescent Supply Current

(standby)

Military/MIL-STD-883

Std.

25

10

mA

µA

I_OZ

Tristate Output Leakage Current V_OH= GND or V_DD

Std.

–10

–F^{3, 5}

100

Notes:

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are available only as commercial.

4. No pull-up resistor.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle.

1-36

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-21 • DC Electrical Specifications (V_DDP= 2.5 V ±0.2V) (Continued)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

I_OSH

Output Short Circuit Current High

High Drive (OB25LPH)

Low Drive (OB25LPL)

mA

V_IN= V_SS

–120

–100

I_OSL

Output Short Circuit Current Low

High Drive (OB25LPH)

Low Drive (OB25LPL)

mA

V_IN= V_DDP

100

30

C_I/O

I/O Pad Capacitance

10

pF

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are available only as commercial.

4. No pull-up resistor.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle.

v5.7

1-37

PLUS

ProASIC

Flash Family FPGAs

Table 1-22 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_OH

Output High Voltage

3.3 V I/O, High Drive (OB33P)

I_OH= –14 mA

I_OH= –24 mA

0.9∗V_DDP

2.4

V

3.3 V I/O, Low Drive (OB33L)

I_OH= –6 mA

0.9∗V_DDP

I_OH= –12 mA

2.4

V_OL

Output Low Voltage

3.3 V I/O, High Drive (OB33P)

I_OL= 15 mA

I_OL= 20 mA

I_OL= 28 mA

0.1V_DDP

0.4

0.7

V

3.3 V I/O, Low Drive (OB33L)

I_OL= 7 mA

I_OL= 10 mA

I_OL= 15 mA

0.1V_DDP

0.4

0.7

6

V_IH

Input High Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

1.6

2

1.7

V_DDP+ 0.3

7

V_IL

Input Low Voltage

3.3 V Schmitt Trigger Inputs

3.3 V LVTTL/LVCMOS

2.5 V Mode

–0.3

0.8

0.7

V

R_WEAKPULLUPWeak

(IOB33U)

Pull-up

Resistance V_IN≥ 1.5 V

7

43

kΩ

R_WEAKPULLUPWeak

(IOB25U)

Pull-up

Resistance V_IN≥ 1.5 V

7

43

I_IN

Input Current

with pull up (V_IN= GND)

–300

–10

–40

10

µA

without pull up (V_IN= GND or V_DD

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

V_IN= GND⁴or V_DD

Std.

–F³

5.0

15

mA

25

I_DDQ

Quiescent Supply Current

(standby)

V_IN= GND⁴or V_DD

Industrial

Std.

5.0

20

25

mA

I_DDQ

Quiescent Supply Current

(standby)

Military

V

_IN= GND⁴or V_DD

Notes:

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are only available as commercial.

4. No pull-up resistor required.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

1-38

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-22 • DC Electrical Specifications (V_DDP= 3.3 V ±0.3 V and V_DD= 2.5 V ±0.2 V) (Continued)

Commercial/Industrial/

Military/MIL-STD-883^{1, 2}

Symbol

Parameter

Conditions

Min.

–10

Typ.

Max.

10

Units

µA

I_OZ

Tristate

Current

Output

Leakage V_OH= GND or V_DD

Std.

–F^{3, 5}

–10

100

µA

I_OSH

Output Short Circuit Current

High

3.3 V High Drive (OB33P)

3.3 V Low Drive (OB33L)

V_IN= GND

–200

–100

I_OSL

Output Short Circuit Current

Low

3.3 V High Drive

3.3 V Low Drive

V_IN= V_DD

200

100

C_I/O

I/O Pad Capacitance

10

pF

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C.

2. All process conditions. Military: Junction Temperature: –55 to +150°C.

3. All –F parts are only available as commercial.

4. No pull-up resistor required.

5. This will not exceed 2 mA total per device.

6. During transitions, the input signal may overshoot to V_DDP+1.0 V for a limited time of no larger than 10% of the duty cycle.

7. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.

v5.7

1-39

PLUS

ProASIC

Flash Family FPGAs

Table 1-23 • DC Specifications (3.3 V PCI Operation)¹

Commercial/

Industrial^2,3

Military/MIL-STD- 883^2,3

Symbol Parameter

Condition

Min.

2.3

Max.

2.7

Min.

2.3

Max.

2.7

Units

V

V_DD

V_DDP

V_IH

V_IL

Supply Voltage for Core

Supply Voltage for I/O Ring

Input High Voltage

3.0

3.6

3.0

3.6

V

0.5V_DDPV_DDP+ 0.5

0.5V_DDP

–0.5

V_DDP+ 0.5

0.3V_DDP

V

Input Low Voltage

–0.5

0.7V_DDP

–10

0.3V_DDP

V

I_IPU

I_IL

Input Pull-up Voltage⁴

Input Leakage Current⁵

0.7V_DDP

–50

V

0 < V_IN< V_DDP

Std.

10

50

μA

V

–F^{3, 6}

–10

100

V_OH

Output High Voltage

I_OUT= –500 µA

I_OUT= 1500 µA

0.9V_DDP

V_OL

Output Low Voltage

0.1V_DDP

10

0.1V_DDP

10

V

C_IN

Input Pin Capacitance (except CLK)

CLK Pin Capacitance

pF

C_CLK

Notes:

5

12

5

12

1. For PCI operation, use GL33, OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.

2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.

3. All –F parts are available as commercial only.

4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum

current at this input voltage.

5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

1-40

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-24 • AC Specifications (3.3 V PCI Revision 2.2 Operation)

Commercial/Industrial/Military/MIL-STD- 883

Symbol Parameter

Condition

Min.

–12V_DDP

Max.

Units

mA

*

I_OH(AC)Switching Current High 0 < V_OUT≤ 0.3V_DDP

*

0.3V_DDP≤ V_OUT< 0.9V_DDP

(–17.1 + (V_DDP– V_OUT))

mA

*

0.7V_DDP< V_OUT< V_DDP

See equation C – page 124 of

the PCI Specification

document rev. 2.2

*

(Test Point)

V_OUT= 0.7V_DDP

–32V_DDP

mA

*

I_OL(AC)

Switching Current Low V_DDP> V_OUT≥ 0.6V_DDP

16V_DDP

1

0.6V_DDP> V_OUT> 0.1V_DDP

(26.7V_OUT

)

0.18V_DDP> V_OUT> 0^*

See equation D – page 124 of

the PCI Specification

document rev. 2.2

(Test Point)

V_OUT= 0.18V_DDP

38V_DDP

mA

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

I_CH

V_DDP+ 4 > V_IN≥ V_DDP+ 1

0.2V_DDPto 0.6V_DDPload^*

0.6V_DDPto 0.2V_DDPload^*

25 + (V_IN– V_DDP– 1)/0.015

mA

slew_R

slew_F

1

4

V/ns

Note: * Refer to the PCI Specification document rev. 2.2.

Pad Loading Applicable to the Rising Edge PCI

1/2 in. max

output

buffer

10 pF

1kΩ

Pad Loading Applicable to the Falling Edge PCI

1kΩ

output

buffer

10 pF

v5.7

1-41

PLUS

ProASIC

Flash Family FPGAs

Tristate Buffer Delays

EN

A

PA D

OTBx

50% 50%

35pF

EN

A

50% 50%

EN

PAD

50% 50%

V_OH

V_DDP

V_OH

50%

V_OL

90%

50%

PAD

50%

PAD

GND

10%

50%

V_OL

t_DLH

t_ENZL

t_ENZH

t_DHL

Figure 1-26 • Tristate Buffer Delays

Table 1-25 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max

Max₃

t_ENZH

Max₄

t_ENZL

1

2

t_DLH

t_DHL

Macro Type

OTB33PH

OTB33PN

OTB33PL

OTB33LH

OTB33LN

OTB33LL

Notes:

Description

Std. –F Std. –F Std. –F Std. –F Units

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4

2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5

2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4

2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6

2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9

3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6

ns

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. All –F parts are only available as commercial.

Table 1-26 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

Max

Max₃

t_ENZH

Max₄

t_ENZL

1

2

t_DLH

t_DHL

Macro Type

Description

2.5 V, Low Power, High Output Current, High Slew Rate⁵

2.5 V, Low Power, High Output Current, Nominal Slew Rate⁵2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5

Std. –F Std. –F Std. –F Std. –F Units

OTB25LPHH

OTB25LPHN

OTB25LPHL

OTB25LPLH

OTB25LPLN

OTB25LPLL

Notes:

2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4

ns

2.5 V, Low Power, High Output Current, Low Slew Rate⁵

2.5 V, Low Power, Low Output Current, High Slew Rate⁵

2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2

2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1

2.5 V, Low Power, Low Output Current, Nominal Slew Rate⁵3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6

2.5 V, Low Power, Low Output Current, Low Slew Rate⁵

4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. Low power I/O work with V_DDP=2.5 V 10% only. V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

1-42

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-27 • Worst-Case Military Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max

t_ENZH

Max

1

2

3

4

t_DLH

Std.

2.2

t_DHL

Std.

2.4

t_ENZL

Std.

2.1

Macro Type

OTB33PH

OTB33PN

OTB33PL

OTB33LH

OTB33LN

OTB33LL

Notes:

Description

Std.

2.3

2.7

2.9

3.0

3.4

3.5

Units

ns

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

2.4

3.2

2.3

ns

2.7

3.5

3.0

ns

2.7

4.3

3.1

ns

3.3

4.7

4.4

ns

3.2

6.0

5.9

ns

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

Table 1-28 • Worst-Case Military Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max

t_DLH

Max

1

2

3

4

t_DHL

Std.

2.3

t_ENZH

Std.

2.4

t_ENZL

Std.

2.1

Macro Type

OTB25LPHH

OTB25LPHN

Description

Std.

2.3

Units

ns

2.5 V, Low Power, High Output Current, High Slew Rate⁵

2.5 V, Low Power, High Output Current, Nominal Slew

Rate⁵

2.7

3.2

2.8

2.1

ns

OTB25LPHL

OTB25LPLH

OTB25LPLN

OTB25LPLL

Notes:

2.5 V, Low Power, High Output Current, Low Slew Rate⁵

2.5 V, Low Power, Low Output Current, High Slew Rate⁵

2.5 V, Low Power, Low Output Current, Nominal Slew Rate⁵

2.5 V, Low Power, Low Output Current, Low Slew Rate⁵

3.2

3.0

3.7

4.4

3.5

5.0

4.5

5.8

3.3

3.2

4.1

4.4

2.8

4.1

5.4

ns

1. t_DLH=Data-to-Pad High

2. t_DHL=Data-to-Pad Low

3. t_ENZH=Enable-to-Pad, Z to High

4. t_ENZL= Enable-to-Pad, Z to Low

5. Low power I/O work with V_DDP=2.5V 10% only. V_DDP=2.3V for delays.

v5.7

1-43

PLUS

ProASIC

Flash Family FPGAs

Output Buffer Delays

A

50%

V_OH

PAD

A

50%

PAD

V_OL

50%

35pF

OBx

t_DLH

t_DHL

Figure 1-27 • Output Buffer Delays

Table 1-29 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

1

2

Max t_DLH

Max t_DHL

Macro Type

OB33PH

OB33PN

OB33PL

Description

3.3 V, PCI Output Current, High Slew Rate

3.3 V, High Output Current, Nominal Slew Rate

3.3 V, High Output Current, Low Slew Rate

3.3 V, Low Output Current, High Slew Rate

3.3 V, Low Output Current, Nominal Slew Rate

3.3 V, Low Output Current, Low Slew Rate

Std.

–F

Std.

2.2

2.9

3.2

4.0

4.3

5.6

–F

2.6

3.5

3.9

4.8

5.2

6.7

Units

ns

2.0

2.2

2.5

2.6

2.9

3.0

2.4

2.6

3.0

3.1

3.5

3.6

ns

OB33LH

OB33LN

OB33LL

ns

Notes:

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. All –F parts are only available as commercial.

Table 1-30 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, 35 pF load, T_J= 70°C

1

2

Max t_DLH

Max t_DHL

Macro Type

Description

Std.

2.0

2.4

2.9

2.7

3.5

4.0

–F

Std.

2.1

3.0

3.2

4.6

4.2

5.3

–F

2.6

3.6

3.8

5.5

5.1

6.4

Units

ns

OB25LPHH

OB25LPHN

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

2.5 V, Low Power, High Output Current, High Slew Rate³

2.4

2.9

3.5

3.3

4.2

4.8

2.5 V, Low Power, High Output Current, Nominal Slew Rate³

2.5 V, Low Power, High Output Current, Low Slew Rate³

2.5 V, Low Power, Low Output Current, High Slew Rate³

2.5 V, Low Power, Low Output Current, Nominal Slew Rate³

2.5 V, Low Power, Low Output Current, Low Slew Rate³

ns

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. Low-power I/Os work with V_DDP=2.5 V 10% only. V_DDP=2.3 V for delays.

4. All –F parts are only available as commercial.

1-44

v5.7

PLUS

ProASIC

Max.

Flash Family FPGAs

Table 1-31 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max.

1

2

t_DLH

t_DHL

Macro Type

OB33PH

OB33PN

OB33PL

Description

Std.

2.1

2.5

2.7

3.3

Std.

2.3

3.2

3.5

4.3

4.7

6.1

Units

ns

3.3V, PCI Output Current, High Slew Rate

3.3V, High Output Current, Nominal Slew Rate

3.3V, High Output Current, Low Slew Rate

3.3V, Low Output Current, High Slew Rate

3.3V, Low Output Current, Nominal Slew Rate

3.3V, Low Output Current, Low Slew Rate

ns

OB33LH

OB33LN

OB33LL

ns

Notes:

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

Table 1-32 • Worst-Case Military Conditions

V_DDP= 2.3 V, V_DD= 2.3V, 35 pF load, T_J= 125°C for Military/MIL-STD-883

Max.

t_DLH

Max.

t_DHL

1

2

Macro Type

Description

Std.

2.3

2.7

3.2

3.0

3.9

4.3

Std.

2.4

3.3

3.5

5.0

4.6

5.7

Units

ns

OB25LPHH

OB25LPHN

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

2.5V, Low Power, High Output Current, High Slew Rate³

2.5V, Low Power, High Output Current, Nominal Slew Rate³

2.5V, Low Power, High Output Current, Low Slew Rate³

2.5V, Low Power, Low Output Current, High Slew Rate³

2.5V, Low Power, Low Output Current, Nominal Slew Rate³

2.5V, Low Power, Low Output Current, Low Slew Rate³

ns

1. t_DLH= Data-to-Pad High

2. t_DHL= Data-to-Pad Low

3. Low power I/O work with V_DDP=2.5V 10% only. V_DDP=2.3V for delays.

v5.7

1-45

PLUS

ProASIC

Flash Family FPGAs

Input Buffer Delays

V

DDP

PAD

0 V

50%

50% 50%

V_DD

Y

PAD

Y

GND

50%

IBx

t

INYH

INYL

Figure 1-28 • Input Buffer Delays

Table 1-33 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

1

2

Max. t_INYH

Std. –F

Max. t_INYL

Macro Type

IB33

Description

Std.

0.6

–F

Units

ns

3.3 V, CMOS Input Levels³, No Pull-up Resistor

0.4

0.6

0.5

0.7

0.9

IB33S

3.3 V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

0.8

ns

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3 V for delays.

5. All –F parts are only available as commercial.

Table 1-34 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, T_J= 70°C

1

2

Max. t_INYH

Max. t_INYL

Macro Type

Description

Std.

0.9

–F

Std.

0.6

–F

0.8

1.1

Units

ns

IB25LP

2.5 V, CMOS Input Levels³, Low Power

1.1

0.9

IB25LPS

Notes:

2.5 V, CMOS Input Levels³, Low Power, Schmitt Trigger

0.7

0.9

ns

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3 V for delays.

5. All –F parts are only available as commercial.

1-46

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-35 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

1

2

Max. t_INYH

Max. t_INYL

Std.

Macro Type

IB33

Description

Std.

0.5

Units

ns

3.3V, CMOS Input Levels³, No Pull-up Resistor

0.6

IB33S

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

0.6

0.8

ns

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

Table 1-36 • Worst-Case Military Conditions

V_DDP= 2.3V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

1

2

Max. t_INYH

Std.

Max. t_INYL

Std.

Macro Type

IB25LP

Description

Units

ns

2.5V, CMOS Input Levels³, Low Power

0.9

0.7

IB25LPS

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

0.8

1.0

ns

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

v5.7

1-47

PLUS

ProASIC

Flash Family FPGAs

Global Input Buffer Delays

Table 1-37 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

1

2

Max. t_INYH

Max. t_INYL

Units

Macro Type

GL33

Description

Std.³

–F

Std.³

–F

3.3 V, CMOS Input Levels⁴, No Pull-up Resistor

3.3 V, CMOS Input Levels⁴, No Pull-up Resistor, Schmitt Trigger

PPECL Input Levels

1.0

1.2

1.1

1.3

ns

GL33S

1.0

1.1

PECL

1.0

1.1

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. Applies to Military ProASIC^PLUSdevices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

Table 1-38 • Worst-Case Commercial Conditions

V_DDP= 2.3 V, V_DD= 2.3 V, T_J= 70°C

1

2

Max. t_INYH

Max. t_INYL

Units

Macro Type

GL25LP

Description

2.5 V, CMOS Input Levels⁴, Low Power

2.5 V, CMOS Input Levels⁴, Low Power, Schmitt Trigger

Std.³

–F

Std.³

–F

1.1

1.2

1.6

1.0

1.3

1.1

ns

GL25LPS

Notes:

1.3

1.0

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. Applies to Military ProASIC^PLUSdevices.

4. LVTTL delays are the same as CMOS delays.

5. For LP Macros, V_DDP=2.3 V for delays.

6. All –F parts are only available as commercial.

1-48

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-39 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

1

2

Max. t_INYH

Max. t_INYL

Std.

Macro Type

GL33

Description

3.3V, CMOS Input Levels³, No Pull-up Resistor

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

PPECL Input Levels

Std.

1.1

GL33S

1.1

PECL

1.1

Notes:

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

Table 1-40 • Worst-Case Military Conditions

V_DDP= 2.3V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

1

2

Max. t_INYH

Std.

Max. t_INYL

Std.

Macro Type

Description

2.5V, CMOS Input Levels³, Low Power

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

GL25LP

GL25LPS

Notes:

1.0

1.1

1.4

1.0

1. t_INYH= Input Pad-to-Y High

2. t_INYL= Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

v5.7

1-49

PLUS

ProASIC

Flash Family FPGAs

Predicted Global Routing Delay

Table 1-41 • Worst-Case Commercial Conditions¹

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max.

Parameter

t_RCKH

Description

Std.

1.1

1.0

0.8

–F²

1.3

1.2

1.0

Units

ns

Input Low to High³

Input High to Low³

Input Low to High⁴

Input High to Low⁴

t_RCKL

ns

t_RCKH

ns

t_RCKL

ns

Notes:

1. The timing delay difference between tile locations is less than 15ps.

2. All –F parts are only available as commercial.

3. Highly loaded row 50%.

4. Minimally loaded row.

Table 1-42 • Worst-Case Military Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Parameter

t_RCKH

Description

Max.

Units

Input Low to High (high loaded row of 50ꢀ)

Input High to Low (high loaded row of 50ꢀ)

Input Low to High (minimally loaded row)

Input High to Low (minimally loaded row)

1.1

1.0

0.8

ns

t_RCKL

t_RCKH

t_RCKL

Note: * The timing delay difference between tile locations is less than 15 ps.

Global Routing Skew

Table 1-43 • Worst-Case Commercial Conditions

V_DDP= 3.0 V, V_DD= 2.3 V, T_J= 70°C

Max.

Parameter

t_RCKSWH

Description

Maximum Skew Low to High

Maximum Skew High to Low

Std.

270

–F*

320

Units

ps

t_RCKSHH

ps

Note: *All –F parts are only available as commercial.

Table 1-44 • Worst-Case Commercial Conditions

V

_DDP= 3.0V, V_DD= 2.3V, T_J= 125°C for Military/MIL-STD-883

Description

Maximum Skew Low to High

Maximum Skew High to Low

Parameter

t_RCKSWH

Max.

Units

ps

270

t_RCKSHH

ps

1-50

v5.7

PLUS

ProASIC

Flash Family FPGAs

Module Delays

A

B

C

Y

50%50%

A

B

50%50%

C

Y

50%50%

50%

t_DBLH

50%

t_DCHL

t_DCLH

t_DBHL

t_DAHL

t_DALH

Figure 1-29 • Module Delays

Sample Macrocell Library Listing

Table 1-45 • Worst-Case Military Conditions¹

V_DD= 2.3 V, T_J= 70º C, T_J= 70°C, T_J= 125°C for Military/MIL-STD-883

Std.

–F²

Cell Name

NAND2

AND2

Description

Max

Min

Max

0.6

0.8

1.0

0.6

1.0

0.8

Min

Units

ns

2-Input NAND

2-Input AND

3-Input NOR

0.5

0.7

0.8

0.5

0.8

0.6

ns

NOR3

ns

MUX2L

OA21

2-1 MUX with Active Low Select

2-Input OR into a 2-Input AND

2-Input Exclusive OR

ns

XOR2

ns

LDL

Active Low Latch (LH/HL)

ns

LH³

HL³

0.9

0.8

1.1

0.9

CLK-Q

ns

t_setup

0.7

0.1

0.8

0.2

t_hold

DFFL

Negative Edge-Triggered D-type Flip-Flop (LH/HL)

LH³

HL³

0.9

0.8

1.1

1.0

CLK-Q

ns

t_setup

t_hold

0.6

0.0

0.7

0.0

Notes:

1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

2. All –F parts are only available as commercial.

3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.

v5.7

1-51

PLUS

ProASIC

Flash Family FPGAs

Table 1-46 • Recommended Operating Conditions

Limits

Parameter

Symbol

f_CLOCK

f_RAM

Commercial/Industrial

180 MHz

Military/MIL-STD-883

180 MHz

Maximum Clock Frequency*

Maximum RAM Frequency*

Maximum Rise/Fall Time on Inputs*

150 MHz

•

Schmitt Trigger Mode (10ꢀ to 90ꢀ)

t_R/t_F

N/A

100 ns

10 ns

Non-Schmitt Trigger Mode (10ꢀ to

90ꢀ)

100 ns

Maximum LVPECL Frequency*

Maximum TCK Frequency (JTAG)

180 MHz

10 MHz

180 MHz

10 MHz

f_TCK

Note: *All –F parts will be 20% slower than standard commercial devices.

Table 1-47 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C

Type

Trig. Level Rising Edge (ns) Slew Rate (V/ns) Falling Edge (ns) Slew Rate (V/ns)

PCI Mode

Yes

No

OB33PH

OB33PN

OB33PL

OB33LH

OB33LN

OB33LL

10ꢀ-90ꢀ

1.60

1.57

3.80

4.19

5.49

1.55

1.70

1.97

3.57

4.65

5.52

1.65

1.68

0.70

0.63

0.48

1.29

1.18

1.02

0.56

0.43

0.36

1.65

3.32

1.99

4.84

3.37

2.98

1.56

2.08

2.09

3.93

3.28

3.44

1.60

0.80

1.32

0.55

0.78

0.89

1.28

0.96

0.51

0.61

0.58

No

OB25LPHH 10ꢀ-90ꢀ

OB25LPHN 10ꢀ-90ꢀ

No

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

10ꢀ-90ꢀ

No

1. Standard and –F parts.

2. All –F only available as commercial.

1-52

v5.7

PLUS

ProASIC

Flash Family FPGAs

Table 1-48 • JTAG Switching Characteristics

Description

Symbol

t_TCKTDI

t_TDOTCK

t_TCKTDO

t_TCK

Min

–4

Max

Unit

ns

Output delay from TCK falling to TDI, TMS

TDO Setup time before TCK rising

TDO Hold time after TCK rising

TCK period

4

10

ns

0

ns

100 ²

1,000

ns

RCK period

t_RCK

100

ns

Notes:

1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-21 on page 1-36 when V_DDP= 2.5 V

and Table 1-22 on page 1-38 when V_DDP= 3.3 V.

2. If RCK is being used, there is no minimum on the TCK period.

TCK

t_TCK

TMS, TDI

t_TCKTDI

TDO

t_TDOTCK

t_TCKTDO

Figure 1-30 • JTAG Operation Timing

v5.7

1-53

PLUS

ProASIC

Flash Family FPGAs

Embedded Memory Specifications

This section discusses ProASIC^PLUSSRAM/FIFO embedded

memory and its interface signals, including timing

diagrams that show the relationships of signals as they

pertain to single embedded memory blocks (Table 1-49).

Table 1-12 on page 1-23 shows basic SRAM and FIFO

configurations. Simultaneous read and write to the same

location must be done with care. On such accesses the DI

bus is output to the DO bus. Refer to the ProASIC^PLUS

RAM and FIFO Blocks application note for more

information.

•

"Asynchronous SRAM Read, RDB Controlled"

section on page 1-59

•

"Synchronous SRAM Write"

Embedded Memory Specifications

The difference between synchronous transparent and

pipeline modes is the timing of all the output signals

from the memory. In transparent mode, the outputs will

change within the same clock cycle to reflect the data

requested by the currently valid access to the memory. If

clock cycles are short (high clock speed), the data

requires most of the clock cycle to change to valid values

(stable signals). Processing of this data in the same clock

cycle is nearly impossible. Most designers add registers at

all outputs of the memory to push the data processing

into the next clock cycle. An entire clock cycle can then

be used to process the data. To simplify use of this

Enclosed Timing Diagrams—SRAM Mode:

•

"Synchronous SRAM Read, Access Timed Output

Strobe (Synchronous Transparent)" section on

page 1-55

•

"Synchronous SRAM Read, Pipeline Mode Outputs

(Synchronous Pipelined)" section on page 1-56

memory

setup,

suitable

registers

have

been

•

"Asynchronous SRAM Write" section on page 1-57

implemented as part of the memory primitive and are

available to the user in the synchronous pipeline mode.

In this mode, the output signals will change shortly after

the second rising edge, following the initiation of the

read access.

"Asynchronous SRAM Read, Address Controlled,

RDB=0" section on page 1-58

Table 1-49 • Memory Block SRAM Interface Signals

SRAM Signal

WCLKS

RCLKS

Bits

1

In/Out

In

Description

Write clock used on synchronization on write side

1

In

Read clock used on synchronization on read side

Read address

RADDR<0:7>

RBLKB

8

In

1

In

True read block select (active Low)

True read pulse (active Low)

RDB

1

In

WADDR<0:7>

WBLKB

8

In

Write address

1

In

Write block select (active Low)

DI<0:8>

WRB

9

In

Input data bits <0:8>, <8> can be used for parity In

Negative true write pulse

1

In

DO<0:8>

RPE

9

Out

In

Output data bits <0:8>, <8> can be used for parity Out

Read parity error (active High)

1

WPE

1

Write parity error (active High)

PARODD

1

Selects Odd parity generation/detect when high, Even when low

Note: Not all signals shown are used in all modes.

1-54

v5.7

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

RCLKS

Cycle Start

RBD, RBLKB

New Valid

RADDR

Address

Old Data Out

New Valid Data Out

DO

RPE

t

RACS

t

RDCS

t

RDCH

t

RACH

t

OCH

t

RPCH

t

CMH

CML

t

OCA

t

RPCA

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-50 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max.

Units

ns

Notes

Cycle time

Clock high phase

3.0

ns

CML

Clock low phase

3.0

ns

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

7.5

ns

OCH

3.0

ns

RACH

RACS

0.5

1.0

0.5

1.0

9.5

ns

RDCH

RDCS

ns

RPCA

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

ns

RPCH

3.0

ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-55

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLKS

Cycle Start

RDB, RBLKB

New Valid

RADDR

Address

DO

New Valid Data Out

New RPE Out

Old Data Out

RPE

Old RPE Out

t

RACS

OCA

t

RACH

RPCH

t

RDCH

OCH

t

RPCA

RDCS

t

CML

CMH

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-32 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-51 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= 0°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max.

Units

ns

Notes

Cycle time

Clock high phase

3.0

ns

CML

Clock low phase

3.0

ns

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

2.0

ns

OCH

0.75

ns

RACH

RACS

0.5

1.0

0.5

1.0

4.0

ns

RDCH

RDCS

ns

RPCA

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

ns

RPCH

1.0

ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

1-56

v5.7

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Write

WADDR

WRB, WBLKB

DI

WPE

t

AWRS

AWRH

t

DWRH

WPDH

t

WPDA

t

DWRS

t

WRMH

WRML

t

WRCYC

Note: The plot shows the normal operation status.

Figure 1-33 • Asynchronous SRAM Write

Table 1-52 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883B

Symbol t_xxx

AWRH

Description

WADDR hold from WB ↑

Min.

1.0

0.5

1.5

0.5

2.5

3.0

Max.

Units

Notes

ns

AWRS

WADDR setup to WB ↓

DI hold from WB ↑

DI setup to WB ↑

WPE access from DI

WPE hold from DI

Cycle time

DWRH

DWRS

PARGEN is inactive.

PARGEN is active.

DWRS

WPDA

WPE is invalid, while PARGEN is

active.

WPDH

1.0

WRCYC

WRMH

WRML

7.5

3.0

WB high phase

Inactive

Active

WB low phase

Note: All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-57

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Read, Address Controlled, RDB=0

RADDR

DO

RPE

t

OAH

t

RPAH

t

OAA

t

RPAA

t

ACYC

Note: The plot shows the normal operation status.

Figure 1-34 • Asynchronous SRAM Read, Address Controlled, RDB=0

Table 1-53 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883B

Symbol t_xxx

ACYC

Description

Read cycle time

Min.

7.5

Max.

Units

ns

Notes

OAA

New DO access from RADDR stable

Old DO hold from RADDR stable

New RPE access from RADDR stable

Old RPE hold from RADDR stable

7.5

ns

OAH

3.0

ns

RPAA

10.0

ns

RPAH

ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

1-58

v5.7

PLUS

ProASIC

Flash Family FPGAs

Asynchronous SRAM Read, RDB Controlled

RB=(RDB+RBLKB)

DO

RPE

t

ORDH

t

RPRDH

t

ORDA

t

RPRDA

t

RDML

RDMH

t

RDCYC

Note: The plot shows the normal operation status.

Figure 1-35 • Asynchronous SRAM Read, RDB Controlled

Table 1-54 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

Min.

Max.

Units

ns

Notes

7.5

ORDH

3.0

ns

RDCYC

RDMH

7.5

3.0

9.5

ns

RB high phase

ns

Inactive setup to new cycle

Active

RDML

RB low phase

ns

RPRDA

RPRDH

New RPE access from RB ↓

Old RPE valid from RB ↓

ns

3.0

ns

Note: All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-59

PLUS

ProASIC

Flash Family FPGAs

Synchronous SRAM Write

WCLKS

WRB, WBLKB

WADDR, DI

WPE

Cycle Start

t

, t

WRCH WBCH

t

, t

WRCS WBCS

t

, t

DCS WDCS

t

WPCH

t

, t

DCH WACH

t

WPCA

t

CML

CMH

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-36 • Synchronous SRAM Write

Table 1-55 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

3.0

0.5

1.0

0.5

1.0

3.0

Max.

Units

ns

Notes

Cycle time

Clock high phase

ns

CML

Clock low phase

ns

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

ns

DCS

ns

WACH

WDCS

WPCA

WPCH

WADDR hold from WCLKS ↑

WADDR setup to WCLKS ↑

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

ns

WPE is invalid while

PARGEN is active

0.5

ns

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

ns

1. On simultaneous read and write accesses to the same location, DI is output to DO.

2. All –F speed grade devices are 20% slower than the standard numbers.

1-60

v5.7

PLUS

ProASIC

Flash Family FPGAs

Synchronous Write and Read to the Same Location

t

CCYC

t

CMH

CML

RCLKS

DO

New Data*

Last Cycle Data

WCLKS

t

WCLKRCLKH

t

WCLKRCLKS

t

OCH

t

OCA

* New data is read if WCLKS ↑ occurs before setup time.

The data stored is read if WCLKS ↑ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-37 • Synchronous Write and Read to the Same Location

Table 1-56 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max.

Units

ns

Notes

Cycle time

CMH

Clock high phase

3.0

ns

CML

Clock low phase

3.0

ns

WCLKRCLKS

WCLKRCLKH

OCH

WCLKS ↑ to RCLKS ↑ setup time

WCLKS ↑ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

– 0.1

ns

7.0

3.0

ns

OCA/OCH displayed for

Access Timed Output

OCA

7.5

ns

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write

clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS

and RCLKS driven by the same design signal.

3. If WCLKS changes after the hold time, the data will be read.

4. A setup or hold time violation will result in unknown output data.

5. All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-61

PLUS

ProASIC

Flash Family FPGAs

Asynchronous Write and Synchronous Read to the Same Location

t

CMH

CML

RCLKS

DO

New Data*

Last Cycle Data

WB = {WRB + WBLKB}

DI

t

WRCKS

t

BRCLKH

t

OCH

OCA

t

DWRRCLKS

DWRH

t

CCYC

* New data is read if WB ↓ occurs before setup time.

The stored data is read if WB ↓ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-38 • Asynchronous Write and Synchronous Read to the Same Location

Table 1-57 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max.

Units

ns

Notes

Cycle time

CMH

Clock high phase

3.0

ns

CML

Clock low phase

3.0

ns

WBRCLKS

WBRCLKH

OCH

WB ↓ to RCLKS ↑ setup time

WB ↓ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

DI to RCLKS ↑ setup time

DI to WB ↑ hold time

–0.1

ns

7.0

3.0

ns

OCA/OCH

Access Timed Output

displayed

for

OCA

7.5

0

ns

DWRRCLKS

DWRH

ns

1.5

ns

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write

signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be

read.

3. A setup or hold time violation will result in unknown output data.

4. All –F speed grade devices are 20% slower than the standard numbers.

1-62

v5.7

PLUS

ProASIC

Flash Family FPGAs

Asynchronous Write and Read to the Same Location

RB, RADDR

NEW

NEWER

DO

OLD

WB = {WRB+WBLKB}

t

ORDA

RAWRH

t

ORDH

t

RAWRS

OWRA

t

OWRH

Note: The plot shows the normal operation status.

Figure 1-39 • Asynchronous Write and Read to the Same Location

Table 1-58 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Min.

Max.

Units

Notes

7.5

ns

ORDH

3.0

OWRA

New DO access from WB ↑

Old DO valid from WB ↑

RB ↓ or RADDR from WB ↓

RB ↑ or RADDR from WB ↑

3.0

OWRH

0.5

RAWRS

RAWRH

Notes:

5.0

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data. Refer to the ProASIC^PLUSRAM and FIFO Blocks application note for more

information.

2. Violation or RAWRS will disturb access to the OLD data.

3. Violation of RAWRH will disturb access to the NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-63

PLUS

ProASIC

Flash Family FPGAs

Synchronous Write and Asynchronous Read to the Same Location

RB, RADDR

NEW

NEWER

DO

OLD

WCLKS

t

ORDA

RAWCLKH

t

ORDH

t

OWRA

t

OWRH

t

RAWCLKS

Note: The plot shows the normal operation status.

Figure 1-40 • Synchronous Write and Asynchronous Read to the Same Location

Table 1-59 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

ORDA

Description

New DO access from RB ↓

Old DO valid from RB ↓

Min.

Max.

Units

ns

Notes

7.5

ORDH

3.0

ns

OWRA

New DO access from WCLKS ↓

Old DO valid from WCLKS ↓

RB ↓ or RADDR from WCLKS ↑

RB ↑ or RADDR from WCLKS ↓

3.0

ns

OWRH

0.5

ns

RAWCLKS

RAWCLKH

Notes:

5.0

ns

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data.

2. Violation of RAWCLKS will disturb access to OLD data.

3. Violation of RAWCLKH will disturb access to NEWER data.

4. All –F speed grade devices are 20% slower than the standard numbers.

1-64

v5.7

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Full and Empty Transitions

The asynchronous FIFO accepts writes and reads while

not full or not empty. When the FIFO is full, all writes are

inhibited. Conversely, when the FIFO is empty, all reads

are inhibited. A problem is created if the FIFO is written

to during the transition from full to not full, or read

during the transition from empty to not empty. The

exact time at which the write or read operation changes

from inhibited to accepted after the read (write) signal

which causes the transition from full or empty to not full

or not empty is indeterminate. For slow cycles, this

indeterminate period starts 1 ns after the RB (WB)

transition, which deactivates full or not empty and ends

3 ns after the RB (WB) transition. For fast cycles, the

indeterminate period ends 3 ns (7.5 ns – RDL (WRL)) after

the RB (WB) transition, whichever is later (Table 1-1 on

page 1-7).

empty flag will be asserted, the counters will reset, the

outputs go to zero, but the internal RAM is not erased.

Enclosed Timing Diagrams – FIFO Mode:

The following timing diagrams apply only to single cell;

they are not applicable to cascaded cells. For more

information, refer to the ProASIC^PLUSRAM/FIFO Blocks

application note.

•

"Asynchronous FIFO Read" section on page 1-67

"Asynchronous FIFO Write" section on page 1-68

"Synchronous FIFO Read, Access Timed Output

Strobe (Synchronous Transparent)" section on

page 1-69

•

"Synchronous FIFO Read, Pipeline Mode Outputs

(Synchronous Pipelined)" section on page 1-70

The timing diagram for write is shown in Figure 1-38 on

page 1-62. The timing diagram for read is shown in

Figure 1-39 on page 1-63. For basic SRAM configurations,

see Table 1-13 on page 1-24. When reset is asserted, the

•

"Synchronous FIFO Write" section on page 1-71

"FIFO Reset" section on page 1-72

Table 1-60 • Memory Block FIFO Interface Signals

FIFO Signal

WCLKS

Bits

In/Out

In

Description

1

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active Low)

RCLKS

1

8

1

9

1

2

In

LEVEL <0:7>*

RBLKB

In

RDB

In

Read pulse (active Low)

RESET

In

Reset for FIFO pointers (active Low)

WBLKB

In

Write block select (active Low)

DI<0:8>

WRB

In

Input data bits <0:8>, <8> will be generated if PARGEN is true

Write pulse (active Low)

In

FULL, EMPTY

EQTH, GEQTH*

Out

FIFO flags. FULL prevents write and EMPTY prevents read

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

9

1

3

1

Out

In

Output data bits <0:8>

Read parity error (active High)

WPE

Write parity error (active High)

LGDEP <0:2>

PARODD

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

In

Selects Odd parity generation/detect when high, Even when low

Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be

possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that

indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.

Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.

v5.7

1-65

PLUS

ProASIC

Flash Family FPGAs

FULL

RB

Write

cycle

Write inhibited

Write accepted

1 ns

3 ns

WB

Note: All –F speed grade devices are 20% slower than the standard numbers.

Figure 1-41 • Write Timing Diagram

EMPTY

WB

Read

cycle

Read inhibited

Read accepted

1 ns

3 ns

RB

Note: All –F speed grade devices are 20% slower than the standard numbers.

Figure 1-42 • Read Timing Diagram

1-66

v5.7

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Read

t

RPRDA

t

RDH

RDL

Cycle Start

RB = (RDB+RBLKB)

(Empty inhibits read)

RDATA

RPE

WB

EMPTY

FULL

EQTH, GETH

t

, t

RDWRS

ERDH FRDH

t

, t

ORDH

ERDA FRDA

t

RPRDH

THRDH

t

ORDA

THRDA

t

RPRDA

t

RDL

RDH

t

RDCYC

Note: The plot shows the normal operation status.

Figure 1-43 • Asynchronous FIFO Read

Table 1-61 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

Description

Min.

Max. Units

Notes

ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

ns

Empty/full/thresh are invalid from the end of

hold until the new access is complete

THRDH

time from RB ↑

ERDA

New EMPTY access from RB ↑

FULL↓ access from RB ↑

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

3.0¹

7.5

ns

FRDA

ORDA

ORDH

RDCYC

RDWRS

3.0

1.0

7.5

3.0²

WB ↑, clearing EMPTY, setup to

RB ↓

Enabling the read operation

Inhibiting the read operation

Inactive

RDH

RB high phase

3.0

9.5

RDL

RB low phase

Active

RPRDA

RPRDH

THRDA

Notes:

New RPE access from RB ↓

Old RPE valid from RB ↓

EQTH or GETH access from RB↑

4.0

4.5

1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.

2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.

3. All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-67

PLUS

ProASIC

Flash Family FPGAs

Asynchronous FIFO Write

Cycle Start

WB = (WRB+WBLKB)

WDATA

WPE

(Full inhibits write)

RB

FULL

EMPTY

EQTH, GETH

t

WRRDS

DWRH

t

WPDH

WPDA

t

DWRS

t

, t

EWRH FWRH

, t

EWRA FWRA

t

THWRH

THWRA

t

WRL

WRH

t

WRCYC

Note: The plot shows the normal operation status.

Figure 1-44 • Asynchronous FIFO Write

Table 1-62 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

DWRH

Description

DI hold from WB ↑

Min.

1.5

Max.

Units

ns

Notes

DWRS

DI setup to WB ↑

0.5

ns

PARGEN is inactive

PARGEN is active

DWRS

2.5

ns

EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

ns

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THWRH

time after WB ↑

EWRA

EMPTY ↓ access from WB ↑

New FULL access from WB ↑

EQTH or GETH access from WB ↑

WPE access from DI

3.0¹

4.5

ns

FWRA

THWRA

WPDA

WPDH

WRCYC

WRRDS

3.0

WPE is invalid while PARGEN is active

WPE hold from DI

1.0

Cycle time

7.5

3.0²

RB ↑, clearing FULL, setup to

WB ↓

Enabling the write operation

Inhibiting the write operation

Inactive

WRH

WRL

WB high phase

WB low phase

3.0

ns

Active

Notes:

1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.

2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.

3. All –F speed grade devices are 20% slower than the standard numbers.

4. After FIFO reset, WRB needs an initial falling edge prior to any write actions.

1-68

v5.7

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out (Empty Inhibits Read)

EMPTY

FULL

EQTH, GETH

t

, t

RDCH

ECBH FCBH

, t

t

ECBA FCBA

RDCS

t

THCBH

t

OCH

t

RPCH

HCBA

t

OCA

t

RPCA

t

CML

CMH

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-63 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min.

7.5

Max. Units

Notes

Cycle time

ns

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓ access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

1.0

3.0

ns

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THCBH

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

7.5

ns

OCH

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

9.5

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

3.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-69

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out

New RPE Out

Old RPE Out

EMPTY

FULL

EQTH, GETH

t

, t

t

ECBH FCBH

OCA

t

, t

RDCH

ECBA FCBA

t

RDCS

THCBH

t

RPCH

OCH

HCBA

t

RPCA

t

CML

CMH

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-64 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

Description

Min. Max. Units

Notes

Cycle time

7.5

3.0

ns

CMH

Clock high phase

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓ access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

THCBH

1.0

Empty/full/thresh are invalid from the end of

hold until the new access is complete

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

2.0

ns

OCH

0.75

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

4.0

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

1.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

1-70

v5.7

PLUS

ProASIC

Flash Family FPGAs

Synchronous FIFO Write

WCLKS

Cycle Start

WRB, WBLKB

(Full Inhibits Write)

DI

WPE

FULL

EMPTY

EQTH, GETH

t

, t

t

, t

WRCH WBCH

ECBH FCBH

, t

t

, t

ECBA FCBA

WRCS WBCS

t

DCS

HCBH

t

HCBA

t

WPCH

t

DCH

t

WPCA

t

CMH

CML

t

CCYC

Note: The plot shows the normal operation status.

Figure 1-47 • Synchronous FIFO Write

Table 1-65 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CCYC

CMH

Description

Min.

7.5

Max. Units

Notes

Cycle time

ns

Clock high phase

3.0

CML

Clock low phase

3.0

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

0.5

DCS

1.0

FCBA

New FULL access from WCLKS ↓

EMPTY↓ access from WCLKS ↓

3.0¹

ECBA

ECBH,

FCBH,

HCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from WCLKS ↓

1.0

0.5

Empty/full/thresh are invalid from the end of

hold until the new access is complete

HCBA

WPCA

WPCH

EQTH or GETH access from WCLKS ↓

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

4.5

3.0

ns

WPE is invalid, while PARGEN is active

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. All –F speed grade devices are 20% slower than the standard numbers.

v5.7

1-71

PLUS

ProASIC

Flash Family FPGAs

FIFO Reset

RESETB

Cycle Start

WRB/RBD¹

WCLKS, RCLKS¹

FULL

Cycle Start

EMPTY

EQTH, GETH

t

CBRSS

t

, t

t

ERSA FRSA

CBRSH

t

WBRSH

t

THRSA

t

RSL

t

WBRSS

Notes:

1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.

2. The plot shows the normal operation status.

Figure 1-48 • FIFO Reset

Table 1-66 • T_J= 0°C to 110°C; V_DD= 2.3 V to 2.7 V for Commercial/industrial

T_J= –55°C to 150°C, V_DD= 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol t_xxx

CBRSH¹

CBRSS¹

ERSA

Description

WCLKS or RCLKS ↑ hold from RESETB ↑

WCLKS or RCLKS ↓ setup to RESETB ↑

New EMPTY ↑ access from RESETB ↓

FULL ↓ access from RESETB ↓

RESETB low phase

Min.

1.5

3.0

7.5

4.5

1.5

Max.

Units

ns

Notes

Synchronous mode only

ns

FRSA

ns

RSL

ns

THRSA

WBRSH¹

WBRSS¹

Notes:

EQTH or GETH access from RESETB ↓

WB ↓ hold from RESETB ↑

ns

Asynchronous mode only

WB ↑ setup to RESETB ↑

ns

1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.

2. All –F speed grade devices are 20% slower than the standard numbers.

1-72

v5.7

PLUS

ProASIC

Flash Family FPGAs

TMS

Test Mode Select

Pin Description

The TMS pin controls the use of boundary-scan circuitry.

This pin has an internal pull-up resistor.

User Pins

TCK

Test Clock

I/O

User Input/Output

Clock input pin for boundary scan (maximum 10 MHz). Actel

recommends adding a nominal 20 kΩ pull-up resistor to this

pin.

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with standard LVTTL and LVCMOS

specifications. Unused I/O pins are configured as inputs

with pull-up resistors.

TDI

Test Data In

Serial input for boundary scan. A dedicated pull-up

resistor is included to pull this pin high when not being

driven.

NC

No Connect

To maintain compatibility with other Actel ProASIC^PLUS

products, it is recommended that this pin not be

connected to the circuitry on the board.

TDO

Test Data Out

Serial output for boundary scan. Actel recommends

adding a nominal 20kΩ pull-up resistor to this pin.

GL

Global Pin

TRST

Test Reset Input

Low skew input pin for clock or other global signals. This

pin can be configured with an internal pull-up resistor.

When it is not connected to the global network or the

clock conditioning circuit, it can be configured and used

as a normal I/O.

Asynchronous, active-low input pin for resetting

boundary-scan circuitry. This pin has an internal pull-up

resistor. For more information, please refer to Power-up

Behavior of ProASIC^PLUSDevices application note.

GLMX

Global Multiplexing Pin

Special Function Pins

Low skew input pin for clock or other global signals. This

pin can be used in one of two special ways (refer to

Actel’s Using ProASIC^PLUSClock Conditioning Circuits).

RCK

Running Clock

A free running clock is needed during programming if

the programmer cannot guarantee that TCK will be

uninterrupted. If not used, this pin has an internal pull-

up and can be left floating.

When the external feedback option is selected for the

PLL block, this pin is routed as the external feedback

source to the clock conditioning circuit.

In applications where two different signals access the

same global net at different times through the use of

GLMXx and GLMXLx macros, this pin will be fixed as one

of the source pins.

NPECL

User Negative Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

This pin can be configured with an internal pull-up

resistor. When it is not connected to the global network

or the clock conditioning circuit, it can be configured and

used as any normal I/O. If not used, the GLMXx pin will

be configured as an input with pull-up.

PPECL

User Positive Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

AVDD

PLL Power Supply

Analog V_DDshould be V_DD(core voltage) 2.5 V (nominal)

and be decoupled from GND with suitable decoupling

capacitors to reduce noise. For more information, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note. If the clock conditioning circuitry is not

used in a design, AVDD can either be left floating or tied

to 2.5 V.

Dedicated Pins

GND

Ground

Common ground supply voltage.

V

Logic Array Power Supply Pin

DD

2.5 V supply voltage.

AGND

PLL Power Ground

V

I/O Pad Power Supply Pin

DDP

The analog ground can be connected to the system

ground. For more information, refer to Actel’s Using

ProASIC^PLUSClock Conditioning Circuits application note.

If the PLLs or clock conditioning circuitry are not used in

a design, AGND should be tied to GND.

2.5 V or 3.3 V supply voltage.

v5.7

1-73

PLUS

ProASIC

Flash Family FPGAs

V

Programming Supply Pin

finite length conductors that distribute the power to the

device. This can be accomplished by providing sufficient

bypass capacitance between the V_PPand V_PNpins and

GND (using the shortest paths possible). Without

sufficient bypass capacitance to counteract the

inductance, the V_PPand V_PNpins may incur a voltage

spike beyond the voltage that the device can withstand.

This issue applies to all programming configurations.

PP

This pin may be connected to any voltage between GND

and 16.5 V during normal operation, or it can be left

unconnected.²For information on using this pin during

programming,

ProASIC^PLUSDevices application note. Actel recommends

floating the pin or connecting it to V_DDP

see

the

In-System Programming

.

V

Programming Supply Pin

PN

The solution prevents spikes from damaging the

ProASIC^PLUSdevices. Bypass capacitors are required for

the V_PPand V_PNpads. Use a 0.01 µF to 0.1 µF ceramic

capacitor with a 25 V or greater rating. To filter low-

frequency noise (decoupling), use a 4.7 µF (low ESR, <1

<Ω, tantalum, 25 V or greater rating) capacitor. The

capacitors should be located as close to the device pins as

possible (within 2.5 cm is desirable). The smaller, high-

frequency capacitor should be placed closer to the device

pins than the larger low-frequency capacitor. The same

dual-capacitor circuit should be used on both the V_PPand

V_PNpins (Figure 1-49).

This pin may be connected to any voltage between 0.5V

and –13.8 V during normal operation, or it can be left

unconnected.³For information on using this pin during

programming,

see

the

In-System Programming

ProASIC^PLUSDevices application note. Actel recommends

floating the pin or connecting it to GND.

Recommended Design Practice

for V /V

PN PP

PLUS

ProASIC

Devices – APA450, APA600,

ProASIC

APA300

Devices – APA075, APA150,

APA750, APA1000

Bypass capacitors are required from V_PPto GND and V_PN

to GND for all ProASIC^PLUSdevices during programming.

During the erase cycle, ProASIC^PLUSdevices may have

current surges on the V_PPand V_PNpower supplies. The

only way to maintain the integrity of the power

distribution to the ProASIC^PLUSdevice during these

current surges is to counteract the inductance of the

These devices do not require bypass capacitors on the V_PP

and V_PNpins as long as the total combined distance of

the programming cable and the trace length on the

board is less than or equal to 30 inches. Note: For trace

lengths greater than 30 inches, use the bypass capacitor

recommendations in the previous section.

2.5cm

_

+

V

PP

0.1μF

+

to

4.7μF

Programming

Header

or

Actel

ProASIC

Device

0.01μF

PLUS

Supplies

_

+

V

PN

0.1μF

to

0.01μF

Figure 1-49 • ProASIC^PLUSV_PPand V_PNCapacitor Requirements

2. There is a nominal 40 kΩ pull-up resistor on V_PP.

3. There is a nominal 40 kΩ pull-down resistor on V_PN

.

1-74

v5.7

PLUS

ProASIC

Flash Family FPGAs

Package Pin Assignments

100-Pin TQFP

100

1

100-Pin TQFP

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-1

PLUS

ProASIC

Flash Family FPGAs

100-Pin TQFP

APA075

APA150

APA075

APA150

APA075

APA150

Number

Function

Number

Function

Number

Function

1

GND

I/O

GND

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

V_DD

GND

V_DDP

GND

I/O

V_DD

GND

V_DDP

GND

I/O

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

2

3

I/O

4

I/O

5

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

6

I/O

7

I/O

8

I/O

9

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O / GLMX1 I/O / GLMX1

I/O

I/O / GL1

AGND

I/O / GL1

AGND

I/O

TCK

TDI

TCK

TDI

I/O

NPECL1

AVDD

NPECL1

AVDD

I/O

TMS

V_DDP

GND

V_PP

TMS

V_DDP

GND

V_PP

I/O

PPECL1 / Input PPECL1 / Input

I/O

I/O / GL2

V_DD

I/O

I/O / GL2

V_DD

I/O

GND

V_DDP

GND

V_DD

I/O

GND

V_DDP

GND

V_DD

I/O

V_PN

I/O

TDO

TRST

RCK

I/O

TDO

TRST

RCK

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

I/O / GL3

I/O

PPECL2 / Input PPECL2 / Input

I/O

AVDD

NPECL2

AGND

AVDD

NPECL2

AGND

I/O

I/O / GL4

V_DDP

I/O

I/O / GLMX2 I/O / GLMX2

I/O

GND

V_DD

I/O

GND

V_DD

I/O

2-2

v5.7

PLUS

ProASIC

Flash Family FPGAs

144-Pin TQFP

144

1

144-Pin

TQFP

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-3

PLUS

ProASIC

Flash Family FPGAs

144-Pin TQFP

Number

APA075

Function

APA075

Function

APA075

Function

APA075

Function

Number

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

Number

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

1

2

I/O

73

V_PP

V_PN

I/O

74

3

I/O

75

TDO

TRST

RCK

I/O

4

I/O

76

I/O

5

I/O

77

I/O

6

I/O

78

I/O

7

I/O

79

I/O

8

I/O

80

I/O

9

V_DD

GND

V_DDP

I/O

81

V_DDP

GND

I/O

V_DDP

GND

V_DD

I/O

10

11

12

13

14

15

16

17

18

19

20

GND

V_DDP

I/O

82

83

84

I/O

85

I/O

86

I/O

I/O / GLMX1

I/O / GL1

AGND

NPECL1

AVDD

I/O

87

I/O

88

I/O / GL3

I/O

89

PPECL2 /

Input

I/O

90

91

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

PPECL1 /

Input

I/O

92

I/O

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

I/O / GL2

I/O

93

I/O

94

I/O

95

I/O

96

I/O

97

I/O

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

I/O

98

V_DDP

GND

V_DD

GND

V_DDP

I/O

99

100

101

102

103

104

105

106

107

108

I/O

TCK

TDI

TMS

NC

I/O

2-4

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

208

1

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-5

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

APA075

APA150

APA300

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

Number

Function

GND

I/O

Function

GND

I/O

1

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

V_DD

GND

I/O

V_DD

GND

I/O

V_DD

GND

I/O

V_DD

GND

I/O

V_DD

GND

I/O

GND

I/O

GND

I/O

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

2-6

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

Number

APA075

Function

APA150

Function

APA300

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

V_DD

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

v5.7

2-7

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

APA075

APA150

APA300

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

Number

Function

V_DD

V_DDP

I/O

Function

V_DD

V_DDP

I/O

71

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

72

73

74

I/O

75

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

I/O

81

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

82

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

89

90

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

96

I/O

97

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

98

99

I/O

100

101

102

103

104

105

I/O

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

2-8

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

Number

APA075

Function

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PN

TDO

TRST

RCK

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

I/O / GL3

PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

V_DDP

I/O

v5.7

2-9

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

APA075

APA150

APA300

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

Number

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

Function

GND

V_DD

I/O

Function

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

2-10

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin PQFP

Number

APA075

Function

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DDP

v5.7

2-11

PLUS

ProASIC

Flash Family FPGAs

208-Pin CQFP

No. 1

1

2

3

4

156

155

154

153

Ceramic

Tie Bar

31

32

33

34

35

36

37

38

39

142

141

140

139

138

137

136

135

134

208-Pin CQFP

49

50

51

52

108

107

106

105

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

2-12

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin CQFP

APA300 APA600

Number

APA300

APA600

APA1000

Function

Number

APA1000

Function

GND

I/O

Function

V_DD

I/O

Function

V_DD

I/O

1

GND

I/O

GND

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

V_DD

I/O

2

3

I/O

4

I/O

5

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

V_DDP

GND

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

V_DD

GND

I/O

V_DD

GND

I/O

GND

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

V_DDP

I/O / GLMX1

I/O / GL2

AGND

NPECL1

AVDD

I/O

PPECL1 / Input PPECL1 / Input PPECL1 / Input

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O / GL1

I/O

GND

I/O

GND

I/O

GND

I/O

v5.7

2-13

PLUS

ProASIC

Flash Family FPGAs

208-Pin CQFP

APA300

APA600

APA1000

Function

Number

APA300

Function

APA600

Function

APA1000

Function

Number

Function

V_DD

V_DDP

I/O

71

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

V_PP

V_PN

TDO

TRST

RCK

I/O

V_PP

V_PN

TDO

TRST

RCK

I/O

72

V_PN

TDO

TRST

RCK

I/O

73

74

I/O

75

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

I/O

81

GND

I/O

GND

I/O

GND

I/O

82

I/O

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

GND

V_DDP

I/O

88

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

89

90

I/O

91

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

92

I/O

93

I/O

I/O / GL3

94

I/O

PPECL2 / Input PPECL2 / Input PPECL2 / Input

95

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

GND

AVDD

NPECL2

AGND

I/O / GL4

I/O / GLMX2

I/O

96

I/O

97

GND

I/O

GND

I/O

GND

I/O

98

99

I/O

100

101

102

103

104

105

I/O

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

TCK

TDI

TMS

V_DDP

GND

I/O

V_DDP

I/O

2-14

v5.7

PLUS

ProASIC

Flash Family FPGAs

208-Pin CQFP

APA300 APA600

Number

APA300

APA600

APA1000

Function

Number

APA1000

Function

GND

V_DD

I/O

Function

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

GND

V_DD

I/O

GND

V_DD

I/O

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

GND

I/O

GND

I/O

GND

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

GND

V_DDP

I/O

]GND

V_DDP

I/O

GND

V_DDP

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

V_DD

I/O

V_DDP

I/O

v5.7

2-15

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

1

2

3

4

264

263

262

261

Pin 1

Ceramic

Tie Bar

223

222

221

220

219

218

217

216

215

41

42

43

44

45

46

47

48

49

352-Pin CQFP

85

86

87

88

180

179

178

177

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

2-16

v5.7

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

APA300 APA600

APA300

APA600

APA1000

Function

APA1000

Function

Pin Number

Function

Pin Number

38

Function

I/O / GLMX1

I/O / GL2

AGND

Function

I/O / GLMX1

I/O / GL2

AGND

1

I/O

I/O / GLMX1

I/O / GL2

AGND

2

I/O

39

3

I/O

40

4

I/O

41

AVDD

5

I/O

42

NPECL1

6

I/O

43

PPECL1 / Input PPECL1 / Input PPECL1 / Input

7

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

44

I/O / GL1

I/O

I/O / GL1

I/O

I/O / GL1

I/O

8

45

9

46

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

47

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

48

I/O

49

I/O

50

I/O

51

I/O

52

I/O

53

I/O

54

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

55

I/O

56

I/O

57

I/O

58

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

59

I/O

60

I/O

61

I/O

62

I/O

63

I/O

64

I/O

65

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

66

I/O

67

I/O

68

I/O

69

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

70

I/O

71

I/O

72

I/O

73

I/O

74

I/O

v5.7

2-17

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

APA300

Function

APA600

Function

APA1000

Function

APA300

APA600

Function

APA1000

Function

Pin Number

75

Pin Number

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Function

GND

V_DD

I/O

GND

V_DD

I/O

GND

V_DD

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

81

I/O

82

I/O

83

I/O

84

I/O

85

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

86

I/O

87

I/O

88

I/O

89

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

90

I/O

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

96

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

97

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

I/O

2-18

v5.7

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

APA300 APA600

APA300

APA600

APA1000

Function

APA1000

Function

Pin Number

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

Function

Pin Number

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

Function

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

TCK

TDI

TCK

TDI

TCK

TDI

I/O

TMS

I/O

TMS

I/O

TMS

I/O

VPP

VPN

TDO

TRST

RCK

I/O

VPP

VPN

TDO

TRST

RCK

I/O

VPP

VPN

TDO

TRST

RCK

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

V_DDP

GND

V_DD

V_DDP

GND

V_DD

I/O

I/O / GL3

PPECL2 / Input PPECL2 / Input PPECL2 / Input

v5.7

2-19

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

APA300

Function

APA600

APA1000

Function

APA300

Function

APA600

Function

APA1000

Function

Pin Number

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

Function

NPECL2

AVDD

AGND

I/O / GL4

I/O / GLMX2

I/O

Pin Number

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

NPECL2

AVDD

AGND

I/O / GL4

I/O / GLMX2

I/O

NPECL2

AVDD

AGND

I/O / GL4

I/O / GLMX2

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

V_DD

GND

V_DD

GND

V_DD

GND

2-20

v5.7

PLUS

ProASIC

Flash Family FPGAs

352-Pin CQFP

APA300 APA600

APA300

APA600

APA1000

Function

APA1000

Function

Pin Number

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

Function

V_DDP

I/O

Function

Pin Number

334

Function

V_DDP

I/O

V_DDP

I/O

335

I/O

336

I/O

337

I/O

338

I/O

339

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

340

I/O

341

I/O

342

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

343

I/O

344

I/O

345

I/O

346

I/O

347

I/O

348

I/O

349

I/O

350

V_DD

GND

V_DDP

V_DD

GND

V_DDP

V_DD

GND

V_DDP

I/O

351

I/O

352

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

v5.7

2-21

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

A1 Ball Pad Corner

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

2-22

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

APA150

APA300

APA450

APA600

APA750

APA1000

Function

Number

Function

V_DDP

I/O

A1

A2

V_DDP

NC

I/O

V_DDP

NC

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

A3

A4

I/O

A5

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

I/O

NC

V_DDP

NC

I/O

NC

V_DDP

NC

I/O

V_DDP

NC

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

B2

B3

B4

I/O

B5

I/O

B6

I/O

B7

I/O

B8

I/O

v5.7

2-23

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

APA150

APA300

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

Number

B9

Function

I/O

V_DDP

I/O

V_DDP

NC

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

I/O

NC

V_DDP

NC

V_DDP

NC

I/O

NC

V_DDP

I/O

C2

C3

V_DDP

NC

I/O

C4

C5

C6

C7

C8

I/O

C9

I/O

C10

C11

C12

C13

C14

C15

C16

I/O

2-24

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

I/O

V_DDP

NC

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

NC

V_DDP

NC

V_DDP

NC

I/O

NC

V_DDP

NC

I/O

V_DDP

NC

I/O

V_DDP

I/O

D2

I/O

D3

I/O

D4

V_DDP

I/O

D5

D6

I/O

D7

I/O

D8

I/O

D9

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

I/O

NC

V_DDP

NC

V_DDP

I/O

V_DDP

I/O

v5.7

2-25

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

D25

D26

E1

NC

V_DD

I/O

NC

I/O

NC

I/O

E2

I/O

E3

I/O

E4

I/O

E5

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

I/O

V_DD

NC

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

F2

I/O

F3

I/O

F4

I/O

F5

V_DD

F22

2-26

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

F23

F24

F25

F26

G1

NC

I/O

NC

V_DD

NC

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

G2

I/O

G3

I/O

G4

I/O

G5

V_DD

I/O

G22

G23

G24

G25

G26

H1

I/O

H2

I/O

H3

I/O

H4

I/O

H5

V_DD

I/O

H22

H23

H24

H25

H26

J1

I/O

J2

I/O

J3

I/O

J4

I/O

J5

I/O

J22

J23

J24

J25

J26

I/O

v5.7

2-27

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

K1

K2

K3

K4

K5

I/O

K22

K23

K24

K25

K26

L1

I/O

L2

I/O

L3

I/O

L4

I/O

L5

I/O

L11

L12

L13

L14

L15

L16

L22

L23

L24

L25

L26

M1

M2

M3

M4

M5

M11

M12

M13

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

I/O / GL1

I/O / GL2

I/O

I/O / GL1

I/O / GL2

I/O

I/O / GL1

I/O / GL2

I/O

I/O / GL1

I/O / GL2

I/O

I/O / GL1

I/O / GL2

I/O

I/O / GL1

I/O / GL2

I/O

GND

2-28

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

M14

M15

M16

M22

M23

M24

M25

M26

N1

GND

I/O / GL4

I/O

I/O / GL4

I/O

I/O / GL4

I/O

I/O / GL4

I/O

I/O / GL4

I/O

I/O / GL4

I/O

N2

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

I/O / GLMX1

AGND

PPECL1 / Input

AVDD

GND

N3

N4

N5

N11

N12

N13

N14

N15

N16

N22

N23

N24

N25

N26

P1

GND

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

NPECL2

I/O / GL3

AVDD

I/O / GLMX2

AGND

I/O

P2

I/O

P3

I/O

P4

I/O

P5

NPECL1

GND

NPECL1

GND

NPECL1

GND

NPECL1

GND

NPECL1

GND

NPECL1

GND

P11

P12

P13

P14

P15

GND

v5.7

2-29

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

P16

P22

P23

P24

P25

P26

R1

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

PPECL2 / Input

I/O

PPECL2 / Input

I/O

PPECL2 / Input

I/O

PPECL2 / Input

I/O

PPECL2 / Input

I/O

PPECL2 / Input

I/O

R2

I/O

R3

I/O

R4

I/O

R5

I/O

R11

R12

R13

R14

R15

R16

R22

R23

R24

R25

R26

T1

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

T2

I/O

T3

I/O

T4

I/O

T5

I/O

T11

T12

T13

T14

T15

T16

T22

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

2-30

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

APA150

APA300

APA450

APA600

APA750

APA1000

Function

Number

Function

I/O

V_DD

I/O

T23

T24

T25

T26

U1

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

U2

U3

U4

U5

U22

U23

U24

U25

U26

V1

V2

V3

V4

V5

V22

V23

V24

V25

V26

W1

W2

W3

W4

W5

W22

W23

W24

W25

W26

v5.7

2-31

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

Y1

Y2

Y3

Y4

Y5

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

NC

V_DD

NC

I/O

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA22

AA23

AA24

AA25

AA26

AB1

NC

V_DD

NC

V_DD

I/O

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

I/O

AB10

AB11

AB12

AB13

AB14

I/O

2-32

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

I/O

V_DD

I/O

NC

I/O

V_DDP

I/O

V_DD

I/O

V_DDP

I/O

TMS

TDO

I/O

V_DD

I/O

V_DDP

I/O

TMS

TDO

I/O

V_DD

NC

V_DDP

NC

I/O

V_DD

I/O

V_DD

I/O

NC

I/O

AC2

I/O

AC3

I/O

AC4

V_DDP

NC

I/O

V_DDP

I/O

AC5

AC6

I/O

TMS

TDO

I/O

AC7

I/O

AC8

I/O

AC9

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

I/O

TMS

TDO

TMS

TDO

TMS

TDO

v5.7

2-33

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

AC23

AC24

AC25

AC26

AD1

V_DDP

RCK

NC

V_DDP

NC

I/O

V_DDP

RCK

NC

I/O

V_DDP

RCK

I/O

V_DDP

RCK

I/O

V_DDP

RCK

I/O

V_DDP

RCK

I/O

NC

I/O

NC

I/O

AD2

I/O

AD3

V_DDP

NC

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

AD4

AD5

I/O

AD6

I/O

AD7

I/O

AD8

I/O

AD9

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

I/O

NC

TCK

V_PP

NC

V_DDP

NC

V_DDP

NC

TCK

V_PP

NC

V_DDP

NC

V_DDP

NC

I/O

TCK

V_PP

NC

V_DDP

I/O

TCK

V_PP

I/O

TCK

V_PP

I/O

TCK

V_PP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

AE2

AE3

AE4

I/O

2-34

v5.7

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

AE5

AE6

NC

I/O

NC

I/O

AE7

I/O

AE8

I/O

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

I/O

NC

V_PN

TRST

V_DDP

NC

I/O

NC

V_PN

TRST

V_DDP

NC

I/O

V_PN

TRST

V_DDP

I/O

V_PN

TRST

V_DDP

I/O

V_PN

TRST

V_DDP

I/O

V_PN

TRST

V_DDP

I/O

AF2

AF3

AF4

I/O

AF5

I/O

AF6

I/O

AF7

I/O

AF8

NC

I/O

AF9

I/O

AF10

AF11

AF12

I/O

v5.7

2-35

PLUS

ProASIC

Flash Family FPGAs

456-Pin PBGA

Number

APA150

Function

APA300

Function

APA450

Function

APA600

Function

APA750

Function

APA1000

Function

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

I/O

NC

TDI

NC

V_DDP

NC

TDI

NC

V_DDP

I/O

TDI

I/O

TDI

I/O

TDI

I/O

TDI

I/O

V_DDP

2-36

v5.7

PLUS

ProASIC

Flash Family FPGAs

144-Pin FBGA

A1 Ball Pad Corner

2

12 11 10

9

8

7

6

5

4

3

1

A

B

C

D

E

F

G

H

J

K

L

M

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-37

PLUS

ProASIC

Flash Family FPGAs

144-FBGA Pin

APA150

APA075

APA150

APA300

APA450

APA075

APA300

APA450

Number Function Function Function Function

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

B1

I/O

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

E1

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

E2

B2

GND

I/O

GND

I/O

GND

I/O

GND

I/O

E3

I/O

B3

E4

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

B4

I/O

E5

B5

I/O

E6

V_DDP

AVDD

V_DDP

V_DD

V_DDP

AVDD

V_DDP

V_DD

V_DDP

AVDD

V_DDP

V_DD

V_DDP

AVDD

V_DDP

V_DD

B6

I/O

E7

B7

I/O

E8

B8

I/O

E9

B9

I/O

E10

E11

E12

F1

B10

B11

B12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

D1

I/O

NPECL2

AGND

I/O / GL2

AGND

NPECL2

AGND

I/O / GL2

AGND

NPECL2

AGND

I/O / GL2

AGND

NPECL2

AGND

I/O / GL2

AGND

GND

I/O

GND

I/O

GND

I/O

GND

I/O

F2

I/O / GL1

I/O

I/O / GL1

I/O

I/O / GL1

I/O

I/O / GL1

I/O

F3

I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1

F4

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

F5

F6

I/O

F7

I/O

F8

I/O

F9

I/O / GL4

GND

I/O / GL4

GND

I/O / GL4

GND

I/O / GL4

GND

I/O

F10

F11

I/O

PPECL2 /

Input

PPECL2 /

Input

PPECL2 /

Input

PPECL2 /

Input

I/O

F12

I/O / GL3

I/O

2-38

v5.7

PLUS

ProASIC

Flash Family FPGAs

144-FBGA Pin

APA150

144-FBGA Pin

APA150

APA075

APA300

APA450

APA075

APA300

APA450

Number Function Function Function Function

G1

PPECL1 /

Input

PPECL1 /

Input

PPECL1 /

Input

PPECL1 /

Input

K1

K2

I/O

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

J1

GND

AVDD

NPECL1

GND

I/O

GND

AVDD

NPECL1

GND

I/O

GND

AVDD

NPECL1

GND

I/O

GND

AVDD

NPECL1

GND

I/O

K3

I/O

K4

I/O

K5

I/O

K6

I/O

K7

GND

I/O

GND

I/O

GND

I/O

GND

I/O

K8

K9

I/O

K10

K11

K12

L1

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

L2

L3

I/O

L4

I/O

L5

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

L6

L7

I/O

L8

I/O

L9

TMS

RCK

I/O

TMS

RCK

I/O

TMS

RCK

I/O

TMS

RCK

I/O

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

TRST

I/O

TRST

I/O

TRST

I/O

TRST

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

J2

I/O

J3

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

J4

I/O

J5

I/O

J6

I/O

J7

V_DD

TCK

I/O

V_DD

TCK

I/O

V_DD

TCK

I/O

V_DD

TCK

I/O

J8

TDI

V_DDP

V_PP

V_PN

TDI

V_DDP

V_PP

V_PN

TDI

V_DDP

V_PP

V_PN

TDI

V_DDP

V_PP

V_PN

J9

J10

J11

J12

TDO

I/O

TDO

I/O

TDO

I/O

TDO

I/O

v5.7

2-39

PLUS

ProASIC

Flash Family FPGAs

256-Pin FBGA

A1 Ball Pad Corner

1

9

7

6

4

3

2

16 15 14 13 12 11 10

8

5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

2-40

v5.7

PLUS

ProASIC

Flash Family FPGAs

256-Pin FBGA

APA300

256-Pin FBGA

APA300

APA150

APA450

APA600

APA150

APA450

APA600

Number Function Function Function Function

A1

A2

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

C4

C5

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

A3

C6

A4

C7

A5

C8

A6

C9

A7

C10

C11

C12

C13

C14

C15

C16

D1

A8

A9

A10

A11

A12

A13

A14

A15

A16

B1

D2

D3

D4

B2

D5

B3

D6

B4

D7

B5

D8

B6

D9

B7

D10

D11

D12

D13

D14

D15

D16

E1

B8

B9

B10

B11

B12

B13

B14

B15

B16

C1

E2

E3

E4

C2

E5

C3

E6

v5.7

2-41

PLUS

ProASIC

Flash Family FPGAs

256-Pin FBGA

APA300

APA150

APA300

APA450

APA600

APA150

APA450

APA600

Number Function Function Function Function

E7

E8

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

G10

G11

G12

G13

G14

G15

G16

H1

GND

V_DD

GND

V_DD

GND

V_DD

GND

V_DD

E9

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

E10

E11

E12

E13

E14

E15

E16

F1

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

I/O / GL1

NPECL1

I/O / GL1

NPECL1

I/O / GL1

NPECL1

I/O / GL1

NPECL1

I/O

H2

I/O

H3

I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1

I/O

H4

AGND

I/O

AGND

I/O

AGND

I/O

AGND

I/O

F2

I/O

H5

F3

I/O

H6

V_DD

F4

I/O

H7

GND

V_DD

GND

V_DD

GND

V_DD

GND

V_DD

F5

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

H8

F6

H9

F7

H10

H11

H12

H13

H14

H15

H16

J1

F8

F9

I/O

F10

F11

F12

F13

F14

F15

F16

G1

G2

G3

G4

G5

G6

G7

G8

G9

I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2

NPECL2

AGND

NPECL2

AGND

NPECL2

AGND

NPECL2

AGND

I/O / GL4

I/O / GL2

I/O / GL4

I/O / GL2

I/O / GL4

I/O / GL2

I/O / GL4

I/O / GL2

I/O

J2

PPECL1 /

Input

PPECL1 /

Input

PPECL1 /

Input

PPECL1 /

Input

I/O

J3

J4

AVDD

I/O

AVDD

I/O

AVDD

I/O

AVDD

I/O

J5

I/O

J6

V_DD

GND

V_DD

GND

V_DD

GND

V_DD

GND

V_DD

I/O

J7

V_DDP

V_DD

GND

V_DDP

V_DD

GND

V_DDP

V_DD

GND

V_DDP

V_DD

GND

J8

J9

J10

J11

2-42

v5.7

PLUS

ProASIC

Flash Family FPGAs

256-Pin FBGA

APA300

256-Pin FBGA

APA300

APA150

APA450

APA600

APA150

APA450

APA600

Number Function Function Function Function

J12

J13

I/O

L14

L15

L16

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

N1

I/O

PPECL2 /

Input

PPECL2 /

Input

PPECL2 /

Input

PPECL2 /

Input

I/O

J14

J15

J16

K1

I/O

AVDD

I/O / GL3

I/O

AVDD

I/O / GL3

I/O

AVDD

I/O / GL3

I/O

AVDD

I/O / GL3

I/O

K2

I/O

K3

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

K4

I/O

K5

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

K6

I/O

K7

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

K8

K9

K10

K11

K12

K13

K14

K15

K16

L1

I/O

N2

I/O

N3

I/O

N4

I/O

L2

I/O

N5

I/O

L3

I/O

N6

I/O

L4

I/O

N7

I/O

L5

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

N8

I/O

L6

N9

I/O

L7

N10

N11

N12

N13

N14

N15

N16

I/O

L8

I/O

L9

I/O

L10

L11

L12

L13

I/O

RCK

I/O

RCK

I/O

RCK

I/O

RCK

I/O

v5.7

2-43

PLUS

ProASIC

Flash Family FPGAs

256-Pin FBGA

APA300

APA150

APA300

APA450

APA600

APA150

APA450

APA600

Number Function Function Function Function

P1

P2

I/O

TCK

V_PP

TRST

I/O

TDI

V_PN

TDO

GND

I/O

TCK

V_PP

TRST

I/O

TDI

V_PN

TDO

GND

I/O

TCK

V_PP

TRST

I/O

TDI

V_PN

TDO

GND

I/O

TCK

V_PP

TRST

I/O

TDI

V_PN

TDO

GND

I/O

T4

T5

I/O

P3

T6

I/O

P4

T7

I/O

P5

T8

I/O

P6

T9

I/O

P7

T10

T11

T12

T13

T14

T15

T16

I/O

P8

I/O

P9

I/O

P10

P11

P12

P13

P14

P15

P16

R1

I/O

TMS

GND

TMS

GND

TMS

GND

TMS

GND

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

T1

T2

T3

2-44

v5.7

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

A1 Ball Pad Corner

1

7

6

4

3

2

22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

5

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-45

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

A1

A2

GND

V_DDP

I/O

GND

V_DDP

I/O

B15

B16

B17

B18

B19

B20

B21

B22

C1

I/O

D7

D8

I/O

GND

I/O

NC

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

A3

I/O

D9

A4

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E1

A5

I/O

A6

I/O

A7

I/O

V_DDP

GND

V_DDP

NC

I/O

V_DDP

GND

V_DDP

I/O

A8

I/O

A9

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

B1

I/O

C2

I/O

C3

I/O

C4

I/O

C5

GND

I/O

GND

I/O

C6

I/O

C7

I/O

C8

V_DD

I/O

V_DD

I/O

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

D1

E2

I/O

E3

V_DDP

GND

V_DDP

I/O

V_DDP

GND

V_DDP

I/O

NC

V_DD

NC

I/O

E4

I/O

E5

V_DD

I/O

E6

E7

B2

E8

B3

I/O

E9

B4

I/O

GND

I/O

GND

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

B5

I/O

B6

I/O

B7

I/O

B8

I/O

V_DDP

I/O

V_DDP

I/O

B9

I/O

B10

B11

B12

B13

B14

I/O

D2

I/O

D3

NC

GND

I/O

D4

GND

I/O

D5

I/O

D6

I/O

2-46

v5.7

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

E21

E22

F1

I/O

NC

I/O

NC

I/O

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

H1

I/O

J5

J6

I/O

J7

I/O

F2

I/O

J8

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

F3

I/O

J9

F4

I/O

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

K1

F5

I/O

F6

I/O

F7

I/O

F8

I/O

F9

I/O

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H2

I/O

H3

V_DD

I/O

V_DD

I/O

H4

I/O

H5

I/O

H6

I/O

NC

I/O

H7

I/O

H8

I/O

H9

V_DDP

I/O

V_DDP

I/O

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

J1

K2

I/O

K3

NC

I/O

K4

I/O

V_DDP

I/O

V_DDP

I/O

K5

I/O

K6

I/O

K7

I/O

K8

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

K9

I/O

K10

K11

K12

K13

K14

K15

K16

K17

K18

I/O

V_DD

I/O

V_DD

I/O

J2

I/O

J3

NC

I/O

J4

I/O

v5.7

2-47

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

K19

K20

K21

K22

L1

I/O

M10

M11

M12

M13

M14

M15

M16

GND

V_DD

GND

V_DD

P1

P2

I/O

P3

I/O

P4

I/O

NC

I/O

P5

I/O

L2

I/O

P6

I/O

L3

I/O

PPECL2 /

Input

PPECL2 /

Input

P7

I/O

L4

I/O / GL1

NPECL1

I/O / GL1

NPECL1

P8

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

M17

M18

M19

M20

M21

M22

N1

I/O

AVDD

I/O / GL3

I/O

AVDD

I/O / GL3

I/O

L5

P9

L6

I/O / GLMX1 I/O / GLMX1

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

R1

L7

AGND

I/O

AGND

I/O

L8

I/O

L9

V_DD

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

M1

M2

M3

M4

M5

GND

V_DD

GND

V_DD

I/O

N2

I/O

N3

NC

I/O

N4

I/O

N5

I/O

N6

I/O

I/O / GLMX2 I/O / GLMX2

NC

I/O

N7

I/O

NPECL2

AGND

I/O / GL4

I/O

NPECL2

AGND

I/O / GL4

I/O

N8

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

N9

I/O

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

R2

I/O

R3

V_DD

I/O

V_DD

I/O

R4

I/O

R5

I/O

R6

I/O

R7

I/O

I/O / GL2

R8

I/O

PPECL1 /

Input

PPECL1 /

Input

R9

V_DDP

I/O

V_DDP

I/O

R10

R11

R12

R13

R14

M6

M7

M8

M9

AVDD

I/O

AVDD

I/O

NC

I/O

V_DDP

V_DD

I/O

2-48

v5.7

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

R15

R16

R17

R18

R19

R20

R21

R22

T1

I/O

V_DD

I/O

NC

I/O

RCK

I/O

NC

I/O

V_DD

I/O

RCK

I/O

U7

U8

I/O

V21

V22

W1

NC

I/O

U9

I/O

NC

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

V1

I/O

W2

I/O

W3

I/O

W4

GND

I/O

GND

I/O

W5

I/O

W6

I/O

W7

I/O

T2

TCK

V_PP

TRST

I/O

TCK

V_PP

TRST

I/O

W8

I/O

T3

W9

I/O

T4

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

Y1

I/O

T5

I/O

T6

NC

I/O

T7

I/O

T8

I/O

T9

I/O

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

U1

V2

I/O

V3

GND

I/O

GND

I/O

V4

TMS

GND

NC

I/O

TMS

GND

I/O

V5

I/O

V6

I/O

V7

I/O

V8

I/O

V9

I/O

V_DDP

I/O

V_DDP

I/O

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

I/O

Y2

I/O

Y3

I/O

Y4

I/O

Y5

GND

I/O

GND

I/O

Y6

I/O

Y7

I/O

U2

I/O

Y8

V_DD

I/O

V_DD

I/O

U3

TDI

V_PN

TDO

GND

TDI

V_PN

TDO

GND

Y9

U4

Y10

Y11

Y12

U5

I/O

U6

I/O

v5.7

2-49

PLUS

ProASIC

Flash Family FPGAs

484-Pin FBGA

Number

APA450

Function

APA600

Function

Number

APA450

Function

APA600

Function

Y13

Y14

I/O

V_DD

I/O

V_DD

I/O

AB5

AB6

I/O

Y15

AB7

I/O

Y16

AB8

I/O

Y17

I/O

AB9

I/O

Y18

GND

I/O

GND

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

I/O

Y19

I/O

Y20

I/O

Y21

NC

I/O

Y22

V_DDP

GND

V_DDP

I/O

V_DDP

GND

V_DDP

I/O

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB1

I/O

NC

I/O

V_DDP

GND

V_DDP

GND

I/O

NC

I/O

NC

I/O

V_DDP

GND

V_DDP

I/O

V_DDP

GND

V_DDP

I/O

AB2

AB3

AB4

2-50

v5.7

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

A1 Ball Pad Corner

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-51

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

A1

A2

GND

I/O

GND

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

I/O

C19

C20

C21

C22

C23

C24

C25

C26

D1

I/O

GND

I/O

GND

I/O

A3

I/O

A4

I/O

A5

I/O

A6

I/O

A7

I/O

A8

I/O

A9

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

I/O

D2

I/O

D3

I/O

D4

I/O

D5

I/O

D6

I/O

D7

I/O

GND

I/O

GND

I/O

D8

I/O

D9

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

I/O

C2

I/O

C3

I/O

C4

I/O

C5

I/O

C6

I/O

C7

I/O

GND

I/O

GND

I/O

C8

I/O

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

I/O

B2

I/O

B3

I/O

B4

I/O

B5

I/O

B6

I/O

B7

I/O

B8

I/O

B9

I/O

2-52

v5.7

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

E2

E3

I/O

GND

I/O

NC

I/O

GND

I/O

NC

I/O

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

I/O

V_DD

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_DDP

I/O

V_DD

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_DDP

G20

G21

G22

G23

G24

G25

G26

H1

NC

I/O

NC

I/O

E4

I/O

E5

I/O

E6

I/O

E7

I/O

E8

I/O

E9

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

H2

I/O

H3

I/O

H4

I/O

H5

I/O

H6

I/O

H7

V_DDP

V_DD

V_DDP

V_DD

I/O

V_DDP

V_DD

V_DDP

V_DD

I/O

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

J1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

F2

F3

F4

I/O

F5

I/O

F6

I/O

F7

I/O

F8

I/O

F9

I/O

F10

J2

I/O

v5.7

2-53

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

J3

I/O

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

L1

GND

V_DD

V_DDP

I/O

GND

V_DD

V_DDP

I/O

L21

L22

I/O

J4

J5

I/O

L23

I/O

J6

I/O

L24

I/O

J7

NC

L25

I/O

J8

V_DDP

V_DD

V_DDP

NC

V_DDP

V_DD

V_DDP

NC

L26

I/O

J9

M1

I/O

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

K1

M2

I/O

M3

I/O

M4

I/O

M5

I/O

M6

I/O

M7

I/O

M8

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

M9

I/O

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

N1

L2

I/O

L3

I/O

L4

I/O

L5

I/O

L6

I/O

L7

NC

I/O

L8

V_DDP

V_DD

GND

V_DD

V_DDP

NC

V_DDP

V_DD

GND

V_DD

V_DDP

NC

I/O

L9

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

K2

I/O

K3

I/O

K4

K5

K6

K7

K8

K9

K10

K11

I/O

V_DDP

V_DD

GND

V_DDP

V_DD

GND

I/O

I/O / GL1

AGND

I/O / GL1

AGND

N2

N3

I/O / GLMX1 I/O / GLMX1

2-54

v5.7

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

N4

N5

I/O

NPECL1

I/O

NPECL1

I/O

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

GND

V_DD

GND

V_DD

R20

R21

R22

R23

R24

R25

R26

T1

NC

I/O

NC

I/O

N6

I/O

N7

NC

I/O

N8

V_DDP

V_DD

V_DDP

V_DD

I/O

N9

I/O

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

P1

GND

V_DD

GND

V_DD

I/O

V_DDP

I/O

V_DDP

I/O

T2

I/O

T3

I/O

I/O / GLMX2 I/O / GLMX2

T4

I/O

T5

I/O

PPECL2 /

Input

PPECL2 /

Input

T6

I/O

T7

I/O

P25

P26

R1

AVDD

AGND

I/O

AVDD

AGND

I/O

T8

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

NC

V_DDP

NC

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

U1

R2

I/O

R3

I/O

I/O / GL3

I/O

I/O / GL3

I/O

R4

I/O

R5

I/O

NPECL2

I/O / GL4

I/O

NPECL2

I/O / GL4

I/O

R6

I/O

R7

NC

R8

V_DDP

V_DD

GND

V_DD

V_DDP

V_DD

GND

V_DD

V_DDP

I/O / GL2

AVDD

I/O

I/O / GL2

AVDD

I/O

R9

P2

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

P3

P4

I/O

P5

PPECL1 /

Input

PPECL1 /

Input

I/O

P6

P7

I/O

P8

V_DDP

V_DD

GND

V_DDP

V_DD

GND

I/O

P9

I/O

P10

P11

I/O

U2

I/O

v5.7

2-55

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

U3

U4

I/O

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

W1

V_DD

V_DDP

I/O

V_DD

V_DDP

I/O

W21

W22

W23

W24

W25

W26

Y1

I/O

V_DDP

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_DD

V_PP

I/O

V_DDP

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_DD

V_PP

I/O

U5

I/O

U6

I/O

U7

NC

U8

V_DDP

V_DD

GND

V_DD

V_DDP

NC

V_DDP

V_DD

GND

V_DD

V_DDP

NC

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V1

Y2

Y3

I/O

Y4

I/O

Y5

I/O

Y6

I/O

Y7

I/O

Y8

I/O

Y9

I/O

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

W2

I/O

W3

I/O

W4

I/O

W5

I/O

W6

I/O

W7

V_DD

V_DDP

V_DD

V_DDP

V_DD

V_DDP

V_DD

V_DDP

I/O

W8

I/O

W9

I/O

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

V2

I/O

V3

I/O

V4

I/O

V5

I/O

V6

I/O

V7

I/O

V8

V_DDP

V_DD

V_DDP

V_DD

V9

V10

V11

2-56

v5.7

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

APA600

APA750

Number

Function

Number

Function

Number

Function

AA4

AA5

I/O

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

I/O

TCK

TRST

I/O

GND

I/O

GND

I/O

TCK

TRST

I/O

GND

I/O

GND

I/O

AC22

AC23

AC24

AC25

AC26

AD1

TMS

RCK

I/O

TMS

RCK

I/O

AA6

GND

I/O

GND

I/O

AA7

I/O

AA8

I/O

AA9

I/O

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

I/O

AD2

I/O

AD3

I/O

AD4

I/O

AD5

I/O

AD6

I/O

AD7

I/O

AD8

I/O

AD9

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

I/O

AC2

I/O

AC3

I/O

TDO

GND

I/O

TDO

GND

I/O

AC4

I/O

AC5

I/O

AC6

I/O

AC7

I/O

AC8

I/O

AC9

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

I/O

AB2

I/O

AB3

I/O

AB4

I/O

AB5

I/O

TDI

V_PN

I/O

TDI

V_PN

I/O

AB6

GND

I/O

GND

I/O

AB7

AB8

I/O

AB9

I/O

GND

I/O

GND

I/O

AB10

AB11

AB12

I/O

AE2

I/O

AE3

I/O

AE4

v5.7

2-57

PLUS

ProASIC

Flash Family FPGAs

676-Pin FBGA

APA600

APA750

APA600

APA750

Number

Function

Number

Function

AE5

AE6

I/O

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

I/O

AE7

I/O

AE8

I/O

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

I/O

GND

I/O

GND

I/O

GND

I/O

AF2

AF3

AF4

AF5

AF6

I/O

AF7

I/O

AF8

I/O

AF9

I/O

AF10

AF11

AF12

AF13

I/O

2-58

v5.7

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

A1 Ball Pad Corner

3029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-59

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

A2

A3

GND

I/O

GND

I/O

B7

B8

I/O

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

D1

I/O

V_DDP

I/O

V_DD

NC

GND

I/O

V_DD

I/O

GND

I/O

V_DDP

I/O

V_DD

I/O

GND

I/O

V_DD

I/O

GND

I/O

A4

B9

I/O

A5

GND

I/O

GND

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

C1

I/O

A6

I/O

A7

GND

I/O

GND

I/O

A8

I/O

A9

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

B1

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

D2

GND

I/O

GND

I/O

GND

I/O

GND

I/O

D3

D4

GND

I/O

GND

I/O

D5

C2

D6

GND

I/O

GND

I/O

C3

V_DD

I/O

V_DD

I/O

D7

C4

D8

C5

V_DDP

I/O

V_DDP

I/O

D9

B2

C6

D10

D11

D12

D13

D14

B3

C7

I/O

B4

V_DD

I/O

V_DD

I/O

C8

I/O

B5

C9

I/O

B6

V_DD

C10

I/O

2-60

v5.7

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

E1

I/O

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

F1

I/O

F23

F24

F25

F26

F27

F28

F29

F30

G1

I/O

GND

I/O

GND

I/O

V_DDP

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

V_DD

I/O

GND

I/O

GND

I/O

V_DDP

I/O

V_DDP

I/O

G2

I/O

G3

I/O

GND

I/O

GND

I/O

G4

I/O

GND

I/O

GND

I/O

G5

V_DDP

I/O

V_DDP

I/O

F2

V_DD

I/O

V_DD

I/O

G6

V_DD

I/O

V_DD

I/O

F3

G7

V_DD

I/O

V_DD

I/O

F4

I/O

G8

GND

I/O

GND

I/O

F5

I/O

G9

V_DDP

I/O

V_DDP

I/O

E2

F6

GND

I/O

GND

I/O

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

E3

V_DDP

I/O

V_DDP

I/O

F7

I/O

E4

F8

I/O

E5

V_DD

I/O

V_DD

I/O

F9

I/O

E6

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

I/O

E7

V_DDP

I/O

V_DDP

I/O

E8

I/O

E9

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

I/O

V_DDP

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DDP

v5.7

2-61

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

G27

G28

G29

G30

H1

I/O

GND

I/O

GND

I/O

GND

I/O

J1

J2

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DDP

I/O

K5

K6

I/O

J3

I/O

K7

I/O

GND

I/O

J4

I/O

K8

I/O

J5

I/O

K9

NC

I/O

H2

I/O

J6

I/O

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

L1

V_DD

NC

V_DD

I/O

H3

I/O

J7

V_DDP

I/O

H4

I/O

J8

V_DDP

NC

V_DDP

I/O

H5

I/O

J9

V_DD

NC

V_DD

I/O

H6

I/O

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

K1

K2

K3

K4

H7

I/O

H8

GND

NC

GND

I/O

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

V_DD

NC

V_DD

I/O

V_DDP

I/O

L2

I/O

L3

I/O

L4

I/O

L5

I/O

L6

I/O

L7

I/O

L8

I/O

2-62

v5.7

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

L9

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L30

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

NC

V_DD

NC

I/O

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

N1

GND

V_DD

V_DDP

NC

GND

V_DD

V_DDP

I/O

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

N27

N28

N29

N30

P1

GND

V_DD

V_DDP

NC

GND

V_DD

V_DDP

I/O

V_DD

I/O

P2

I/O

P3

I/O

P4

I/O

P5

I/O

N2

I/O

P6

I/O

N3

I/O

P7

I/O

N4

I/O

P8

I/O

N5

I/O

P9

I/O

N6

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

V_DDP

V_DD

GND

V_DD

V_DDP

V_DD

GND

V_DD

I/O

N7

I/O

N8

I/O

N9

NC

I/O

N10

N11

N12

N13

N14

N15

N16

V_DDP

V_DD

GND

V_DDP

V_DD

GND

I/O

NC

V_DDP

V_DD

GND

I/O

V_DDP

V_DD

GND

v5.7

2-63

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

R1

V_DDP

I/O

V_DDP

I/O

R25

R26

R27

R28

R29

R30

T1

I/O

T29

T30

U1

AVDD

I/O

AVDD

I/O

NPECL2

AGND

NPECL2

AGND

I/O

U2

I/O

I/O / GLMX2 I/O / GLMX2

U3

I/O

U4

I/O

U5

I/O

T2

AVDD

I/O / GL2

AVDD

I/O / GL2

U6

I/O

T3

U7

I/O

T4

PPECL1 / Input PPECL1 / Input

U8

I/O

T5

I/O

U9

NC

I/O

R2

I/O / GLMX1 I/O / GLMX1

T6

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

V1

V_DDP

V_DD

GND

V_DD

V_DDP

NC

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

R3

AGND

NPECL1

I/O / GL1

I/O

AGND

NPECL1

I/O / GL1

I/O

T7

I/O

R4

T8

I/O

R5

T9

I/O

R6

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

R7

I/O

R8

I/O

R9

NC

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

V_DDP

V_DD

V_DDP

V_DD

GND

V_DD

GND

V_DD

I/O

V_DDP

I/O

V_DDP

I/O

PPECL2 / Input PPECL2 / Input

I/O

I/O / GL4

I/O / GL3

I/O / GL4

I/O / GL3

I/O

V2

I/O

2-64

v5.7

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

V3

V4

I/O

W7

W8

I/O

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

V_DD

NC

I/O

V_DD

I/O

V5

I/O

W9

NC

I/O

V6

I/O

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

W27

W28

W29

W30

Y1

V_DDP

V_DD

GND

V_DD

V_DDP

NC

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V7

I/O

V8

I/O

V9

NC

I/O

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

V27

V28

V29

V30

W1

W2

W3

W4

W5

W6

V_DDP

V_DD

GND

V_DD

V_DDP

NC

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

Y2

I/O

Y3

I/O

Y4

I/O

Y5

I/O

NC

V_DD

NC

V_DDP

I/O

Y6

I/O

V_DD

I/O

Y7

I/O

Y8

I/O

V_DDP

I/O

Y9

NC

I/O

Y10

NC

I/O

v5.7

2-65

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AB1

V_DDP

NC

V_DD

NC

I/O

V_DDP

I/O

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AC1

NC

V_DD

I/O

V_DD

I/O

V_DDP

I/O

GND

I/O

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AD1

GND

I/O

GND

I/O

V_DDP

I/O

V_DD

I/O

GND

I/O

GND

I/O

AD2

I/O

AD3

I/O

AD4

I/O

AD5

V_DDP

I/O

V_DDP

I/O

AC2

I/O

AD6

I/O

AC3

I/O

AD7

V_DD

I/O

V_DD

I/O

AC4

I/O

AD8

I/O

AC5

I/O

AD9

V_DDP

I/O

V_DDP

I/O

AB2

I/O

AC6

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AB3

I/O

AC7

I/O

AB4

I/O

AC8

GND

NC

I/O

AB5

I/O

AC9

I/O

AB6

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

I/O

AB7

V_DDP

I/O

V_DDP

I/O

AB8

I/O

AB9

V_DD

NC

V_DD

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

I/O

V_DDP

TCK

V_DD

TRST

V_DDP

TCK

V_DD

TRST

V_DDP

I/O

2-66

v5.7

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

AD27

AD28

AD29

AD30

AE1

I/O

GND

I/O

V_DD

I/O

GND

I/O

GND

I/O

V_DD

I/O

GND

I/O

V_DD

I/O

GND

I/O

GND

I/O

V_DD

I/O

AF1

AF2

GND

I/O

GND

I/O

AG5

AG6

I/O

AF3

V_DDP

I/O

V_DDP

I/O

AG7

I/O

AF4

AG8

I/O

AF5

V_DD

I/O

V_DD

I/O

AG9

I/O

AE2

AF6

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AH1

I/O

AE3

AF7

V_DDP

I/O

V_DDP

I/O

AE4

AF8

I/O

AE5

AF9

I/O

AE6

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AF30

AG1

AG2

AG3

AG4

I/O

AE7

I/O

AE8

I/O

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

I/O

GND

RCK

V_DD

I/O

GND

RCK

V_DD

I/O

V_DDP

I/O

V_DDP

I/O

V_DD

TDO

V_DDP

V_PN

GND

I/O

V_DD

TDO

V_DDP

V_PN

GND

I/O

GND

I/O

GND

I/O

AH2

AH3

V_DD

I/O

V_DD

I/O

AH4

AH5

V_DDP

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

AH6

AH7

I/O

GND

AH8

I/O

v5.7

2-67

PLUS

ProASIC

Flash Family FPGAs

896-Pin FBGA

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

Number

APA750

Function

APA1000

Function

AH9

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AJ1

I/O

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AK2

I/O

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_DD

I/O

V_DD

I/O

V_DD

TMS

GND

I/O

V_DD

TMS

GND

I/O

V_DDP

TDI

V_DD

V_PP

GND

I/O

V_DDP

TDI

V_DD

V_PP

GND

I/O

AK3

AK4

AK5

GND

I/O

GND

I/O

AK6

AJ2

AK7

GND

I/O

GND

I/O

AJ3

AK8

AJ4

V_DD

I/O

V_DD

I/O

AK9

I/O

AJ5

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

I/O

AJ6

V_DD

I/O

V_DD

I/O

AJ7

I/O

AJ8

I/O

AJ9

I/O

AJ10

AJ11

AJ12

I/O

2-68

v5.7

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

A1 Ball Pad Corner

3433323130 2928 272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.7

2-69

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

Number

APA1000

Function

Number

APA1000

Function

Number

APA1000

Function

APA1000

Function

Number

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

E1

A2

NC

GND

I/O

B6

NC

I/O

C9

GND

I/O

A3

B7

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

D1

A4

B8

NC

I/O

A5

B9

I/O

A6

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

C1

NC

I/O

A7

V_DD

I/O

A8

GND

I/O

A9

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

B1

V_DDP

I/O

GND

I/O

GND

I/O

V_DDP

I/O

V_DDP

I/O

GND

I/O

V_DD

I/O

GND

I/O

GND

I/O

V_DD

I/O

V_DDP

I/O

NC

GND

I/O

GND

I/O

GND

I/O

NC

GND

NC

I/O

V_DD

I/O

NC

GND

NC

GND

I/O

E2

E3

E4

D2

E5

V_DD

I/O

GND

NC

D3

E6

GND

NC

D4

E7

V_DDP

I/O

C2

D5

E8

C3

D6

V_DD

I/O

E9

I/O

NC

C4

GND

I/O

D7

E10

E11

E12

E13

E14

I/O

B2

NC

C5

D8

V_DD

I/O

B3

GND

C6

D9

I/O

B4

C7

GND

I/O

D10

D11

I/O

B5

C8

I/O

2-70

v5.7

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

APA1000

Function

APA1000

Function

APA1000

Function

APA1000

Function

Number

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

F1

Number

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

G1

Number

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

H1

Number

H24

H25

H26

H27

H28

H29

H30

H31

H32

H33

H34

J1

I/O

GND

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DDP

I/O

NC

V_DD

I/O

GND

I/O

GND

I/O

J2

V_DDP

I/O

V_DD

I/O

V_DD

NC

I/O

J3

GND

I/O

J4

V_DD

I/O

NC

V_DD

I/O

H2

J5

I/O

H3

J6

I/O

GND

I/O

H4

V_DD

I/O

J7

V_DDP

I/O

G2

H5

J8

G3

GND

I/O

H6

I/O

J9

V_DD

I/O

G4

H7

I/O

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

F2

NC

I/O

G5

V_DDP

I/O

H8

GND

I/O

V_DDP

I/O

F3

G6

H9

F4

V_DD

I/O

G7

V_DD

I/O

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

I/O

F5

G8

I/O

F6

GND

I/O

G9

V_DDP

I/O

F7

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

I/O

F8

I/O

F9

I/O

F10

F11

F12

F13

F14

F15

F16

F17

I/O

V_DDP

I/O

V_DD

v5.7

2-71

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

Number

APA1000

Function

APA1000

Function

Number

APA1000

Function

Number

APA1000

Function

Number

K30

K31

K32

K33

K34

L1

J27

I/O

V_DDP

I/O

NC

V_DD

I/O

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DDP

I/O

L33

I/O

N2

I/O

J28

L34

N3

J29

M1

GND

I/O

N4

I/O

J30

I/O

M2

N5

I/O

J31

I/O

M3

N6

I/O

J32

GND

I/O

M4

I/O

N7

I/O

J33

L2

M5

I/O

N8

I/O

J34

V_DD

NC

I/O

L3

M6

I/O

N9

I/O

K1

L4

M7

I/O

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

N27

N28

N29

N30

N31

N32

N33

N34

P1

I/O

K2

L5

M8

I/O

K3

L6

M9

I/O

K4

I/O

L7

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

M31

M32

M33

M34

N1

I/O

V_DD

I/O

K5

I/O

L8

I/O

K6

I/O

L9

V_DD

I/O

K7

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L30

L31

L32

K8

I/O

V_DDP

I/O

K9

I/O

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

GND

I/O

V_DD

I/O

GND

I/O

V_DDP

I/O

GND

I/O

P2

I/O

P3

I/O

P4

I/O

2-72

v5.7

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

Number

APA1000

Function

Number

APA1000

Function

APA1000

Function

APA1000

Function

Number

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

T31

T32

T33

T34

U1

Number

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

U31

U32

U33

U34

V1

P5

I/O

R8

I/O

V_DDP

V_DD

GND

V_DD

P6

R9

P7

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

T1

I/O

P8

I/O

GND

V_DD

P9

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

P31

P32

P33

P34

R1

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

I/O

V_DDP

I/O

V_DDP

I/O

NPECL2

AGND

I/O / GLMX2

I/O

GND

I/O

V2

I/O

V3

I/O

GND

I/O

V4

AVDD

I/O / GL2

I/O

V_DDP

I/O

U2

V5

I/O

U3

V6

PPECL1 /

Input

I/O

U4

I/O / GLMX1

AGND

NPECL1

I/O / GL1

I/O

V7

V8

I/O

V_DDP

I/O

T2

I/O

U5

T3

I/O

U6

V9

I/O

T4

I/O

U7

V10

V11

V12

V13

V14

V15

I/O

R2

T5

I/O

U8

I/O

R3

T6

I/O

U9

I/O

V_DDP

V_DD

GND

R4

I/O

T7

I/O

U10

U11

U12

U13

I/O

R5

I/O

T8

I/O

R6

I/O

T9

I/O

V_DDP

V_DD

R7

I/O

T10

I/O

v5.7

2-73

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

Number

APA1000

Function

APA1000

Function

Number

APA1000

Function

APA1000

Function

Number

W18

W19

W20

W21

W22

W23

W24

W25

W26

W27

W28

W29

W30

W31

W32

W33

W34

Y1

Number

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AA31

AA32

AA33

AA34

AB1

V16

GND

V_DD

V_DDP

I/O

GND

V_DD

V_DDP

I/O

Y21

GND

V_DD

V_DDP

I/O

V17

Y22

V18

Y23

I/O

V19

Y24

I/O

V20

Y25

I/O

V21

Y26

I/O

V22

Y27

I/O

V23

I/O

Y28

I/O

V24

I/O

Y29

I/O

V25

I/O

Y30

I/O

V_DDP

I/O

V26

I/O

Y31

I/O

V27

I/O

Y32

I/O

V28

PPECL2 /

Input

I/O

Y33

V_DDP

I/O

AB2

I/O

Y34

AB3

I/O

V29

V30

V31

V32

V33

V34

W1

I/O / GL4

I/O / GL3

AVDD

I/O

AA1

AB4

I/O

AA2

AB5

I/O

AA3

AB6

I/O

V_DDP

I/O

AA4

I/O

AB7

I/O

GND

I/O

Y2

AA5

I/O

AB8

I/O

Y3

AA6

I/O

AB9

I/O

Y4

I/O

AA7

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

I/O

W2

I/O

Y5

I/O

AA8

I/O

W3

I/O

Y6

I/O

AA9

I/O

W4

I/O

Y7

I/O

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

I/O

V_DD

I/O

W5

I/O

Y8

I/O

W6

I/O

Y9

I/O

V_DDP

V_DD

GND

V_DD

V_DDP

W7

I/O

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

I/O

W8

I/O

W9

I/O

V_DDP

V_DD

GND

W10

W11

W12

W13

W14

W15

W16

W17

I/O

V_DDP

V_DD

GND

I/O

2-74

v5.7

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

APA1000

Function

APA1000

Function

APA1000

Function

Number

APA1000

Function

Number

AB27

AB28

AB29

AB30

AB31

AB32

AB33

AB34

AC1

Number

AC30

AC31

AC32

AC33

AC34

AD1

Number

AD33

AD34

AE1

I/O

V_DD

NC

I/O

GND

I/O

GND

I/O

NC

V_DD

AF2

I/O

GND

I/O

AF3

I/O

AF4

I/O

GND

I/O

AE2

AF5

I/O

AE3

AF6

I/O

AE4

AF7

V_DDP

I/O

AD2

I/O

AE5

AF8

I/O

AD3

I/O

AE6

AF9

V_DD

I/O

GND

I/O

AD4

I/O

AE7

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AF30

AF31

AF32

AF33

AF34

AG1

AG2

AG3

AG4

AC2

AD5

I/O

AE8

V_DDP

I/O

AC3

AD6

I/O

AE9

AC4

I/O

AD7

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

AE31

AE32

AE33

AE34

AF1

I/O

AC5

I/O

AD8

I/O

AC6

I/O

AD9

V_DDP

I/O

AC7

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AD32

I/O

AC8

I/O

V_DD

I/O

AC9

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

I/O

V_DD

I/O

V_DDP

I/O

V_DDP

TCK

V_DD

TRST

V_DDP

I/O

V_DD

I/O

V_DD

I/O

V_DDP

I/O

GND

I/O

V_DD

NC

I/O

V_DD

v5.7

2-75

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

Number

APA1000

Function

Number

APA1000

Function

APA1000

Function

APA1000

Function

Number

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AJ31

AJ32

AJ33

AJ34

AK1

Number

AK14

AK15

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AK31

AK32

AK33

AK34

AL1

AG5

I/O

AH8

I/O

V_DDP

I/O

AG6

AH9

AG7

I/O

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AH31

AH32

AH33

AH34

AJ1

I/O

AG8

GND

I/O

AG9

I/O

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AG31

AG32

AG33

AG34

AH1

I/O

V_DDP

TDI

V_DD

V_PP

GND

I/O

V_DDP

I/O

GND

RCK

V_DD

I/O

V_DD

TDO

V_DDP

V_PN

GND

I/O

GND

I/O

NC

GND

I/O

AL2

AL3

I/O

AL4

I/O

AK2

AL5

V_DD

I/O

V_DD

I/O

AK3

AL6

V_DD

I/O

AK4

AL7

NC

V_DD

I/O

AJ2

NC

I/O

AK5

V_DD

I/O

AL8

V_DD

I/O

AJ3

AK6

AL9

AJ4

V_DD

I/O

AK7

V_DDP

I/O

AL10

AL11

AL12

AL13

AL14

AL15

AL16

I/O

AH2

AJ5

AK8

I/O

AH3

GND

I/O

AJ6

GND

I/O

AK9

I/O

AH4

AJ7

AK10

AK11

AK12

AK13

I/O

AH5

V_DDP

I/O

AJ8

I/O

AH6

AJ9

I/O

AH7

V_DD

AJ10

I/O

2-76

v5.7

PLUS

ProASIC

Flash Family FPGAs

1152-Pin FBGA

APA1000

Function

APA1000

Function

APA1000

Function

Number

APA1000

Function

Number

AL17

AL18

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AL31

AL32

AL33

AL34

AM1

Number

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AM31

AM32

AM33

AM34

AN1

Number

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AP2

I/O

GND

I/O

AP27

V_DD

I/O

AP28

I/O

NC

AP29

I/O

AP30

GND

NC

I/O

NC

AP31

I/O

AP32

I/O

GND

I/O

NC

AP33

I/O

GND

NC

I/O

GND

I/O

V_DD

I/O

GND

NC

V_DD

TMS

GND

NC

GND

NC

AP3

GND

I/O

AP4

AP5

AN2

NC

AP6

AN3

GND

NC

AP7

V_DD

I/O

AN4

AP8

AM2

AN5

AP9

AM3

AN6

AP10

AP11

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AM4

GND

I/O

AN7

I/O

AM5

AN8

NC

GND

I/O

AM6

AN9

I/O

AM7

GND

I/O

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

NC

V_DDP

I/O

AM8

I/O

AM9

GND

I/O

GND

I/O

AM10

AM11

AM12

AM13

AM14

AM15

AM16

AM17

AM18

AM19

GND

I/O

V_DDP

I/O

V_DDP

I/O

GND

I/O

GND

I/O

V_DDP

I/O

V_DD

I/O

v5.7

2-77

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

Top View

D

A

A2

A1

A1 Corner

Index Area

b

E

Side View

D1

e

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

E1

K

J

H

G

F

E

D

C

B

A

e

1

5

9

6 7 8

13

17

21

2

3 4

10 1112 1415 16 18 19 20 22 2324 25

Bottom View

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

2-78

v5.7

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

APA600

APA1000

APA600

APA1000

APA600

APA1000

Number

Function

Number

Function

Number

Function

A2

A3

I/O

V_DDP

GND

I/O

GND

V_DDP

I/O

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

C1

I/O

C22

C23

C24

C25

D1

I/O

GND

V_DD

I/O

GND

V_DD

I/O

A4

I/O

A5

I/O

A6

I/O

A7

I/O

D2

I/O

A8

I/O

D3

V_DD

GND

I/O

V_DD

GND

I/O

A9

I/O

D4

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

B1

I/O

D5

I/O

D6

I/O

D7

I/O

V_DD

GND

V_DDP

I/O

V_DD

GND

V_DDP

I/O

D8

I/O

D9

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

E1

I/O

GND

I/O

GND

I/O

C2

V_DDP

GND

V_DD

I/O

V_DDP

GND

V_DD

I/O

C3

I/O

C4

I/O

C5

GND

I/O

GND

I/O

C6

I/O

C7

GND

I/O

GND

I/O

C8

I/O

V_DDP

GND

I/O

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

I/O

B2

GND

V_DDP

I/O

B3

I/O

B4

I/O

B5

I/O

B6

I/O

B7

I/O

E2

I/O

B8

I/O

E3

I/O

B9

I/O

GND

I/O

GND

I/O

E4

I/O

B10

B11

I/O

E5

I/O

E6

I/O

v5.7

2-79

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

APA600

APA1000

APA600

APA1000

APA600

APA1000

Number

Function

I/O

GND

I/O

Number

Function

I/O

GND

I/O

Number

Function

E7

E8

I/O

GND

I/O

F17

F18

F19

F20

F21

F22

F23

F24

F25

G1

I/O

GND

I/O

H2

H3

I/O

GND

I/O

GND

I/O

E9

H4

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

F1

H5

I/O

H6

I/O

H7

I/O

H8

V_DDP

I/O

V_DDP

I/O

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

J1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

H1

I/O

F2

I/O

F3

GND

I/O

GND

I/O

F4

F5

I/O

F6

I/O

F7

J2

I/O

F8

J3

I/O

F9

J4

I/O

F10

F11

F12

F13

F14

F15

F16

J5

I/O

J6

GND

I/O

GND

I/O

J7

J8

V_DDP

GND

V_DDP

GND

J9

J10

J11

2-80

v5.7

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

Number

APA600

Function

APA1000

Number

APA600

Function

APA1000

Function

Number

APA600

Function

APA1000

Function

GND

V_DDP

I/O

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

K1

GND

V_DDP

I/O

K22

K23

K24

K25

L1

I/O

M7

M8

I/O / GLMX1 I/O / GLMX1

I/O

V_DDP

GND

V_DD

V_DDP

GND

V_DD

I/O

M9

I/O

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

N1

I/O

GND

V_DD

GND

V_DD

L2

I/O

L3

I/O

L4

I/O

GND

I/O

GND

I/O

L5

I/O

L6

I/O

L7

I/O

GND

V_DDP

GND

V_DDP

I/O

L8

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

L9

I/O / GLMX2 I/O / GLMX2

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

M1

M2

M3

M4

M5

M6

I/O / GL4

NPECL2

AGND

I/O

I/O / GL4

NPECL2

AGND

I/O

K2

I/O

K3

I/O

K4

I/O

K5

I/O

K6

I/O

K7

I/O

N2

I/O

K8

V_DDP

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DDP

I/O

N3

I/O

K9

N4

AVDD

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

I/O

N5

PPECL1 /

Input

PPECL1 /

Input

I/O

N6

N7

I/O / GL1

I/O

I/O / GL1

I/O

N8

V_DDP

GND

V_DD

V_DDP

GND

V_DD

I/O

N9

I/O

N10

N11

N12

N13

N14

N15

I/O

GND

I/O

AGND

NPECL1

I/O / GL2

AGND

NPECL1

I/O / GL2

I/O

v5.7

2-81

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

APA600

APA1000

APA600

APA1000

APA600

APA1000

Number

Function

Number

Function

Number

Function

V_DD

GND

V_DDP

I/O

N16

N17

N18

N19

N20

N21

V_DD

GND

V_DD

P25

R1

I/O

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

U1

V_DD

GND

V_DDP

I/O

GND

I/O

V_DDP

R2

I/O

R3

I/O

I/O / GL3

R4

I/O

PPECL2 /

Input

PPECL2 /

Input

R5

I/O

R6

I/O

N22

N23

N24

N25

P1

AVDD

I/O

AVDD

I/O

R7

I/O

R8

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

R9

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

T1

I/O

P2

I/O

P3

I/O

P4

GND

I/O

GND

I/O

P5

I/O

P6

I/O

P7

I/O

U2

I/O

P8

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

V_DDP

GND

V_DD

GND

V_DD

GND

V_DDP

I/O

U3

I/O

P9

U4

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

I/O

U5

I/O

U6

GND

I/O

GND

I/O

U7

I/O

U8

V_DDP

GND

V_DDP

I/O

V_DDP

GND

V_DDP

I/O

U9

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

I/O

T2

I/O

T3

I/O

T4

I/O

T5

I/O

T6

I/O

GND

I/O

GND

I/O

T7

I/O

T8

V_DDP

GND

V_DDP

GND

I/O

T9

2-82

v5.7

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

APA600

APA1000

APA600

APA1000

APA600

APA1000

Number

Function

GND

I/O

Number

Function

Number

Function

U20

U21

U22

U23

U24

U25

V1

GND

I/O

W5

W6

I/O

TMS

TDO

I/O

GND

I/O

Y15

Y16

I/O

GND

I/O

TCK

VPP

VPN

I/O

TDI

TRST

I/O

W7

I/O

Y17

GND

I/O

W8

I/O

Y18

I/O

W9

I/O

Y19

TCK

VPP

VPN

I/O

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

Y1

I/O

Y20

I/O

Y21

V2

I/O

Y22

V3

GND

I/O

GND

I/O

Y23

I/O

V4

I/O

Y24

I/O

V5

I/O

Y25

I/O

V6

I/O

AA1

I/O

V7

I/O

AA2

I/O

V8

V_DDP

RCK

I/O

V_DDP

RCK

I/O

AA3

I/O

V9

TMS

TDO

I/O

AA4

I/O

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

W1

W2

W3

W4

AA5

I/O

AA6

I/O

AA7

I/O

AA8

I/O

AA9

I/O

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

I/O

Y2

I/O

Y3

I/O

Y4

I/O

Y5

I/O

Y6

I/O

Y7

I/O

GND

I/O

GND

I/O

Y8

GND

I/O

Y9

I/O

Y10

Y11

Y12

Y13

Y14

I/O

TDI

TRST

I/O

v5.7

2-83

PLUS

ProASIC

Flash Family FPGAs

624-Pin CCGA/LGA

APA600

APA1000

APA600

APA1000

APA600

APA1000

Number

Function

Number

Function

Number

Function

AA25

AB1

I/O

GND

I/O

GND

I/O

V_DD

GND

I/O

GND

I/O

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AD1

I/O

GND

I/O

V_DD

I/O

V_DDP

GND

V_DD

I/O

AD20

AD21

AD22

AD23

AD24

AD25

AE1

I/O

AB2

I/O

AB3

I/O

V_DD

GND

V_DDP

GND

V_DDP

I/O

V_DD

GND

V_DDP

GND

V_DDP

I/O

AB4

I/O

AB5

I/O

AB6

I/O

AB7

I/O

AE2

AB8

I/O

AE3

AB9

I/O

GND

I/O

AE4

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AC1

I/O

AE5

I/O

GND

I/O

AE6

I/O

AE7

I/O

AE8

I/O

V_DD

I/O

AE9

I/O

GND

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

I/O

V_DDP

GND

V_DD

I/O

AD2

I/O

AD3

I/O

AD4

I/O

AD5

I/O

AD6

I/O

AD7

I/O

AD8

I/O

AD9

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

I/O

AC2

V_DD

GND

I/O

AC3

I/O

AC4

I/O

V_DDP

GND

V_DDP

GND

AC5

I/O

AC6

I/O

AC7

GND

I/O

AC8

I/O

AC9

I/O

2-84

v5.7

PLUS

ProASIC

Flash Family FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous version

Changes in current version (v5.7)

Page

v5.6

V

and V data in Table 1-22 was changed back to the data in v5.5.

page 1-38

OH

OL

(August 2008)

v5.5

V

and V data was updated in Table 1-22.

page 1-38

OH

OL

(February 2007)

v5.4

(October 2006)

A statement about single cell and cascaded cell timing diagrams was added to the "Enclosed page 1-65

Timing Diagrams – FIFO Mode:" section.

The following pins were updated in the "144-FBGA Pin" table:

page 2-38

Pin Number

Updated Function

I/O / GL1

C2

F1

I/O / GL2

v5.3

The heading, MIL-STD-883B, and note 4 were added to the "Device Resources" table.

page iii

(May 2006)

The "Temperature Grade Offerings" table was updated to include the military (M) temperature page iv

grade in the following device/packages:

APA300-FG144

APA300-FG256

APA600-FG256

APA600-FG484

APA600-FG676

APA1000-FG896

v5.2

90° and 270° phase shift support was removed from the datasheet.

The "Ordering Information" section was updated to include RoHS information.

The last paragraph of the "Boundary Scan (JTAG)" section was updated.

The Output Frequency Range in the "Timing Control and Characteristics" section.

The title for Table 1-18 was updated.

N/A

(December 2005)

page ii

page 1-11

page 1-13

page 1-34

page 1-72

N/A

The caption was updated in Figure 1-48.

v5.1

v5.0

MIL-STD-883 was added to the datasheet.

V

and V

were changed to V .

DDP

N/A

CC

CCI

Table 1-9 was updated to include 135°C.

page 1-20

page 2-6

In the "208-Pin PQFP" table, the following pin numbers have been updated:

Pin Number

Function

I/O / GL2

I/O / GL1

24

30

In the "208-Pin CQFP" table, the following pin numbers have been updated:

page 2-13

Pin Number

Function

23

I/O / GLMX1

I/O / GL2

24

28

PPECL1 / Input

I/O / GL1

30

128

129

134

135

I/O / GL3

PPECL2 / Input

I/O / GL4

I/O / GLMX2

v5.7

3-1

PLUS

ProASIC

Flash Family FPGAs

Previous version

Changes in current version (v5.7)

Page

page 2-79

v4.1

In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated:

Pin Number

M6

Function

I/O / GL2

M7

I/O / GLMX1

I/O / GLMX2

I/O / GL4

M19

M20

N5

PPECL1 / Input

I/O / GL1

N6

N20

I/O / GL3

N21

PPECL2 / Input

MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is

complete.

Green packaging information in the "Ordering Information" section was updated.

The "Temperature Grade Offerings" table was updated for the CG624.

The "Ordering Information" section was updated.

The "Live at Power-Up" section is new.

page ii

page iv

page ii

page 1-3

page 1-4

page 1-9

page 1-10

page 1-13

page 1-33

page 1-35

Note 2 in Figure 1-4 was updated.

The 3.3 V column in Table 1-3 was updated.

The "Input/Output Blocks" section was updated.

The note was removed from Table 1-4.

The "Power-Up Sequencing" section was updated.

The first bullet in the "ProASICPLUS Clock Management System" section was updated.

The first paragraph in the "Performance Retention" section was updated.

Mixed Voltage was removed from Table 1-19.

Table 1-20 was updated.

Mixed Mode Voltage was removed from Table 1-21 and the Military/MIL-STD-883B column was page 1-36

updated.

All tables from page 1-42 to page 1-51 were updated.

page 1-42 to

page 1-51

Table 1-48 is new.

page 1-53

page 1-55

page 1-59

page 1-72

Table 1-66

page 1-73

Figure 1-30 is new.

Note 1 in Table 1-50 was updated.

The notes in Table 1-54 were updated.

A note was added to Figure 1-48.

A note was added to Table 1-66.

The "TRST Test Reset Input" section was updated in the "Pin Description" section.

The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all page 2-78

pin data.

v4.0

Figure 1-20 was updated.

page 1-19

page 1-52

page 2-69

Table 1-46 was updated.

The "1152-Pin FBGA" figure was updated.

Pin names were changed to more accurately reflect the multiple functions supported by each

pin.

3-2

v5.7

PLUS

ProASIC

Flash Family FPGAs

Page

Previous version

Changes in current version (v5.7)

PLUS

v3.5

The ProASIC

and ProASIC

Military/Aerospace datasheets were combined. This

document now supports Commercial, Industrial, and Military Temperature devices.

Table 1 was updated.

page i-i

page i-ii

The "Ordering Information" section was updated.

"Plastic Device Resources" table was updated.

The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated. page 1-21

The "Calculating Typical Power Dissipation" section was updated.

"Performance Retention" section

page 1-30

page 1-33

page 1-34

page 1-35

page 1-36

page 1-38

page 1-52

page i-iv

Table 1-18

Table 1-20 was updated.

Table 1-21 was updated.

Table 1-22 was updated.

Table 1-46 was updated.

v3.4

The "Temperature Grade Offerings" table is new.

The "Speed Grade and Temperature Matrix" table is new.

The "ProASICPLUS Clock Management System" section was updated.

The "Lock Signal" section was updated.

page i-iv

page 1-13

page 1-16

page 1-21

page 1-22

page 1-27

page 1-29

page 1-65

page 1-73

page 2-4

The "PLL Electrical Specifications" table was updated.

The "User Security" section was updated.

The "Design Environment" section was updated.

Table 1-15 was updated.

The "Asynchronous FIFO Full and Empty Transitions" section was updated.

The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.

The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed:

v3.3

v3.2

Pin 15 = GLMX1

Pin 16 = GL1

Pin 21 = GL2

Pin 88 = GL3

Pin93 = GL4

Pin 94 = GLMX2

The "ProASICPLUS Clock Management System" section was updated.

Figure 1-14 was updated.

page 1-13

page 1-14

page 1-15

page 1-19

page 1-21

page 1-42

page 1-30

page 1-33

page 1-74

Table 1-7 is new.

Figure 1-20 was updated.

The "PLL Electrical Specifications" section was updated.

Figure 1-26 was updated.

In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.

The "Programming, Storage, and Operating Limits" section was updated.

The "Recommended Design Practice for VPN/VPP" section was updated.

v3.1

v3.0

The datasheet was updated to include references to guidelines concerning the use of certain

PLUS

ProASIC

I/O standards.

In Table 1-2 on page 1-8, the Memory Rows – Bottom coordinates were changed.

Figure 1-8 was updated.

page 1-8

page 1-38

page 1-44

The V Minimum in the Table 1-22 was changed from 0.3 to –0.3.

IL

In the "Output Buffer Delays" section, the OB25LPLL t

Standard changed to 5.3.

DHL

In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51

and the –F maximum changed to 0.8.

v5.7

3-3

PLUS

ProASIC

Flash Family FPGAs

Previous version

Changes in current version (v5.7)

The Table 1 was updated.

Page

page i-i

v2.0

The "Ordering Information" section was updated.

The "Plastic Device Resources" section was updated.

The "ProASICPLUS Architecture" section was updated.

Table 1-2 was updated.

page i-ii

page 1-2

page 1-8

page 1-16

page 1-10

Table 1-8 is new.

Figure 1-11 is new.

The Introduction section in the "ProASICPLUS Clock Management System" section was page 1-13

updated.

The "Physical Implementation" section was updated.

page 1-13

The "Functional Description" on page 1-13 was updated.

Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated.

page 1-14 to page

1-19

The "PLL Electrical Specifications" on page 1-21 was updated.

Figure 1-25 on page 1-26 was updated.

page 1-21

page 1-26

page 1-30

page 1-34

page 1-38

page 1-42

page 1-44

page 1-46

page 1-50

page 1-51

page 1-73

page 2-1

The "Calculating Typical Power Dissipation" on page 1-30 was updated.

The ’Nominal Supply Voltages’ section was updated.

The Table 1-22 was updated.

The "Tristate Buffer Delays" on page 1-42 was updated.

The "Output Buffer Delays" on page 1-44 was updated.

The"Input Buffer Delays" on page 1-46 was updated.

"Global Routing Skew" on page 1-50 was updated.

The"Sample Macrocell Library Listing" on page 1-51 was updated.

The "Pin Description" on page 1-73 was updated.

The following pins have been changed in the "100-Pin TQFP" table:

Pin Number

Function

I/O (GLMX1)

GL1

NPECL1

PPECL1(I/P)

GL2

Pin Number

Function

GL3

PPECL2 (I/P)

NPECL2

GL4

10

11

13

15

16

60

61

63

65

66

I/O (GLMX2)

"144-Pin TQFP" section is new.

The following pins have been changed in the "208-Pin PQFP" table:

page 2-3

page 2-5

Pin Number

Function

I/O (GLMX1)

GL1

NPECL1

PPECL1 (I/P)

GL2

Pin Number

128

129

132

134

Function

GL3

PPECL2 (I/P)

NPECL2

GL4

23

24

26

28

30

135

I/O (GLMX2)

The following pins have been changed in the "456-Pin PBGA" table:

page 2-22

Pin Number

Function

GL1

GL2

GL4

I/O (GLMX1)

PPECL1 (I/P)

Pin Number

Function

NPECL2

GL3

I/O (GLMX2)

NPECL1

PPECL2 (I/P)

M1

M2

M22

N2

N22

N23

N25

P5

N4

P26

3-4

v5.7

PLUS

ProASIC

Flash Family FPGAs

Previous version

Changes in current version (v5.7)

Page

v2.0 (continued)

The following pins have been changed in the "144-Pin FBGA" table:

page 2-37

Pin Number

Function

GL2

I/O (GLMX2

NPECL2

GL1

Pin Number

F9

)F11

F12

G1

G4

Function

GL4

PPECL2 (I/P

GL3

PPECL1 (I/P)

NPECL1

C2

D12

E11

F1

F3

I/O (GLMX1)

The following pins have been changed in the "256-Pin FBGA" table:

page 2-40

page 2-45

page 2-51

page 2-59

page 2-69

Pin Number

H1

H2

Function

GL1

NPECL1

Pin Number

H16

J1

Function

GL4

GL2

PPECL1 (I/P)

PPECL2 (I/P)

GL3

H3

H13

H14

I/O (GLMX1)

I/O (GLMX2)

NPECL2

J2

J13

J16

The following pins have been changed in the "484-Pin FBGA" table:

Pin Number

L4

Function

GL1

Pin Number

L19

Function

GL4

GL2

PPECL1 (I/P)

PPECL2 (I/P)

GL3

L5

NPECL1

M4

L6

L16

L17

I/O (GLMX1)

I/O (GLMX2)

NPECL2

M5

M16

M19

The following pins have been changed in the "676-Pin FBGA" table:

Pin Number

N1

N3

N5

N22

N24

Function

GL1

I/O (GLMX1)

NPECL1

GL3

Pin Number

N25

P1

P5

P22

P24

Function

GL4

GL2

PPECL1 (I/P)

I/O (GLMX2)

PPECL2 (I/P)

NPECL2

The following pins have been changed in the "896-Pin FBGA" table:

Pin Number

R2

R4

Function

I/O (GLMX1)

NPECL1

Pin Number

T3

T4

Function

GL2

PPECL1 (I/P)

PPECL2 (I/P)

GL4

R5

R27

R29

GL1

NPECL2

I/O (GLMX2)

T26

T27

T28

GL3

The following pins have been changed in the "1152-Pin FBGA" table:

Pin Number

Function

I/O (GLMX1)

NPECL1

GL1

GL2

PPECL1 (I/P)

Pin Number

U29

U31

V28

V29

Function

NPECL2

I/O (GLMX2)

PPECL2 (I/P)

GL4

U4

U6

U7

V5

V6

V30

GL3

v5.7

3-5

PLUS

ProASIC

Flash Family FPGAs

Previous version

Changes in current version (v5.7)

Page

page 1-2

Advanced v0.7

The "ProASICPLUS Architecture" section was updated.

The "Array Coordinates" section and Table 1-2 are new.

The "Power-Up Sequencing" section is new.

"I/O Features" section was updated.

page 1-8

page 1-10

page 1-9

The "Timing Control and Characteristics" section was updated. "Physical Implementation" page 1-13 to page

section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration 1-16

Options" section are new.

"PLL Block – Top-Level View and Detailed PLL Block Diagram" section was updated.

Figure 1-15 was updated.

page 1-14

page 1-15

"Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew page 1-16

Minimization" section are new.

Figure 1-16, Figure 1-17, Figure 1-18, Figure 1-19, and Figure 1-20 are new.

page 1-17 to page

1-19

The "PLL Electrical Specifications" section is new.

The "Design Environment" section was updated.

Figure 1-26 was updated.

page 1-21

page 1-27

page 1-42

page 1-30

page 1-36

page 1-38

page 1-40

page 1-42

page 1-44

page 1-46

page 1-48

page 1-50

page 1-51

page 1-73

page 1-74

page 2-69

page i-i

The "Calculating Typical Power Dissipation" section was updated.

The "DC Electrical Specifications (V

The Table 1-22 was updated.

= 2.5 V 0.2V)" section was updated.

DDP

The "DC Specifications (3.3 V PCI Operation)1" section was updated.

The "Tristate Buffer Delays" section (the figure and table) have been updated.

The "Output Buffer Delays" section (the figure and table) have been updated.

The "Input Buffer Delays" section was updated.

The "Global Input Buffer Delays" section was updated.

The "Predicted Global Routing Delay" section was updated.

The "Global Routing Skew" section was updated.

The "Sample Macrocell Library Listing" section was updated.

The "Pin Description" section was updated. GLMX is new.

The "Recommended Design Practice for VPN/VPP" section was updated.

Pin AK31 of FG1152 for the APA1000 changed to V .

PP

(Advanced v0.6)

The "Features and Benefits" on page i-i were updated.

PLUS

The "ProASIC

Product Profile" on page i-i was updated.

page i-i

The "Ordering Information" on page i-ii was updated.

The "Plastic Device Resources" on page i-ii was updated.

The "ProASICPLUS Architecture" on page 1-2 was updated.

Table 1-1 was updated.

page i-ii

page 1-2

page 1-7

page 1-14

page 1-27

page 1-29

page 1-30

page 1-33

page 1-34

page 1-35

page 1-36

Figure 1-14 was updated.

The "Design Environment" section was updated.

The "Package Thermal Characteristics" section was updated.

The "Calculating Typical Power Dissipation" section was updated.

The "Absolute Maximum Ratings*" section was updated.

The "Programming, Storage, and Operating Limits" section was updated.

The ’Nominal Supply Voltages’ section was updated.

The "Recommended Operating Conditions" section was updated.

The "DC Electrical Specifications (V

= 2.5 V 0.2V)" section was updated.

DDP

The "DC Electrical Specifications (V

updated.

= 3.3 V 0.3 V and V = 2.5 V 0.2 V)" section was page 1-38

DDP

DD

3-6

v5.7

PLUS

ProASIC

Flash Family FPGAs

Previous version

Advanced v0.6

(continued)

Changes in current version (v5.7)

Page

The "Synchronous Write and Read to the Same Location" section was updated.

page 1-61

The "Asynchronous Write and Synchronous Read to the Same Location" section was updated. page 1-62

The "Asynchronous FIFO Read" section was updated.

The "Pin Description" section has been updated.

The "Recommended Design Practice for VPN/VPP" section is new.

The "100-Pin TQFP" section is new.

page 1-67

page 1-73

page 1-74

page 2-1

page 2-45

page 1-74

page i-ii

The "484-Pin FBGA" section is new.

Advanced v0.5

Advanced v0.4

The description for the V pin has changed.

PN

The "Plastic Device Resources" section has been updated.

Figure 1-12 and Figure 1-13 have been updated.

page 1-14

page 1-42

page 1-44

page 1-46

page 1-48

page 2-22

page 2-51

page i-i

The "Tristate Buffer Delays" section has been updated.

The "Output Buffer Delays" section has been updated.

The "Input Buffer Delays" section has been updated.

The "Global Input Buffer Delays" section has been updated.

The "456-Pin PBGA" section has been updated.

The "676-Pin FBGA" section has been updated.

PLUS

Advanced v0.3

The "ProASIC

Product Profile" section has been changed.

The "Plastic Device Resources" section has been updated.

page i-ii

The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated.

page 1-9

WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent

with the signal names found in the Macro Library Guide.

Figure 1-21 and Figure 1-22 have been updated.

page 1-24

and page 1-25

The "Design Environment" section and Figure 1-26 have been updated.

page 1-27

and page 1-42

The table in the "Package Thermal Characteristics" section has been updated.

The "Calculating Typical Power Dissipation" section is new.

page 1-29

page 1-30

page 1-33

page 1-34

page 1-36

The "Programming, Storage, and Operating Limits" section is new.

The ’Nominal Supply Voltages’ section has been updated.

The "DC Electrical Specifications (V

= 2.5 V 0.2V)" section was updated.

DDP

The "DC Electrical Specifications (V

updated.

= 3.3 V 0.3 V and V = 2.5 V 0.2 V)" section was page 1-38

DD

DDP

The "Recommended Operating Conditions" section was updated.

The "ProASICPLUS Clock Management System" section was updated.

Figure 1-14 was updated.

page 1-35

page 1-13

page 1-14

page 1-12

Advanced v0.3

(continued)

Figure 1-13 is new.

Tables 5, 6, and 7 from Advanced v0.3 were removed.

The "Memory Block SRAM Interface Signals" section was updated.

The "Memory Block FIFO Interface Signals" section was updated.

All pinout tables have been updated, and several packages are new:

page 1-24

page 1-25

208-Pin PQFP – APA150, APA300, APA450, APA600

456-Pin PBGA – APA150, APA300, APA450, APA600

144-Pin FBGA – APA150, APA300, APA450

256-Pin FBGA – APA150, APA300, APA450, APA600

676-Pin FBGA – APA600

Advanced v0.1

Figure 1-23 has been updated.

page 1-26

v5.7

3-7

PLUS

ProASIC

Flash Family FPGAs

Data Sheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Export Administration Regulations (EAR)

The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could

require an approved export license prior to export from the United States. An export includes release of product or

disclosure of technology to a foreign national inside or outside the United States.

3-8

v5.7

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

2061 Stierlin Court

Mountain View, CA

94043-4655 USA

River Court,Meadows Business Park EXOS Ebisu Buillding 4F

Room 2107, China Resources Building

26 Harbour Road

Wanchai, Hong Kong

Station Approach, Blackwater

Camberley Surrey GU17 9AB

United Kingdom

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Phone 650.318.4200

Fax 650.318.4600

Phone +81.03.3445.7671

Fax +81.03.3445.7668

Phone +852 2185 6460

Fax +852 2185 6488

Phone +44 (0) 1276 609 300

Fax +44 (0) 1276 607 540

http://jp.actel.com

www.actel.com.cn

5172161-23/9.08


型号：	APA075-CQI
厂家：	Actel Corporation
描述：	ProASIC Flash Family FPGAs 的ProASIC闪存系列FPGA 闪存
文件：	总174页 (文件大小：4720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

APA075-CQI [ACTEL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E