EX256-FCS100I [ACTEL]
eX Automotive Family FPGAs; 汽车的eX系列FPGA
| 型号： | EX256-FCS100I |
| 厂家： | 
Actel Corporation |
| 描述： | eX Automotive Family FPGAs |
| 文件： | 总44页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v3.2
™
eX Automotive Family FPGAs
u
e
•
•
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew-Rate Control
2.5 V and 3.3 V I/Os
Software Design Support with Actel Designer and
Libero® Integrated Design Environment (IDE)
Tools
Up to 100% Resource Utilization with 100% Pin
Locking
Specifications
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22 µm CMOS Process Technology
•
•
•
Up to 132 User-Programmable I/O Pins
Features
•
•
250 MHz Internal Performance, Low-Power Antifuse
FPGA
•
•
Deterministic Timing
•
•
Advanced Small-Footprint Packages
Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Live on Power-Up
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
FuseLock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
•
•
•
•
•
•
Product Profile
Device
eX64
eX128
eX256
Capacity
3,000
2,000
6,000
4,000
12,000
8,000
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
Maximum User I/Os
128
84
256
100
512
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades*
Std.
A
Std.
A
Std.
A
Temperature Grades*
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
100
128, 180
Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to the eX
Family FPGAs datasheet for more details.
June 2006
i
© 2006 Actel Corporation
eX Automotive Family FPGAs
Ordering Information
eX128
TQ
G
100
A
Application (Ambient Temperature Range)
A= Automotive (-40˚C to 125˚C)
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
=
TQ Thin Quad Flat Pack (1.4mm pitch)
=
CS
Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 64 Dedicated Flip-Flops (3,000 System Gates)
=
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on
characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to
ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing
options available.
Plastic Device Resources
User I/Os (Including Clock Buffers)
Device
eX64
64-Pin TQFP
100-Pin TQFP
49-Pin CSP
128-Pin CSP
180-Pin CSP
41
46
—
56
70
81
36
36
—
84
—
—
eX128
eX256
100
100
132
Note: Package Definitions: TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
Speed Grade and Temperature Grade Matrix
Std.
A
✓
Note: Refer to the eX Family FPGAs datasheet for more details on commercial-
and industrial-grade offerings.
Contact your local Actel representative for device availability.
ii
v3.2
eX Automotive Family FPGAs
Table of Contents
eX Automotive Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
CEQ Values for eX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
This datasheet version contains information that is considered to be final. . . . . . 3-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.2
iii
eX Automotive Family FPGAs
eX Automotive Family FPGAs
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
General Description
Based on a 0.22 µm CMOS process technology, the eX
family of FPGAs is a low-cost solution for low-power,
high-performance designs. With the automotive
temperature grade support (–40ºC to 125ºC), the eX
devices can address many in-cabin telematics and
automobile interconnect applications. The low-power
attributes inherent in antifuse technology make the eX
devices ideal for designers who are looking to integrate
low-density, power-sensitive automotive applications
into a programmable logic solution, enabling quick time-
to-market.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-1). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hardwired clock or the
routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure 1-2 on page 1-2). Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
eX Family Architecture
The Actel eX family is implemented on a high-voltage
twin-well CMOS process using 0.22 µm design rules. The
eX family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing nontiming-
critical paths and when the design engineer is running
out of R-cells. For more information about the CC macro,
refer to the Actel Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros application
note.
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25 Ω with a capacitance of 1.0 fF for
Routed
Data Input
S0
S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CLR
CKS
CKP
Figure 1-1 • R-Cell
v3.2
1-1
eX Automotive Family FPGAs
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring R-cell
in a given SuperCluster. DirectConnect uses a hardwired
signal path requiring no programmable interconnection to
achieve its fast signal propagation time of less than 0.1 ns.
Module Organization
C-cell and R-cell logic modules are arranged into
horizontal banks called Clusters, each of which contains
two C-cells and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called
SuperClusters for improved design efficiency and device
performance, as shown in Figure 1-3 on page 1-3. Each
SuperCluster is a two-wide grouping of Clusters.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering maximum pin-to-pin
propagation of 0.6 ns.
Routing Resources
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources, known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
fully automatic place-and-route software to minimize
signal propagation delays.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-4 on page 1-3). This
routing architecture also dramatically reduces the
number of antifuses required to complete a circuit,
ensuring the highest possible performance.
D0
D1
Y
D2
D3
Sa
Sb
DB
B1
A1
A0 B0
Figure 1-2 • C-Cell
1-2
v3.2
eX Automotive Family FPGAs
R-Cell
C-Cell
Routed
Data Input
D0
D1
S1
S0
PSET
CLR
Y
D2
D3
DirectConnect
Input
Q
D
Y
Sb
Sa
HCLK
CLKA,
CLKB,
DB
Internal Logic
CKS
CKP
A0 B0
A1
B1
Cluster
Cluster
SuperCluster
Figure 1-3 • Cluster Organization
DirectConnect
• No antifuses
• 0.1 ns routing delay
SuperClusters
FastConnect
• One antifuse
• 0.6 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 1-4 • DirectConnect and FastConnect for SuperClusters
v3.2
1-3
eX Automotive Family FPGAs
Clock Resources
eX’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-cell.
HCLK cannot be connected to combinational logic. This
provides a dedicated propagation path for the clock signal
for the automotive-grade eX devices. The hardwired clock
is tuned to provide a clock skew of less than 0.1 ns worst
case. If not used, the HCLK pin must be tied Low or High
and must not be left floating. Figure 1-5 describes the
clock circuit used for the constant load HCLK.
from internal logic signals (via the CLKINT routed clock
buffer) within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals, the
external clock pin cannot be used for any other input
and must be tied Low or High and must not float.
Figure 1-6 describes the CLKA and CLKB circuit used in eX
devices.
Table 1-1 describes the possible connections of the
routed clock networks, CLKA and CLKB.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Designer
software and the pin must be tied to GND on the board.
(See the "TRST, I/O Boundary Scan Reset Pin" section on
page 1-24).
Unused clock pins must not be left floating and must be
tied to High or Low.
Constant Load
Clock Network
HCLKBUF
The remaining two clocks (CLKA, CLKB) are global routed
clock networks that can be sourced from external pins or
Figure 1-5 • eX HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-6 • eX Routed Clock Buffer
Table 1-1 • Connections of Routed Clock Networks, CLKA
and CLKB
Module
C-Cell
Pins
A0, A1, B0 and B1
CLKA, CLKB, S0, S1, PSET, and CLR
EN
R-Cell
I/O Cell
1-4
v3.2
eX Automotive Family FPGAs
to GND on the board. Each I/O module has an available
pull-up or pull-down resistor of approximately 50 kΩ
that can configure the I/O in a known state during
power-up. Just shortly before VCCA reaches 2.5 V, the
resistors are disabled and the I/Os will be controlled by
user logic.
Other Architectural Features
Performance
The combination of the various architectural features
enables automotive-grade eX devices to operate with
internal clock frequencies at 250 MHz for fast execution
of complex logic functions.
Table 1-2 describes the I/O features of eX devices. For
more information on I/Os, refer to the Actel eX, SX-A,
and RT54SX-S I/Os application note.
Automotive-grade eX devices are the optimal platforms
upon which to integrate in-cabin telematics and
automobile interconnect applications previously only
contained in ASICs or gate arrays.
The automotive eX devices support I/O operation at 2.5 V
and 3.3 V.
The detailed description of the I/O pins in eX automotive
devices can be found in "Pin Description" section on
page 1-24.
eX devices meet the performance goals of gate arrays,
and, at the same time, present significant improvements
in cost and time to market. Using timing-driven place-
and-route tools, designers can achieve highly
deterministic device performance.
Table 1-2 • I/O Features
Function
Description
Input Buffer • 3.3 V LVTTL
Threshold
•
2.5 V LVCMOS2
User Security
Selection
Nominal
Output Drive
•
•
3.3 V LVTTL
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, there is a special Security
Fuse inside the eX device that disables the probing
circuitry and prohibits further programming of the
device. This Fuse cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
2.5 V LVCMO 2
Output Buffer “Hot-Swap” Capability
•
I/O on an unpowered device does not sink
current
•
•
Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up
Individually selectable pull-ups and pull-downs
during power-up (default is to power-up in
tristate)
Look for this symbol to ensure your valuable IP is secure.
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
FuseLock
Hot Swapping
eX I/Os are configured to be hot-swappable. During
power-up/down (or partial up/down), all I/Os are tristated,
provided VCCA ramps up within a diode drop of VCCI. VCCA
and VCCI do not have to be stable during power-up/down,
and they do not require a specific power-up or power-
down sequence in order to avoid damage to the eX
devices. In addition, all outputs can be programmed to
have a weak resistor pull-up or pull-down for tristate
output at power-up. After the eX device is plugged into
an electrically active system, the device will not degrade
the reliability of or cause damage to the host system. The
device's output pins are driven to a high impedance state
until normal chip operating conditions are reached. Please
see the application note, Actel SX-A and RT54SX-S Devices
in Hot-Swap and Cold-Sparing Applications, which also
applies to eX devices, for more information on hot
swapping.
Figure 1-7 • FuseLock
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. I/O cells in
eX devices do not contain embedded latches or flip-flops
and can be inferred directly from HDL code. The device
can easily interface with any other device in the system,
which in turn enables parallel design of system
components and reduces overall design time.
All unused I/Os are configured as tristate outputs by
Actel's Designer software, for maximum flexibility when
designing new boards or migrating existing designs.
However, it is still recommended to tie all unused I/O pins
v3.2
1-5
eX Automotive Family FPGAs
Power Requirements
Power consumption is extremely low for the automotive-grade eX devices due to the low capacitance of the antifuse
interconnects. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM),
making it the lowest-power FPGA architecture available today.
Figure 1-8 through Figure 1-11 on page 1-7 show some sample power characteristics of eX devices.
300
250
eX64
eX128
eX256
200
150
100
50
0
50
100
150
200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-8 • eX Dynamic Power Consumption – High Frequency
80
70
60
50
40
30
20
10
0
eX64
eX128
eX256
0
10
20
30
40
50
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-9 • eX Dynamic Power Consumption – Low Frequency
1-6
v3.2
eX Automotive Family FPGAs
180
160
140
120
100
80
32-bit Decoder
8 x 8-bit Counters
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
Figure 1-10 • Total Dynamic Power (mW)
12
10
8
5% DC
10% DC
15% DC
6
4
2
0
0
10
20
30
40
50
60
Frequency (MHz)
Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle
v3.2
1-7
eX Automotive Family FPGAs
Boundary Scan Testing (BST)
Flexible Mode
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test
pins (TMS, TDI, TCK, TDO and TRST). The functionality of
each pin is defined by two available modes, Dedicated
and Flexible, and is described in Table 1-3. In the
dedicated test mode, TCK, TDI, and TDO are dedicated
pins and cannot be used as regular I/Os. In flexible mode
(default mode), TMS should be set High through a pull-
up resistor of 10 kΩ. TMS can be pulled Low to initiate
the test sequence.
In Flexible mode, TDI, TCK and TDO may be used as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are disabled in flexible
JTAG mode, and an external 10 kΩ pull-resistor to VCCI is
required on the TMS pin.
To select the Flexible mode, users need to uncheck the
"Reserve JTAG" box in "Device Selection Wizard" in
Actel Designer software. The functionality of TDI, TCK,
and TDO pins is controlled by the BST TAP controller. The
TAP controller receives two control inputs; TMS and TCK.
Upon power-up, the TAP controller enters the Test-Logic-
Reset state. In this state, TDI, TCK, and TDO function as
user I/Os. The TDI, TCK, and TDO pins are transformed
from user I/Os into BST pins when the TMS pin is Low at
the first rising edge of TCK. The TDI, TCK, and TDO pins
return to user I/Os when TMS is held High for at least five
TCK cycles.
Table 1-3 • Boundary Scan Pin Functionality
Dedicated Test Mode
Flexible Mode
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and
BST pins may be used as I/Os
No need for pull-up resistor for Use a pull-up resistor of 10 kΩ
Table 1-4
describes
the
different
configuration
TMS and TDI
on TMS
requirements of BST pins and their functionality in
different modes.
Dedicated Test Mode
Table 1-4 • Boundary Scan Pin Configurations and
Functions
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Mode
Dedicated (JTAG)
Flexible (User I/O)
Flexible (JTAG)
Checked
Unchecked
Unchecked
Any
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-12). JTAG pins comply with LVTTL/TTL I/O
specification regardless of whether they are used as a
user I/O or a JTAG I/O. Refer to the "3.3 V LVTTL Electrical
Specifications" section on page 1-13 for detailed
specifications.
Test-Logic-Reset
Any EXCEPT Test-
Logic-Reset
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the "Reserve JTAG Test Reset" option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. It is recommended to connect this pin to GND in
normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or be driven High.
When the "Reserve JTAG Test Reset" option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 • Device Selection Wizard
1-8
v3.2
eX Automotive Family FPGAs
The procedure for programming an eX device using
Silicon Sculptor II is as follows:
JTAG Instructions
Table 1-5 lists the supported instructions with the
corresponding IR codes for eX devices.
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
Table 1-5 • JTAG Instruction Code
Instructions (IR4: IR0)
EXTEST
Binary Code
00000
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
SAMPLE / PRELOAD
INTEST
00001
00010
For more details on programming eX Automotive
devices, please refer to the Programming Antifuse
Devices and the Silicon Sculptor II User's Guides.
USERCODE
IDCODE
00011
00100
HIGHZ
01110
CLAMP
01111
Probing Capabilities
Diagnostic
BYPASS
10000
Automotive-grade eX devices provide internal probing
capability that is accessed with the JTAG pins. The Silicon
Explorer II Diagnostic hardware is used to control the
TDI, TCK, TMS, and TDO pins to select the desired nets
for debugging. The user assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the BST pins are in JTAG mode and the
TRST pin is driven High or left floating. If the TRST pin is
held Low, the TAP controller will remain in the Test-
Logic-Reset state, so no probing can be performed. The
Silicon Explorer II automatically places the device into
JTAG mode, but the user must drive the TRST pin High or
allow the internal pull-up resistor to pull TRST High.
11111
Reserved
All others
Table 1-6 lists the codes returned after executing the
IDCODE instruction for eX devices. Note that bit 0 is
always "1." Bits 11-1 are always "02F," which is Actel's
manufacturer code.
Table 1-6 • IDCODE for eX Devices
Device
eX64
Revision
Bits 31-28
Bits 27-12
40B2, 42B2
40B0, 42B0
40B5, 42B5
40B2, 42B2
40B0, 42B0
40B5, 42B5
0
0
0
1
1
1
8
9
9
A
B
B
eX128
eX256
eX64
When you select the "Reserve Probe" box, as shown in
Figure 1-12 on page 1-8, the Designer software reserves
the PRA and PRB pins as dedicated outputs for probing.
This "reserve" option is merely a guideline. If the
Designer software requires that the PRA and PRB pins be
user I/Os to achieve successful layout, the tool will use
these pins for user I/Os. If you assign user I/Os to the PRA
and PRB pins and select the "Reserve Probe" option,
Designer Layout will override the option and place user
I/Os on those pins.
eX128
eX256
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site
device programmer for the PC.
To allow for probing capabilities, the security fuse must
not be programmed. Programming the security fuse will
disable the probe circuitry. Table 1-7 on page 1-10
summarizes the possible device configurations for
probing once the device leaves the "Test-Logic-Reset"
JTAG state.
With standalone software, Silicon Sculptor II allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive
hardware self-testing capability.
v3.2
1-9
eX Automotive Family FPGAs
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the
interconnection between Silicon Explorer II and the
automotive-grade eX device to perform in-circuit
verification.
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with Actel
Designer software tools, allows users to examine any of
the internal nets of the device while it is operating in a
prototype or a production system. The user can probe
into an eX device via the PRA and PRB pins without
changing the placement and routing of the design and
without using any additional resources. Silicon
Explorer II's noninvasive method does not alter timing or
loading effects, thus shortening the debug cycle.
Silicon Explorer II does not require relayout or additional
MUXes to bring signals out to an external pin, which is
necessary when using programmable logic devices from
other suppliers.
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon
Explorer II attaches to a PC's standard COM port, turning
the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
70Ω series termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70 Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
Table 1-7 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mode
Dedicated
Flexible
TRST1
Low
Low
High
High
–
Security Fuse Programmed
PRA, PRB2
User I/O3
User I/O3
TDI, TCK, TDO2
Probing Unavailable
User I/O3
No
No
No
No
Yes
Dedicated
Flexible
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit Secured
Probe Circuit Inputs
Probe Circuit Inputs
Probe Circuit Secured
–
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = High in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
Actel’s Designer software.
16 Pin
Connection
eX FPGAs
TDI
TCK
TMS
TDO
Serial
Silicon Explorer II
Connection
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-13 • Silicon Explorer II Probe Setup
1-10
v3.2
eX Automotive Family FPGAs
Development Tool Support
The automotive-grade eX family of FPGAs is fully
supported by both the Actel Libero® Integrated Design
Environment (IDE) and Designer FPGA Development
software. Actel Libero IDE is a design management
environment, seamlessly integrating design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®,
ViewDraw® for Actel from Mentor Graphics®,
ModelSim® HDL Simulator from Mentor Graphics,
WaveFormer Lite™ from SynaptiCAD®, and Designer
software from Actel. Refer to the Libero IDE flow
(located on Actel’s website) diagram for more
information.
Related Documents
Datasheet
eX Family FPGAs
http://www.actel.com/documents/eX_DS.pdf
Application Notes
Maximizing Logic Utilization in eX, SX and SX-A FPGA
Devices Using CC Macros
http://www.actel.com/documents/CC_Macro_AN.pdf
Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/
Antifuse_Security_AN.pdf
Actel eX, SX-A, and RT54SX-S I/Os
http://www.actel.com/documents/antifuseIO_AN.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-
Sparing Applications
http://www.actel.com/documents/
HotSwapColdSparing_AN.pdf
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
Design for Low Power in Actel Antifuse FPGAs
http://www.actel.com/documents/Low_Power_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
timing-driven place-and-route, and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmartGen core builder, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity,
Synopsys®, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
User Guides
Silicon Sculptor II User's Guide
http://www.actel.com/techdocs/manuals/
default.asp#programmers
Miscellaneous
Libero IDE flow
http://www.actel.com/products/tools/libero/flow.html
v3.2
1-11
eX Automotive Family FPGAs
Operating Conditions
Table 1-8 • Absolute Maximum Ratings*
Symbol
VCCI
VCCA
VI
Parameter
Limits
–0.3 to +4.0
–0.3 to +3.0
–0.5 to VCCI + 0.5
–0.5 to +VCCI
–65 to +150
–65 to +150
Units
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
V
V
V
VO
Output Voltage
V
TSTG
Tj
Storage Temperature
Maximum Junction Temperature
°C
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to
temperatures between absolute maximum and recommended operating conditions for extended periods may affect device
reliability. Devices should not be operated outside the Recommended Operating Conditions.
Table 1-9 • Recommended Operating Conditions
Parameter
Automotive
–40 to +125
2.3 to 2.7
Units
°C
Temperature Range (Tj)
2.5 V Power Supply
V
Range (VCCA, VCCI
)
3.3 V Power Supply
3.0 to 3.6
V
Range (VCCI
)
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on
characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing
to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing
options available.
Table 1-10 • Typical Automotive-Grade eX Standby Current at 25°C
VCCA= 2.5 V
VCCA = 2.5 V
Product
eX64
VCCI = 2.5 V
VCCI = 3.3 V
397 µA
497 µA
eX128
eX256
696 µA
795 µA
698 µA
796 µA
1-12
v3.2
eX Automotive Family FPGAs
Automotive
2.5 V LVCMOS2 Electrical Specifications
Symbol
VOH
Parameter
Min.
Max.
Units
V
VCCI = MIN, VI = VIH or VIL
(IOH = –1 mA)
(IOL= 1 mA)
2.0
VOL
VCCI = MIN, VI = VIH or VIL
0.4
0.7
V
VIL
Input Low Voltage, VOUT ≤ VOL(max)
Input High Voltage, VOUT ≥ VOH(min)
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current, VOUT = Tristate
Input Transition Time tR, tF
Input Capacitance
V
VIH
1.7
–20
–20
V
IIL / IIH
IOZ
20
20
10
10
25
µA
µA
ns
1,2
tR, tF
CIN
pF
3
ICC
Standby Current
mA
IV Curve
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.7 V to 1.7 V.
2. tF is the transition time from 1.7 V to 0.7 V.
3. ICC = ICCI + ICCA
3.3 V LVTTL Electrical Specifications
Automotive
Symbol
VOH
Parameter
Min.
Max.
Units
V
VCCI = MIN, VI = VIH or VIL
(IOH = –3.5 mA)
(IOL= 3.5 mA)
2.4
VOL
VCCI = MIN, VI = VIH or VIL
0.4
0.8
V
VIL
Input Low Voltage, VOUT ≤ VOL(max)
Input High Voltage, VOUT ≥ VOH(min)
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current, VOUT = Tristate
Input Transition Time tR, tF
Input Capacitance
V
VIH
2.0
–20
–20
V
IIL / IIH
IOZ
20
20
10
10
35
µA
µA
ns
1,2
tR, tF
CIN
pF
mA
3
ICC
Standby Current
IV Curve
Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.8 V to 2.0 V.
2. tF is the transition time from 2.0 V to 0.8 V.
3. ICC = ICCI + ICCA
4. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.
v3.2
1-13
eX Automotive Family FPGAs
5 V Tolerance of 3.3 V LVTTL I/Os Using a Tristate Buffer
Input: 3.3 V LVTTL I/Os are 5-V-input tolerant only if the non-PCI mode is used (no clamp diode).
Output: To configure an Actel eX device to drive 5 V with VCCI = 3.3 V, users can utilize an Open Drain configuration of
the I/O cell with an array inverter cell and an external pull-up resistor to 5 V. The recommended configuration is
illustrated in Figure 1-14. The I/O configuration must be set to LVTTL to disable the PCI clamp diode. For the
recommended resistor value in a specific application, please contact Actel Technical Support. For more details, refer to
the Design Tips section of the Actel eX, SX-A and RT54SX-S I/Os application note.
Actel Open Drain Configuration
5 V
User Internal Signal
E
PAD
TRIBUFF
Figure 1-14 • Open-Drain Configuration for eX
CEQ = Equivalent capacitance
Power Dissipation
F
= switching frequency
Power consumption for eX devices can be divided into
two components: static and dynamic.
Equivalent capacitance is calculated by measuring ICCA at
a specified frequency and voltage for each circuit
component of interest. Measurements have been made
Static Power Component
over a range of frequencies at a fixed value of VCCA
.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
The power due to standby current is typically a small
component of the overall power. Typical standby current
for eX devices is listed in Table 1-10 on page 1-12. For
example, the typical static power for eX128 at 3.3 V VCCI
is:
I
CC * VCCA = 795 µA x 2.5 V = 1.99 mW
CEQ Values for eX Devices
Combinatorial modules (Ceqcm) 1.70 pF
Dynamic Power Component
Sequential modules (Ceqsm)
Input buffers (Ceqi)
Output buffers (Ceqo)
Routed array clocks (Ceqcr)
1.70 pF
1.30 pF
7.40 pF
1.05 pF
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Dynamic power dissipation results from
charging internal chip capacitance. An additional
component of the dynamic power dissipation is the
totem pole current in the CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance
that can be combined with frequency and voltage to
represent dynamic power dissipation.
The variable and fixed capacitance of other device
components must also be taken into account when
estimating the dynamic power dissipation.
Dynamic power dissipation = CEQ * VCCA2 x F
1-14
v3.2
eX Automotive Family FPGAs
Table 1-11 shows the capacitance of the clock
components of eX devices.
fn
fp
= Average input buffer switching frequency,
typically F/5
= Average output buffer switching frequency,
typically F/5
= Frequency of routed clock A
= Frequency of routed clock B
= Frequency of dedicated array clock
Table 1-11 • Capacitance of Clock Components of eX
Devices
fq1
fq2
fs1
eX64
eX128
eX256
Dedicated array clock –
variable (Ceqhv)
0.85 pF
0.85 pF
0.85 pF
The eX, SX-A and RTSX-S Power Calculator can be used to
estimate the total power dissipation (static and dynamic)
of eX devices and can be found at
http://www.actel.com/products/rescenter/power/
calculators.aspx.
Dedicated array clock – fixed
(Ceqhf)
18.00 pF 20.00 pF 25.00 pF
Routed array clock A (r1)
Routed array clock B (r2)
23.00 pF 28.00 pF 35.00 pF
23.00 pF 28.00 pF 35.00 pF
Junction Temperature
The estimation of the dynamic power dissipation is a
piece-wise linear summation of the power dissipation of
each component.
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-1,
shown below, can be used to calculate junction
temperature. Please refer to Table 1-9 on page 1-12 for
the recommended operating conditions.
Dynamic power dissipation
= VCCA2 * [(mc * Ceqcm * fmC)Comb Modules + (ms * Ceqsm
*
fmS)Seq Modules + (n * Ceqi * fn)Input Buffers + (0.5 * (q1 *
Ceqcr * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * Ceqcr * fq2) +
(r2 * fq2))RCLKB + (0.5 * (s1 * Ceqhv * fs1)+(Ceqhf
*
fs1))HCLK] + VCCI2 * [(p * (Ceqo + CL) * fp)Output Buffers
where:
]
EQ 1-1
mc
ms
n
= Number of combinatorial cells switching at
Junction Temperature = ∆T + Ta(1)
frequency fm, typically 20% of C-cells
= Number of sequential cells switching at
frequency fm, typically 20% of R-cells
= Number of input buffers switching at
frequency fn, typically number of inputs / 4
= Number of output buffers switching at
frequency fp, typically number of outputs / 4
= Number of R-cells driven by routed array
clock A
Where:
Ta = Ambient Temperature
∆T = Temperature gradient between junction (silicon)
and ambient = θja * P
p
P = Power
q1
q2
θ
= Junction to ambient of package. θ numbers are
ja
located in the "Package Thermal Characteristics" section
on page 1-16.
ja
= Number of R-cells driven by routed array
clock B
r1
r2
s1
= Fixed capacitance due to routed array clock A
= Fixed capacitance due to routed array clock B
= Number of R-cells driven by dedicated array
clock
Ceqcm = Equivalent capacitance of combinatorial
modules
Ceqsm = Equivalent capacitance of sequential modules
Ceqi = Equivalent capacitance of input buffers
Ceqcr = Equivalent capacitance of routed array clocks
Ceqhv = Variable capacitance of dedicated array clock
Ceqhf = Fixed capacitance of dedicated array clock
Ceqo = Equivalent capacitance of output buffers
CL
= Average output loading capacitance, typically
10pF
fmc
= Average C-cell switching frequency, typically
F/10
fms = Average R-cell switching frequency, typically
F/10
v3.2
1-15
eX Automotive Family FPGAs
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates. θjc is provided for reference.
The maximum power dissipation allowed for eX devices
is a function of θja. A sample calculation of the absolute
maximum power dissipation allowed for a TQFP 100-pin
package at automotive temperature and still air is as
follows:
The maximum junction temperature is 150°C.
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C
--------------------------------------------------------------------------------------------------------------------------------- -------------------------------------
= 0.746 W
Maximum Power Allowed =
=
θja(°C/W)
33.5°C/W
Table 1-12 • Package Thermal Characteristics
θja
ja 1.0 m/s
36.3
Package Type
Pin Count
θjc
Still Air
42.4
θ
θ
ja 2.5 m/s
Units
°C/W
°C/W
°C/W
°C/W
°C/W
Thin Quad Flat Pack
Thin Quad Flat Pack
Chip-Scale Package
Chip-Scale Package
Chip-Scale Package
64
100
49
12.0
14.0
34.0
33.5
27.4
25.0
72.2
59.5
54.1
128
180
54.1
44.6
40.6
57.8
47.6
43.3
1-16
v3.2
eX Automotive Family FPGAs
eX Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.5 ns
= 0.7 ns
I/O Module
I/O Module
IRD1
IRD2
t
= 1.3 ns
INYH
t
= 4.9 ns
DHL
t
= 1.1 ns
PD
t
t
t
= 0.6 ns
RD1
= 1.1 ns
RD4
= 1.9 ns
RD8
I/O Module
Register
Cell
t
= 4.0 ns
ENZL
D
Q
t
t
t
RD1
= 0.8 ns
= 0.6 ns
SUD
HD
= 0.0 ns
t
= 4.9 ns
DHL
Routed
Clock
t
= 2.3 ns
RCKH
t
= 1.0 ns
(100% Load)
RCO
I/O Module
Register
Cell
I/O Module
t
= 1.3 ns
t
= 4.0 ns
INYH
ENZL
t
= 0.5 ns
= 0.8 ns
IRD1
D
Q
t
t
t
RD1
= 0.6 ns
SUD
= 0.0 ns
HD
t
= 4.9 ns
DHL
Hardwired
Clock
t
t
RCO
= 1.8 ns
= 1.0 ns
HCKH
Note: *Values shown for eX128, worst-case automotive conditions (2.3 V VCCA, 3.3 V VCCI, 35 pF Pad Load).
Figure 1-15 • eX Timing Model
Hardwired Clock
Routed Clock
External Setup = tINYH + tIRD1 + tSUD – tHCKH
External Setup = tINYH + tIRD2 + tSUD – tRCKH
=
1.3 + 0.5 + 0.8 – 1.8 = 0.8 ns
=
1.3 + 0.7 + 0.8 – 2.3 = 0.5 ns
Clock-to-Out (Pad-to-Pad), typical
Clock-to-Out (Pad-to-Pad), typical
=
=
t
HCKH + tRCO + tRD1 + tDHL
=
=
t
RCKH + tRCO + tRD1 + tDHL
1.8 + 1.0 + 0.6 + 4.9 = 8.3 ns
2.3 + 1.0 + 0.6 + 4.9 = 8.8 ns
v3.2
1-17
eX Automotive Family FPGAs
Output Buffer Delays
E
D
PAD To AC test loads (shownbelow)
VCC
TRIBUFF
VCC
VCC
50% 50%
VCC
In
50%
50%
GND
1.5 V
50% 50%
VOH
GND
En
GND
90%
En
Out
VOH
1.5 V
1.5 V
10%
Out
VOL
1.5 V
Out
GND
VOL
t
t
t
t
t
ENHZ
t
DHL
DLH
ENZL
ENZH
ENLZ
Table 1-13 • Output Buffer Delays
AC Test Loads
Load 3
(Used to measure disable delays)
Load 1
(used to measure
propagation delay)
Load 2
(Used to measure enable delays)
GND
GND
VCC
VCC
To the output
under test
t
t
R to VCC for PLZ
R to VCC for PZL
35 pF
t
t
To the output
under test
To the output
under test
R to GND for PHZ
R to GND for PHZ
R = 1 kΩ
R = 1 kΩ
35 pF
5 pF
Figure 1-16 • AC Test Loads
1-18
v3.2
eX Automotive Family FPGAs
Input Buffer Delays
C-Cell Delays
S
Y
A
B
Y
PAD
INBUF
VCC
S, A, or B
50%
tPD
50%
VCC
GND
3V
1.5 V 1.5 V
50%
Out
GND
50%
In
0V
tPD
V
CC
50%
VCC
Out
Out
50%
GND
tPD
50%
tPD
50%
GND
tINY
tINY
Table 1-14 • Input Buffer Delays
Table 1-15 • C-Cell Delays
Cell Timing Characteristics
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tHP
tSUD
tHPWH
,
tRPWH
CLK
,
tHPWL
tRPWL
tRCO
Q
tPRESET
tCLR
tWASYN
CLR
PRESET
Figure 1-17 • Flip-Flops
v3.2
1-19
eX Automotive Family FPGAs
Long Tracks
Timing Characteristics
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, no more than six
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to
8.4 ns delay. This additional delay is represented
statistically in higher fanout routing delays.
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer tool in the Designer software or performing
simulation with post-layout delays.
Table 1-17
on
page 1-21
lists
sample
timing
characteristics for automotive eX devices.
Timing Derating
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature, and worst-case processing.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to six percent of the nets in a design may be designated
as critical.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 125°C, VCCA = 2.3 V)
Junction Temperature (TJ)
25 70
VCCA
2.3
–55
0.70
0.65
0.61
–40
0.70
0.66
0.62
0
85
125
1.00
0.93
0.88
0.77
0.72
0.67
0.78
0.73
0.69
0.88
0.83
0.78
0.91
0.85
0.80
2.5
2.7
1-20
v3.2
eX Automotive Family FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
‘Std.’ Speed
Parameter
Description
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
1.1
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, DirectConnect
0.1
0.6
0.6
0.7
0.9
1.1
1.9
2.8
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, FastConnect
FO=1 Routing Delay
tRD1
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
tRD12
R-Cell Timing
tRCO
FO=12 Routing Delay
Sequential Clock-to-Q
1.0
0.9
1.0
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
tPRESET
tSUD
0.8
0.0
2.2
0.6
0.6
tHD
tWASYN
tRECASYN
tHASYN
2.5 V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
1.1
1.4
ns
ns
3.3 V Input Module Propagation Delays
tINYH
Input Data Pad-to-Y High
1.3
1.6
ns
ns
tINYL
Input Data Pad-to-Y Low
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
0.5
0.7
0.9
ns
ns
ns
tIRD2
tIRD3
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
v3.2
1-21
eX Automotive Family FPGAs
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
‘Std.’ Speed
Parameter
tIRD4
Description
Min.
Max.
Units
ns
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
1.1
1.9
2.8
tIRD8
ns
tIRD12
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-Cell Input)
1.8
1.8
ns
ns
tHCKL
Input High to Low
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
2.0
2.0
ns
ns
0.1
ns
Minimum Period
4.0
ns
fHMAX
Maximum Frequency
250
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-Cell Input)
1.6
1.6
1.9
1.9
2.3
2.3
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-Cell Input)
Input Low to High (50% Load)
(Pad to R-Cell Input)
Input High to Low (50% Load)
(Pad to R-Cell Input)
Input Low to High (100% Load)
(Pad to R-Cell Input)
Input High to Low (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width High
2.0
2.0
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width Low
3
3
3
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.3
0.2
0.1
2.5 V LVCMOS2 Output Module Timing4 (VCCI = 2.3 V)
tDLH
Data-to-Pad Low to High
5.9
6.3
ns
ns
ns
tDHL
Data-to-Pad High to Low
tDHLS
Notes:
Data-to-Pad High to Low—Low Slew
20.8
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
1-22
v3.2
eX Automotive Family FPGAs
‘Std.’ Speed
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
Parameter
tENZL
Description
Min.
Max.
4.5
Units
ns
Enable-to-Pad, Z to L
tENZLS
tENZH
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
21.2
6.1
ns
ns
tENLZ
Enable-to-Pad, L to Z
3.8
ns
tENHZ
Enable-to-Pad, H to Z
7.1
ns
dTLH
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
0.058
0.028
0.090
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
3.3 V LVTTL Output Module Timing1 (VCCI = 3.0 V)
tDLH
Data-to-Pad Low to High
5.0
4.9
ns
ns
tDHL
Data-to-Pad High to Low
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
Data-to-Pad High to Low—Low Slew
Enable-to-Pad, Z to L
17.4
4.0
ns
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
17.4
5.0
ns
ns
Enable-to-Pad, L to Z
5.0
ns
Enable-to-Pad, H to Z
4.8
ns
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
0.038
0.028
0.090
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
v3.2
1-23
eX Automotive Family FPGAs
Pin Description
CLKA/B
Routed Clock A and B
TDI, I/O
Test Data Input
These pins are clock inputs for clock distribution
networks. Input levels are compatible with LVTTL and
LVCMOS specifications. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
Low or High on the board. It must not be left floating.
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set Low (refer to Table 1-3 on page 1-8). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
GND
Ground
TDO, I/O
Test Data Output
Low supply voltage.
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set Low (refer to
Table 1-3 on page 1-8). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer is being used, TDO
will act as an output when the "checksum" command is
run. It will return to a user I/O when "checksum" is
complete.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with LVTTL and LVCMOS
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set Low or High
on the board. It must not be left floating.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode, when the TMS pin is set Low, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-3 on
page 1-8). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic
reset” state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output levels are
compatible with LVTTL and LVCMOS specifications.
Unused I/O pins are automatically tristated by the
Designer software. It is recommended to tie unused I/Os
to Low on the board. This also applies to dual-purpose
pins when configured as I/Os.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in the Designer software.
PRA/PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-
defined design node within the device. This diagnostic
pin can be used independently or in conjunction with the
other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be
employed as a user-defined I/O when verification has
been completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
V
Supply Voltage
CCI
Supply voltage for I/Os.
V
Supply Voltage
CCA
Supply voltage for Array.
TCK, I/O
Test Clock
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set Low (refer to Table 1-3 on
page 1-8). This pin functions as an I/O when the
boundary scan state machine reaches the “logic reset”
state.
1-24
v3.2
eX Automotive Family FPGAs
Package Pin Assignments
64-Pin TQFP
64
1
64-Pin
TQFP
Figure 2-1 • 64-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/rescenter/package/index.html.
v3.2
2-1
eX Automotive Family FPGAs
64-Pin TQFP
64-Pin TQFP
eX64
eX128
eX64
eX128
Pin Number
Function
Function
Pin Number
Function
Function
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
I/O
GND
I/O
2
3
I/O
I/O
4
TMS
GND
VCCI
I/O
TMS
GND
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
5
6
7
I/O
I/O
8
I/O
I/O
NC
I/O
9
NC
I/O
NC
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
I/O
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
PRB, I/O
VCCA
GND
I/O
PRB, I/O
VCCA
GND
I/O
I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
TDO, I/O
TCK, I/O
TCK, I/O
2-2
v3.2
eX Automotive Family FPGAs
100-Pin TQFP
100
1
100-Pin
TQFP
Figure 2-2 • 100-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/rescenter/package/index.html.
v3.2
2-3
eX Automotive Family FPGAs
100-Pin TQFP
100-Pin TQFP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
Function
Function
Pin Number
Function
GND
NC
Function
Function
1
GND
TDI, I/O
NC
GND
TDI, I/O
NC
GND
TDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
NC
GND
NC
2
3
I/O
I/O
I/O
4
NC
NC
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
5
NC
NC
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
TMS
TMS
TMS
I/O
I/O
I/O
8
V
V
V
CCI
I/O
I/O
I/O
CCI
CCI
9
GND
NC
GND
I/O
GND
I/O
V
V
V
CCI
CCI
CCI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
NC
TDO, I/O
I/O
TDO, I/O
I/O
NC
I/O
I/O
TRST, I/O
NC
TRST, I/O
I/O
TRST, I/O
I/O
GND
NC
GND
NC
GND
I/O
I/O
I/O
I/O
NC
NC
I/O
NC
I/O
I/O
NC
NC
I/O
V
V
V
CCI
I/O
I/O
I/O
CCI
CCI
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCA
CCA
CCA
NC
NC
I/O
V
V
V
CCI
CCI
CCI
NC
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
V
CCA
CCA
CCA
I/O
I/O
I/O
GND
GND
GND
PRB, I/O
PRB, I/O
PRB, I/O
GND
I/O
GND
I/O
GND
I/O
V
V
V
CCA
CCA
CCA
2-4
v3.2
eX Automotive Family FPGAs
100-Pin TQFP
eX64
eX128
eX256
Pin Number
Function
Function
Function
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
V
V
V
CCI
CCI
CCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
V
V
V
CCA
CCA
CCA
GND
PRA, I/O
I/O
GND
PRA, I/O
I/O
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
v3.2
2-5
eX Automotive Family FPGAs
49-Pin CSP
A1 Ball Pad Corner
2
3
6
1
5
7
4
A
B
C
D
E
F
G
Figure 2-3 • 49-Pin CSP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/rescenter/package/index.html.
2-6
v3.2
eX Automotive Family FPGAs
49-Pin CSP
49-Pin CSP
eX64
eX128
eX64
eX128
Pin Number
Function
Function
Pin Number
Function
Function
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
I/O
I/O
I/O
I/O
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
TRST, I/O
VCCI
GND
I/O
TRST, I/O
VCCI
GND
I/O
I/O
I/O
TCK, I/O
I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
PRA, I/O
CLKA
I/O
PRA, I/O
CLKA
I/O
F2
I/O
I/O
F3
I/O
I/O
GND
I/O
GND
I/O
F4
I/O
I/O
F5
HCLK
I/O
HCLK
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
F6
F7
TDO, I/O
I/O
TDO, I/O
I/O
G1
G2
G3
G4
G5
G6
G7
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
I/O
PRB, I/O
VCCA
I/O
I/O
I/O
TMS
GND
GND
TMS
GND
GND
I/O
I/O
v3.2
2-7
eX Automotive Family FPGAs
128-Pin CSP
A1 Ball Pad Corner
2
3
4
5
6
8
12
1
7
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-4 • 128-Pin CSP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/rescenter/package/index.html.
2-8
v3.2
eX Automotive Family FPGAs
128-Pin CSP
128-Pin CSP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
A1
Function
Function
Function
Pin Number
C12
D1
Function
Function
Function
I/O
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
A2
TCK, I/O
VCCI
I/O
NC
A3
D2
I/O
I/O
I/O
A4
D3
I/O
I/O
I/O
A5
I/O
I/O
I/O
D4
I/O
I/O
I/O
A6
VCCA
I/O
VCCA
I/O
VCCA
I/O
D5
I/O
I/O
I/O
A7
D6
GND
I/O
GND
I/O
GND
I/O
A8
I/O
I/O
I/O
D7
A9
VCCI
I/O
VCCI
I/O
VCCI
I/O
D8
GND
I/O
GND
I/O
GND
I/O
A10
A11
A12
B1
D9
I/O
I/O
I/O
D10
D11
D12
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O
TMS
I/O
TMS
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
B2
B3
I/O
I/O
I/O
E2
VCCI
I/O
VCCI
I/O
VCCI
I/O
B4
I/O
I/O
I/O
E3
B5
I/O
I/O
I/O
E4
GND
GND
I/O
GND
GND
I/O
GND
GND
I/O
B6
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
E9
B7
E10
E11
E12
F1
B8
GND
VCCA
NC
GND
VCCA
I/O
GND
VCCA
I/O
B9
I/O
I/O
I/O
B10
B11
B12
C1
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
F2
NC
I/O
I/O
F3
NC
I/O
I/O
I/O
I/O
I/O
F4
I/O
I/O
I/O
C2
TDI, I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
F9
GND
NC
GND
I/O
GND
I/O
C3
F10
F11
F12
G1
C4
I/O
I/O
I/O
I/O
I/O
I/O
C5
I/O
I/O
I/O
I/O
I/O
I/O
C6
CLKA
I/O
CLKA
I/O
CLKA
I/O
NC
I/O
I/O
C7
G2
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
C8
I/O
I/O
I/O
G3
C9
I/O
I/O
I/O
G4
GND
GND
NC
GND
GND
I/O
GND
GND
I/O
C10
C11
NC
I/O
I/O
G9
NC
I/O
I/O
G10
v3.2
2-9
eX Automotive Family FPGAs
128-Pin CSP
128-Pin CSP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
Function
Function
Pin Number
K8
Function
Function
Function
G11
G12
H1
H2
H3
H4
H9
H10
H11
H12
J1
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K9
I/O
GND
I/O
GND
I/O
GND
I/O
K10
K11
K12
L1
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
VCCI
VCCA
NC
VCCI
VCCA
I/O
VCCI
VCCA
I/O
L3
NC
I/O
I/O
L4
I/O
I/O
I/O
L5
I/O
I/O
I/O
NC
NC
VCCA
I/O
L6
I/O
I/O
I/O
J2
I/O
I/O
L7
I/O
I/O
I/O
J3
VCCI
I/O
VCCI
I/O
VCCI
I/O
L8
I/O
I/O
I/O
J4
L9
I/O
I/O
I/O
J5
I/O
I/O
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
J6
I/O
I/O
I/O
NC
I/O
I/O
J7
GND
I/O
GND
I/O
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
J8
J9
GND
I/O
GND
I/O
GND
I/O
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
HCLK
PRB, I/O
HCLK
PRB, I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
2-10
v3.2
eX Automotive Family FPGAs
180-Pin CSP
A1 Ball Pad Corner
12
1
2
3
4
5
6
7
9 10
14
13
8
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2-5 • 180-Pin CSP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/rescenter/package/index.html.
v3.2
2-11
eX Automotive Family FPGAs
180-Pin CSP
180-Pin CSP
180-Pin CSP
180-Pin CSP
Pin
eX256
Pin
eX256
Pin
eX256
Pin
eX256
Number
Function
Number
Function
Number
E11
E12
E13
E14
F1
Function
Number
H14
J1
Function
A1
A2
I/O
I/O
C6
I/O
PRA, I/O
CLKB
I/O
I/O
I/O
I/O
I/O
C7
A3
GND
NC
C8
VCCI
I/O
J2
GND
I/O
A4
C9
J3
A5
NC
C10
C11
C12
C13
C14
D1
I/O
I/O
J4
VCCI
GND
I/O
A6
NC
I/O
F2
I/O
J5
A7
NC
GND
I/O
F3
VCCI
I/O
J10
J11
J12
J13
J14
K1
A8
NC
F4
VCCI
VCCA
I/O
A9
NC
I/O
F5
GND
GND
I/O
A10
A11
A12
A13
A14
B1
NC
I/O
F10
F11
F12
F13
F14
G1
NC
D2
I/O
I/O
I/O
D3
TDI, I/O
I/O
GND
VCCA
I/O
I/O
I/O
D4
K2
VCCA
I/O
I/O
D5
I/O
K3
I/O
D6
I/O
VCCA
I/O
K4
VCCI
I/O
B2
I/O
D7
CLKA
I/O
G2
K5
B3
TCK, I/O
VCCI
I/O
D8
G3
I/O
K6
I/O
B4
D9
I/O
G4
I/O
K7
I/O
B5
D10
D11
D12
D13
D14
E1
I/O
G5
I/O
K8
GND
I/O
B6
I/O
I/O
G10
G11
G12
G13
G14
H1
GND
I/O
K9
B7
VCCA
I/O
I/O
K10
K11
K12
K13
K14
L1
GND
I/O
B8
I/O
I/O
B9
I/O
I/O
I/O
I/O
B10
B11
B12
B13
B14
C1
VCCI
I/O
I/O
VCCA
I/O
I/O
E2
I/O
I/O
I/O
E3
I/O
H2
I/O
I/O
I/O
E4
I/O
H3
TRST, I/O
I/O
L2
I/O
I/O
E5
I/O
H4
L3
I/O
I/O
E6
I/O
H5
GND
GND
I/O
L4
I/O
C2
TMS
I/O
E7
GND
I/O
H10
H11
H12
H13
L5
I/O
C3
E8
L6
I/O
C4
I/O
E9
GND
I/O
I/O
L7
PRB, I/O
HCLK
C5
I/O
E10
I/O
L8
2-12
v3.2
eX Automotive Family FPGAs
180-Pin CSP
180-Pin CSP
Pin
eX256
Pin
eX256
Number
Function
Number
N14
P1
Function
L9
I/O
I/O
I/O
I/O
L10
L11
L12
L13
L14
M1
I/O
P2
I/O
TDO, I/O
I/O
P3
I/O
P4
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
I/O
P5
I/O
P6
M2
I/O
P7
M3
I/O
P8
M4
I/O
P9
M5
I/O
P10
P11
P12
P13
M6
I/O
M7
I/O
M8
I/O
M9
I/O
M10
M11
M12
M13
M14
N1
I/O
I/O
I/O
VCCI
I/O
I/O
N2
GND
I/O
N3
N4
I/O
N5
I/O
N6
I/O
N7
I/O
N8
VCCA
I/O
N9
N10
N11
N12
N13
I/O
I/O
I/O
I/O
v3.2
2-13
eX Automotive Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (v3.2)
Page
v3.1
The "Ordering Information" section was updated to include RoHS information. The TQFP ii
measurement was also updated.
(Published 4/06)
The "Dedicated Test Mode" section was updated.
1-8
Note 4 was added to the"3.3 V LVTTL Electrical Specifications" table.
A note was added to the "Ordering Information" section.
1-13
ii
v3.0
(Published 6/04)
The Junction temperature was added to Table 1-8 • Absolute Maximum Ratings*.
The note was changed in Table 1-9 • Recommended Operating Conditions.
The IOH and IOL values were updated in the "3.3 V LVTTL Electrical Specifications" table.
The "5 V Tolerance of 3.3 V LVTTL I/Os Using a Tristate Buffer" section is new.
1-12
1-12
1-13
1-14
A reference to Table 1-9 • Recommended Operating Conditions was added to the 1-12
"Junction Temperature".
v2.0
"Speed Grade and Temperature Grade Matrix" section table is new.
Table 1-2 was updated.
ii
1-5
Table 1-9 was updated.
1-12
1-14
1-16
1-19
1-17
1-24
The "CEQ Values for eX Devices" sectionis new.
The "Package Thermal Characteristics" section was updated.
Table 1-14 was updated.
Figure 1-15 was updated.
The "Pin Description" section was updated.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require
an approved export license prior to export from the United States. An export includes release of product or disclosure
of technology to a foreign national inside or outside the United States.
v3.2
3-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
www.jp.actel.com
Actel Hong Kong
www.actel.com.cn
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Fax +81.03.3445.7668
Phone +852 2185 6460
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51700017-4/6.06
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