EX256-FCS180I [MICROSEMI]

Field Programmable Gate Array;


型号：	EX256-FCS180I
厂家：	Microsemi
描述：	Field Programmable Gate Array 时钟栅可编程逻辑
文件：	总49页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v4.3

eX Family FPGAs

FuseLock

•

Live on Power-Up

No Power-Up/Down Sequence Required for Supply

Voltages

Leading Edge Performance

•

240 MHz System Performance

350 MHz Internal Performance

3.9 ns Clock-to-Out (Pad-to-Pad)

•

Configurable Weak-Resistor Pull-Up or Pull-Down

for Tristated Outputs during Power-Up

Individual Output Slew Rate Control

2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation

with 5.0V Input Tolerance and 5.0V Drive Strength

Software Design Support with Actel Designer and

Libero™ Integrated Design Environment (IDE)

Tools

•

Specifications

•

3,000 to 12,000 Available System Gates

Maximum 512 Flip-Flops (Using CC Macros)

0.22µm CMOS Process Technology

Up to 132 User-Programmable I/O Pins

•

Up to 100% Resource Utilization with 100% Pin

Locking

•

Deterministic Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Fuselock™ Secure Programming Technology

Prevents Reverse Engineering and Design Theft

Features

•

High-Performance, Low-Power Antifuse FPGA

•

LP/Sleep Mode for Additional Power Savings

Advanced Small-Footprint Packages

Hot-Swap Compliant I/Os

Single-Chip Solution

Nonvolatile

Product Profile

Device

eX64

eX128

eX256

Capacity

3,000

2,000

6,000

4,000

12,000

8,000

System Gates

Typical Gates

Dedicated Flip-Flops

Maximum Flip-Flops

128

256

512

Combinatorial Cells

Maximum User I/Os

128

256

100

512

132

Global Clocks

Hardwired

Routed

Speed Grades

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

–F, Std, –P

C, I, A

Temperature Grades*

Package (by pin count)

TQFP

CSP

64, 100

49, 128

64, 100

49, 128

100

128, 180

Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.

June 2006

eX Family FPGAs

Ordering Information

eX128

100

Application (Ambient Temperature Range)

Blank = Commercial (0˚C to 70˚C)

I = Industrial (-40˚C to 85˚C)

A= Automotive (-40˚C to 125˚C)

PP = Pre-production

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS Compliant Packaging

Package Type

TQ Thin Quad Flat Pack (0.5 mm pitch)

Chip-Scale Package (0.8 mm pitch)

Speed Grade

Blank= Standard Speed

P = Approximately 30% Faster than Standard

F = Approximately 40% Slower than Standard

Part Number

eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)

eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)

eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)

Plastic Device Resources

User I/Os (Including Clock Buffers)

Device

TQFP 64-Pin

TQFP 100-Pin

CSP 49-Pin

CSP 128-Pin

CSP 180-Pin

eX64

—

eX128

eX256

100

132

Note: Package Definitions:TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package

Temperature Grade Offerings

Device\Package

eX64

TQFP 64-Pin

C, I, A

TQFP 100-Pin

C, I, A

CSP 49-Pin

C, I, A

CSP 128-Pin

C, I, A

CSP 180-Pin

C, I, A

eX128

C, I, A

eX256

C, I, A

Notes:

C = Commercial

I = Industrial

A = Automotive

Speed Grade and Temperature Grade Matrix

–F

✓

Std

✓

–P

✓

Notes:

P = Approximately 30% faster than Standard

–F = Approximately 40% slower than Standard

Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.

Contact your local Actel representative for device availability.

v4.3

eX Family FPGAs

Table of Contents

eX Family FPGAs

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Package Pin Assignments

64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

v4.3

iii

eX Family FPGAs

impedance connection. Actel’s eX family provides two

types of logic modules, the register cell (R-cell) and the

combinatorial cell (C-cell).

General Description

The eX family of FPGAs is a low-cost solution for low-

power, high-performance designs. The inherent low

power attributes of the antifuse technology, coupled

with an additional low static power mode, make these

devices ideal for power-sensitive applications. Fabricated

with an advanced 0.22µm CMOS antifuse technology,

these devices achieve high performance with no power

penalty.

The R-cell contains a flip-flop featuring asynchronous

clear, asynchronous preset, and clock enable (using the

S0 and S1 lines) control signals (Figure 1-1). The R-cell

registers feature programmable clock polarity selectable

on a register-by-register basis. This provides additional

flexibility while allowing mapping of synthesized

functions into the eX FPGA. The clock source for the R-

cell can be chosen from either the hard-wired clock or

the routed clock.

eX Family Architecture

The C-cell implements a range of combinatorial functions

up to five inputs (Figure 1-2 on page 1-2). Inclusion of

the DB input and its associated inverter function enables

the implementation of more than 4,000 combinatorial

functions in the eX architecture in a single module.

Actel's eX family is implemented on a high-voltage twin-

well CMOS process using 0.22µm design rules. The eX

family architecture uses a “sea-of-modules” structure

where the entire floor of the device is covered with a

grid of logic modules with virtually no chip area lost to

interconnect elements or routing. Interconnection

among these logic modules is achieved using Actel’s

Two C-cells can be combined together to create a flip-

flop to imitate an R-cell via the use of the CC macro. This

is particularly useful when implementing non-timing-

critical paths and when the design engineer is running

out of R-cells. More information about the CC macro can

be found in Actel’s Maximizing Logic Utilization in eX, SX

and SX-A FPGA Devices Using CC Macros application

note.

patented

metal-to-metal

programmable

antifuse

interconnect elements. The antifuse interconnect is

made up of a combination of amorphous silicon and

dielectric material with barrier metals and has an "on"

state resistance of 25Ω with a capacitance of 1.0fF for

low-signal impedance. The antifuses are normally open

circuit and, when programmed, form a permanent low-

Routed

Data Input

PSET

DirectConnect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CLR

CKS

CKP

Figure 1-1 • R-Cell

v4.3

1-1

eX Family FPGAs

Module Organization

C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells

and one R-cell in a C-R-C configuration.

Clusters are further organized into modules called SuperClusters for improved design efficiency and device

performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters.

A0 B0

Figure 1-2 • C-Cell

R-Cell

C-Cell

Routed

Data Input

PSET

CLR

DirectConnect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CKS

CKP

A0 B0

Cluster

SuperCluster

Figure 1-3 • Cluster Organization

1-2

v4.3

eX Family FPGAs

Routing Resources

Clusters and SuperClusters can be connected through the

use of two innovative local routing resources called

FastConnect and DirectConnect, which enable extremely

fast and predictable interconnection of modules within

Clusters and SuperClusters (Figure 1-4). This routing

architecture also dramatically reduces the number of

antifuses required to complete a circuit, ensuring the

highest possible performance.

FastConnect enables horizontal routing between any

two logic modules within a given SuperCluster and

vertical routing with the SuperCluster immediately

below it. Only one programmable connection is used in a

FastConnect path, delivering maximum pin-to-pin

propagation of 0.3 ns (–P speed grade).

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing

between SuperClusters. The exact combination of track

lengths and antifuses within each path is chosen by the

fully automatic place-and-route software to minimize

signal propagation delays.

DirectConnect is a horizontal routing resource that

provides connections from a C-cell to its neighboring R-

cell in a given SuperCluster. DirectConnect uses a hard-

wired signal path requiring no programmable

interconnection to achieve its fast signal propagation

time of less than 0.1 ns (–P speed grade).

DirectConnect

• No antifuses

SuperClusters

• 0.1 ns routing delay

FastConnect

• One antifuse

• 0.5 ns routing delay

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Figure 1-4 • DirectConnect and FastConnect for SuperClusters

v4.3

1-3

eX Family FPGAs

The remaining two clocks (CLKA, CLKB) are global routed

clock networks that can be sourced from external pins or

from internal logic signals (via the CLKINT routed clock

buffer) within the eX device. CLKA and CLKB may be

connected to sequential cells or to combinational logic. If

CLKA or CLKB is sourced from internal logic signals, the

external clock pin cannot be used for any other input

and must be tied LOW or HIGH and must not float.

Figure 1-6 describes the CLKA and CLKB circuit used in eX

devices.

Clock Resources

eX’s high-drive routing structure provides three clock

networks. The first clock, called HCLK, is hardwired from

the HCLK buffer to the clock select MUX in each R-Cell.

HCLK cannot be connected to combinational logic. This

provides a fast propagation path for the clock signal,

enabling the 3.9 ns clock-to-out (pad-to-pad)

performance of the eX devices. The hard-wired clock is

tuned to provide a clock skew of less than 0.1 ns worst

case. If not used, the HCLK pin must be tied LOW or HIGH

and must not be left floating. Figure 1-5 describes the

clock circuit used for the constant load HCLK.

Table 1-1 describes the possible connections of the

routed clock networks, CLKA and CLKB.

HCLK does not function until the fourth clock cycle each

time the device is powered up to prevent false output

levels due to any possible slow power-on-reset signal and

fast start-up clock circuit. To activate HCLK from the first

cycle, the TRST pin must be reserved in the Design

software and the pin must be tied to GND on the board.

(See the "TRST, I/O Boundary Scan Reset Pin" on page 1-

26).

Unused clock pins must not be left floating and must be

tied to HIGH or LOW.

Constant Load

Clock Network

HCLKBUF

Figure 1-5 • eX HCLK Clock Pad

Clock Network

From Internal Logic

CLKBUF

CLKBUFI

CLKINT

CLKINTI

Figure 1-6 • eX Routed Clock Buffer

Table 1-1 • Connections of Routed Clock Networks, CLKA

and CLKB

Module

C-Cell

Pins

A0, A1, B0 and B1

CLKA, CLKB, S0, S1, PSET, and CLR

R-Cell

I/O-Cell

1-4

v4.3

eX Family FPGAs

Other Architectural Features

All unused I/Os are configured as tristate outputs by

Actel's Designer software, for maximum flexibility when

designing new boards or migrating existing designs. Each

I/O module has an available pull-up or pull-down resistor

of approximately 50 kΩ that can configure the I/O in a

known state during power-up. Just shortly before V_CCA

reaches 2.5 V, the resistors are disabled and the I/Os will be

controlled by user logic.

Performance

The combination of architectural features described

above enables eX devices to operate with internal clock

frequencies exceeding 350 MHz for very fast execution

of complex logic functions. The eX family is an optimal

platform upon which the functionality previously

contained in CPLDs can be integrated. eX devices meet

the performance goals of gate arrays, and at the same

time, present significant improvements in cost and time

to market. Using timing-driven place-and-route tools,

designers can achieve highly deterministic device

performance.

Table 1-2 describes the I/O features of eX devices. For

more information on I/Os, refer to Actel eX, SX-A, and

RT54SX-S I/Os application note.

Table 1-2 • I/O Features

Function

Description

User Security

Input Buffer • 5.0V TTL

Threshold

•

3.3V LVTTL

The Actel FuseLock advantage ensures that unauthorized

users will not be able to read back the contents of an

Actel antifuse FPGA. In addition to the inherent

strengths of the architecture, special security fuses that

prevent internal probing and overwriting are hidden

throughout the fabric of the device. They are located

such that they cannot be accessed or bypassed without

destroying the rest of the device, making both invasive

and more-subtle noninvasive attacks ineffective against

Actel antifuse FPGAs.

Selection

2.5V LVCMOS2

5.0V TTL/CMOS

3.3V LVTTL

Nominal

Output Drive

2.5V LVCMOS 2

Output Buffer “Hot-Swap” Capability

•

I/O on an unpowered device does not sink

current

•

Can be used for “cold sparing”

Look for this symbol to ensure your valuable IP is secure.

Selectable on an individual I/O basis

Individually selectable low-slew option

Power-Up

Individually selectable pull ups and pull downs

during power-up (default is to power up in

tristate)

Enables deterministic power-up of device

FuseLock

V_CCAand V_CCIcan be powered in any order

Figure 1-7 • Fuselock

For more information, refer to Actel's Implementation of

Security in Actel Antifuse FPGAs application note.

The eX family supports mixed-voltage operation and is

designed to tolerate 5.0 V inputs in each case.

A detailed description of the I/O pins in eX devices can be

found in "Pin Description" on page 1-26.

I/O Modules

Each I/O on an eX device can be configured as an input,

an output, a tristate output, or a bidirectional pin. Even

without the inclusion of dedicated I/O registers, these I/

Os, in combination with array registers, can achieve

clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells

in eX devices do not contain embedded latches or flip-

flops and can be inferred directly from HDL code. The

device can easily interface with any other device in the

system, which in turn enables parallel design of system

components and reduces overall design time.

v4.3

1-5

eX Family FPGAs

Hot Swapping

Low Power Mode

eX I/Os are configured to be hot-swappable. During

power-up/down (or partial up/down), all I/Os are

tristated, provided V_CCAramps up within a diode drop of

V_CCI. V_CCAand V_CCIdo not have to be stable during

power-up/down, and they do not require a specific

power-up or power-down sequence in order to avoid

damage to the eX devices. In addition, all outputs can be

programmed to have a weak resistor pull-up or pull-

down for output tristate at power-up. After the eX

device is plugged into an electrically active system, the

device will not degrade the reliability of or cause

damage to the host system. The device's output pins are

driven to a high impedance state until normal chip

operating conditions are reached. Please see the

application note, Actel SX-A and RT54SX-S Devices in

Hot-Swap and Cold-Sparing Applications, which also

applies to the eX devices, for more information on hot

swapping.

The eX family has been designed with a Low Power

Mode. This feature, activated with setting the special LP

pin to HIGH for a period longer than 800 ns, is

particularly useful for battery-operated systems where

battery life is a primary concern. In this mode, the core of

the device is turned off and the device consumes minimal

power with low standby current. In addition, all input

buffers are turned off, and all outputs and bidirectional

buffers are tristated when the device enters this mode.

Since the core of the device is turned off, the states of

the registers are lost. The device must be re-initialized

when returning to normal operating mode. I/Os can be

driven during LP mode. For details, refer to the Design

for Low Power in Actel Antifuse FPGAs application note

under the section Using the LP Mode Pin on eX Devices.

Clock pins should be driven either HIGH or LOW and

should not float; otherwise, they will draw current and

burn power. The device must be re-initialized when

exiting LP mode. To exit the LP mode, the LP pin must be

driven LOW for over 200µs to allow for the charge

pumps to power-up and device initialization can begin.

Table 1-3 illustrates the standby current of eX devices in

LP mode.

Power Requirements

Power consumption is extremely low for the eX family

due to the low capacitance of the antifuse interconnects.

The antifuse architecture does not require active circuitry

to hold a charge (as do SRAM or EPROM), making it the

lowest-power FPGA architecture available today.

Table 1-3 • Standby Power of eX Devices in LP Mode

Typical Conditions, V_CCA, V_CCI= 2.5 V, T_J= 25° C

Product

eX64

Low Power Standby Current

Units

µA

100

111

134

eX128

eX256

µA

1-6

v4.3

eX Family FPGAs

Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.

300

250

eX64

200

150

100

eX128

eX256

100

150

200

Frequency (MHz)

Notes:

1. Device filled with 16-bit counters.

2. V_CCA, V_CCI= 2.7 V, device tested at room temperature.

Figure 1-8 • eX Dynamic Power Consumption – High Frequency

eX64

eX128

eX256

Frequency (MHz)

Notes:

1. Device filled with 16-bit counters.

2. V_CCA, V_CCI= 2.7 V, device tested at room temperature.

Figure 1-9 • eX Dynamic Power Consumption – Low Frequency

v4.3

1-7

eX Family FPGAs

180

160

140

120

100

32-bit Decoder

8 x 8-bit Counters

SDRAM Controller

100

125

150

175

200

Frequency (MHz)

Figure 1-10 • Total Dynamic Power (mW)

12,000

10,000

8,000

6,000

4,000

2,000

5% DC

10% DC

15% DC

Frequency (MHz)

Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle

1-8

v4.3

eX Family FPGAs

Boundary Scan Testing (BST)

Flexible Mode

All eX devices are IEEE 1149.1 compliant. eX devices offer

superior diagnostic and testing capabilities by providing

Boundary Scan Testing (BST) and probing capabilities.

These functions are controlled through the special test

pins (TMS, TDI, TCK, TDO and TRST). The functionality of

each pin is defined by two available modes: Dedicated

and Flexible, and is described in Table 1-4. In the

dedicated test mode, TCK, TDI, and TDO are dedicated

pins and cannot be used as regular I/Os. In flexible mode

(default mode), TMS should be set HIGH through a pull-

up resistor of 10 kΩ. TMS can be pulled LOW to initiate

the test sequence.

In Flexible Mode, TDI, TCK and TDO may be used as

either user I/Os or as JTAG input pins. The internal

resistors on the TMS and TDI pins are disabled in flexible

JTAG mode, and an external 10 kΩ pull-resistor to V_CCIis

required on the TMS pin.

To select the Flexible mode, users need to uncheck the

"Reserve JTAG" box in "Device Selection Wizard" in

Actel's Designer software. The functionality of TDI, TCK,

and TDO pins is controlled by the BST TAP controller. The

TAP controller receives two control inputs, TMS and TCK.

Upon power-up, the TAP controller enters the Test-Logic-

Reset state. In this state, TDI, TCK, and TDO function as

user I/Os. The TDI, TCK, and TDO pins are transformed

from user I/Os into BST pins when the TMS pin is LOW at

the first rising edge of TCK. The TDI, TCK, and TDO pins

return to user I/Os when TMS is held HIGH for at least

five TCK cycles.

Table 1-4 • Boundary Scan Pin Functionality

Dedicated Test Mode

Flexible Mode

TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and

BST pins may be used as I/Os

No need for pull-up resistor for Use a pull-up resistor of 10 kΩ

Table 1-5

describes

the

different

configuration

TMS and TDI

on TMS

requirements of BST pins and their functionality in

different modes.

Dedicated Test Mode

Table 1-5 • Boundary-Scan Pin Configurations and

Functions

In Dedicated mode, all JTAG pins are reserved for BST;

designers cannot use them as regular I/Os. An internal

pull-up resistor is automatically enabled on both TMS

and TDI pins, and the TMS pin will function as defined in

the IEEE 1149.1 (JTAG) specification.

Designer

"Reserve JTAG"

Selection

TAP Controller

State

Mode

Dedicated (JTAG)

Flexible (User I/O)

Flexible (JTAG)

Checked

Unchecked

Any

To select Dedicated mode, users need to reserve the JTAG

pins in Actel's Designer software by checking the

"Reserve JTAG" box in "Device Selection Wizard"

(Figure 1-12). JTAG pins comply with LVTTL/TTL I/O

specification regardless of whether they are used as a

user I/O or a JTAG I/O. Refer to the "3.3V LVTTL Electrical

Specifications" and "5.0V TTL Electrical Specifications"

on page 1-15 for detailed specifications.

Test-Logic-Reset

Any EXCEPT Test-

Logic-Reset

TRST Pin

The TRST pin functions as a dedicated Boundary-Scan

Reset pin when the "Reserve JTAG Test Reset" option is

selected as shown in Figure 1-12. An internal pull-up

resistor is permanently enabled on the TRST pin in this

mode. It is recommended to connect this pin to GND in

normal operation to keep the JTAG state controller in

the Test-Logic-Reset state. When JTAG is being used, it

can be left floating or be driven HIGH.

When the "Reserve JTAG Test Reset" option is not

selected, this pin will function as a regular I/O. If unused

as an I/O in the design, it will be configured as a tristated

output.

Figure 1-12 • Device Selection Wizard

v4.3

1-9

eX Family FPGAs

1. Load the .AFM file

JTAG Instructions

Table 1-6 lists the supported instructions with the

corresponding IR codes for eX devices.

2. Select the device to be programmed

3. Begin programming

When the design is ready to go to production, Actel

offers device volume-programming services either

through distribution partners or via in-house

programming from the factory.

Table 1-6 • JTAG Instruction Code

Instructions (IR4: IR0)

EXTEST

Binary Code

00000

For more details on programming eX devices, please

refer to the Programming Antifuse Devices application

note and the Silicon Sculptor II User's Guide.

SAMPLE / PRELOAD

INTEST

00001

00010

USERCODE

IDCODE

00011

Probing Capabilities

00100

eX devices provide internal probing capability that is

accessed with the JTAG pins. The Silicon Explorer II

Diagnostic hardware is used to control the TDI, TCK, TMS

and TDO pins to select the desired nets for debugging.

The user simply assigns the selected internal nets in the

Silicon Explorer II software to the PRA/PRB output pins

for observation. Probing functionality is activated when

the BST pins are in JTAG mode and the TRST pin is driven

HIGH or left floating. If the TRST pin is held LOW, the

TAP controller will remain in the Test-Logic-Reset state so

no probing can be performed. The Silicon Explorer II

automatically places the device into JTAG mode, but the

user must drive the TRST pin HIGH or allow the internal

pull-up resistor to pull TRST HIGH.

HIGHZ

01110

CLAMP

01111

Diagnostic

BYPASS

10000

11111

Reserved

All others

Table 1-7 lists the codes returned after executing the

IDCODE instruction for eX devices. Note that bit 0 is

always "1." Bits 11-1 are always "02F", which is Actel's

manufacturer code.

Table 1-7 • IDCODE for eX Devices

When you select the "Reserve Probe Pin" box as shown

in Figure 1-12 on page 1-9, the layout tool reserves the

PRA and PRB pins as dedicated outputs for probing. This

"reserve" option is merely a guideline. If the Layout tool

requires that the PRA and PRB pins be user I/Os to

achieve successful layout, the tool will use these pins for

user I/Os. If you assign user I/Os to the PRA and PRB pins

and select the "Reserve Probe Pin" option, Designer

Layout will override the "Reserve Probe Pin" option and

place your user I/Os on those pins.

Device

eX64

Revision

Bits 31-28

Bits 27-12

40B2, 42B2

40B0, 42B0

40B5, 42B5

40B2, 42B2

40B0, 42B0

40B5, 42B5

eX128

eX256

eX64

eX128

eX256

To allow for probing capabilities, the security fuse must

not be programmed. Programming the security fuse will

disable the probe circuitry. Table 1-8 on page 1-11

summarizes the possible device configurations for

probing once the device leaves the "Test-Logic-Reset"

JTAG state.

Programming

Device programming is supported through Silicon

Sculptor series of programmers. In particular, Silicon

Sculptor II is a compact, robust, single-site and multi-site

device programmer for the PC.

With standalone software, Silicon Sculptor II allows

concurrent programming of multiple units from the

same PC, ensuring the fastest programming times

possible. Each fuse is subsequently verified by Silicon

Sculptor II to insure correct programming. In addition,

integrity tests ensure that no extra fuses are

programmed. Silicon Sculptor II also provides extensive

hardware self-testing capability.

Silicon Explorer II Probe

Silicon Explorer II is an integrated hardware and

software solution that, in conjunction with Actel’s

Designer software tools, allow users to examine any of

the internal nets of the device while it is operating in a

prototype or a production system. The user can probe

into an eX device via the PRA and PRB pins without

changing the placement and routing of the design and

without using any additional resources. Silicon

The procedure for programming an eX device using

Silicon Sculptor II is as follows:

1-10

v4.3

eX Family FPGAs

Explorer II's noninvasive method does not alter timing or

loading effects, thus shortening the debug cycle.

interconnection between Silicon Explorer II and the eX

device to perform in-circuit verification.

Silicon Explorer II does not require re-layout or

additional MUXes to bring signals out to an external pin,

which is necessary when using programmable logic Design Considerations

devices from other suppliers.

The TDI, TCK, TDO, PRA, and PRB pins should not be used

Silicon Explorer II samples data at 100 MHz

(asynchronous) or 66 MHz (synchronous). Silicon Explorer

II attaches to a PC's standard COM port, turning the PC

into a fully functional 18-channel logic analyzer. Silicon

Explorer II allows designers to complete the design

verification process at their desks and reduces

verification time from several hours per cycle to a few

seconds.

as input or bidirectional ports. Since these pins are active

during probing, critical signals input through these pins

are not available while probing. In addition, the Security

Fuse should not be programmed because doing so

disables the probe circuitry. It is recommended to use a

series 70Ω termination resistor on every probe connector

(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series

termination is used to prevent data transmission

corruption during probing and reading back the

checksum.

The Silicon Explorer II tool uses the boundary scan ports

(TDI, TCK, TMS and TDO) to select the desired nets for

verification. The selected internal nets are assigned to the

PRA/PRB pins for observation. Figure 1-13 illustrates the

Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved)

JTAG Mode

Dedicated

Flexible

TRST¹

LOW

HIGH

–

Security Fuse Programmed

PRA, PRB²

User I/O³

TDI, TCK, TDO²

Probing Unavailable

User I/O³

Yes

User I/O³

Dedicated

Flexible

Probe Circuit Outputs

Probe Circuit Secured

Probe Circuit Inputs

Probe Circuit Secured

–

Notes:

1. If TRST pin is not reserved, the device behaves according to TRST = HIGH in the table.

2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input

signals will not pass through these pins and may cause contention.

3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by

Actel’s Designer software.

16 Pin

Connection

eX FPGAs

TDI

TCK

TMS

TDO

Serial

Silicon Explorer II

Connection

PRA

PRB

22 Pin

Connection

Additional 16 Channels

(Logic Analyzer)

Figure 1-13 • Silicon Explorer II Probe Setup

v4.3

1-11

eX Family FPGAs

Development Tool Support

The eX family of FPGAs is fully supported by both Actel's

Libero™ Integrated Design Environment and Designer

FPGA Development software. Actel Libero IDE is a design

management environment that streamlines the design

flow. Libero IDE provides an integrated design manager

that seamlessly integrates design tools while guiding the

user through the design flow, managing all design and

log files, and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment. Libero IDE

includes Synplify® for Actel from Synplicity®, ViewDraw

for Actel from Mentor Graphics, ModelSim™ HDL

Simulator from Mentor Graphics®, WaveFormer Lite™

from SynaptiCAD™, and Designer software from Actel.

Refer to the Libero IDE flow (located on Actel’s website)

diagram for more information.

Related Documents

Datasheet

eX Automotive Family FPGAs

http://www.actel.com/documents/eXAuto_DS.pdf

Application Notes

Maximizing Logic Utilization in eX, SX and SX-A FPGA

Devices Using CC Macros

http://www.actel.com/documents/CC_Macro_AN.pdf

Actel's Implementation of Security in Actel Antifuse FPGAs

http://www.actel.com/documents/

Antifuse_Security_AN.pdf

Actel eX, SX-A, and RT54SX-S I/Os

http://www.actel.com/documents/antifuseIO_AN.pdf

Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-

Sparing Applications

http://www.actel.com/documents/

HotSwapColdSparing_AN.pdf

Design For Low Power in Actel Antifuse FPGAs

http://www.actel.com/documents/Low_Power_AN.pdf

Programming Antifuse Devices

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

timing-driven place-and-route, and

world-class

integrated static timing analyzer and constraints editor.

With the Designer software, a user can lock his/her

design pins before layout while minimally impacting the

results of place-and-route. Additionally, the back-

annotation flow is compatible with all the major

simulators and the simulation results can be cross-probed

with Silicon Explorer II, Actel’s integrated verification

and logic analysis tool. Another tool included in the

Designer software is the SmartGen core generator, which

easily creates popular and commonly used logic

functions for implementation into your schematic or HDL

design. Actel's Designer software is compatible with the

most popular FPGA design entry and verification tools

from companies such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

http://www.actel.com/documents/

AntifuseProgram_AN.pdf

User Guides

Silicon Sculptor II User's Guide

http://www.actel.com/techdocs/manuals/

default.asp#programmers

Miscellaneous

Libero IDE flow

http://www.actel.com/products/tools/libero/flow.html

1-12

v4.3

eX Family FPGAs

2.5 V / 3.3 V /5.0 V Operating Conditions

Table 1-9 • Absolute Maximum Ratings*

Symbol

V_CCI

V_CCA

V_I

Parameter

Limits

Units

DC Supply Voltage for I/Os

DC Supply Voltage for Array

Input Voltage

–0.3 to +6.0

–0.3 to +3.0

–0.5 to +5.75

–0.5 to +V_CCI

–65 to +150

V_O

Output Voltage

T_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

Recommended Operating Conditions.

Table 1-10 • Recommended Operating Conditions

Parameter

Commercial

0 to +70

Industrial

–40 to +85

2.3 to 2.7

Units

°C

Temperature Range*

2.5V Power Supply

2.3 to 2.7

Range (V_CCA, V_CCI

)

3.3V Power Supply

3.0 to 3.6

Range (V_CCI

)

5.0V Power Supply

4.75 to 5.25

Range (V_CCI

)

Note: *Ambient temperature (T_A).

Table 1-11 • Typical eX Standby Current at 25°C

_CCA= 2.5 V

V_CCA= 2.5 V

Product

eX64

V_CCI= 2.5 V

V_CCI= 3.3 V

V_CCI= 5.0 V

397 µA

696 µA

698 µA

49 7µA

795 µA

796 µA

700 µA

eX128

eX256

1,000 µA

2,000 µA

v4.3

1-13

eX Family FPGAs

2.5 V LVCMOS2 Electrical Specifications

Commercial

Industrial

Symbol Parameter

Min.

(I_OH= -100 µA) 2.1

Max.

Min.

Max.

Units

V_OH

V_CCI= MIN, V_I= V_IHor V_IL

_CCI= MIN, V_I= V_IHor V_IL

2.1

2.0

1.7

(I_OH= -1 mA)

(I_OH= -2 mA)

(I_OL= 100 µA)

(I_OL= 1mA)

2.0

1.7

V_CCI= MIN, V_I= V_IHor V_IL

V_OL

0.2

0.4

0.7

0.2

0.4

0.7

_CCI= MIN, V_I= V_IHor V_IL

V_CCI= MIN,V_I= V_IHor V_IL

(I_OL= 2 mA)

V_IL

Input Low Voltage, V_OUT≤ V_OL(max)

Input High Voltage, V_OUT≥ V_OH(min)

–0.3

-0.3

V_IH

1.7 V_CCI+ 0.3 1.7

V_CCI

0.3

I_IL/ I_IH

I_OZ

Input Leakage Current, V_IN= V_CCIor GND

3-State Output Leakage Current, V_OUT= V_CCIor GND

Input Transition Time

–10

1.0

–10

3.0

µA

1,2

t_R, t_F

C_IO

I/O Capacitance

3,4

I_CC

Standby Current

IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.

Notes:

1. t_Ris the transition time from 0.7 V to 1.7 V.

2. t_Fis the transition time from 1.7 V to 0.7 V.

3. I_CCmax Commercial –F = 5.0 mA

4. I_CC= I_CCI+ I_CCA

1-14

v4.3

eX Family FPGAs

3.3 V LVTTL Electrical Specifications

Commercial

Industrial

Symbol Parameter

Min.

Max.

Min.

Max.

Units

V_OH

V_OL

V_IL

V_CCI= MIN, V_I= V_IHor V_IL

Input Low Voltage

(I_OH= –8 mA)

(I_OL= 12 mA)

2.4

0.4

0.8

0.4

0.8

V_IH

Input High Voltage

2.0

–10

V_CCI+0.5

2.0

–10

V_CCI+0.5

I_IL/ I_IH

I_OZ

Input Leakage Current, V_IN= V_CCIor GND

3-State Output Leakage Current, V_OUT= V_CCIor GND

Input Transition Time

µA

1,2

t_R, t_F

C_IO

I/O Capacitance

3,4

I_CC

Standby Current

1.5

IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.

Notes:

1. t_Ris the transition time from 0.8 V to 2.0 V.

2. t_Fis the transition time from 2.0 V to 0.8 V.

3. I_CCmax Commercial –F = 5.0 mA

4. I_CC= I_CCI+ I_CCA

5. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.

5.0VTTLElectricalSpecifications

Commercial

Industrial

Symbol Parameter

Min.

Max.

Min.

Max. Units

V_OH

V_OL

V_IL

V_CCI= MIN, V_I= V_IHor V_IL

(I_OH= –8 mA)

(I_OL= 12 mA)

2.4

V_CCI= MIN, V_I= V_IHor V_IL

Input Low Voltage

0.4

0.8

0.4

0.8

V_IH

Input High Voltage

2.0

–10

V_CCI+0.5

2.0

–10

V_CCI+0.5

I_IL/ I_IH

Input Leakage Current, V_IN= V_CCIor GND

3-State Output Leakage Current, V_OUT= V_CCIor GND

Input Transition Time

µA

I_OZ

1,2

t_R, t_F

C_IO

I/O Capacitance

3,4

I_CC

Standby Current

IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.

Note:

1. t_Ris the transition time from 0.8 V to 2.0 V.

2. t_Fis the transition time from 2.0 V to 0.8 V.

3. I_CCmax Commercial –F=20mA

4. I_CC= I_CCI+ I_CCA

5. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.

v4.3

1-15

eX Family FPGAs

CEQ Values for eX Devices

Combinatorial modules (Ceqcm) 1.70 pF

Power Dissipation

Power consumption for eX devices can be divided into

two components: static and dynamic.

Sequential modules (Ceqsm)

Input buffers (Ceqi)

Output buffers (Ceqo)

Routed array clocks (Ceqcr)

1.70 pF

1.30 pF

7.40 pF

1.05 pF

Static Power Component

The power due to standby current is typically a small

component of the overall power. Typical standby current

for eX devices is listed in the Table 1-11 on page 1-13. For

example, the typical static power for eX128 at 3.3 V V_CCI

is:

The variable and fixed capacitance of other device

components must also be taken into account when

estimating the dynamic power dissipation.

Table 1-12 shows the capacitance of the clock

components of eX devices.

_CC* V_CCA= 795 µA x 2.5 V = 1.99 mW

Table 1-12 • Capacitance of Clock Components of eX

Devices

Dynamic Power Component

eX64

eX128

eX256

Power dissipation in CMOS devices is usually dominated

by the dynamic power dissipation. This component is

frequency-dependent and a function of the logic and the

external I/O. Dynamic power dissipation results from

charging internal chip capacitance due to PC board

traces and load device inputs. An additional component

of the dynamic power dissipation is the totem pole

current in the CMOS transistor pairs. The net effect can

be associated with an equivalent capacitance that can be

combined with frequency and voltage to represent

dynamic power dissipation.

Dedicated array clock

variable (Ceqhv)

–

0.85 pF

Dedicated array clock – fixed 18.00 pF 20.00 pF 25.00 pF

(Ceqhf)

Routed array clock A (r1)

Routed array clock B (r2)

23.00 pF 28.00 pF 35.00 pF

The estimation of the dynamic power dissipation is a

piece-wise linear summation of the power dissipation of

each component.

Dynamic power dissipation = CEQ * V_CCA²x F

where:

Dynamic power dissipation

= V_CCA²* [(m_c* C_eqcm* fm_C)_{Comb Modules}+ (m_s* C_eqsm

CEQ = Equivalent capacitance

fm_S)_{Seq Modules}+ (n * C_eqi* fn)_{Input Buffers}+ (0.5 * (q1 *

C_eqcr* fq1) + (r1 * fq1))_RCLKA+ (0.5 * (q2 * C_eqcr* fq2) +

= switching frequency

Equivalent capacitance is calculated by measuring I_CCAat

a specified frequency and voltage for each circuit

component of interest. Measurements have been made

(r2 * fq2))_RCLKB+ (0.5 * (s1 * C_eqhv* fs1)+(C_eqhf

fs1))_HCLK] + V_CCI²* [(p * (C_eqo+ C_L) * fp)_{Output Buffers}

where:

]

over a range of frequencies at a fixed value of V_CC

m_c

m_s

= Number of combinatorial cells switching at

Equivalent capacitance is frequency-independent, so the

results can be used over a wide range of operating

conditions. Equivalent capacitance values are shown

below.

frequency fm, typically 20% of C-cells

= Number of sequential cells switching at

frequency fm, typically 20% of R-cells

= Number of input buffers switching at

frequency fn, typically number of inputs / 4

= Number of output buffers switching at

frequency fp, typically number of outputs / 4

= Number of R-cells driven by routed array

clock A

Number of R-cells driven by routed array

clock B

= Fixed capacitance due to routed array clock A

= Fixed capacitance due to routed array clock B

= Number of R-cells driven by dedicated array

clock

C_eqcm

Equivalent capacitance of combinatorial

modules

1-16

v4.3

eX Family FPGAs

C_eqsm

Equivalent capacitance of sequential

modules

Thermal Characteristics

The temperature variable in the Designer software refers

to the junction temperature, not the ambient

temperature. This is an important distinction because the

heat generated from dynamic power consumption is

usually hotter than the ambient temperature. EQ 1-1,

shown below, can be used to calculate junction

temperature.

C_eqi= Equivalent capacitance of input buffers

C_eqcr= Equivalent capacitance of routed array clocks

C_eqhv= Variable capacitance of dedicated array clock

C_eqhf= Fixed capacitance of dedicated array clock

C_eqo= Equivalent capacitance of output buffers

C_L

Average output loading capacitance,

typically 10 pF

fm_c

= Average C-cell switching frequency, typically

F/10

EQ 1-1

Junction Temperature = ∆T + T_a(1)

Where:

fm_s= Average R-cell switching frequency, typically

F/10

= Average input buffer switching frequency,

typically F/5

= Average output buffer switching frequency,

typically F/5

T_a= Ambient Temperature

∆T = Temperature gradient between junction

(silicon) and ambient = θ_ja* P

fq1

fq2

fs1

= Frequency of routed clock A

= Frequency of routed clock B

= Frequency of dedicated array clock

P = Power

= Junction to ambient of package. θ numbers are

located in the "Package Thermal Characteristics" section

below.

The eX, SX-A and RTSX-S Power Calculator can be used to

estimate the total power dissipation (static and dynamic)

of eX devices and can be found at

http://www.actel.com/products/rescenter/power/

calculators.asp.

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θ_jc,

and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two

different air flow rates. θ_jcis provided for reference.

The maximum junction temperature is 150°C.

The maximum power dissipation allowed for eX devices

is a function of θ_ja. A sample calculation of the absolute

maximum power dissipation allowed for a TQFP 100-pin

package at commercial temperature and still air is as

follows:

Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C

--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------

Maximum Power Allowed =

= 2.39W

θ_ja(°C/W)

33.5°C/W

θ_ja

1.0 m/s

2.5 m/s

Package Type

Pin Count

θ_jc

Still Air

42.4

200 ft/min

500 ft/min

Units

°C/W

Thin Quad Flat Pack (TQFP)

Chip Scale Package (CSP)

100

12.0

14.0

36.3

27.4

59.5

44.6

47.6

34.0

25.0

54.1

40.6

43.3

33.5

72.2

128

180

54.1

57.8

v4.3

1-17

eX Family FPGAs

eX Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

Combinatorial

Cell

= 0.3 ns

= 0.4 ns

I/O Module

IRD1

IRD2

= 0.7 ns

INYH

= 2.6 ns

DHL

= 0.7 ns

= 0.3 ns

RD1

= 0.7 ns

RD4

= 1.2 ns

RD8

I/O Module

Cell

= 1.9 ns

ENZL

RD1

= 0.5 ns

= 0.3 ns

SUD

= 0.0 ns

= 2.6 ns

DHL

Routed

Clock

= 1.3 ns

RCKH

= 0.6 ns

(100% Load)

RCO

I/O Module

Cell

I/O Module

= 1.3 ns

= 1.9 ns

INYH

ENZL

= 0.3 ns

= 0.5 ns

IRD1

RD1

= 0.3 ns

SUD

= 0.0 ns

= 2.6 ns

DHL

Hard-Wired

Clock

RCO

= 1.1 ns

= 0.6 ns

HCKH

Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).

Figure 1-14 • eX Timing Model

Hardwired Clock

Routed Clock

External Setup = t_INYH+ t_IRD1+ t_SUD– t_HCKH

External Setup = t_INYH+ t_IRD2+ t_SUD– t_RCKH

0.7 + 0.4 + 0.5 – 1.3= 0.3 ns

Clock-to-Out (Pad-to-Pad), typical

0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns

Clock-to-Out (Pad-to-Pad), typical

_HCKH+ t_RCO+ t_RD1+ t_DHL

_RCKH+ t_RCO+ t_RD1+ t_DHL

1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns

1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns

1-18

v4.3

eX Family FPGAs

Output Buffer Delays

PAD To AC test loads (shownbelow)

V_CC

TRIBUFF

V_CC

50% 50%

V_CC

50%

GND

1.5 V

50% 50%

V_OH

GND

90%

Out

V_OH

1.5 V

10%

Out

V_OL

1.5 V

Out

GND

V_OL

ENHZ

DHL

DLH

ENZL

ENZH

ENLZ

Table 1-13 • Output Buffer Delays

AC Test Loads

Load 3

(Used to measure disable delays)

Load 1

(used to measure

propagation delay)

Load 2

(Used to measure enable delays)

GND

V_CC

To the output

under test

R to V_CCfor PLZ

R to V_CCfor PZL

35 pF

To the output

under test

To the output

under test

R to GND for PHZ

R = 1 kΩ

35pF

5pF

Figure 1-15 • AC Test Loads

v4.3

1-19

eX Family FPGAs

Input Buffer Delays

C-Cell Delays

PAD

INBUF

V_CC

50%

S, A or B

GND

V_CC

50%

Out

GND

1.5 V 1.5 V

50%

Out

V_CC

Out

50%

GND

50%

GND

t_INY

Table 1-14 • Input Buffer Delays

Table 1-15 • C-Cell Delays

Cell Timing Characteristics

PRESET

CLR

CLK

(Positive edge triggered)

t_HD

t_HP

t_SUD

t_HPWH

t_RPWH

CLK

t_HPWL

t_RPWL

t_RCO

t_PRESET

t_CLR

t_WASYN

CLR

PRESET

Figure 1-16 • Flip-Flops

1-20

v4.3

eX Family FPGAs

Long Tracks

Timing Characteristics

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three to five

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, no more than six

percent of nets in a fully utilized device require long

tracks. Long tracks contribute approximately 4 ns to

8.4 ns delay. This additional delay is represented

statistically in higher fanout routing delays.

Timing characteristics for eX devices fall into three

categories: family-dependent, device-dependent, and

design-dependent. The input and output buffer

characteristics are common to all eX family members.

Internal routing delays are device-dependent. Design

dependency means actual delays are not determined

until after placement and routing of the user’s design are

complete. Delay values may then be determined by using

the Timer utility or performing simulation with post-

layout delays.

Timing Derating

Critical Nets and Typical Nets

eX devices are manufactured with a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case

processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating

temperature, and worst-case processing.

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most timing

critical paths. Critical nets are determined by net

property assignment prior to placement and routing. Up

to six percent of the nets in a design may be designated

as critical.

Temperature and Voltage Derating Factors

Table 1-16 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_CCA= 2.3V)

Junction Temperature (T_J)

25 70

V_CCA

2.3

–55

0.79

0.74

0.69

–40

0.80

0.74

0.70

125

1.13

1.06

1.00

0.87

0.81

0.76

0.88

0.83

0.78

1.00

0.93

0.88

1.04

0.97

0.91

2.5

2.7

v4.3

1-21

eX Family FPGAs

eX Family Timing Characteristics

Table 1-17 • eX Family Timing Characteristics

(Worst-Case Commercial Conditions, V_CCA= 2.3 V T_J= 70°C)

‘–P’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.7

1.0

1.4

Predicted Routing Delays²

t_DC

FO=1 Routing Delay, DirectConnect

0.1

0.3

0.4

0.5

0.7

1.2

1.7

0.1

0.5

0.6

0.8

1.0

1.7

2.5

0.2

0.7

0.8

1.1

1.3

2.4

3.5

t_FC

FO=1 Routing Delay, FastConnect

FO=1 Routing Delay

t_RD1

t_RD2

FO=2 Routing Delay

t_RD3

FO=3 Routing Delay

t_RD4

FO=4 Routing Delay

t_RD8

FO=8 Routing Delay

t_RD12

R-Cell Timing

t_RCO

FO=12 Routing Delay

Sequential Clock-to-Q

0.6

0.7

0.9

0.8

0.9

1.3

1.2

1.3

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Hold Time

t_PRESET

t_SUD

0.5

0.0

1.3

0.3

0.7

0.0

1.9

0.5

1.0

0.0

2.6

0.7

t_HD

t_WASYN

t_RECASYN

t_HASYN

2.5 V Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.6

0.8

0.9

1.1

1.3

1.5

3.3 V Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.7

0.9

1.0

1.3

1.4

1.8

5.0 V Input Module Propagation Delays

t_INYH

t_INYL

Input Data Pad-to-Y HIGH

Input Data Pad-to-Y LOW

0.7

0.9

1.0

1.3

1.4

1.8

Input Module Predicted Routing Delays²

t_IRD1

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.4

0.6

0.8

1.0

1.7

2.5

0.5

0.8

1.1

1.3

2.4

3.5

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.

1-22

v4.3

eX Family FPGAs

Table 1-18 • eX Family Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.3 V, V_CCI= 4.75 V, T_J= 70°C)

‘–P’ Speed ‘Std’ Speed

Min. Max.

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max. Units

Dedicated (Hard-Wired) Array Clock Networks

t_HCKH

t_HCKL

Input LOW to HIGH

(Pad to R-Cell Input)

1.1

1.6

2.3

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

2.0

2.8

<0.1

357

<0.1

250

<0.1

178

Minimum Period

2.8

4.0

5.6

f_HMAX

Maximum Frequency

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input) MAX.

1.1

1.0

1.2

1.3

1.6

1.4

1.7

1.9

2.2

2.0

2.4

2.6

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input) MAX.

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input) MAX.

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input) MAX.

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input) MAX.

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input) MAX.

t_RPWH

Min. Pulse Width HIGH

1.5

2.1

3.0

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.2

0.1

0.3

0.2

0.1

0.4

0.3

0.2

Note: *Clock skew improves as the clock network becomes more heavily loaded.

v4.3

1-23

eX Family FPGAs

Table 1-19 • eX Family Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.3V, V_CCI= 2.3 V or 3.0V, T_J= 70°C)

‘–P’ Speed ‘Std’ Speed

Min. Max.

‘–F’ Speed

Min. Max. Units

Parameter

Description

Min.

Max.

Dedicated (Hard-Wired) Array Clock Networks

t_HCKH

t_HCKL

Input LOW to HIGH

(Pad to R-Cell Input)

1.1

1.6

2.3

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

1.4

2.0

2.8

<0.1

357

<0.1

250

<0.1

178

Minimum Period

2.8

4.0

5.6

f_HMAX

Maximum Frequency

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input) MAX.

1.0

1.2

1.4

1.7

2.0

2.4

2.8

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input) MAX.

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input) MAX.

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input) MAX.

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input) MAX.

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input) MAX.

t_RPWH

Min. Pulse Width HIGH

1.4

2.0

2.8

t_RPWL

Min. Pulse Width LOW

t_RCKSW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

0.2

0.1

0.3

0.2

0.1

0.4

0.3

0.2

Note: *Clock skew improves as the clock network becomes more heavily loaded.

1-24

v4.3

eX Family FPGAs

Table 1-20 • eX Family Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.3 V, T_J= 70°C)

‘–P’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

2.5 V LVCMOS Output Module Timing¹(V_CCI= 2.3 V)

t_DLH

Data-to-Pad LOW to HIGH

3.3

3.5

4.7

5.0

6.6

7.0

t_DHL

Data-to-Pad HIGH to LOW

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

Data-to-Pad HIGH to LOW—Low Slew

Enable-to-Pad, Z to L

11.6

2.5

16.6

3.6

23.2

5.1

Enable-to-Pad Z to L—Low Slew

Enable-to-Pad, Z to H

11.8

3.4

16.9

4.9

23.7

6.9

Enable-to-Pad, L to Z

2.1

3.0

4.2

Enable-to-Pad, H to Z

2.4

5.67

0.046

0.022

0.072

7.94

0.066

0.05

0.1

Delta Delay vs. Load LOW to HIGH

Delta Delay vs. Load HIGH to LOW

Delta Delay vs. Load HIGH to LOW—Low Slew

0.034

0.016

0.05

ns/pF

d_THL

d_THLS

3.3 V LVTTL Output Module Timing¹(V_CCI= 3.0 V)

t_DLH

Data-to-Pad LOW to HIGH

2.8

2.7

4.0

3.9

5.6

5.4

t_DHL

Data-to-Pad HIGH to LOW

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

Data-to-Pad HIGH to LOW—Low Slew

Enable-to-Pad, Z to L

9.7

13.9

3.2

19.5

4.4

2.2

Enable-to-Pad Z to L—Low Slew

Enable-to-Pad, Z to H

9.7

13.9

4.0

19.6

5.6

2.8

Enable-to-Pad, L to Z

2.8

4.0

5.6

Enable-to-Pad, H to Z

2.6

3.8

5.3

Delta Delay vs. Load LOW to HIGH

Delta Delay vs. Load HIGH to LOW

Delta Delay vs. Load HIGH to LOW—Low Slew

0.02

0.016

0.05

0.03

0.022

0.072

0.046

0.05

0.1

ns/pF

d_THL

d_THLS

5.0 V TTL Output Module Timing^*(V_CCI= 4.75 V)

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Data-to-Pad HIGH to LOW—Low Slew

Enable-to-Pad, Z to L

2.0

2.6

6.8

1.9

6.8

2.1

3.3

2.9

3.7

9.7

2.7

9.8

3.0

4.8

4.0

5.2

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

13.6

3.8

Enable-to-Pad Z to L—Low Slew

Enable-to-Pad, Z to H

13.7

4.1

Enable-to-Pad, L to Z

6.6

Note: *Delays based on 35 pF loading.

v4.3

1-25

eX Family FPGAs

Pin Description

CLKA/B

Routed Clock A and B

TCK, I/O

Test Clock

These pins are clock inputs for clock distribution

networks. Input levels are compatible with standard TTL

or LVTTL specifications. The clock input is buffered prior

to clocking the R-cells. If not used, this pin must be set

LOW or HIGH on the board. It must not be left floating.

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active

when the TMS pin is set LOW (refer to Table 1-4 on

page 1-9). This pin functions as an I/O when the

boundary scan state machine reaches the “logic reset”

state.

GND

Ground

TDI, I/O

Test Data Input

LOW supply voltage.

Serial input for boundary scan testing and diagnostic

probe. In flexible mode, TDI is active when the TMS pin is

set LOW (refer to Table 1-4 on page 1-9). This pin

functions as an I/O when the boundary scan state

machine reaches the “logic reset” state.

HCLK

Dedicated (Hardwired)

Array Clock

This pin is the clock input for sequential modules. Input

levels are compatible with standard TTL or LVTTL

specifications. This input is directly wired to each R-cell

and offers clock speeds independent of the number of R-

cells being driven. If not used, this pin must be set LOW

or HIGH on the board. It must not be left floating.

TDO, I/O

Test Data Output

Serial output for boundary scan testing. In flexible mode,

TDO is active when the TMS pin is set LOW (refer to

Table 1-4 on page 1-9). This pin functions as an I/O when

the boundary scan state machine reaches the "logic

reset" state. When Silicon Explorer is being used, TDO

will act as an output when the "checksum" command is

run. It will return to user I/O when "checksum" is

complete.

I/O

Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Based on certain configurations,

input and output levels are compatible with standard

TTL or LVTTL specifications. Unused I/O pins are

automatically tristated by the Designer software.

TMS

Test Mode Select

Low Power Pin

The TMS pin controls the use of the IEEE 1149.1

Boundary scan pins (TCK, TDI, TDO, TRST). In flexible

mode when the TMS pin is set LOW, the TCK, TDI, and

TDO pins are boundary scan pins (refer to Table 1-4 on

page 1-9). Once the boundary scan pins are in test mode,

they will remain in that mode until the internal

boundary scan state machine reaches the “logic reset”

state. At this point, the boundary scan pins will be

released and will function as regular I/O pins. The “logic

reset” state is reached five TCK cycles after the TMS pin is

set HIGH. In dedicated test mode, TMS functions as

specified in the IEEE 1149.1 specifications.

Controls the low power mode of the eX devices. The

device is placed in the low power mode by connecting

the LP pin to logic HIGH. In low power mode, all I/Os are

tristated, all input buffers are turned OFF, and the core

of the device is turned OFF. To exit the low power mode,

the LP pin must be set LOW. The device enters the low

power mode 800 ns after the LP pin is driven to a logic

HIGH. It will resume normal operation 200 µs after the LP

pin is driven to a logic LOW. LP pin should not be left

floating. Under normal operating condition it should be

tied to GND via 10 kΩ resistor.

No Connection

TRST, I/O

Boundary Scan Reset Pin

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

Once it is configured as the JTAG Reset pin, the TRST pin

functions as an active-low input to asynchronously

initialize or reset the boundary scan circuit. The TRST pin

is equipped with an internal pull-up resistor. This pin

functions as an I/O when the “Reserve JTAG Reset Pin” is

not selected in the Designer software.

PRA/PRB, I/O

Probe A/B

The Probe pin is used to output data from any user-

defined design node within the device. This diagnostic

pin can be used independently or in conjunction with the

other probe pin to allow real-time diagnostic output of

any signal path within the device. The Probe pin can be

used as a user-defined I/O when verification has been

completed. The pin’s probe capabilities can be

permanently disabled to protect programmed design

confidentiality.

Supply Voltage

CCI

Supply voltage for I/Os.

Supply Voltage

CCA

Supply voltage for Array.

1-26

v4.3

eX Family FPGAs

Package Pin Assignments

64-Pin TQFP

64-Pin

TQFP

Figure 2-1 • 64-Pin TQFP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v4.3

2-1

eX Family FPGAs

64-Pin TQFP

eX64

eX128

eX64

eX128

Pin Number

Function

Pin Number

Function

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

45*

GND

I/O

GND

I/O

TMS

GND

V_CCI

I/O

TMS

GND

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

TRST, I/O

I/O

TRST, I/O

I/O

V_CCA

GND/LP

GND

I/O

V_CCA

GND/ LP

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

PRB, I/O

V_CCA

GND

I/O

PRB, I/O

V_CCA

GND

I/O

CLKA

CLKB

V_CCA

GND

PRA, I/O

I/O

CLKA

CLKB

V_CCA

GND

PRA, I/O

I/O

HCLK

I/O

HCLK

I/O

V_CCI

I/O

V_CCI

I/O

TDO, I/O

TCK, I/O

Note: *Please read the LP pin descriptions for restrictions on their use.

2-2

v4.3

eX Family FPGAs

100-Pin TQFP

100

100-Pin

TQFP

Figure 2-2 • 100-Pin TQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v4.3

2-3

eX Family FPGAs

100-Pin TQFP

eX64

eX128

eX256

eX64

eX128

eX256

Pin Number

Function

GND

TDI, I/O

Function

Pin Number

Function

GND

Function

GND

TDI, I/O

GND

TDI, I/O

I/O

GND

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

TMS

V_CCI

GND

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCA

V_CCI

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

GND/LP

GND

I/O

V_CCA

GND/LP

GND

I/O

V_CCA

GND/LP

GND

I/O

PRB, I/O

V_CCA

PRB, I/O

V_CCA

PRB, I/O

V_CCA

Note: *Please read the LP pin descriptions for restrictions on their use.

2-4

v4.3

eX Family FPGAs

100-Pin TQFP

eX64

eX128

eX256

Pin Number

Function

100

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

CLKA

CLKB

CLKA

CLKB

CLKA

CLKB

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

TCK, I/O

Note: *Please read the LP pin descriptions for restrictions on their use.

v4.3

2-5

eX Family FPGAs

49-Pin CSP

A1 Ball Pad Corner

Figure 2-3 • 49-Pin CSP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

2-6

v4.3

eX Family FPGAs

49-Pin CSP

eX64

eX128

eX64

eX128

Pin Number

Function

Pin Number

Function

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

TRST, I/O

V_CCI

GND

I/O

TRST, I/O

V_CCI

GND

I/O

TCK, I/O

I/O

TCK, I/O

I/O

V_CCI

I/O

V_CCI

I/O

PRA, I/O

CLKA

I/O

PRA, I/O

CLKA

I/O

B7*

GND/LP*

I/O

GND/LP*

I/O

HCLK

I/O

HCLK

I/O

TDI, I/O

V_CCI

GND

CLKB

V_CCA

I/O

TDI, I/O

V_CCI

GND

CLKB

V_CCA

I/O

TDO, I/O

I/O

TDO, I/O

I/O

PRB, I/O

V_CCA

I/O

PRB, I/O

V_CCA

I/O

TMS

GND

TMS

GND

I/O

Note: *Please read the LP pin descriptions for restrictions on their use.

v4.3

2-7

eX Family FPGAs

128-Pin CSP

A1 Ball Pad Corner

Figure 2-4 • 128-Pin CSP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

2-8

v4.3

eX Family FPGAs

128-Pin CSP

eX64

eX128

eX256

eX64

eX128

eX256

Pin Number

Function

Pin Number

C12

Function

I/O

TCK, I/O

V_CCI

I/O

TCK, I/O

V_CCI

I/O

TCK, I/O

V_CCI

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

A10

A11

A12

I/O

D10

D11

D12

I/O

TMS

I/O

TMS

I/O

TMS

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

PRA, I/O

CLKB

I/O

PRA, I/O

CLKB

I/O

PRA, I/O

CLKB

I/O

E10

E11*

E12

GND/LP*

V_CCA

GND/LP*

V_CCA

I/O

GND/LP*

V_CCA

I/O

B10

B11

B12

I/O

GND

I/O

GND

I/O

GND

I/O

TDI, I/O

I/O

TDI, I/O

I/O

TDI, I/O

I/O

GND

I/O

GND

I/O

F10

F11

F12

I/O

CLKA

I/O

CLKA

I/O

CLKA

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

GND

I/O

GND

I/O

C10

C11

I/O

G10

Note: *Please read the LP pin descriptions for restrictions on their use.

v4.3

2-9

eX Family FPGAs

128-Pin CSP

eX64

eX128

eX256

eX64

eX128

eX256

Pin Number

Function

Pin Number

Function

G11

G12

H10

H11

H12

I/O

GND

I/O

GND

I/O

GND

I/O

K10

K11

K12

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

V_CCI

V_CCA

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

V_CCA

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

L10

L11

L12

M10

M11

M12

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

GND

I/O

GND

I/O

GND

I/O

J10

J11

J12

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

PRB, I/O

HCLK

PRB, I/O

HCLK

PRB, I/O

HCLK

I/O

Note: *Please read the LP pin descriptions for restrictions on their use.

2-10

v4.3

eX Family FPGAs

180-Pin CSP

A1 Ball Pad Corner

9 10

Figure 2-5 • 180-Pin CSP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v4.3

2-11

eX Family FPGAs

180-Pin CSP

eX256

Number

Function

Number

Function

Number

Function

Number

J10

J11

J12

J13

J14

Function

I/O

CLKB

I/O

V_CCI

V_CCA

I/O

GND

C10

C11

C12

C13

C14

I/O

V_CCI

I/O

A10

A11

A12

A13

A14

I/O

GND

I/O

GND

I/O

F10

F11

F12*

F13

F14

I/O

V_CCA

I/O

GND/LP*

V_CCA

I/O

V_CCI

I/O

TDI, I/O

I/O

V_CCA

I/O

GND

I/O

CLKA

I/O

K10

K11

K12

K13

K14

GND

I/O

G10

G11

G12

G13

G14

GND

I/O

TCK, I/O

V_CCI

I/O

D10

D11

D12

D13

D14

I/O

V_CCA

I/O

V_CCA

I/O

TRST, I/O

I/O

B10

B11

B12

B13

B14

V_CCI

I/O

GND

I/O

H10

H11

H12

H13

H14

PRB, I/O

HCLK

I/O

GND

I/O

L10

L11

L12

L13

L14

I/O

TMS

I/O

GND

I/O

E10

E11

E12

E13

E14

I/O

TDO, I/O

I/O

GND

I/O

V_CCI

I/O

V_CCI

GND

I/O

PRA, I/O

I/O

Note: *Please read the LP pin descriptions for restrictions on their use.

2-12

v4.3

eX Family FPGAs

180-Pin CSP

eX256

Number

M10

M11

M12

M13

M14

Function

Number

Function

I/O

V_CCI

I/O

GND

I/O

V_CCA

I/O

P10

P11

P12

GND

I/O

P13

N10

N11

N12

N13

N14

Note: *Please read the LP pin descriptions for restrictions on their use.

v4.3

2-13

eX Family FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous version Changes in current version (v4.3)

Page

v4.2

The "Ordering Information" was updated with RoHS information. The TQFP measurement ii

was also updated.

(June 2004)

The "Dedicated Test Mode" was updated.

1-9

Note 5 was added to the "3.3V LVTTL Electrical Specifications" and "5.0V TTL Electrical 1-15

Specifications" tables

The "LP Low Power Pin" description was updated.

The "eX Timing Model" was updated.

1-26

1-18

1-12

1-17

1-i

v4.1

v4.0

The "Development Tool Support" section was updated.

The "Package Thermal Characteristics" section was updated.

The "Product Profile" section was updated.

v3.0

The "Ordering Information" section was updated.

The "Temperature Grade Offerings" section is new.

The "Speed Grade and Temperature Grade Matrix" section is new.

The "General Description" section was updated.

The "Clock Resources" section was updated.

1-ii

1-1

1-4

Table 1-1 • Connections of Routed Clock Networks, CLKA and CLKB is new.

The "User Security" section was updated.

1-4

1-5

The "I/O Modules" section was updated.

1-5

The "Hot Swapping" section was updated.

1-6

The "Power Requirements" section was updated.

The "Low Power Mode" section was updated.

1-6

The "Boundary Scan Testing (BST)" section was updated.

The "Dedicated Test Mode" section was updated.

The "Flexible Mode" section was updated.

1-9

Table 1-5 • Boundary-Scan Pin Configurations and Functions is new.

The "TRST Pin" section was updated.

1-9

The "Probing Capabilities" section is new.

1-10

1-11

1-12

1-13

1-21

1-26

The "Programming" section was updated.

The "Probing Capabilities" section was updated.

The "Silicon Explorer II Probe" section was updated.

The "Design Considerations" section was updated.

The "Development Tool Support" section was updated.

The "Absolute Maximum Ratings*" section was updated.

The "Temperature and Voltage Derating Factors" section was updated.

The "TDI, I/O Test Data Input" section was updated.

v4.3

3-1

eX Family FPGAs

Previous version Changes in current version (v4.3)

Page

1-26

v3.0

The "TDO, I/O Test Data Output" section was updated.

The "TMS Test Mode Select" section was updated.

The "TRST, I/O Boundary Scan Reset Pin" section was updated.

All VSV pins were changed to V_CCA. The change affected the following pins:

64-Pin TQFP –Pin 36

(continued)

100-Pin TQFP –Pin 57

49-Pin CSP –Pin D5

128-Pin CSP–Pin H11 and Pin J1 for eX256

180-Pin CSP –Pins J12 and K2

v2.0.1

The "Recommended Operating Conditions" section has been changed.

The "3.3V LVTTL Electrical Specifications" section has been updated.

The "5.0V TTL Electrical Specifications" section has been updated.

The "Total Dynamic Power (mW)" section is new.

The "System Power at 5%, 10%, and 15% Duty Cycle" section is new.

The "eX Timing Model" section has been updated.

The I/O Features table, Table 1-2 on page 1-5, was updated.

1-13

1-15

1-8

1-18

1-5

Advanced v0.4

The table, "Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 1-6

2.5V, TJ = 25× C" section, was updated.

"Typical eX Standby Current at 25°C" section is a new table.

1-13

The table in the section, "Package Thermal Characteristics" section has been updated for 1-17

the 49-Pin CSP.

The "eX Timing Model" section has been updated.

1-18

The timing numbers found in, "eX Family Timing Characteristics" section have been 1-22

updated.

The V_SVpin has been added to the "Pin Description" section.

1-26

Please see the following pin tables for the V_SVpin and an important footnote including the 2-1, 2-3, 2-6, 2-11

pin: "64-Pin TQFP","100-Pin TQFP",, ,"128-Pin CSP", and "180-Pin CSP".

The figure, "64-Pin TQFP" section has been updated.

2-1

1-i

Advanced v0.3

In the Product Profile, the Maximum User I/Os for eX64 was changed to 84.

In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100.

3-2

v4.3

eX Family FPGAs

Previous version Changes in current version (v4.3)

Advanced v0.2 The Mechanical Drawings section has been removed from the data sheet. The mechanical

Page

drawings are now contained in a separate document, “Package Characteristics and

Mechanical Drawings,” available on the Actel web site.

A new section describing "Clock Resources"has been added.

A new table describing "I/O Features"has been added.

The "Pin Description"section has been updated and clarified.

1-4

1-5

1-26

The original Electrical Specifications table was separated into two tables (2.5V and 3.3/ Page 8 and 9

5.0V). In both tables, several different currents are specified for V_OHand V_OL

A new table listing 2.5V low power specifications and associated power graphs were added. page 9

Pin functions for eX256 TQ100 have been added to the "100-Pin TQFP"table. 2-3

A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions have page 26

been added.

A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin pages 26-27

functions have been added.

A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. pages 27, 31

Advanced v.1

The following table note was added to the eX Timing Characteristics table for clarification: pages 14-15

Clock skew improves as the clock network becomes more heavily loaded.

v4.3

3-3

eX Family FPGAs

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Export Administration Regulations (EAR)

The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require

an approved export license prior to export from the United States. An export includes release of product or disclosure

of technology to a foreign national inside or outside the United States.

3-4

v4.3

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

www.jp.actel.com

Actel Hong Kong

www.actel.com.cn

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Phone +852 2185 6460

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EX256-FCS180I [MICROSEMI]

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