RT54SX16-1CG256B_技术文档

SX Family FPGAs RadTolerant and HiRel

General Description

The Actel RadTolerant (RT) and HiRel versions of the SX

Radiation Survivability

Family of FPGAs offer many advantages for applications

such as commercial and military satellites, deep space

probes, and all types of military and high reliability

equipment.

Total dose results are summarized in two ways. First, by

the maximum total dose level that is reached when the

parts fail to meet a device specification but remain

functional. For Actel FPGAs, the parameter that exceeds

the specification first is I_CC, the standby supply current.

Second, by the maximum total dose that is reached prior

to the functional failure of the device.

The RT and HiRel versions are fully pin-compatible,

allowing designs to migrate across different applications

that may or may not have radiation requirements. Also,

the HiRel devices can be used as a low cost prototyping

tool for RT designs.

The RTSX devices have varying total dose radiation

survivability. The ability of these devices to survive

radiation effects is both device- and lot-dependent. The

customer must evaluate and determine the applicability

of these devices to their specific design and

environmental requirements.

The programmable architecture of these devices offers

high performance, design flexibility, and fast and

inexpensive prototyping—all without the expense of test

vectors, NRE charges, long lead times, and schedule and

cost penalties for design modifications required by ASIC

devices.

Actel will provide total dose radiation testing data along

with the test data on each pedigreed lot available for

sale. These reports are available on the Actel website, or

you can contact your local sales representative to receive

a copy. A listing of available lots and devices will also be

provided. These results are only provided for reference

and for customer information.

Device Description

The RT54SX16 and A54SX16 devices have 16,000

available gates and up to 179 I/Os. The RT54SX32 and

A54SX32 have 32,000 available gates and up to 228 I/Os.

All of these devices support JTAG boundary scan

testability.

For a radiation performance summary, see Radiation

Performance of Actel Products. This summary will also

show single event upset (SEU) and single event latch-up

(SEL) testing that has been performed on Actel FPGAs.

All of these devices are available in Ceramic Quad Flat

Pack (CQFP) packaging, with 208-pin and 256-pin

versions. The 256-pin version offers the user the highest

I/O capability, while the 208-pin version offers pin

compatibility with the commercial Plastic Quad Flat Pack

(PQFP-208). This compatibility allows the user to

prototype using the very low cost plastic package and

then switch to the ceramic package for production. For

more information on plastic packages, refer to the 54SX

Family FPGAs datasheet.

QML Certification

Actel has achieved full QML certification, demonstrating

that quality management, procedures, processes, and

controls are in place and comply with MIL-PRF-38535, the

performance specification used by the Department of

Defense for monolithic integrated circuits. QML

certification is a good example of Actel's commitment to

supplying the highest quality products for all types of

high-reliability, military, and space applications.

The A54SX16 and A54SX32 devices are manufactured

using

a

0.35

µ

technology at the Chartered

Semiconductor facility in Singapore. These devices offer

the highest speed performance available in FPGAs today.

Many suppliers of microelectronics components have

implemented QML as their primary worldwide business

system. Appropriate use of this system not only helps in

the implementation of advanced technologies, but also

allows for quality, reliable, and cost-effective logistics

support throughout the life cycles of QML products.

The RT54SX16 and RT54SX32 devices are manufactured

using a 0.6 µ technology at the Matsushita (MEC) facility

in Japan. These devices offer levels of radiation

survivability far in excess of typical CMOS devices.

v2.1

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SX Family FPGAs RadTolerant and HiRel

Disclaimer

Programmable Interconnect Element

All radiation performance information is provided for

information purposes only and is not guaranteed. The

total dose effects are lot-dependent, and Actel does not

guarantee that future devices will continue to exhibit

similar radiation characteristics. In addition, actual

performance can vary widely due to a variety of factors,

including but not limited to, characteristics of the orbit,

radiation environment, proximity to satellite exterior,

amount of inherent shielding from other sources within

the satellite, and actual bare die variations. For these

reasons, Actel does not guarantee any level of radiation

survivability, and it is solely the responsibility of the

customer to determine whether the device will meet the

requirements of the specific design.

Actel’s SX family provides much more efficient use of

silicon by locating the routing interconnect resources

between the Metal 2 (M2) and Metal 3 (M3) layers

(Figure 1-1). This completely eliminates the channels of

routing and interconnect resources between logic

modules (as implemented on SRAM FPGAs and previous

generations of antifuse FPGAs), and enables the entire

floor of the device to be spanned with an uninterrupted

grid of logic modules.

Interconnection between these logic modules is achieved

using Actel’s patented metal-to-metal programmable

antifuse interconnect elements, which are embedded

between the M2 and M3 layers. The antifuses are

normally open circuit and, when programmed, form a

permanent low-impedance connection.

The extremely small size of these interconnect elements

gives the SX family abundant routing resources and

provides excellent protection against design pirating.

Reverse engineering is virtually impossible, because it is

extremely difficult to distinguish between programmed

and unprogrammed antifuses, and there is no

configuration bitstream to intercept.

SX Family Architecture

The SX family architecture was designed to satisfy next-

generation performance and integration requirements

for production-volume designs in a broad range of

applications.

Additionally, the interconnects (i.e., the antifuses and

metal tracks) have lower capacitance and lower

resistance than any other device of similar capacity,

leading to the fastest signal propagation in the industry.

Routing Tracks

Metal 3

Amorphous Silicon/

Dielectric Antifuse

Tungsten Plug Via

Metal 2

Metal 1

Tungsten Plug

Contact

Silicon Substrate

Figure 1-1 • SX Family Interconnect Elements

1-2

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SX Family FPGAs RadTolerant and HiRel

Logic Module Design

The SX family architecture has been called a “sea-of-

modules” architecture because the entire floor of the

device is covered with a grid of logic modules with

virtually no chip area lost to interconnect elements or

routing (see Figure 1-2). Actel provides two types of logic

modules, the register cell (R-cell) and the combinatorial

cell (C-cell).

FPGA. The clock source for the R-cell can be chosen from

the hardwired clock or the routed clock.

The C-cell implements a range of combinatorial functions

with up to five inputs (Figure 1-4 on page 1-4). Inclusion

of the DB input and its associated inverter function

dramatically increases the number of combinatorial

functions that can be implemented in a single module

from 800 options in previous architectures to more than

4,000 in the SX architecture. An example of the improved

flexibility enabled by the inversion capability is the

ability to integrate a three-input exclusive-OR function

into a single C-cell. This facilitates construction of nine-

bit parity-tree functions with 2 ns propagation delays. At

the same time, the C-cell structure is extremely synthesis-

friendly, simplifying the overall design and reducing

synthesis time.

The R-cell contains a flip-flop featuring more control

signals than in previous Actel architectures, including

asynchronous clear, asynchronous preset, and clock

enable (using the S0 and S1 lines). The R-cell registers

feature programmable clock polarity, selectable on a

register-by-register basis (Figure 1-3 on page 1-4). This

provides the designer with additional flexibility while

allowing mapping of synthesized functions into the SX

Channeled Array Architecture

Sea-of-Modules Architecture

Figure 1-2 • Channeled Array and Sea-of-Modules Architectures

v2.1

1-3

SX Family FPGAs RadTolerant and HiRel

Routed

Data Input

S0

S1

PSETB

CLRB

Direct

Connect

Input

D

Q

Y

HCLK

CLKA

CLKB

CKS

CKP

Figure 1-3 • R-Cell

D0

D1

Y

D2

D3

Sa

Sb

DB

A0 B0

A1 B1

Figure 1-4 • C-Cell

1-4

v2.1

SX Family FPGAs RadTolerant and HiRel

To increase design efficiency and device performance,

Actel has further organized these modules into

SuperClusters (see Figure 1-5). SuperCluster 1 is a two-

wide grouping of Type 1 Clusters. SuperCluster 2 is a two-

wide group containing one Type 1 Cluster and one

Type 2 Cluster. SX devices feature more SuperCluster 1

modules than SuperCluster 2 modules because designers

typically require more combinatorial logic than flip-flops.

Chip Architecture

The SX family’s chip architecture provides a unique

approach to module organization and chip routing that

delivers the best register/logic mix for a wide variety of

new and emerging applications.

Module Organization

Actel has arranged all C-cell and R-cell logic modules into

horizontal banks called Clusters. There are two types of

Clusters: Type 1 contains two C-cells and one R-cell, and

Type 2 contains one C-cell and two R-cells.

R-Cell

C-Cell

Routed

D0

D1

Data Input

S1

S0

PSETB

Y

D2

Direct

Connect

D3

D

Q

Y

Input

Sa

Sb

HCLK

CLKA

CLKB

CLRB

DB

CKS

CKP

A0 B0

A1 B1

Cluster 1

Cluster 2

Cluster 1

Type 1 SuperCluster

Type 2 SuperCluster

Figure 1-5 • Cluster Organization

v2.1

1-5

SX Family FPGAs RadTolerant and HiRel

Routing Resources

Clusters and SuperClusters can be connected through the

use of two innovative local routing resources called

FastConnect and DirectConnect that enable extremely

fast and predictable interconnections of modules within

Clusters and SuperClusters (see Figure 1-6 and Figure 1-7

on page 1-7). This routing architecture also dramatically

reduces the number of antifuses required to complete a

circuit, ensuring the highest possible performance.

FastConnect enables horizontal routing between any

two logic modules within a given SuperCluster, and

vertical routing to the SuperCluster immediately below

it. Only one programmable connection is used in a

FastConnect path, delivering a maximum pin-to-pin

propagation of 0.4 ns.

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing

between SuperClusters. The exact combination of track

lengths and antifuses within each path is chosen by the

100% automatic place-and-route software to minimize

signal propagation delays.

DirectConnect is a horizontal routing resource that

provides connections from a C-cell to its neighboring

R-cell in a given SuperCluster. DirectConnect uses a

hardwired signal path requiring no programmable

interconnection to achieve its fast signal propagation

time of less than 0.1 ns.

DirectConnect

• No Antifuses

FastConnect

• One Antifuse

Routing Segments

• Typically Two Antifuses

• Max. Five Antifuses

Type 1 SuperClusters

Figure 1-6 • DirectConnect and FastConnect for Type 1 SuperClusters

1-6

v2.1

SX Family FPGAs RadTolerant and HiRel

DirectConnect

• No Antifuses

FastConnect

• One Antifuse

Routing Segments

• Typically Two Antifuses

• Max. Five antifuses

Type 2 SuperClusters

Figure 1-7 • DirectConnect and FastConnect for Type 2 SuperClusters

Clock Resources

Actel’s high-drive routing structure provides three clock

networks. The first clock, called HCLK, is hardwired from

the HCLK buffer to the clock select MUX in each R-cell.

HCLK cannot be connected to combinational logic. This

provides a fast propagation path for the clock signal,

enabling the 8.9 ns clock-to-out (pad-to-pad)

performance of the RTSX devices. The hardwired clock is

tuned to provide clock skew is less than 0.5 ns worst case.

Constant Load

Clock Network

HCLKBUF

Figure 1-8 • RTSX Constant Load Clock Pad

The remaining two clocks (CLKA and CLKB) are global

clocks that can be sourced from external pins or from

internal logic signals within the RTSX device. CLKA and

CLKB may be connected to sequential cells or to

combinational logic. If CLKA or CLKB is sourced from

internal logic signals, then the external clock pin cannot

be used for any other input and must be tied low or

high. Figure 1-8 describes the clock circuit used for the

constant load HCLK. Figure 1-9 describes the CLKA and

CLKB circuit used in all RTSX devices with the exception

of the RT54SX72S device.

Clock Network

From Internal Logic

CLKBUF

CLKBUFI

CLKINT

CLKINTI

Figure 1-9 • RTSX Clock Pads

v2.1

1-7

SX Family FPGAs RadTolerant and HiRel

Power Requirements

Other Architecture

The RTSX family supports either 3.3 V or 5.0 V I/O voltage

operation and is designed to tolerate 5 V inputs in each

case (Table 1-1). Power consumption is extremely low

due to the very short distances signals are required to

travel to complete a circuit. Power requirements are

further reduced due to the small number of antifuses in

the path, and because of the low resistance properties of

the antifuses. The antifuse architecture does not require

active circuitry to hold a charge (as do SRAM or EPROM),

making it the lowest-power architecture on the market.

Performance

The combination of architectural features described

above enables RT54SX devices to operate with internal

clock frequencies exceeding 160 MHz, enabling very fast

execution of complex logic functions. Thus, the RTSX

family is an optimal platform upon which to integrate

the functionality previously contained in multiple CPLDs.

In addition, designs that previously would have required

a gate array to meet performance goals can now be

integrated into an RTSX device with dramatic

improvements in cost and time-to-market. Using timing-

driven place-and-route tools, designers can achieve

highly deterministic device performance. With RTSX

devices, there is no need to use complicated

performance-enhancing design techniques such as

redundant logic to reduce fanout on critical nets, or the

instantiation of macros in HDL code to achieve high

performance.

Table 1-1 • Supply Voltages

Maximum Maximum

Input

Output

Drive

V_CCAV_CCIV_CCRTolerance

A54SX16 3.3 V 3.3 V 5.0 V

A54SX32

5.0 V

3.3 V

RTSX16

RTSX32

3.3 V 3.3 V 5.0 V

3.3 V

I/O Modules

Boundary Scan Testing (BST)

Each I/O on an RTSX device can be configured as an input,

an output, a tristate output, or a bidirectional pin. Even

without the inclusion of dedicated registers, these I/Os, in

combination with array registers, can achieve clock-to-out

(PAD-to-PAD) timing as fast as 5.8 ns. I/O cells including

embedded latches and flip-flops require instantiation in

HDL code. This is a design complication not encountered

in RTSX FPGAs. Fast PAD-to-PAD timing ensures that the

device will have little trouble interfacing with any other

device in the system, which in turn enables parallel design

of system components and reduces overall design time.

All RTSX devices are IEEE 1149.1 (JTAG) compliant. They

offer superior diagnostic and testing capabilities by

providing BST and probing capabilities. These functions

are controlled through the special test pins in conjunction

with the program fuse. The functionality of each pin is

described in Table 1-2. Figure 1-10 on page 1-9 is a block

diagram of the RTSX JTAG circuitry.

Table 1-2 • Boundary Scan Pin Functionality

Program Fuse Blown

(Dedicated Test Mode)

Program Fuse Not Blown

(Flexible Mode)

TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and

test pins may be used as I/Os

No need for pull-up resistor for Use a pull-up resistor of

TMS 10 kΩ on TMS

1-8

v2.1

SX Family FPGAs RadTolerant and HiRel

TDI

Data Registers (DRs)

0

Output

TDO

Stage

1

Instruction Register (IR)

Clocks and/or Controls

TMS

TCK

TAP Controller

TRST External

Hardwired Pin

Figure 1-10 • RTSX JTAG Circuitry

Configuring Diagnostic Pins

Dedicated Test Mode

The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and

PRB) are placed in the desired mode by selecting the

appropriate check boxes in the Variation dialog

window. This dialog window is accessible through the

Design Setup Wizard under the Tools menu in the Actel

Designer software.

When the Reserve JTAG check box is selected in the

Designer software, the RTSX is placed in Dedicated Test

mode, which configures the TDI, TCK, and TDO pins for

BST or in-circuit verification with Silicon Explorer II. An

internal pull-up resistor is automatically enabled on both

the TMS and TDI pins. In dedicated test mode, TCK, TDI,

and TDO are dedicated test pins and become unavailable

for pin assignment in the Pin Editor. The TMS pin will

function as specified in the IEEE 1149.1 (JTAG)

Specification.

TRST Pin

The TRST pin functions as a Boundary Scan Reset pin. The

TRST pin is an asynchronous, active-low input to initialize

or reset the BST circuit. An internal pull-up resistor is

automatically enabled on the TRST pin.

v2.1

1-9

SX Family FPGAs RadTolerant and HiRel

Actel Designer software is a place-and-route tool and

provides a comprehensive suite of back-end support

tools for FPGA development. The Designer software

includes timing-driven place-and-route and a world-class

integrated static timing analyzer and constraints editor.

With the Designer software, a user can lock his/her

design pins before layout while minimally impacting the

results of place-and-route. Additionally, the back-

annotation flow is compatible with all the major

simulators and the simulation results can be cross-probed

with Silicon Explorer II, the Actel integrated verification

and logic analysis tool. Another tool included in the

Designer software is the ACTgen macro builder, which

easily creates popular and commonly used logic

functions for implementation in your schematic or HDL

design. Actel Designer software is compatible with the

most popular FPGA design entry and verification tools

from companies such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

Flexible Mode

When the Reserve JTAG check box is cleared (the

default setting in the Designer software), the RTSX is

placed in flexible mode, which allows the TDI, TCK, and

TDO pins to function as user I/Os or BST pins. In this

mode the internal pull-up resistors on the TMS and TDI

pins are disabled. An external 10 kΩ pull-up resistor to

V_CCIis required on the TMS pin.

The TDI, TCK, and TDO pins are transformed from user I/Os

into BST pins when a rising edge is detected on TCK while

TMS is at logical low. Once the BST pins are in test mode

they will remain in BST mode until the internal BST state

machine reaches the "logic reset" state. At this point the

BST pins will be released and will function as regular I/O

pins. The "logic reset" state is reached five TCK cycles after

the TMS pin is set to logical HIGH.

The program fuse determines whether the device is in

Dedicated Test or Flexible mode. The default (fuse not

programmed) is Flexible mode.

Development Tool Support

RTSX Probe Circuit Control Pins

The RTSX family of FPGAs is fully supported by both Actel

Libero^®Integrated Design Environment (IDE) and

Designer FPGA Development software. Actel Libero IDE

is a design management environment that streamlines

the design flow. Libero IDE provides an integrated

design manager that seamlessly integrates design tools

while guiding the user through the design flow,

managing all design and log files, and passing necessary

design data among tools. Additionally, Libero IDE allows

users to integrate both schematic and HDL synthesis into

a single flow and verify the entire design in a single

environment. Libero IDE includes Synplify^®for Actel

from Synplicity^®, ViewDraw® for Actel from Mentor

Graphics^®, ModelSim™ HDL Simulator from Mentor

Graphics, WaveFormer Lite™ from SynaptiCAD™, and

Designer software from Actel. Refer to the Libero IDE

Design Flow (located on the Actel website) diagram for

more information.

The RTSX RadTolerant devices contain internal probing

circuitry that provides built-in access to every node in a

design, enabling 100-percent real-time observation and

analysis of a device's internal logic nodes without design

iteration. The probe circuitry is accessed using Silicon

Explorer II, an easy-to-use integrated verification and

logic analysis tool that can sample data at 100 MHz

(asynchronous) or 66 MHz (synchronous). Silicon Explorer

attaches to a PC’s standard COM port, turning the PC

into a fully functional 18-channel logic analyzer. Silicon

Explorer allows designers to complete the design

verification process at their desks and reduces

verification time from several hours per cycle to a few

seconds.

The Silicon Explorer II tool uses the boundary scan ports

(TDI, TRST, TCK, TMS, and TDO) to select the desired nets

for verification. The selected internal nets are assigned

to the PRA/PRB pins for observation. Figure 1-11 on page

1-11 illustrates the interconnection between Silicon

Explorer II and the FPGA to perform in-circuit

verification.

1-10

v2.1

SX Family FPGAs RadTolerant and HiRel

Design Considerations

For prototyping, the TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because

these pins are active during probing, critical signals input through these pins are not available while probing. In

addition, the security fuse should not be programmed during prototyping because doing so disables the probe

circuitry.

RTSX-S FPGA

TRST

TCK

TMS

Silicon Explorer II

Serial Connection

TDO

PRA

PRB

Figure 1-11 • Probe Setup

Related Documents

Datasheets

54SX Family FPGAs

http://www.actel.com/documents/A54SXDS.pdf

Application Notes

Power-Up and Power-Down Behavior of 54SX and RT54SX Devices

http://www.actel.com/documents/PowerUpAN.pdf

v2.1

1-11

SX Family FPGAs RadTolerant and HiRel

3.3 V / 5 V Operating Conditions

Recommended Operating Conditions

Table 1-3 • Absolute Maximum Ratings

Symbol

V_CCR

V_CCA

V_CCI

V_I

Parameter

Limits

Units

DC Supply Voltage

Input Voltage

–0.3 to +6.0

–0.3 to +4.0

–0.5 to +5.5

–0.5 to +3.6

–30 to +5.0

V

V_O

Output Voltage

V

I_IO

I/O Source Sink

Current²

mA

T_STG

Storage Temperature

–40 to +125

°C

Notes:

1. Stresses beyond those listed in Table 1-3 may cause permanent damage to the device. Exposure to absolute maximum rated

conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating

Conditions.

2. The I/O source sink numbers refer to tristated inputs and outputs

Table 1-4 • Recommended Operating Conditions

Parameter

Commercial

0 to +70

±10

Military

–55 to +125

±10

Units

°C

Temperature Range¹

3.3 V Power²

%V_CC

Supply Tolerance

5 V Power Supply ²

Tolerance

±5

±10

%V_CC

Notes:

1. Ambient temperature (T_A) is used for commercial and industrial; case temperature (T_C) is used for military.

2. All power supplies must be in the recommended operating range for 250 µs. For more information, refer to the Power-Up and

Power-Down Behavior of 54SX and RT54SX Devices application note.

1-12

v2.1

SX Family FPGAs RadTolerant and HiRel

Electrical Specifications

Table 1-5 • Electrical Specifications

Commercial

Military

Symbol

Parameter

(I_OH= –20 µA) (CMOS)

Min.

Max.

Min.

Max.

Units

V_OH

(V_CCI– 0.1)

2.4

V_CCI

(V_CCI– 0.1)

V_CCI

V

(I_OH= –8 mA) (TTL)

(I_OH= –6 mA) (TTL)

2.4

V_CCI

V_OL

(I_OL= 20 µA) (CMOS)

(I_OL= 12 mA) (TTL)

(I_OL= 8 mA) (TTL)

0.10

0.50

V

0.50

0.8

V_IL

Low Level Inputs

0.8

V

V_IH

High Level Inputs

2.0

t_R, t_F

C_IO

Input Transition Time t_R, t_F

C_IOI/O Capacitance

Standby Current, I_CC

50

10

50

10

25

ns

pF

mA

I_CC

4.0

I_CC(D)

I_{CC(D) Dynamic}

I

V_CCSupply Current

See the "Power Dissipation" section on page 1-15.

Power-Up Sequencing

Table 1-6 • RT54SX16, A54SX16, RT54SX32, A54SX32

V_CCA

V_CCR

V_CCI

Power-Up Sequence

Comments

No possible damage to device

3.3 V

5.0 V

3.3 V

5.0 V First

3.3 V Second

3.3 V First

Possible damage to device

5.0 V Second

Power-Down Sequencing

Table 1-7 • RT54SX16, A54SX16, RT54SX32, A54SX32

V_CCA

V_CCR

V_CCI

Power-Down Sequence

Comments

3.3 V

5.0 V

3.3 V

5.0 V First

Possible damage to device

3.3 V Second

3.3 V First

No possible damage to device

5.0 V Second

v2.1

1-13

SX Family FPGAs RadTolerant and HiRel

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θ_jc, and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different air flow rates.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power dissipation allowed for an RT54SX16 in a CQFP 256-pin package

at military temperature and still air is shown in EQ 1-1:

Max. junction temp. (°C) – Max. ambient temp. (°C)

Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------ = -------------------------------------- = 1.09 W

(°C/W) 23°C/W

150°C – 125°C

θ

ja

EQ 1-1

Table 1-8 • Package Thermal Characteristics

θ_ja

Package Type

Pin Count

θ_jc

Still Air

Units

RT54SX16

Ceramic Quad Flat Pack (CQFP)

RT54SX32

208

256

7.5

4.6

29

23

°C/W

Ceramic Quad Flat Pack (CQFP)

A54SX16

208

256

6.9

3.5

35

20

°C/W

Ceramic Quad Flat Pack (CQFP)

A54SX32

208

256

7.9

5.6

30

25

°C/W

Ceramic Quad Flat Pack (CQFP)

208

256

7.6

4.8

30

24

°C/W

1-14

v2.1

SX Family FPGAs RadTolerant and HiRel

Active Power Component

Power Dissipation

Power dissipation in CMOS devices is usually dominated

by the active (dynamic) power dissipation. This

component is frequency-dependent, a function of the

logic and the external I/O. Active power dissipation

results from charging the internal chip capacitances of

the interconnects, unprogrammed antifuses, module

inputs, and module outputs, plus external capacitance

due to PCB traces and load device inputs. An additional

component of the active power dissipation is the totem

pole current in CMOS transistor pairs. The net effect can

be associated with an equivalent capacitance that can be

combined with frequency and voltage to represent

active power dissipation.

P = (I_CCstandby + I_CCactive) * V_CCA+ I_OL* V_OL* N +

I_OH* (V_CCA– V_OH) * M

EQ 1-2

where:

I_CCstandby is the current flowing when no inputs or

outputs are changing.

I

_CCactive is the current flowing due to CMOS switching.

_OL, I_OHare TTL sink/source currents.

V

_OL, V_OHare TTL level output voltages.

N is the number of outputs driving TTL loads to V_OL

M is the number of outputs driving TTL loads to V_OH

.

Equivalent Capacitance

The power dissipated by a CMOS circuit can be expressed

by EQ 1-3:

Accurate values for N and M are difficult to determine

because they depend on the design and on the system I/O.

The power can be divided into two components: static

and active.

Power (µW) = C_EQ* V_CCA²* F

EQ 1-3

Static Power Component

where:

Power consumption due to standby current is typically a

small component of the total power consumption.

Standby power is shown below for military, worst-case

conditions (70°C).

C_EQ

V_CCA

F

= Equivalent capacitance in pF

= Power supply in volts (V)

= Switching frequency in MHz

I_CC

V_CC

Power

Equivalent capacitance is calculated by measuring

_CCactive at a specified frequency and voltage for each

20 mA

3.6 V

72 mW

I

circuit component of interest. Measurements have been

made over a range of frequencies at a fixed value of

V_CCA. Equivalent capacitance is frequency-independent

so that the results may be used over a wide range of

operating conditions. Equivalent capacitance values are

shown in Table 1-9.

Table 1-9 • Equivalent Capacitance Values

RT54SX16

A54SX16

RT54SX32

A54SX32

Equivalent Capacitance (pF)

Modules

C_EQM

C_EQI

7.0

2.0

3.9

1.0

7.0

2.0

3.9

1.0

Input Buffers

Output Buffers

C_EQO

C_EQCR

C_EQCD

10.0

0.4

5.0

10.0

0.6

5.0

Routed Array Clock Buffer Loads

Dedicated Clock Buffer Loads

Fixed Capacitance (pF)

routed_Clk1

0.2

0.3

0.25

0.15

0.34

0.23

r₁

r₂

120

60

210

107

routed_Clk2

Fixed Clock Loads

Clock Loads on Dedicated Array Clock

s₁

528

1,080

v2.1

1-15

SX Family FPGAs RadTolerant and HiRel

C

Values (pF)

Determining Average Switching

Frequency

To determine the switching frequency for a design, you

must have a detailed understanding of the data input

values to the circuit. The following guidelines are meant

to represent worst-case scenarios so they can be

generally used to predict the upper limits of power

dissipation.

EQ

To calculate the active power dissipated by the complete

design, the switching frequency of each part of the logic

must be known. EQ 1-4 shows a piecewise linear

summation over all components.

Power = V_CCA²* [(m * C_EQM* f_m)_modules

(n * C_EQI* f_n)_inputs+ (p * (C_EQO+ C_L) * f_p)_outputs

0.5 * (q₁* C_EQCR* f_{q1 routed_Clk1}+ (r₁* f_{q1 routed_Clk1}

0.5 * (q₂* C_EQCR* f_{q2 routed_Clk2}+ (r₂* f_{q2 routed_Clk2}

0.5 * (s₁* C_EQCD* f_s1)_{dedicated_CLK}

+

)

+

)

Logic Modules (m)

=

80% of modules

# inputs/4

]

Inputs Switching (n)

EQ 1-4

Outputs Switching (p)

First Routed Array Clock Loads (q₁)

# output/4

where:

40% of sequential

modules

m

n

= Number of logic modules switching at f_m

= Number of input buffers switching at f_n

= Number of output buffers switching at f_p

Second Routed Array Clock Loads =

(q₂)

40% of sequential

modules

p

Load Capacitance (C_L)

=

35 pF

F/10

q₁

= Number of clock loads on the first routed

array clock

Average Logic Module Switching =

Rate (f_m)

q₂

r₁

r₂

s₁

= Number of clock loads on the second routed

array clock

Average Input Switching Rate (f_n)

=

F/5

= Fixed capacitance due to first routed array

clock

Average Output Switching Rate (f_p) =

Average First Routed Array Clock =

F/10

F/2

= Fixed capacitance due to second routed

array clock

Rate (f_q1

Average Second Routed Array =

Clock Rate (f_q2

)

F/2

F

= Fixed number of clock loads on the

dedicated array clock (528 for A54SX16)

)

Average Dedicated Array Clock =

Rate (f_s1)

C_EQM= Equivalent capacitance of logic modules in

pF

C_EQI

= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in

pF

C_EQCR= Equivalent capacitance of routed array clock

in pF

C_EQCD= Equivalent capacitance of dedicated array

clock in pF

C_L

f_m

f_n

= Output lead capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

f_p

f_q1

f_q2

= Average second routed array clock rate in

MHz

1-16

v2.1

SX Family FPGAs RadTolerant and HiRel

Temperature and Voltage Derating Factors

Table 1-10 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_CCA= 3.0 V)

Junction Temperature (T_J)

V_CCA

3.0

–40

0.78

0.73

0.69

0

25

70

85

125

1.16

1.08

1.02

0.87

0.82

0.77

0.89

0.83

0.78

1.00

0.93

0.87

1.04

0.97

0.92

3.3

3.6

SX Timing Model

Predicted

Routing

Delays

Input Delays

I/O Module

Internal Delays

Output Delays

I/O Module

Combinatorial Cell

t

INY = 2.2 ns

IRD2 = 1.2 ns

t

DHL = 2.8 ns

t

RD1 = 0.7 ns

RD4 = 2.2 ns

RD8 = 4.3 ns

t

PD = 0.9 ns

I/O Module

t

DLH = 2.8 ns

Register Cell

D

Q

D

Q

t

RD1 = 0.7 ns

t

ENZH = 2.8 ns

t

SUD = 0.8 ns

HD = 0.0 ns

t

RCO = 0.6 ns

Routed

Clock

t

RCKH = 2.8 ns (100% Load)

F

MAX = 175 MHz

Hardwired

Clock

t

HCKH = 1.3 ns

F

HMAX = 240 MHz

Note:

Values shown for A54SX16-1 at worst-case commercial conditions.

Figure 1-12 • SX Timing Model

Hardwired Clock

External Setup

Routed Clock

External Setup

=

t_INY+ t_IRD1+ t_SUD– t_RCKH

=

t_INY+ t_IRD1+ t_SUD– t_HCKH

=

2.2 + 0.7 + 0.8 – 2.4 = 1.3 ns

t_RCKH+ t_RCO+ t_RD1+ t_DHL

2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns

Clock-to-Out (Pin-to-Pin)

t

_HCKH+ t_RCO+ t_RD1+ t_DHL

Clock-to-Out (Pin-to-Pin)

1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns

2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns

v2.1

1-17

SX Family FPGAs RadTolerant and HiRel

E

D

PAD To AC Test Loads (shown below)

TRIBUFF

V_CC

GND

En

GND

90%

In

50%

V_OH

En

50%

50% 50%

V_CC

50% 50%

V_OH

1.5 V

Out

V_OL

1.5 V

Out

GND

10%

V_OL

t

DLH

DHL

ENZL

ENLZ

ENZH

ENHZ

Figure 1-13 • Output Buffer Delays

Load 2

(Used to Measure rising/falling delays)

Load 1

(Used to measure

propagation delay)

V_CC

GND

To the Output

Under Test

R to V_CCfor t

R to GND for t

R = 1 kΩ

/t

PLZ PZL

50 pF

/

To the Output

Under Test

PHZ tPZL

50 pF

Figure 1-14 • AC Test Loads

S

A

B

Y

PA D

INBUF

V_CC

S, A or B

50%

CC

GND

50%

V

50%

3 V

Out

In

0 V

1.5 V

V_CC

1.5 V

GND

t_PD

50%

Out

GND

50%

V_CC

50%

Out

50%

t_PD

GND

t_PD

t

INY

Figure 1-15 • Input Buffer Delays

Figure 1-16 • C-Cell Delays

1-18

v2.1

SX Family FPGAs RadTolerant and HiRel

D

PRESET

CLR

Q

CLK

(Positive Edge Triggered)

t_HD

D

t_HP

t_SUD

t_HPWH'

t_RPWH

CLK

t_HPWL'

t_RPWL

t_RCO

Q

t_PRESET

t_CLR

CLR

t_WASYN

PRESET

Figure 1-17 • Register Cell Timing Characteristics – Flip-Flops

Long Tracks

Timing Characteristics

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and

sometimes five antifuse connections. This increases

capacitance and resistance, resulting in longer net delays

for macros connected to long tracks. Typically up to 6

percent of nets in a fully utilized device require long

tracks. Long tracks contribute approximately 4 ns to 8.4

ns delay. This additional delay is represented statistically

in higher fanout (FO = 24) routing delays in the data

sheet specifications section.

Timing characteristics for SX devices fall into three

categories: family-dependent, device-dependent, and

design-dependent. The input and output buffer

characteristics are common to all SX family members.

Internal routing delays are device-dependent. Design

dependence means actual delays are not determined

until after placement and routing of the user’s design is

complete. Delay values may then be determined by using

the Timer tool or performing simulation with post-layout

delays.

Critical Nets and Typical Nets

Timing Derating

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most time-

critical paths. Critical nets are determined by net

property assignment prior to placement and routing. Up

to 6 percent of the nets in a design may be designated as

critical, whereas 90 percent of the nets in a design are

typical.

SX devices are manufactured in a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process variations. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case

processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating

temperature, and worst-case processing.

v2.1

1-19

SX Family FPGAs RadTolerant and HiRel

A54SX16 Timing Characteristics

Table 1-11 • A54SX16

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.9

1.0

ns

Predicted Routing Delays²

t_DC

FO = 1 Routing Delay, Direct Connect

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.1

0.6

0.7

1.2

1.7

2.2

4.3

5.6

9.4

12.4

0.1

0.7

ns

t_FC

t_RD1

0.8

t_RD2

FO = 2 Routing Delay

1.4

t_RD3

FO = 3 Routing Delay

2.0

t_RD4

FO = 4 Routing Delay

2.6

t_RD8

FO = 8 Routing Delay

5.0

t_RD12

t_RD18

t_RD24

R-Cell Timing

t_RCO

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

6.6

11.0

14.6

Sequential Clock-to-Q

0.6

0.8

ns

t_CLR

Asynchronous Clear-to-Q

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_SUD

0.8

0.0

2.4

0.9

0.0

2.9

t_HD

t_WASYN

I/O Module Input Propagation Delays

t_INYH

Input Data Pad-to-Y HIGH

2.2

2.6

ns

t_INYL

Input Data Pad-to-Y LOW

Predicted Input Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

0.7

1.2

1.7

2.2

4.3

5.6

9.4

12.4

0.8

1.4

ns

t_IRD2

t_IRD3

2.0

t_IRD4

2.6

t_IRD8

5.0

t_IRD12

t_IRD18

t_IRD24

Notes:

6.6

11.0

14.6

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

1-20

v2.1

SX Family FPGAs RadTolerant and HiRel

Table 1-12 • A54SX16

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

I/O Module – TTL Output Timing*

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to LOW

Enable-to-Pad, Z to HIGH

Enable-to-Pad, LOW to Z

Enable-to-Pad, HIGH to Z

Delta LOW to HIGH

2.8

3.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

2.3

2.8

ns

2.8

3.3

ns

4.5

5.2

ns

2.2

2.6

ns

0.05

0.06

0.08

ns/pF

Delta HIGH to LOW

Dedicated (Hardwired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.7

1.9

2.0

2.2

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

2.1

2.4

ns

0.4

ns

Minimum Period

4.2

4.9

ns

f_HMAX

Maximum Frequency

240

205

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

2.4

2.7

2.9

2.8

2.9

3.1

3.3

3.5

3.3

3.5

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

3.1

3.7

ns

t_RPWL

t_RCKSW

0.6

0.8

0.9

Note: *Delays based on 35 pF loading, except for t_ENZLand t_ENZH. For t_ENZLand t_ENZH,the loading is 5 pF.

v2.1

1-21

SX Family FPGAs RadTolerant and HiRel

RT54SX16 Timing Characteristics

Table 1-13 • RT54SX16

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

1.7

1.8

ns

Predicted Routing Delays²

t_DC

FO = 1 Routing Delay, Direct Connect

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.2

1.1

0.2

1.3

ns

t_FC

t_RD1

1.3

1.5

t_RD2

FO = 2 Routing Delay

2.2

2.6

t_RD3

FO = 3 Routing Delay

3.1

3.6

t_RD4

FO = 4 Routing Delay

4.0

4.7

t_RD8

FO = 8 Routing Delay

7.8

9.0

t_RD12

t_RD18

t_RD24

R-Cell Timing

t_RCO

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

10.1

17.0

22.4

11.9

19.8

26.3

Sequential Clock-to-Q

1.5

2.0

ns

t_CLR

Asynchronous Clear-to-Q

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_SUD

2.0

0.0

4.4

2.2

0.0

5.3

t_HD

t_WASYN

I/O Module Input Propagation Delays

t_INYH

Input Data Pad-to-Y HIGH

4.0

4.7

ns

t_INYL

Input Data Pad-to-Y LOW

Predicted Input Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

1.3

2.2

1.5

2.6

ns

t_IRD2

t_IRD3

3.1

3.6

t_IRD4

4.0

4.7

t_IRD8

7.8

9.0

t_IRD12

t_IRD18

t_IRD24

Notes:

10.1

17.0

22.4

11.9

19.8

26.3

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

1-22

v2.1

SX Family FPGAs RadTolerant and HiRel

Table 1-14 • RT54SX16

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

I/O Module – TTL Output Timing*

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to LOW

Enable-to-Pad, Z to HIGH

Enable-to-Pad, LOW to Z

Enable-to-Pad, HIGH to Z

Delta LOW to HIGH

5.1

6.0

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

4.2

5.1

ns

5.1

6.0

ns

8.1

9.4

ns

4.0

4.7

ns

0.09

0.11

0.15

ns/pF

Delta HIGH to LOW

Dedicated (Hardwired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

3.1

3.5

3.6

4.0

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

3.8

4.4

ns

0.8

ns

Minimum Period

7.6

8.9

ns

f_HMAX

Maximum Frequency

130

110

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

4.4

4.9

5.3

5.1

5.3

5.6

6.0

6.3

6.0

6.3

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

5.6

6.7

ns

t_RPWL

t_RCKSW

1.1

1.5

1.7

Note: *Delays based on 35 pF loading, except for t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5 pF.

v2.1

1-23

SX Family FPGAs RadTolerant and HiRel

A54SX32 Timing Characteristics

Table 1-15 • A54SX32 Timing Characteristics

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.9

1.0

ns

Predicted Routing Delays²

t_DC

FO = 1 Routing Delay, Direct Connect

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.1

0.6

0.7

1.2

1.7

2.2

4.3

5.6

9.4

12.4

0.1

0.7

ns

t_FC

t_RD1

0.8

t_RD2

FO = 2 Routing Delay

1.4

t_RD3

FO = 3 Routing Delay

2.0

t_RD4

FO = 4 Routing Delay

2.6

t_RD8

FO = 8 Routing Delay

5.0

t_RD12

t_RD18

t_RD24

R-Cell Timing

t_RCO

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

6.6

11.0

14.6

Sequential Clock-to-Q

0.6

0.8

ns

t_CLR

Asynchronous Clear-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_SUD

0.8

0.0

2.4

0.9

0.0

2.9

t_HD

t_WASYN

I/O Module Input Propagation Delays

t_INYH

Input Data Pad-to-Y HIGH

2.2

2.6

ns

t_INYL

Input Data Pad-to-Y LOW

Predicted Input Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

0.7

1.2

1.7

2.2

4.3

5.6

9.4

12.4

0.8

1.4

ns

t_IRD2

t_IRD3

2.0

t_IRD4

2.6

t_IRD8

5.0

t_IRD12

t_IRD18

t_IRD24

Notes:

6.6

11.0

14.6

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

1-24

v2.1

SX Family FPGAs RadTolerant and HiRel

Table 1-16 • A54SX32 Timing Characteristics

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

I/O Module – TTL Output Timing*

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to LOW

Enable-to-Pad, Z to HIGH

Enable-to-Pad, LOW to Z

Enable-to-Pad, HIGH to Z

Delta LOW to HIGH

2.8

3.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

2.3

2.8

ns

2.8

3.3

ns

4.5

5.2

ns

2.2

2.6

ns

0.05

0.06

0.08

ns/pF

Delta HIGH to LOW

Dedicated (Hardwired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

1.7

1.9

2.0

2.2

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

2.1

2.4

ns

0.4

ns

Minimum Period

4.2

4.8

ns

f_HMAX

Maximum Frequency

240

205

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

2.4

2.7

2.9

2.8

2.9

3.1

3.3

3.5

3.3

3.5

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

3.1

3.7

ns

t_RPWL

t_RCKSW

0.6

0.8

0.9

Note: *Delays based on 35 pF loading, except t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5 pF.

v2.1

1-25

SX Family FPGAs RadTolerant and HiRel

RT54SX32 Timing Characteristics

Table 1-17 • RT54SX32 Timing Characteristics

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

1.7

1.8

ns

Predicted Routing Delays²

t_DC

FO = 1 Routing Delay, Direct Connect

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.2

1.1

0.2

1.3

ns

t_FC

t_RD1

1.3

1.5

t_RD2

FO = 2 Routing Delay

2.2

2.6

t_RD3

FO = 3 Routing Delay

3.1

3.6

t_RD4

FO = 4 Routing Delay

4.0

4.7

t_RD8

FO = 8 Routing Delay

7.8

9.0

t_RD12

t_RD18

t_RD24

R-Cell Timing

t_RCO

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

10.1

17.0

22.4

11.9

19.8

26.3

Sequential Clock-to-Q

1.5

2.0

ns

t_CLR

Asynchronous Clear-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

t_SUD

2.0

0.0

4.4

2.2

0.0

5.3

t_HD

t_WASYN

I/O Module Input Propagation Delays

t_INYH

Input Data Pad-to-Y HIGH

4.0

4.7

ns

t_INYL

Input Data Pad-to-Y LOW

Predicted Input Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

FO = 18 Routing Delay

FO = 24 Routing Delay

1.3

2.2

1.5

2.6

ns

t_IRD2

t_IRD3

3.1

3.6

t_IRD4

4.0

4.7

t_IRD8

7.8

9.0

t_IRD12

t_IRD18

t_IRD24

Notes:

10.1

17.0

22.4

11.9

19.8

26.3

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

1-26

v2.1

SX Family FPGAs RadTolerant and HiRel

Table 1-18 • RT54SX32 Timing Characteristics

(Worst-Case Military Conditions, V_CCR= 4.75 V, V_CCA, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

I/O Module – TTL Output Timing*

t_DLH

Data-to-Pad LOW to HIGH

Data-to-Pad HIGH to LOW

Enable-to-Pad, Z to LOW

Enable-to-Pad, Z to HIGH

Enable-to-Pad, LOW to Z

Enable-to-Pad, HIGH to Z

Delta LOW to HIGH

5.1

6.0

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

d_THL

4.2

5.1

ns

5.1

6.0

ns

8.1

9.4

ns

4.0

4.7

ns

0.09

0.11

0.15

ns/pF

Delta HIGH to LOW

Dedicated (Hardwired) Array Clock Network

t_HCKH

Input LOW to HIGH

(Pad to R-Cell Input)

3.1

3.5

3.6

4.0

ns

t_HCKL

Input HIGH to LOW

(Pad to R-Cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

3.8

4.4

ns

0.8

ns

Minimum Period

7.6

8.9

ns

f_HMAX

Maximum Frequency

130

110

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input LOW to HIGH (Light Load)

(Pad to R-Cell Input)

4.4

4.9

5.3

5.1

5.3

5.6

6.0

6.3

6.0

6.3

ns

Input HIGH to LOW (Light Load)

(Pad to R-Cell Input)

Input LOW to HIGH (50% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (50% Load)

(Pad to R-Cell Input)

Input LOW to HIGH (100% Load)

(Pad to R-Cell Input)

Input HIGH to LOW (100% Load)

(Pad to R-Cell Input)

t_RPWH

t_RPWL

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

5.6

6.7

ns

Note: *Delays based on 35 pF loading, except t_ENZLand t_ENZH. For t_ENZLand t_ENZHthe loading is 5 pF.

v2.1

1-27

SX Family FPGAs RadTolerant and HiRel

Pin Description

CLKA/B

Clock A and B

TDI, I/O

Test Data Input

These pins are clock inputs for clock distribution

networks. Input levels are compatible with standard TTL,

LVTTL, 3.3 V PCI, or 5.0 V PCI specifications. The clock

input is buffered prior to clocking the R-cells. If not used,

this pin must be set LOW or HIGH on the board. It must

not be left floating. (For RT54SX72S, these clocks can be

configured as user I/O.)

Serial input for boundary scan testing and diagnostic

probe. In flexible mode, TDI is active when the TMS pin is

set LOW (refer to Table 1-2 on page 1-8). This pin

functions as an I/O when the boundary scan state

machine reaches the “logic reset” state.

TDO, I/O

Test Data Output

Serial output for boundary scan testing. In flexible mode,

TDO is active when the TMS pin is set LOW (refer to

Table 1-2 on page 1-8). This pin functions as an I/O when

the boundary scan state machine reaches the “logic

reset” state.

GND

Ground

LOW supply voltage.

HCLK

Dedicated (Hardwired) Array Clock

This pin is the clock input for sequential modules. Input

levels are compatible with standard TTL, LVTTL, 3.3 V PCI

or 5.0 V PCI specifications. This input is directly wired to

each R-cell and offers clock speeds independent of the

number of R-cells being driven. If not used, this pin must

be set LOW or HIGH on the board. It must not be left

floating.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1

boundary scan pins (TCK, TDI, TDO, TRST). In flexible

mode, when the TMS pin is set LOW, the TCK, TDI, and

TDO pins are boundary scan pins (refer to Table 1-2 on

page 1-8). Once the boundary scan pins are in test mode,

they will remain in that mode until the internal

boundary scan state machine reaches the "logic reset"

state. At this point, the boundary scan pins will be

released and will function as regular I/O pins. The "logic

reset" state is reached five TCK cycles after the TMS pin is

set HIGH. In dedicated test mode, TMS functions as

specified in the IEEE 1149.1 specifications.

I/O

Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Based on certain configurations,

input and output levels are compatible with standard TTL,

LVTTL, 3.3 V PCI, or 5.0 V PCI specifications. Unused I/O

pins are automatically tristated by the Designer software.

NC

No Connection

TRST, I/O

Boundary Scan Reset Pin

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

Once it is configured as the JTAG Reset pin, the TRST pin

functions as an active-low input to asynchronously

initialize or reset the boundary scan circuit. The TRST pin

is equipped with an internal pull-up resistor. This pin

functions as an I/O when the Reserve JTAG Reset Pin

check box is cleared in Designer.

PRA, I/O,

Probe A/B PRB, I/O

The Probe pin is used to output data from any user-

defined design node within the device. This independent

diagnostic pin can be used in conjunction with the other

probe pin to allow real-time diagnostic output of any

signal path within the device. The Probe pin can be used

as a user-defined I/O when verification has been

completed. The pin’s probe capabilities can be

permanently disabled to protect programmed design

confidentiality.

V

Supply Voltage

CCI

Supply voltage for I/Os. See Table 1-1 on page 1-8.

V

Supply Voltage

CCA

Supply voltage for Array. See Table 1-1 on page 1-8.

V

Supply Voltage

CCR

Supply voltage for input tolerance (required for internal

biasing). See Table 1-1 on page 1-8.

TCK, I/O

Test Clock (Input)

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active

when the TMS pin is set LOW (see Table 1-2 on page 1-8).

This pin functions as an I/O when the JTAG state machine

reaches the "logic reset" state.

1-28

v2.1

SX Family FPGAs RadTolerant and HiRel

Package Pin Assignments

208-Pin CQFP

208 207 206 205 204 203 202 201 200

164 163 162 161 160 159 158 157

Pin #1

Index

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

208-Pin

CQFP

44

45

46

47

48

49

50

51

52

113

112

111

110

109

108

107

106

105

53 54 55 56 57 58 59 60 61

97 98 99 100 101 102 103 104

Figure 2-1 • 208-Pin CQFP (Top View)

v2.1

2-1

SX Family FPGAs RadTolerant and HiRel

208-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

NC

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

NC

I/O

2

3

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

V_CCR

GND

V_CCA

GND

I/O

V_CCR

GND

V_CCA

GND

I/O

V_CCR

GND

V_CCA

GND

I/O

V_CCR

GND

V_CCA

GND

I/O

TRST

I/O

TRST

I/O

Notes:

1. Pin 30 in RT54SX16 and RT54SX32-CQ208 is a TRST pin.

2. Pin 65 in A54SX32 and RT54SX32-CQ208 is a No Connect.

2-2

v2.1

SX Family FPGAs RadTolerant and HiRel

208-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

73

74

I/O

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

I/O

75

I/O

76

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

PRB, I/O

GND

V_CCA

GND

V_CCR

I/O

77

I/O

78

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

79

80

81

I/O

82

HCLK

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

I/O

89

I/O

90

I/O

91

I/O

92

I/O

93

I/O

GND

V_CCA

GND

V_CCR

I/O

GND

V_CCA

GND

V_CCR

I/O

GND

V_CCA

GND

V_CCR

I/O

GND

V_CCA

GND

V_CCR

I/O

94

I/O

95

I/O

96

I/O

97

I/O

98

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

99

I/O

100

101

102

103

104

105

106

107

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

108

I/O

Notes:

1. Pin 30 in RT54SX16 and RT54SX32-CQ208 is a TRST pin.

2. Pin 65 in A54SX32 and RT54SX32-CQ208 is a No Connect.

v2.1

2-3

SX Family FPGAs RadTolerant and HiRel

208-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

CLKB

V_CCR

GND

V_CCA

GND

PRA, I/O

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TCK, I/O

I/O

180

Notes:

CLKA

1. Pin 30 in RT54SX16 and RT54SX32-CQ208 is a TRST pin.

2. Pin 65 in A54SX32 and RT54SX32-CQ208 is a No Connect.

2-4

v2.1

SX Family FPGAs RadTolerant and HiRel

256-Pin CQFP

256 255 254 253 252 251 250 249 248

200 199 198 197 196 195 194 193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121 122 123 124 125 126 127 128

Figure 2-2 • 256-Pin CQFP (Top View)

v2.1

2-5

SX Family FPGAs RadTolerant and HiRel

256-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

I/O

NC

I/O

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

I/O

GND

I/O

V_CCA

I/O

GND

I/O

2

3

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

I/O

TMS

NC

I/O

TMS

NC

I/O

TMS

I/O

TMS

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

GND

V_CCA

GND

NC

I/O

V_CCI

GND

V_CCA

GND

NC

I/O

V_CCI

GND

V_CCA

GND

I/O

V_CCI

GND

V_CCA

GND

I/O

TRST

I/O

TRST

I/O

NC

I/O

NC

I/O

Note: Pin 34 in RT54SX16 and RT54SX32-CQ256 is a TRST pin.

2-6

v2.1

SX Family FPGAs RadTolerant and HiRel

256-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

75

76

I/O

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

I/O

77

NC

I/O

NC

I/O

NC

I/O

NC

I/O

78

I/O

79

I/O

80

I/O

81

I/O

NC

I/O

NC

I/O

82

I/O

83

I/O

84

I/O

85

I/O

NC

I/O

NC

I/O

86

I/O

87

I/O

88

I/O

NC

TDO, I/O

NC

GND

I/O

NC

TDO, I/O

NC

GND

I/O

89

I/O

TDO, I/O

I/O

TDO, I/O

I/O

90

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

91

GND

I/O

GND

I/O

92

93

I/O

94

I/O

95

I/O

96

HCLK

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

97

I/O

98

NC

I/O

NC

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

I/O

NC

V_CCA

I/O

NC

V_CCA

I/O

NC

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

Note: Pin 34 in RT54SX16 and RT54SX32-CQ256 is a TRST pin.

v2.1

2-7

SX Family FPGAs RadTolerant and HiRel

256-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

I/O

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

NC

GND

V_CCR

GND

V_CCI

I/O

NC

GND

V_CCR

GND

V_CCI

I/O

GND

V_CCR

GND

V_CCI

I/O

GND

V_CCR

GND

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

CLKA

CLKB

V_CCI

GND

CLKA

CLKB

V_CCI

GND

CLKA

CLKB

V_CCI

GND

CLKA

CLKB

V_CCI

GND

I/O

NC

I/O

NC

I/O

Note: Pin 34 in RT54SX16 and RT54SX32-CQ256 is a TRST pin.

2-8

v2.1

SX Family FPGAs RadTolerant and HiRel

256-Pin CQFP

A54SX16 RT54SX16 A54SX32 RT54SX32

Number Function Function Function Function

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

V_CCR

GND

PRA, I/O

I/O

V_CCR

GND

PRA, I/O

I/O

V_CCR

GND

PRA, I/O

I/O

V_CCR

GND

PRA, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

TCK, I/O

Note: Pin 34 in RT54SX16 and RT54SX32-CQ256 is a TRST pin.

v2.1

2-9

SX Family FPGAs RadTolerant and HiRel

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v2.1)

Page

v2.0

The "Product Profile" was updated.

The "Ordering Information" was updated.

The "Product Plan" was updated.

Table 1-1 was updated.

i

ii

8

Preliminary v1.5

Power-up and -down sequencing information was modified: damage to the device is possible when 13

3.3 V is powered-up first and when 5.0 V is powered-down first.

The last line of EQ 1-4 was cut off in the previous version. It has been replaced in the existing version.

The User I/Os changed.

16

8

Preliminary v1.5.2

The following sections are new or were updated: "Clock Resources", "Performance", "I/O Modules", 7

"Power Requirements", "Boundary Scan Testing (BST)","Configuring Diagnostic Pins", "TRST Pin", 11

"Dedicated Test Mode", "Flexible Mode", "Development Tool Support", "RTSX Probe Circuit Control

Pins", and "Design Considerations".

to

The "Pin Description" has been updated.

28

Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated from the N/A

data sheet. The mechanical drawings are now contained in a separate document, Package Characteristics

and Mechanical Drawings, available on the Actel web site.

v2.1

3-1

SX Family FPGAs RadTolerant and HiRel

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Export Administration Regulations (EAR)

The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require

an approved export license prior to export from the United States. An export includes release of product or disclosure

of technology to a foreign national inside or outside the United States.

3-2

v2.1

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

www.jp.actel.com

Actel Hong Kong

www.actel.com.cn

2061 Stierlin Court

Mountain View, CA

94043-4655 USA

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Suite 2114, Two Pacific Place

88 Queensway, Admiralty

Hong Kong

Phone 650.318.4200

Fax 650.318.4600

Phone +44 (0) 1276 401 450

Fax +44 (0) 1276 401 490

Phone +81.03.3445.7671

Fax +81.03.3445.7668

Phone +852 2185 6460

Fax +852 2185 6488

5172141-8/3.05


型号：	RT54SX16-1CG256B
厂家：	Actel Corporation
描述：	SX Family FPGAs RadTolerant and HiRel SX系列FPGA RadTolerant和HiRel它
文件：	总46页 (文件大小：393K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT54SX16-1CG256B [ACTEL]

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