ACT8798_09 [ACTIVE-SEMI]
Six Channel Integrated Power Management IC for Handheld Portable Equipment; 六通道集成电源管理IC，适用于手持便携式设备
| 型号： | ACT8798_09 |
| 厂家： | 
ACTIVE-SEMI, INC |
| 描述： | Six Channel Integrated Power Management IC for Handheld Portable Equipment |
| 文件： | 总34页 (文件大小：613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT8798
Rev 1, 16-Nov-09
Six Channel Integrated Power Management IC
for Handheld Portable Equipment
FEATURES
• Multiple Patents Pending
• Six Integrated Regulators
− 1.2A PWM Step-Down DC/DC
− 1.2A PWM Step-Down DC/DC
− 750mA PWM Step-Down DC/DC
− 250mA Low Noise LDO
− 250mA Low Noise LDO
− 250mA Low Noise LDO
• I2CTM Compatible Serial Interface
− Programmable Output Voltages
− Configurable Operating Modes
GENERAL DESCRIPTION
The patent-pending ACT8798 is a complete, cost-
effective, highly-efficient ActivePMUTM power
management solution that is ideal for a wide range
of portable handheld equipment. This device
integrates three step-down DC/DC converters and
three low dropout linear regulators (LDOs) into a
single, thin, space-saving package. An I2C Serial
Interface provides programmability for the DC/DC
converters and LDOs.
REG1, REG2 and REG3 are fixed-frequency,
current-mode PWM step-down DC/DC converters
that are optimized for high efficiency and are
capable of supplying up to 1.2A, 1.2A and 750mA,
respectively. REG4, REG5 and REG6 are low
noise, high PSRR linear regulators that are capable
• Minimal External Components
• 4x4mm, Thin-QFN (TQFN44-24) Package
− Only 0.75mm Height
of supplying up to 250mA each.
− RoHS Compliant
The ACT8798 is available in a tiny 4mm × 4mm 24-
pin Thin-QFN package that is just 0.75mm thin.
APPLICATIONS
• Portable Devices and PDAs
• Wireless Handhelds
• DMB Enabled Devices
• GPS Receivers, etc.
SYSTEM BLOCK DIAGRAM
OUT2
1.1V to 4.4V
Up to 1.2A
REG2
Step-Down
DC/DC
Battery
nMSTR
nRSTO
OUT3
1.1V to 4.4V
Up to 750mA
REG3
Step-Down
DC/DC
PWRHLD
ON3
System
Control
SCL
OUT4
0.645V to 3.7V
Up to 250mA
REG4
LDO
SDA
Pb-free
OUT1
1.1V to 4.4V
Up to 1.2A
REG1
Step-Down
DC/DC
OUT5
1.4V to 3.7V
Up to 250mA
REG5
LDO
OUT6
1.4V to 3.7V
Up to 250mA
REG6
LDO
ACT8798
TM
ActivePMU
Innovative PowerTM
- 1 -
www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
FUNCTIONAL BLOCK DIAGRAM
VP1
To Battery
ACT8798
SCL
SW1
Serial
OUT1
SDA
Interface
OUT1
GP12
VP2
To Battery
OUT2
INL
SW2
nMSTR
OUT2
GP12
PUSH
BUTTON
OUT2
VP3
To Battery
nRSTO
SW3
OUT3
GP3
OUT3
PWRHLD
ON3
System
Control
INL
To Battery
OUT4
OUT4
LDO
REG4
REFBP
Reference
OUT5
OUT6
LDO
REG5
OUT5
OUT6
GA
LDO
REG6
Innovative PowerTM
- 2 -
www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
ORDERING INFORMATIONcd
TEMPERATURE
RANGE
PART NUMBER VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 PACKAGE PINS
ACT8798QLGHW-T 3.0V
3.3V 1.35V 1.35V 2.8V 1.8V
TQFN44-24
24
-40°C to +85°C
OUTPUT VOLTAGE CODES (VOUT1 AND VOUT2
)
C
D
E
F
G
H
I
1.2V
1.5V
1.8V
2.5V
3.0V
3.3V
2.8V
c: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders.
Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order
quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations.
d: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
TOP VIEW
24
23
22
21
20
19
OUT4
SCL
1
2
3
4
5
6
18 OUT3
17 GA
SDA
16 REFBP
15 PWRHLD
14 ON3
GA
ACT8798
nMSTR
nRSTO
EP
13 OUT2
7
8
9
10
11
12
Thin - QFN (TQFN44-24)
Innovative PowerTM
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www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Output Voltage for REG4. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
1
OUT4
2
3
SCL
SDA
Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock.
Data Input for I2C Serial Interface. Data is read on the rising edge of the clock.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12, and GP3 together
at a single point as close to the IC as possible.
4, 17
GA
Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. REG1, REG2, and
REG3 are enabled while nMSTR is asserted.
5
6
7
nMSTR
nRSTO
OUT1
Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the
IC is enabled.
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
8
VP1
SW1
GP12
SW2
VP2
9
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single point as
close to the IC as possible.
10
11
12
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
13
14
15
16
18
OUT2
ON3
Enable Input for REG3, ON3 is functional only when PWRHLD is driven high. Drive ON3 to a logic
high to turn on the REG3. Drive ON3 to a logic low to turn off the REG3.
Power Hold Input. Drive PWRHLD to logic high to enable the IC. Drive PWRHLD to a logic low to
disable all regulators.
PWRHLD
REFBP
OUT3
Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is dis-
charged to GA in shutdown.
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as
possible to the IC.
19
20
21
VP3
SW3
GP3
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the IC
as possible.
Output Voltage for REG5. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
22
23
OUT5
OUT6
Output Voltage for REG6. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
Power Input for REG4, REG5 and REG6. Bypass to GA with a high quality ceramic capacitor
placed as close as possible to the IC.
24
INL
EP
EP
Exposed Pad. Must be soldered to ground on PCB.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
VP1, VP2, SW1, SW2 to GP12
VP3, SW3 to GP3
-0.3 to +6
-6 to +0.3
V
SCL, SDA, INL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, ON3, REFBP, nRSTO,
PWRHLD, nMSTR to GA
SW1 to VP1
SW2 to VP2
SW3 to VP3
V
GP12, GP3 to GA
-0.3 to +0.3
30
V
°C/W
W
Junction to Ambient Thermal Resistance (θJA)
RMS Power Dissipation (TA = 70°C)
Operating Temperature Range
Junction Temperature
1.8
-40 to 85
125
°C
°C
Storage Temperature
-55 to 150
300
°C
°C
Lead Temperature (Soldering, 10 sec)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
REGISTER DESCRIPTIONS
Table 1:
Global Register Map
ADDRESS
DATA (DEFAULT VALUE)
OUTPUT
HEX A7 A6
A5
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
A4
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
REG1
REG1
REG1
REG1
REG2
REG2
REG2
REG2
REG3
REG3
REG3
REG3
REG4
REG4
REG5
REG6
10h
11h
12h
13h
20h
21h
22h
23h
30h
31h
32h
33h
03h
40h
41h
42h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
V
R
R
R
V
R
R
R
V
R
R
R
V
R
R
R
R
V
R
R
R
V
R
R
R
V
R
R
R
V
0
V
R
R
R
V
R
R
R
V
R
R
R
V
R
V
V
1
V
R
R
R
V
R
R
R
V
R
R
R
V
R
V
V
1
V
R
R
0
V
R
R
R
V
R
R
R
V
R
R
R
V
R
V
V
0
V
0
R
1
V
R
R
0
V
0
R
1
V
R
R
0
V
0
R
1
V
R
V
V
1
V
R
V
V
R
0
0
REG456CFG 43h
R
KEY:
R: Read-Only bits. No Default Assigned.
V: Default Values Depend on Voltage Option. Default Values May Vary.
Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those
specified in Table 1.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
TYPICAL PERFORMANCE CHARACTERISTICS
(VINL = 3.6V, TA = 25°C, unless otherwise specified.)
Oscillator Frequency vs. Temperature
1.71
1.68
1.65
1.62
1.59
1.56
1.53
1.50
20
40
60
85
-40
-20
0
Temperature (°C)
Startup Sequence
CH1
CH2
CH3
CH4
CH1: VnMSTR, 5V/div
CH2: VnRSTO, 2V/div
CH3: VPWRHLD, 5V/div
CH4: VOUT1, 2V/div
TIME: 100ms/div
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
2.6
TYP
MAX UNIT
5.5
V
V
INL Voltage Rising
INL Voltage Falling
2.25
2.4
80
2.55
INL UVLO Hysteresis
mV
MHz
µA
kΩ
V
Oscillator Frequency
1.35
1.6
1.5
500
1.85
INL Supply Current
PWRHLD = ON3 = GA
nMSTR Internal Pull-Up Resistance
Logic High Input Voltage
Logic Low Input Voltage
Logic Low Output Voltage
Leakage Current
250
1.4
PWRHLD, ON3, nMSTR
PWRHLD, ON3, nMSTR
0.4
0.3
1
V
I
SINK = 5mA
V
nRSTO, VnRSTO = 4.2V
µA
ms
°C
°C
nRSTO Delay
240
300
160
20
360
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
Temperature falling
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www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
SCL, SDA Low Input Voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.4
V
V
SCL, SDA High Input Voltage
1.4
SCL, SDA Leakage Current
1
µA
V
SDA Low Output Voltage
I
OL = 5mA
0.3
SCL Clock Period, tSCL
fSCL clock freq = 400kHz
2.5
100
300
100
100
µs
ns
ns
ns
ns
SDA Data In Setup Time to SCL High, tSU
SDA Data Out Hold Time after SCL Low, tHD
SDA Data Low Setup Time to SCL Low, tST
Start Condition
SDA Data High Hold Time after Clock High, tHP Stop Condition
Figure 1:
I2C Serial Bus Timing
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Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION
Manual Enable Due to Asserting nMSTR Low
General Description
System startup is initiated when the user presses
the push-button, asserting nMSTR low. When this
occurs, REG1, REG2, REG3, and REG4 are
enabled and nRSTO is asserted low to hold the
microprocessor in RESET for 260ms. nRSTO goes
high-Z upon expiration of the reset timer, de-
asserting the processor's reset input and allowing
the microprocessor to initiate its power up
sequence. Once the power-up routine is
successfully completed, the microprocessor must
assert PWRHLD so that the ACT8798 remains
enabled after the push-button is released by the
user. Upon completion of the start-up sequence the
processor assumes control of the power system
and all further operation is software-controlled.
The ACT8798 offers an array of system
management functions that allow it to provide
optimal performance in
applications.
a
wide range of
I2C Serial Interface
At the core of the ACT8798's flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
To ensure compatibility with a wide range of system
processors, the ACT8798 uses standard I2C
commands; I2C write-byte commands are used to
program the ACT8798, and I2C read-byte
commands are used to read the ACT8798's internal
registers. The ACT8798 always operates as a slave
device, and is addressed using a 7-bit slave
address followed by an eighth bit, which indicates
whether the transaction is a read-operation or a
write-operation, [1011011x].
Manual Enable Due to Asserting PWRHLD High
The ACT8798 is compatible with applications that
do not utilize its push-button control function, and
may be enabled by simply driving PWRHLD to a
logic-high to enable REG1, REG2, and REG4. In
this case, the signal driving PWRHLD controls
enable/disable timing, although software-controlled
enable/disable sequences are still supported if the
processor assumes control of the power system
once the startup sequence is completed.
SDA is a bi-directional data line and SCL is a clock
input. The master initiates a transaction by issuing a
START condition, defined by SDA transitioning from
high to low while SCL is high. Data is transferred in
8-bit packets, beginning with the MSB, and is
clocked-in on the rising edge of SCL. Each packet
of data is followed by an Acknowledge (ACK) bit,
used to confirm that the data was transmitted
successfully.
Shutdown Sequence
Once a successful power-up routine is completed,
the system processor controls the operation of the
power system, including the system shutdown
timing and sequence. When using the application
circuits shown in Figure 2, the nIRQ signal is
asserted when nMSTR is asserted low, providing a
simple means of alerting the system processor
when the user wishes to shut the system down.
Asserting nIRQ interrupts the system processor,
initiating an interrupt service routine in the
processor which will reveal that the user pressed
the push-button. The microprocessor may validate
the input, such as by ensuring that the push-button
is asserted for a minimum amount of time, then
initiates a software controlled power-down routine,
the final step of which is to de-assert the PWRHLD
input, disabling the regulators and shutting the
system down.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com
System Startup and Shutdown
The ACT8798 features
a
flexible control
architecture that supports a variety of software-
controlled enable/disable functions that make it a
simple yet flexible and highly configurable solution.
The ACT8798 is automatically enabled when either
of the following conditions exists:
1) nMSTR is asserted low, or
2) PWRHLD is asserted high.
If either of these conditions is true, the ACT8798
enables REG1, REG2, REG4, and may be REG3,
powering up the system processor so that the
startup and shutdown sequences may be controlled
via software. These startup conditions are
described in detail below.
nMSTR Enable Input
In most applications, connect nMSTR to an active
low, momentary push-button switch to utilize the
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION (CONT’D)
ACT8798's closed-loop enable/disable functionality.
nIRQ Output
If a momentary-on switch is not used, drive nMSTR
to GA or to a logic low to initiate a startup
sequence.
Figure 2 shows two simple circuits that can be used
to generate nIRQ, a processor interrupt signal,
which can be used as part of the ACT8798’s push-
button control logic. This signal is typically used to
drive the interrupt input of the system processor,
and is useful in a variety of software-controlled
enable/disable control routines. Figure 2A provides
an active-low, open-collector push-button status
output that sinks current when nMSTR is driven to a
logic-low. Figure 2B provides an active-high, open-
collector push-button status output that sources
current when nMSTR is driven to a logic-low.
Enable/Disable Inputs
The ACT8798 provides two manual enable/disable
inputs, PWRHLD and ON3. PWRHLD is the master
enable input. When driven high, PWRHLD enables
REG1, REG2, and REG4, and also activates the
enable/disable control logic for the other regulators.
ON3 is the enable input for REG3, and is active
when either of the following conditions exists:
1) nMSTR is asserted low, or
2) PWRHLD is asserted high.
Thermal Shutdown
The ACT8798 integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8798 die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C
(typ).
Power-On Reset Output
The ACT8798 integrates a 260ms power-on reset
generator, reducing system size and cost. nRSTO
is an open-drain output. Connect a 10kꢀ or greater
pull-up resistor from nRSTO to an appropriate
voltage supply. nRSTO asserts low upon startup
and remains low until the reset-timeout period
expires, at which point nRSTO goes high-Z.
Figure 2:
Simple Circuits
nMSTR
OUT2
INL
ACT8798
VCC
100k
100k
500k
OUT2
PB
VCC
100k
nIRQ
nIRQ
100k
PB
ACT8798
CPU
(A)
(B)
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Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG1)
(VVP1 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP1 Operating Voltage Range
VP1 UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.9
3
3.1
V
VP1 UVLO Hysteresis
Input Voltage Falling
80
mV
µA
µA
Standby Supply Current
Shutdown Supply Current
130
0.1
200
1
REG1 is disabled, VVP1 = 4.2V
c
V
NOM1 < 1.3V, IOUT1 = 10mA
-2.4%
-1.2%
VNOM1
VNOM1
0.15
+1.8%
+1.8%
Output Voltage Regulation Accuracy
V
VNOM1 ≥ 1.3V, IOUT1 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V
OUT1 = 10mA to 1.2A
%/V
%/mA
A
I
0.0017
1.2
V
OUT1 ≥ 20% of VNOM1
1.35
1.6
530
0.28
0.20
1.85
MHz
kHz
ꢀ
Oscillator Frequency
VOUT1 = 0V
PMOS On-Resistance
NMOS On-Resistance
SW1 Leakage Current
Power Good Threshold
Minimum On-Time
I
SW1 = -100mA
SW1 = 100mA
0.50
0.35
1
I
ꢀ
V
VP1 = 5.5V, VSW1 = 5.5V or 0V
µA
94
70
%VNOM1
ns
c: VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section.
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 2:
REG1 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
10h
11h
12h
13h
VRANGE
VSET
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MODE
R
R
R
W/E
OK
ON
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1
Table 3:
REG1 Control Register Bit Descriptions
ADDRESS
NAME
BIT
ACCESS
FUNCTION
DESCRIPTION
See Table 4
10h
VSET
[5:0]
R/W
REG1 Output Voltage Selection
0
1
Min VOUT = 1.1V
Min VOUT = 1.25V
READ ONLY
PWM/PFM
REG1 Voltage Range
Selection
10h
10h
11h
VRANGE
MODE
[6]
[7]
[0]
R/W
R
0
1
R/W
Mode Selection
Forced PWM
READ ONLY
READ ONLY
REG1 Disable
REG1 Enable
Output is not OK
Output is OK
WRITE-EXACT
READ ONLY
11h
12h
[7:1]
[7:0]
R
R
0
1
0
1
13h
13h
ON
OK
[0]
[1]
R/W
R
REG1 Enable
REG1 Power-OK
13h
13h
[2]
W/E
R
[7:3]
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ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 4:
REG1/VSET[ ] Output Voltage Setting
REG1/VSET[5:4]
REG1/VSET[3:0]
REG1/VRANGE[ ] = [0]
REG1/VRANGE[ ] = [1]
00
01
10
11
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.455
1.480
1.505
1.530
1.555
1.585
1.610
1.635
1.660
1.685
1.710
1.735
1.760
1.785
1.810
1.835
1.860
1.890
1.915
1.940
1.965
1.990
2.015
2.040
2.065
2.090
2.115
2.140
2.165
2.190
2.200
2.245
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
N/A
1.100
1.125
1.150
1.175
1.200
1.225
1.255
1.280
1.305
1.330
1.355
1.380
1.405
1.430
(N/A): Not Available
Innovative PowerTM
- 14 -
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG2)
(VVP2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP2 Operating Voltage Range
VP2 UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.9
3
3.1
V
VP2 UVLO Hysteresis
Input Voltage Falling
80
mV
µA
µA
Standby Supply Current
Shutdown Supply Current
130
0.1
200
1
REG2 Disabled, VVP2 = 4.2V
c
V
NOM2 < 1.3V, IOUT2 = 10mA
-2.4%
-1.2%
VNOM2
VNOM2
0.15
+1.8%
+1.8%
Output Voltage Regulation Accuracy
V
VNOM2 ≥ 1.3V, IOUT2 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V
OUT2 = 10mA to 1.2A
%/V
%/mA
A
I
0.0017
1.2
VOUT2 ≥ 20% of VNOM2
OUT2 = 0V
1.35
1.6
530
0.28
0.20
1.85
MHz
kHz
ꢀ
Oscillator Frequency
V
PMOS On-Resistance
NMOS On-Resistance
SW2 Leakage Current
Power Good Threshold
Minimum On-Time
I
I
SW2 = -100mA
0.50
0.35
1
SW2 = 100mA
ꢀ
V
VP2 = 5.5V, VSW2 = 5.5V or 0V
µA
94
70
%VNOM2
ns
c: VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 5:
REG2 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
20h
21h
22h
23h
VRANGE
VSET
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MODE
R
R
R
W/E
OK
ON
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1
Table 6:
REG2 Control Register Bit Descriptions
ADDRESS
NAME
BIT
ACCESS
FUNCTION
DESCRIPTION
See Table 7
20h
VSET
[5:0]
R/W
REG2 Output Voltage Selection
0
1
Min VOUT = 1.1V
Min VOUT = 1.25V
READ ONLY
PWM/PFM
REG2 Voltage Range
Selection
20h
20h
21h
VRANGE
MODE
[6]
[7]
[0]
R/W
R
0
1
R/W
Mode Selection
Forced PWM
READ ONLY
READ ONLY
REG2 Disable
REG2 Enable
Output is not OK
Output is OK
WRITE-EXACT
READ ONLY
21h
22h
[7:1]
[7:0]
R
R
0
1
0
1
23h
23h
ON
OK
[0]
[1]
R/W
R
REG2 Enable
REG2 Power-OK
23h
23h
[2]
W/E
R
[7:3]
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 7:
REG2/VSET[ ] Output Voltage Setting
REG2/VSET[5:4]
REG2/VSET[3:0]
REG2/VRANGE[ ] = [0]
REG2/VRANGE[ ] = [1]
00
01
10
11
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.455
1.480
1.505
1.530
1.555
1.585
1.610
1.635
1.660
1.685
1.710
1.735
1.760
1.785
1.810
1.835
1.860
1.890
1.915
1.940
1.965
1.990
2.015
2.040
2.065
2.090
2.115
2.140
2.165
2.190
2.200
2.245
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
N/A
1.100
1.125
1.150
1.175
1.200
1.225
1.255
1.280
1.305
1.330
1.355
1.380
1.405
1.430
(N/A): Not Available
Innovative PowerTM
- 17 -
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG3)
(VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP3 Operating Voltage Range
VP3 UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.9
3
3.1
V
VP3 UVLO Hysteresis
Input Voltage Falling
80
mV
µA
µA
Standby Supply Current
Shutdown Supply Current
130
0.1
200
1
REG3 Disabled, VVP3 = 4.2V
c
V
NOM3 < 1.3V, IOUT3 = 10mA
-2.4%
-1.2%
VNOM3
VNOM3
0.15
0.0017
1.1
+1.8%
+1.8%
Output Voltage Regulation Accuracy
V
VNOM3 ≥ 1.3V, IOUT3 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP3 = Max(VNOM3 + 1V, 3.2V) to 5.5V
OUT3 = 10mA to 750mA
%/V
%/mA
A
I
0.85
1.35
VOUT3 ≥ 20% of VNOM3
1.6
1.85
MHz
kHz
ꢀ
Oscillator Frequency
V
OUT3 = 0V
530
PMOS On-Resistance
NMOS On-Resistance
SW3 Leakage Current
Power Good Threshold
Minimum On-Time
I
SW3 = -100mA
SW3 = 100mA
0.28
0.20
0.50
0.35
1
I
ꢀ
V
VP3 = 5.5V, VSW3 = 5.5V or 0V
µA
94
70
%VNOM3
ns
c: VNOM3 refers to the nominal output voltage level for VOUT3 as defined by the Ordering Information section.
Innovative PowerTM
- 18 -
www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 8:
REG3 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
30h
31h
32h
33h
VRANGE
VSET
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MODE
R
R
R
W/E
OK
ON
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1
Table 9:
REG3 Control Register Bit Descriptions
ADDRESS
NAME
BIT
ACCESS
FUNCTION
DESCRIPTION
See Table 10
Min VOUT = 1.1V
Min VOUT = 1.25V
READ ONLY
PWM/PFM
30h
VSET
[5:0]
R/W
REG3 Output Voltage Selection
0
1
REG3 Voltage Range
Selection
30h
30h
31h
VRANGE
MODE
[6]
[7]
[0]
R/W
R
0
1
R/W
Mode Selection
Forced PWM
READ ONLY
READ ONLY
REG3 Disable
REG3 Enable
Output is not OK
Output is OK
31h
32h
[7:1]
[7:0]
R
R
0
1
0
1
33h
33h
ON
OK
[0]
[1]
R/W
R
REG3 Enable
REG3 Power-OK
33h
33h
[2]
W/E
R
WRITE-EXACT
READ ONLY
[7:3]
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 10:
REG3/VSET[ ] Output Voltage Setting
REG3/VSET[5:4]
REG3/VSET[3:0]
REG3/VRANGE[ ] = [0]
REG3/VRANGE[ ] = [1]
00
01
10
11
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.455
1.480
1.505
1.530
1.555
1.585
1.610
1.635
1.660
1.685
1.710
1.735
1.760
1.785
1.810
1.835
1.860
1.890
1.915
1.940
1.965
1.990
2.015
2.040
2.065
2.090
2.115
2.140
2.165
2.190
2.200
2.245
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
N/A
1.100
1.125
1.150
1.175
1.200
1.225
1.255
1.280
1.305
1.330
1.355
1.380
1.405
1.430
(N/A): Not Available
Innovative PowerTM
- 20 -
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8798QLGHW, VVP1 = VVP2 = 3.6V, L = 3.3µH, CVP1 = CVP2 = 2.2μF, COUT1 = COUT2 = 10μF, TA = 25°C, unless otherwise specified.)
REG1 Efficiency vs. Load Current
REG2 Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
VOUT1 = 3.3V
VOUT1 = 1.8V
3.6V
4.2V
3.6V
4.2V
1
10
100
1000
1
10
100
1000
Output Current (mA)
Output Current (mA)
OUT1 Regulation Voltage
OUT2 Regulation Voltage
0.545
0.363
0.181
0.000
-0.181
0.545
0.363
0.181
0.000
-0.181
-0.363
-0.545
IOUT1 = 35mA
IOUT2 = 35mA
-0.363
-0.545
85
-40
-20
0
20
40
60
-40
-20
0
20
40
60
85
Temperature (°C)
Temperature (°C)
REG2 MOSFET Resistance
REG1 MOSFET Resistance
500
400
500
400
PMOS
NMOS
PMOS
NMOS
300
200
100
0
300
200
100
0
3
3.5
4.0
4.5
5.0
5.5
3
3.5
4.0
4.5
5.0
5.5
VP2 Voltage (V)
VP1 Voltage (V)
Innovative PowerTM
- 21 -
www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8798QLGHW, VVP1 = VVP2 = VVP3 = 3.6V, L = 3.3µH, CVP1 = CVP2 = CVP3 = 2.2μF, COUT1 = COUT2 = COUT3 = 10μF, TA = 25°C, unless
otherwise specified.)
REG3 Efficiency vs. Load Current
95
VOUT3 = 1.8V
3.6V
90
85
80
75
70
60
4.2V
65
55
50
10
100
1
1000
Output Current (mA)
OUT3 Regulation Voltage
0.666
0.444
0.222
0.0
IOUT3 = 35mA
-0.222
-0.444
-0.666
-40
-20
0
20
40
60
85
Temperature (°C)
REG3 MOSFET Resistance
500
450
400
350
300
250
200
150
100
PMOS
NMOS
50
0
3
3.5
4.0
4.5
5.0
5.5
VP3 Voltage (V)
Innovative PowerTM
- 22 -
www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
FUNCTIONAL DESCRIPTION
Programming the Output Voltage
General Description
By default, REG1, REG2, and REG3 each power
up and regulate to their default output voltage.
Once the system is enabled, each regulator's output
voltage may be independently programmed to a
different value, typically in order to reduce the
power consumption of a microprocessor in standby
mode. Program the output voltages via the I2C
serial interface by writing to the REGx/VSETx[ ] and
REGx/VRANGE[ ] registers.
REG1, REG2, and REG3 are fixed-frequency,
current-mode, synchronous PWM step down
converters that achieve peak efficiencies of up to
97%. REG1 and REG2 are capable of supplying up
to 1.2A of output current, while REG3 supports up
to 750mA. These regulators operate with a fixed
frequency of 1.6MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. Each of the step-down DC/DCs are
available with a variety of standard and custom
output voltages, and each may be software-
controlled via the I2C interface by systems that
require advanced power management functions.
Programmable Operating Mode
By default, REG1, REG2, and REG3 each operate
in fixed-frequency PWM mode at medium to heavy
loads, then transition to a proprietary power-saving
mode at light loads in order to save power. In
applications where low noise is critical, force fixed-
frequency PWM operation across the entire load
current range, at the expense of light-load
efficiency, by setting the REGx/MODE[ ] bit to [1].
100% Duty Cycle Operation
REG1, REG2, and REG3 are each capable of
operating at up to 100% duty cycle. During 100%
duty-cycle operation, the high-side power MOSFET
is held on continuously, providing
a
direct
connection from the input to the output (through the
inductor), ensuring the lowest possible dropout
voltage in battery powered applications.
Power-OK
REG1, REG2, and REG3 each feature a variety of
status bits that can be read by the system
microprocessor. If either output voltage is lower
than the power-OK threshold, typically 6% below
the programmed regulation voltage, REGx/OK[ ] will
clear to 0.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated n-
channel synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Soft-Start
REG1, REG2, and REG3 each include matched
soft-start circuitry. When enabled, the output
voltages track the internal 80µs soft-start ramp and
both power up in a monotonic manner that is
independent of loading on either output. This
circuitry ensures that each output powers up in a
controlled manner, greatly simplifying power
sequencing design considerations.
Enabling and Disabling REG1, REG2,
and REG3
Enable/disable functionality is typically implemented
as part of a controlled enable/disable scheme
utilizing nMSTR and other system control features
of the ACT8798. REG1 and REG2 are
automatically enabled whenever either of the
following conditions re met:
Compensation
1) nMSTR is driven low, or
REG1, REG2, and REG3 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. No
compensation design is required; simply follow a
few simple guidelines described below when
choosing external components.
2) PWRHLD is asserted high.
When none of these conditions are true, or if a
regulator’s ON[_] bit is set to [0], REG1 and REG2
are disabled, and each regulator’s quiescent supply
current drops to less than 1µA.
REG3 is enabled whenever ON3 is asserted high,
and is disabled whenever ON is asserted low or if
the REG3/ON[_] bit is set to [0].
Innovative PowerTM
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www.active-semi.com
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
STEP-DOWN DC/DC CONVERTERS
FUNCTIONAL DESCRIPTION (CONT’D)
noise injection. Finally, the exposed pad should be
directly connected to the backside ground plane
using multiple via to achieve low electrical and
thermal resistance.
Input Capacitor Selection
The input capacitor reduces peak currents and
noise induced upon the voltage source. A 2.2µF
ceramic capacitor for each of REG1, REG2, and
REG3 is recommended for most applications.
Output Capacitor Selection
For most applications, 10µF ceramic output
capacitors are recommended for REG1, REG2, and
REG3. Although the these regulators were
designed to take advantage of the benefits of
ceramic capacitors, namely small size and very-low
ESR, low-ESR tantalum capacitors can provide
acceptable results as well.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. These
devices were optimized for operation with 3.3µH
inductors, although inductors in the 2.2µH to 4.7µH
range can be used. Choose an inductor with a low
DC-resistance, and avoid inductor saturation by
choosing inductors with DC ratings that exceed the
maximum output current of the application by at
least 30%.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-
down DC/DC converter design. A good design
minimizes excessive EMI on the feedback paths
and voltage gradients in the ground plane, both of
which can result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor,
and output filter capacitor should be connected as
close together as possible, with short, direct, and
wide traces. The ground nodes for each regulator's
power loop should be connected at a single point in
a star-ground configuration, and this point should
be connected to the backside ground plane with
multiple via. The output node for each regulator
should be connected to its corresponding OUTx pin
through the shortest possible route, while keeping
sufficient distance from switching nodes to prevent
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
ELECTRICAL CHARACTERISTICS (REG4)
(VINL = 3.6V, COUT4 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX UNIT
5.5
3.1
V
V
V
V
V
V
V
V
INL Input Rising
2.9
3
UVLO Hysteresis
INL Input Falling
0.1
c
NOM4 < 1.3V, IOUT4 = 10mA
NOM4 ≥ 1.3V, IOUT4 = 10mA
INL = Max(VOUT4 + 0.5V, 3.6V) to 5.5V
-2.4% VNOM4
+1.8%
+1.8%
Output Voltage Accuracy
V
-1.2%
VNOM4
Line Regulation Error
Load Regulation Error
0
-0.07
60
mV
I
OUT4 = 1mA to 250mA
mV/mA
f = 1kHz, IOUT4 = 250mA, COUT4 = 1µF
f = 10kHz, IOUT4 = 250mA, COUT4 = 1µF
Regulator Enabled
Power Supply Rejection Ratio
dB
50
40
Supply Current Per Output
µA
mV
mA
Regulator Disabled
0
Dropout Voltaged
IOUT4 = 120mA, VOUT4 > 3.1V
100
200
250
Output Current
Current Limit3
VOUT4 = 95% of regulation voltage
280
Internal Soft-Start
100
89
µs
%
Power Good Flag High Threshold
Output Noise
V
OUT4, hysteresis = -4%
OUT4 = 10µF, f = 10Hz to 100kHz
C
40
µVRMS
µF
Stable COUT4 Range
Discharge Resistor in Shutdown
1
20
LDO Disabled, DIS4[ ] = [1]
650
ꢀ
c: VNOM4 refers to the nominal output voltage level for VOUT4 as defined by the Ordering Information section.
d: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Un-
der heavy overload conditions the output current limit folds back by 30% (typ)
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
ELECTRICAL CHARACTERISTICS (REG5)
(VINL = 3.6V, COUT5 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX UNIT
5.5
3.1
V
V
V
V
INL Input Rising
INL Input Falling
2.9
3
UVLO Hysteresis
V
0.1
c
TA = 25°C
-1.2
-2.5
VNOM5
VNOM5
0
+2
+3
Output Voltage Accuracy
%
TA = -40°C to 85°C
Line Regulation Error
Load Regulation Error
VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V
mV
I
OUT5 = 1mA to 250mA
-0.07
70
mV/mA
f = 1kHz, IOUT5 = 250mA, COUT5 = 1µF
f = 10kHz, IOUT5 = 250mA, COUT5 = 1µF
Regulator Enabled
Power Supply Rejection Ratio
dB
µA
60
40
Supply Current Per Output
Regulator Disabled
0
Dropout Voltaged
IOUT5 = 120mA, VOUT5 > 3.1V
100
200
250
mV
mA
mA
µs
Output Current
Current Limit3
VOUT5 = 95% of regulation voltage
280
Internal Soft-Start
100
89
Power Good Flag High Threshold
Output Noise
V
OUT5, hysteresis = -4%
OUT5 = 10µF, f = 10Hz to 100kHz
%
C
40
µVRMS
µF
Stable COUT5 Range
Discharge Resistor in Shutdown
1
20
LDO Disabled, DIS5[ ] = [1]
650
ꢀ
c: VNOM5 refers to the nominal output voltage level for VOUT5 as defined by the Ordering Information section.
d: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Un-
der heavy overload conditions the output current limit folds back by 30% (typ)
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
ELECTRICAL CHARACTERISTICS (REG6)
(VINL = 3.6V, COUT6 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
3.1
TYP
MAX UNIT
5.5
3.1
V
V
V
V
INL Input Rising
INL Input Falling
2.9
3
UVLO Hysteresis
V
0.1
c
TA = 25°C
-1.2
-2.5
VNOM6
VNOM6
0
+2
+3
Output Voltage Accuracy
%
TA = -40°C to 85°C
Line Regulation Error
Load Regulation Error
VINL = Max(VOUT6 + 0.5V, 3.6V) to 5.5V
mV
I
OUT6 = 1mA to 250mA
-0.07
70
mV/mA
f = 1kHz, IOUT6 = 250mA, COUT6 = 1µF
f = 10kHz, IOUT6 = 250mA, COUT6 = 1µF
Regulator Enabled
Power Supply Rejection Ratio
dB
µA
60
40
Supply Current Per Output
Regulator Disabled
0
Dropout Voltaged
IOUT6 = 120mA, VOUT6 > 3.1V
100
200
250
mV
mA
mA
µs
Output Current
Current Limit3
VOUT6 = 95% of regulation voltage
280
Internal Soft-Start
100
89
Power Good Flag High Threshold
Output Noise
V
OUT6, hysteresis = -4%
OUT6 = 10µF, f = 10Hz to 100kHz
%
C
40
µVRMS
µF
Stable COUT6 Range
Discharge Resistor in Shutdown
1
20
LDO Disabled, DIS6[ ] = [1]
650
ꢀ
c: VNOM6 refers to the nominal output voltage level for VOUT6 as defined by the Ordering Information section.
d: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Un-
der heavy overload conditions the output current limit folds back by 30% (typ)
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I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 11:
Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
03h
40h
41h
42h
43h
VRANGE
VSET4
R
R
R
W/E
ON5
ON6
OK4
R
R
R
R
R
R
VSET5
VSET6
DIS4
R
R
OK6
OK5
DIS6
DIS5
W/E
R
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 12:
REG56 Control Register Bit Descriptions
ADDRESS
NAME
BIT ACCESS
FUNCTION
DESCRIPTION
REG4 Output Voltage
Selection
03h
VSET4
[5:0]
[6]
R/W
R/W
See Table 14
0
1
Min VOUT = 0.645V
Min VOUT = 1.25V
READ ONLY
REG4 Output Voltage
Selection
03h
VRANGE
03h
40h
40h
40h
[7]
[4:0]
[5]
R
R
READ ONLY
WRITE-EXACT
READ ONLY
W/E
R
[7:6]
REG5 Output Voltage
Selection
41h
41h
VSET5
ON5
[4:0]
[5]
R/W
R/W
See Table 13
0
1
REG5 Disable
REG5 Enable
READ ONLY
REG5 Enable
41h
42h
[7:6]
[4:0]
R
REG6 Output Voltage
Selection
VSET6
ON6
R/W
See Table 13
0
1
REG6 Disable
REG6 Enable
READ ONLY
42h
[5]
R/W
REG6 Enable
42h
43h
43h
[7:6]
[0]
R
R
READ ONLY
[1]
W/E
WRITE-EXACT
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Copyright © 2009 Active-Semi, Inc.
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
REGISTER DESCRIPTIONS CONT’D
Table 12:
Control Register Bit Descriptions (Cont’d)
ADDRESS
NAME
BIT
ACCESS
FUNCTION
DESCRIPTION
Discharge Disable
Discharge Enable
Discharge Disable
Discharge Enable
Discharge Disable
Discharge Enable
Output is not OK
Output is OK
0
1
0
1
0
1
0
1
0
1
0
1
43h
DIS4
[2]
R/W
REG4 Discharge Enable
43h
43h
43h
43h
43h
DIS5
DIS6
OK4
OK5
OK6
[3]
[4]
[5]
[6]
[7]
R/W
R/W
R
REG5 Discharge Enable
REG6 Discharge Enable
REG4 Power-OK
Output is not OK
Output is OK
R
REG5 Power-OK
Output is not OK
Output is OK
R
REG6 Power-OK
Table 13:
REG56/VSETx[ ] Output Voltage Setting
REG56CFG/VSETx[4:3]
REG56CFG/VSETx[2:0]
00
01
10
11
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
000
001
010
011
100
101
110
111
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
REGISTER DESCRIPTIONS CONT’D
Table 14:
REG4/VRANGE[ ] Output Voltage Setting
REG4/VSET[5:4]
REG4/VSET[3:0]
REG4/VRANGE[ ] = [0]
REG4/VRANGE[ ] = [1]
00
01
10
11
00
01
10
11
3.650
3.700
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.645
0.670
0.695
0.720
0.745
0.770
0.795
0.820
0.845
0.870
0.895
0.920
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.255
1.280
1.305
1.330
1.355
1.380
1.405
1.430
1.455
1.480
1.505
1.530
1.555
1.585
1.610
1.635
1.660
1.685
1.710
1.735
1.760
1.785
1.810
1.835
1.860
1.890
1.915
1.940
1.965
1.990
2.015
2.040
2.065
2.090
2.115
2.140
2.165
2.190
2.200
2.245
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
(N/A): Not Available
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Copyright © 2009 Active-Semi, Inc.
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8798QLGHW, VVIN = 5V, TA = 25°C, unless otherwise specified.)
Dropout Voltage vs. Output Current
Load Regulation
0.5
0.4
0.3
200
180
160
140
120
100
80
VIN = 3.1V
0.2
0.1
VIN = 3.3V
0.0
VIN = 3.6V
-0.1
-0.2
-0.3
60
40
-0.4
-0.5
20
0
0
25 50 75 100 125 150 175 200 225 250
0
50
150
200
100
250
Load Current (mA)
Output Current (mA)
Output Voltage Deviation vs. Temperature
LDO Output Voltage Noise
0.5
0.4
0.3
0.2
0.1
0.0
ILOAD = 0mA
CH1
-0.1
-0.2
-0.3
CREF = 10nF
-0.4
-0.5
-40
-15
10
35
60
85
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
Temperature (°C)
Region of Stable COUT ESR vs. Output Current
1
0.1
Stable ESR
0.01
0
50
100
150
200
250
Output Current (mA)
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
FUNCTIONAL DESCRIPTION
Reference Bypass Pin
The ACT8798 contains a reference bypass pin
which filters noise from the reference, providing a
low noise voltage reference to the LDOs. Bypass
REF to G with a 0.01µF ceramic capacitor.
General Description
REG4, REG5, and REG6 are low-noise, low-
dropout linear regulators (LDOs) that are optimized
for low noise and high-PSRR operation, achieving
more than 60dB PSRR at frequencies up to 10kHz.
Optional LDO Output Discharge
LDO Output Voltage Programming
Each of the ACT8798’s LDOs features an optional,
independent output voltage discharge feature.
When this feature is enabled, the LDO output is
discharged to ground through a 650ꢀ resistance
when the LDO is shutdown. This feature may be
enabled or disabled via the I2C interface by writing
to the REG456CFG/DISx[ ] bits.
All LDOs feature independently-programmable
output voltages that are set via the I2C serial
interface, increasing the ACT8798’s flexibility while
reducing total solution size and cost. Set the output
voltage by writing to the REG456CFG/VSETx[ ]
registers.
Output Current Capability
Output Capacitor Selection
REG4, REG5, and REG6 each supply an output
current of 250mA. Excellent performance is
achieved over this load current range.
REG4, REG5, and REG6 each require only a small
ceramic capacitor for stability. For best
performance, each output capacitor should be
connected directly between the OUTx and G pins
as possible, with a short and direct connection. To
ensure best performance for the device, the output
capacitor should have a minimum capacitance of
1µF, and ESR value between 10mꢀ and 200mꢀ.
High quality ceramic capacitors such as X7R and
X5R dielectric types are strongly recommended.
Output Current Limit
In order to ensure safe operation under over-load
conditions, each LDO features current-limit circuitry
with current fold-back. The current-limit circuitry
limits the current that can be drawn from the output,
providing protection in over-load conditions. For
additional protection under extreme over current
conditions, current-fold-back protection reduces the
current-limit by approximately 30% under extreme
overload conditions.
PCB Layout Considerations
PCB Layout Considerations The ACT8798’s LDOs
provide good DC, AC, and noise performance over
a wide range of operating conditions, and are
relatively insensitive to layout considerations. When
designing a PCB, however, careful layout is
necessary to prevent other circuitry from degrading
LDO performance.
Enabling and Disabling the LDOs
REG4 is enabled whenever either of the following
conditions are met:
1) nMSTR is driven low, or
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
2) PWRHLD is asserted high.
Furthermore, once these conditions are met REG5
and REG6 maybe independently enabled or
disabled via the I2C serial interface by writing the
appropriate REG56/ONx[_] bit.
Power-OK
REFBP is a filtered reference noise, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
Each of the LDOs features power-OK status bit that
can be read by the system microprocessor via the
I2C interface. If an output voltage is lower than the
power-OK threshold, typically 15% below the
programmed regulation voltage, the corresponding
REG456CFG/OKx[ ] will clear to 0.
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Copyright © 2009 Active-Semi, Inc.
ACT8798
Active- Semi
Rev 1, 16-Nov-09
LOW-DROPOUT LINEAR REGULATORS
FUNCTIONAL DESCRIPTION (CONT’D)
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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ACT8798
Active- Semi
Rev 1, 16-Nov-09
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE
TQFN44-24 PACKAGE OUTLINE AND DIMENSIONS
D
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
D/2
SYMBOL
MIN
0.700
0.000
MAX
0.800
0.050
MIN
0.028
0.000
MAX
0.031
0.002
A
A1
A3
b
E/2
E
0.200 REF
0.008 REF
PIN #1 INDEX AREA
D/2 x E/2
0.180
3.850
3.850
2.500
2.500
0.300
4.150
4.150
2.800
2.800
0.007
0.152
0.152
0.098
0.098
0.012
0.163
0.163
0.110
0.110
D
E
D2
E2
e
A
0.500 BSC
0.020 BSC
A3
A1
D2
L
0.350
0.450
---
0.014
0.018
---
L
b
R
0.200 TYP
0.008 TYP
K
0.200
0.008
e
E2
PIN #1 INDEX AREA
D/2 x E/2
K
R
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com. For other inquiries, please send to:
2728 Orchard Parkway, San Jose, CA 95134-2012, USA
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I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
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