ACT8935QJ1E2-T_技术文档

ACT8935

Rev 4, 17-Sep-13

Advanced PMU for SiRF Prima^TMand Atlas IV^TM

FEATURES

GENERAL DESCRIPTION

• Optimized for SiRF Prima^TM/Atlas IV^TMProcessors

• Three Step-Down DC/DC Converters

• Four Low-Dropout Linear Regulators

• Integrated ActivePath^TMCharger

The ACT8935 is a complete, cost effective, highly-

efficient ActivePMU^TMpower management solution,

optimized for the unique power, voltage-

sequencing, and control requirements of the SiRF

Prima^TMand Atlas IV^TMprocessors.

• I²C^TMSerial Interface

This device features three step-down DC/DC

converters and four low-noise, low-dropout linear

regulators, along with a complete battery charging

solution featuring the advanced ActivePath^TM

system-power selection function.

• Advanced Enable/Disable Sequencing Controller

• Minimal External Components

• Tiny 5×5mm TQFN55-40 Package

− 0.75mm Package Height

The three DC/DC converters utilize

a high-

efficiency, fixed-frequency (2MHz), current-mode

PWM control architecture that requires a minimum

number of external components. Two DC/DCs are

capable of supplying up to 900mA of output current,

while the third supports up to 700mA. All four low-

dropout linear regulators are high-performance,

low-noise regulators that each supply up to 150mA.

− Pb-Free and RoHS Compliant

The ACT8935 is available in a compact, Pb-Free

and RoHS-compliant TQFN55-40 package.

TYPICAL APPLICATION DIAGRAM

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I²C^TMis a trademark of NXP.

SiRF Prima^TMand Atlas IV^TMare trademarks of SiRF Technology, Inc.

ACT8935

Rev 4, 17-Sep-13

TABLE OF CONTENTS

General Information.....................................................................................................................................p. 01

Functional Block Diagram............................................................................................................................p. 03

Ordering Information....................................................................................................................................p. 04

Pin Configuration .........................................................................................................................................p. 04

Pin Descriptions...........................................................................................................................................p. 05

Absolute Maximum Ratings.........................................................................................................................p. 07

I²C Interface Electrical Characteristics ........................................................................................................p. 08

Global Register Map....................................................................................................................................p. 09

Register and Bit Descriptions ......................................................................................................................p. 10

System Control Electrical Characteristics....................................................................................................p. 15

Step-Down DC/DC Electrical Characteristics..............................................................................................p. 16

Low-Noise LDO Electrical Characteristics...................................................................................................p. 17

ActivePath^TMCharger Electrical Characteristics..........................................................................................p. 18

Typical Performance Characteristics...........................................................................................................p. 20

Application Information ................................................................................................................................p. 27

Interfacing with the SiRF Prima^TM/Atlas IV^TM...................................................................................p. 27

Control Signals.................................................................................................................................p. 28

Push-Button Control.........................................................................................................................p. 29

Control Sequences...........................................................................................................................p. 29

Functional Description .................................................................................................................................p. 33

I²C Interface .....................................................................................................................................p. 33

Voltage Monitor and Interrupt...........................................................................................................p. 33

Thermal Shutdown ...........................................................................................................................p. 34

Step-Down DC/DC Regulators ....................................................................................................................p. 35

General Description..........................................................................................................................p. 35

100% Duty Cycle Operation.............................................................................................................p. 35

Synchronous Rectification................................................................................................................p. 35

Soft-Start ..........................................................................................................................................p. 35

Compensation ..................................................................................................................................p. 35

Configuration Options.......................................................................................................................p. 35

OK[ ] and Output Fault Interrupt.......................................................................................................p. 36

PCB Layout Considerations.............................................................................................................p. 36

Low-Noise, Low-Dropout Linear Regulators................................................................................................p. 37

General Description..........................................................................................................................p. 37

Output Current Limit.........................................................................................................................p. 37

Compensation ..................................................................................................................................p. 37

Configuration Options.......................................................................................................................p. 37

OK[ ] and Output Fault Interrupt.......................................................................................................p. 37

PCB Layout Considerations.............................................................................................................p. 37

ActivePath^TMCharger ..................................................................................................................................p. 39

General Description..........................................................................................................................p. 39

ActivePath Architecture....................................................................................................................p. 39

System Configuration Optimization..................................................................................................p. 39

Input Protection ................................................................................................................................p. 39

Battery Management........................................................................................................................p. 39

Charge Current Programming..........................................................................................................p. 40

Charger Input Interrupts ...................................................................................................................p. 40

Charge-Control State Machine.........................................................................................................p. 42

State Machine Interrupts..................................................................................................................p. 42

Thermal Regulation..........................................................................................................................p. 43

Charge Safety Timers ......................................................................................................................p. 43

Charge Timer Interrupts ...................................................................................................................p. 43

Charge Status Indicator....................................................................................................................p. 43

Reverse-Current Protection .............................................................................................................p. 43

Battery Temperature Monitoring ......................................................................................................p. 43

Battery Temperature Interrupts........................................................................................................p. 44

TQFN55-40 Package Outline and Dimensions ...........................................................................................p. 45

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ACT8935

Rev 4, 17-Sep-13

FUNCTIONAL BLOCK DIAGRAM

(Optional)

BODY

SWITCH

CHGIN

ACIN

AC Adaptor

USB

ACT8935

4.35V to 6V

System Supply

VSYS

BODY

SWITCH

ActivePath

Control

BAT

Li+ Battery

VSYS

+

nSTAT

102µA

CURRENT SENSE

VOLTAGE SENSE

CHARGE STATUS

TH

PRE-

CONDITION

CHGLEV

ISET

Charge

Control

2.85V

VP1

To VSYS

THERMAL

REGULATION

OUT2

110°C

SW1

OUT1

GP12

OUT1

nRSTO

PBIN

PUSH BUTTON

VP2

To VSYS

OUT2

SW2

OUT2

GP12

nPBSTAT

OUT2

nIRQ

VP3

To VSYS

SW3

OUT3

GP3

PWRHLD

OUT3

System

Control

PWREN

EXTON

SCL

INL

To VSYS

OUT4

REG4

LDO

SDA

BAT

OUT5

OUT6

OUT7

LBI

REG5

LDO

-

OUT5

OUT6

OUT7

1.2V

OUT2

+

nLBO

REG6

LDO

REG7

LDO

REFBP

Reference

GA

EP

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ACT8935

Rev 4, 17-Sep-13

ORDERING INFORMATION^ꢀꢁ

TEMPERATURE

RANGE

PART NUMBER

V_OUT1

V_OUT2

V_OUT3V_OUT4V_OUT5V_OUT6V_OUT7PACKAGE PINS

ACT8935QJ10D-T

ACT8935QJ1E2-T

1.8V

2.5V

3.3V

1.2V

1.2V 1.2V 2.5V 3.3V TQFN55-40

40

-40°C to +85°C

ꢀ: All Active-Semi components are RoHS Compliant and with Pb-free plating unless otherwise specified.

ꢁ: Standard product options are listed in this table. Contact factory for custom options. Minimum order quantity is 12,000 units.

ACT8935QJ_ _ _-T

Active-Semi

Product Number

Package Code

Pin Count

Option Code

Tape and Reel

PIN CONFIGURATION

TOP VIEW

ACTIVE

AA33

DATE CODE

Thin - QFN (TQFN55-40)

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ACT8935

Rev 4, 17-Sep-13

PIN DESCRIPTIONS

NAME

DESCRIPTION

Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is

discharged to GA in shutdown.

1

REFBP

2

3

4

5

6

7

8

OUT1

GA

Output Feedback Sense for REG1.

Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3

together at a single point as close to the IC as possible.

REG4 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic

capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.

OUT4

OUT5

INL

REG5 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic

capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.

Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic

capacitor placed as close to the IC as possible.

REG7 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic

capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.

OUT7

OUT6

REG6 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic

capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.

Master Enable Input. Drive PBIN to VSYS through a 50kꢀ resistor to enable the IC, drive PBIN

directly to VSYS to assert a manual reset condition. Refer to the PBIN Multi-Function Input section

for more information. PBIN is internally pulled down to GA through a 35kꢀ resistor.

9

PBIN

10

11

PWRHLD Power Hold Input. Refer to the Control Sequences section for more information.

nRSTO

nIRQ

Active Low Reset Output. See the nRSTO Output section for more information.

Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or a

charger interrupt occurs. See the nIRQ Output section for more information.

12

13

Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the PBIN

is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.

nPBSTAT

Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the

IC as possible.

14

15

16

GP3

SW3

VP3

Switching Node Output for REG3.

Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the

IC as possible.

17

18

19

OUT3

Output Feedback Sense for REG3.

PWREN Power Enable Input. Refer to the Control Sequences section for more information.

Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than

nLBO

1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information.

Low Battery Input. The input voltage is compared to 1.2V and the output of this comparison drives

nLBO. See the Precision Voltage Detector section for more information.

20

LBI

21

22

ACIN

AC Input Supply Detection. See the Charge Current Programming section for more information.

CHGLEV Charge Current Selection Input. See the Charge Current Programming section for more information.

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ACT8935

Rev 4, 17-Sep-13

PIN DESCRIPTIONS CONT’D

NAME

DESCRIPTION

Charge Current Set. Program the charge current by connecting a resistor (R_ISET) between ISET

and GA. See the Charge Current Programming section for more information.

23

ISET

Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102µA (typ) current

internally. See the Battery Temperature Monitoring section for more information.

24

25

TH

System Wake Up Input. Drive to VSYS or a logic high to wake up the IC from Sleep Mode or

Deep Sleep Mode.

EXTON

26

27

SCL

SDA

Clock Input for I²C Serial Interface.

Data Input for I²C Serial Interface. Data is read on the rising edge of SCL.

Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it

to directly drive an indicator LED without additional external components. See the Charge Status

Indicator section for more information.

28

nSTAT

29, 30

31, 32

BAT

Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)

System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.

VSYS

Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to

the IC as possible. The battery charger is automatically enabled when a valid voltage is present

on CHGIN .

33

34

CHGIN

OUT2

Output Feedback Sense for REG2.

Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close to

the IC as possible.

35

36

37

38

39

VP2

SW2

GP12

SW1

VP1

Switching Node Output for REG2.

Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as

close to the IC as possible.

Switching Node Output for REG1.

Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close to

the IC as possible.

40

NC

EP

No Connect. Not internally connected.

EP

Exposed Pad. Must be soldered to ground on PCB.

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ACT8935

Rev 4, 17-Sep-13

ABSOLUTE MAXIMUM RATINGS^ꢀ

PARAMETER

VALUE

UNIT

VP1, VP2 to GP12

VP3 to GP3

-0.3 to + 6

V

BAT, VSYS, INL to GA

CHGIN to GA

-0.3 to + 6

-0.3 to +14

V

SW1, OUT1 to GP12

-0.3 to (V_VP1+ 0.3)

-0.3 to (V_VP2+ 0.3)

-0.3 to (V_VP3+ 0.3)

-0.3 to + 6

SW2, OUT2 to GP12

SW3, OUT3 to GP3

nIRQ, nLBO, nPBSTAT, nRSTO, nSTAT to GA

PBIN, ACIN, CHGLEV, ISET, LBI, PWRHLD, PWREN, REFBP, SCL, SDA, TH,

EXTON to GA

-0.3 to (VSYS +

0.3)

V

OUT4, OUT5, OUT6, OUT7 to GA

GP12, GP3 to GA

-0.3 to (V_INL+ 0.3)

-0.3 to + 0.3

-40 to 85

V

Operating Ambient Temperature

Maximum Junction Temperature

°C

125

Maximum Power Dissipation

2.7

W

TQFN55-40 (Thermal Resistance θ_JA= 30^oC/W)

Storage Temperature

-65 to 150

300

°C

Lead Temperature (Soldering, 10 sec)

ꢀ: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may

affect device reliability.

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ACT8935

Rev 4, 17-Sep-13

I²C INTERFACE ELECTRICAL CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

SCL, SDA Input Low

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_VSYS= 3.1V to 5.5V, T_A= -40ºC to 85ºC

0.35

SCL, SDA Input High

SDA Leakage Current

SCL Leakage Current

SDA Output Low

V

_VSYS= 3.1V to 5.5V, T_A= -40ºC to 85ºC

1.55

V

1

µA

V

8

18

I

_OL= 5mA

0.35

SCL Clock Period, t_SCL

SDA Data Setup Time, t_SU

SDA Data Hold Time, t_HD

Start Setup Time, t_ST

Stop Setup Time, t_SP

1.5

100

300

100

µs

ns

For Start Condition

For Stop Condition

Figure 1:

I²C Compatible Serial Bus Timing

t_SCL

SCL

t_ST

t_HD

t_SU

t_SP

SDA

Start

Stop

condition

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ACT8935

Rev 4, 17-Sep-13

GLOBAL REGISTER MAP

BITS

OUTPUT ADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

NAME

DEFAULT^ꢀ

TRST

nSYSMODE nSYSLEVMSK nSYSSTAT SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]

SYS

0x00

0

1

0

R

0

1

NAME

Reserved

PWRDS

Reserved

SCRATCH SCRATCH

DSRDY

SDREQ

SYS

0x01

0x20

0x21

0x22

0x30

0x31

0x32

0x40

0x41

0x42

0x50

0x51

0x54

0x55

0x60

0x61

0x64

0x65

0x70

0x71

0x78

0x79

0x7A

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[2]

VSET[1]

VSET[0]

REG1

REG2

REG3

REG4

REG5

REG6

REG7

APCH

0

1

0

1

Reserved

1

0

Reserved

0

NAME

Reserved

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

ON

PHASE

MODE

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

1

0

R

NAME

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[2]

VSET[1]

VSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

Reserved

0

Reserved

0

1

Reserved

0

1

NAME

ON

PHASE

MODE

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

R

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[2]

VSET[1]

VSET[0]

0

1

0

Reserved

0

Reserved

0

NAME

Reserved

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

ON

PWRSTAT

MODE

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

VSET[2]

0

VSET[1]

0

R

NAME

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

ON

DIS

LOWIQ

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

1

0

VSET[2]

0

VSET[1]

0

R

NAME

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

ON

DIS

LOWIQ

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

1

0

VSET[2]

0

VSET[1]

0

R

NAME

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

1

ON

DIS

LOWIQ

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

1

0

VSET[2]

0

VSET[1]

0

R

NAME

Reserved

VSET[5]

VSET[4]

VSET[3]

VSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

ON

DIS

LOWIQ

DELAY[2]

DELAY[1]

DELAY[0] nFLTMSK

OK

0

1

0

Reserved

0

Reserved

1

0

Reserved

0

Reserved

0

Reserved

0

R

Reserved

0

NAME

Reserved

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

SUSCHG

0

1

Reserved

0

TOTTIMO[1] TOTTIMO[0] PRETIMO[1] PRETIMO[0] OVPSET[1] OVPSET[0]

1

0

CHGSTAT

0

1

0

INDAT

R

0

NAME

TIMRSTAT TEMPSTAT

INSTAT

TIMRDAT TEMPDAT

CHGDAT

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

R

TIMRTOT

TEMPIN

INCON

CHGEOCIN TIMRPRE TEMPOUT

INDIS

0

CHGEOCOUT

0

Reserved

0

Reserved

0

CSTATE[0]

R

0

Reserved

R

NAME

DEFAULT^ꢀ

CSTATE[1] Reserved

Reserved ACINSTAT

R

ꢀ: Default values of ACT8935QJ10D-T.

2: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.

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ACT8935

Rev 4, 17-Sep-13

REGISTER AND BIT DESCRIPTIONS

Table 1:

Global Register Map

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Reset Timer Setting. Defines the reset time-out threshold. Reset

time-out is 65ms when value is 1, reset time-out is 260ms when

value is 0. See nRSTO Output section for more information.

SYS

0x00

[7]

TRST

R/W

SYSLEV Mode Select. Defines the response to the SYSLEV

voltage detector, 1: Generate an interrupt when V_VSYSfalls

below the programmed SYSLEV threshold, 0: automatic

shutdown when V_VSYSfalls below the programmed SYSLEV

threshold.

[6]

nSYSMODE

R/W

System Voltage Level Interrupt Mask. SYSLEV interrupt is

masked by default, set to 1 to unmask this interrupt. See the

Programmable System Voltage Monitor section for more

information

SYS

0x00

[5] nSYSLEVMSK R/W

System Voltage Status. Value is 1 when V_VSYSis lower than the

SYSLEV voltage threshold, value is 0 when V_VSYSis higher than

the system voltage detection threshold.

[4]

nSYSSTAT

R

System Voltage Detect Threshold. Defines the SYSLEV voltage

threshold. See the Programmable System Voltage Monitor

section for more information.

SYS

0x00

0x01

[3:0]

[7:6]

[5]

SYSLEV

R/W

-

Reserved.

DEEP-SLEEP Enable Bit. Set bit to 1 to enter DEEP-SLEEP

mode, clear bit to 0 to wake from DEEP-SLEEP. Bit

automatically cleared to 0 when PBIN asserted.

PWRDS

-

[4]

Reserved.

Scratchpad Bits. Non-functional bits, maybe be used by user to

store system status information. Volatile bits, which are cleared

when system voltage falls below UVLO threshold.

[3:2]

SCRATCH

Deep-Sleep Ready Flag. Set bit to 1 before entering DEEP-

SLEEP mode, then read bit during enable sequence to identify

system status: if bit value is 1 the system is waking from DEEP-

SLEEP mode, if bit value is 0 the system is waking from a

disabled state.

SYS

0x01

[1]

DSRDY

R/W

Shutdown Request Flag. Set the bit value right after start-up

then microprocessor could check whenever the second push-

button is asserted.

SYS

0x01

[0]

SDREQ

REG1

0x20

0x21

0x22

[7:6]

[5:0]

[7:0]

[7]

-

VSET

-

R

Reserved.

Output Voltage Selection. See the Output Voltage Programming

section for more information.

R/W

R

Reserved.

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

ON

R/W

Regulator Phase Control. Set bit to 1 for the regulator to operate

180° out of phase with the oscillator, clear bit to 0 for the

regulator to operate in phase with the oscillator.

REG1

0x22

[6]

[5]

PHASE

MODE

R/W

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-

savings mode under light-load conditions.

Regulator Turn-On Delay Control. See the REG1, REG2, REG3

Turn-on Delay section for more information.

REG1

0x22

[4:2]

[1]

DELAY

nFLTMSK

OK

R/W

R

Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,

clear bit to 0 to disable fault-interrupts.

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

[0]

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ACT8935

Rev 4, 17-Sep-13

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

REG2

0x30

0x31

0x32

[7:6]

[5:0]

[7:0]

[7]

-

R

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

-

R/W

R

Reserved.

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

ON

R/W

Regulator Phase Control. Set bit to 1 for the regulator to

operate 180° out of phase with the oscillator, clear bit to 0 for

the regulator to operate in phase with the oscillator.

REG2

0x32

[6]

[5]

PHASE

MODE

R/W

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-

savings mode under light-load conditions.

Regulator Turn-On Delay Control. See the REG1, REG2,

REG3 Turn-on Delay section for more information.

REG2

0x32

[4:2]

[1]

DELAY

R/W

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG2

REG3

0x32

0x40

0x41

0x42

[0]

OK

R

[7:6]

[5:0]

[7:0]

[7]

-

VSET

-

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

R/W

R

Reserved.

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

ON

R/W

Configures regulator behavior with respect to the PBIN input.

Set bit to 0 to enable regulator when PBIN is asserted

REG3

0x42

[6]

[5]

PWRSTAT

MODE

R/W

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-

savings mode under light-load conditions.

Regulator Turn-On Delay Control. See the REG1, REG2,

REG3 Turn-on Delay section for more information.

REG3

0x42

[4:2]

[1]

DELAY

R/W

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG3

REG4

0x42

0x50

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

REG4

0x51

[7]

[6]

ON

R/W

Output Discharge Control. When activated, LDO output is

discharged to GA through 1.5kꢀ resistor when in shutdown.

Set bit to 1 to enable output voltage discharge in shutdown,

clear bit to 0 to disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG4

0x51

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

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ACT8935

Rev 4, 17-Sep-13

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG4

REG5

0x51

0x54

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG5

0x55

[7]

[6]

ON

R/W

Output Discharge Control. When activated, LDO output is

discharged to GA through 1.5kꢀ resistor when in shutdown.

Set bit to 1 to enable output voltage discharge in shutdown,

clear bit to 0 to disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG5

0x55

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG5

REG6

0x55

0x60

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG6

0x61

[7]

[6]

ON

R/W

Output Discharge Control. When activated, LDO output is

discharged to GA through 1.5kꢀ resistor when in shutdown.

Set bit to 1 to enable output voltage discharge in shutdown,

clear bit to 0 to disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG6

0x61

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG6

REG7

0x61

0x64

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG7

0x65

[7]

[6]

ON

R/W

Output Discharge Control. When activated, LDO output is

discharged to GA through 1.5kꢀ resistor when in shutdown.

Set bit to 1 to enable output voltage discharge in shutdown,

clear bit to 0 to disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG7

0x65

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

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ACT8935

Rev 4, 17-Sep-13

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG7

APCH

0x65

0x70

[0]

OK

R

[7:0]

-

R

Reserved.

Charge Suspend Control Input. Set bit to 1 to suspend

charging, clear bit to 0 to allow charging to resume.

APCH

0x71

[7]

[6]

SUSCHG

-

R/W

Reserved.

Total Charge Time-out Selection. See the Charge Safety

Timers section for more information.

[5:4]

TOTTIMO

Precondition Charge Time-out Selection. See the Charge

Safety Timers section for more information.

APCH

0x71

[3:2]

[1:0]

PRETIMO

OVPSET

R/W

Input Over-Voltage Protection Threshold Selection. See the

Input Over-Voltage Protection section for more information.

Charge Time-out Interrupt Status. Set this bit with

TIMRPRE[ ] and/or TIMRTOT[ ] to 1 to generate an interrupt

when charge safety timers expire, read this bit to get charge

time-out interrupt status. See the Charge Safety Timers

section for more information.

APCH

0x78

[7]

TIMRSTAT¹

R/W

Battery Temperature Interrupt Status. Set this bit with

TEMPIN[ ] and/or TEMPOUT[ ] to 1 to generate an interrupt

when a battery temperature event occurs, read this bit to get

the battery temperature interrupt status. See the Battery

Temperature Monitoring section for more information.

[6] TEMPSTAT¹

Input Voltage Interrupt Status. Set this bit with INCON[ ] and/

or INDIS[ ] to generate an interrupt when UVLO or OVP

condition occurs, read this bit to get the input voltage

interrupt status. See the Charge Current Programming

section for more information.

[5]

[4]

INSTAT

Charge State Interrupt Status. Set this bit with

CHGEOCIN[ ] and/or CHGEOCOUT[ ] to 1 to generate an

interrupt when the state machine gets in or out of EOC state,

read this bit to get the charger state interrupt status. See the

State Machine Interrupts section for more information.

CHGSTAT¹

Charge Timer Status. Value is 1 when precondition time-out

or total charge time-out occurs. Value is 0 in other case.

APCH

0x78

[3]

[2]

[1]

[0]

TIMRDAT¹

TEMPDAT¹

INDAT

R

Temperature Status. Value is 0 when battery temperature is

outside of valid range. Value is 1 when battery temperature is

inside of valid range.

Input Voltage Status. Value is 1 when a valid input at CHGIN

is present. Value is 0 when a valid input at CHGIN is not

present.

Charge State Machine Status. Value is 1 indicates the

charger state machine is in EOC state, value is 0 indicates

the charger state machine is in other states.

CHGDAT¹

Total Charge Time-out Interrupt control. Set both this bit and

TIMRSTAT[ ] to 1 to generate an interrupt when a total

charge time-out occurs. See the Charge Safety Timers

section for more information.

APCH

0x79

[7]

[6]

TIMRTOT

TEMPIN

R/W

Battery Temperature Interrupt Control. Set both this bit and

TEMPSTAT[ ] to 1 to generate an interrupt when the battery

temperature goes into the valid range. See the Battery

Temperature Monitoring section for more information.

ꢀ: Valid only when CHGIN UVLO Threshold<V_CHGIN<CHGIN OVP Threshold.

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ACT8935

Rev 4, 17-Sep-13

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Input Voltage Interrupt Control. Set both this bit and

INSTAT[ ] to 1 to generate an interrupt when CHGIN input

voltage goes into the valid range. See the Charge Current

Programming section for more information.

APCH

0x79

[5]

[4]

[3]

[2]

[1]

INCON

R/W

Charge State Interrupt Control. Set both this bit and

CHGSTAT[ ] to 1 to generate an interrupt when the state

machine goes into the EOC state. See the State Machine

Interrupts section for more information.

CHGEOCIN

TIMRPRE

TEMPOUT

INDIS

R/W

PRECHARGE Time-out Interrupt control. Set both this bit

and TIMRSTAT[ ] to 1 to generate an interrupt when a

PRECHARGE time-out occurs. See the Charge Safety

Timers section for more information.

Battery Temperature Interrupt Control. Set both this bit and

TEMPSTAT[ ] to 1 to generate an interrupt when the battery

temperature goes out of the valid range. See the Battery

Temperature Monitoring section for more information.

Input Voltage Interrupt Control. Set both this bit and

INSTAT[ ] to 1 to generate an interrupt when CHGIN input

voltage goes out of the valid range. See the Charge Current

Programming section for more information.

Charge State Interrupt Control. Set both this bit and

CHGSTAT[ ] to 1 to generate an interrupt when the state

machines jumps out of the EOC state. See the State

Machine Interrupts section for more information.

[0] CHGEOCOUT

APCH

0x7A

[7:6]

[5:4]

[3:2]

-

R

Reserved.

Charge State. Values indicate the current charging state.

See the State Machine Interrupts section for more

information.

CSTATE

-

Reserved.

ACIN Status. Indicates the state of the ACIN input, typically

in order to identify the type of input supply connected. Value

is 1 when ACIN is above the 1.2V precision threshold, value

is 0 when ACIN is below this threshold.

APCH

0x7A

[1]

[0]

ACINSTAT

-

R

Reserved.

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ACT8935

Rev 4, 17-Sep-13

SYSTEM CONTROL ELECTRICAL CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

Input Voltage Range

TEST CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

UVLO Threshold Voltage

UVLO Hysteresis

V

_VSYSRising

_VSYSFalling

2.2

2.45

200

2.65

V

mV

REG1 Enabled. REG2, REG3, REG4,

REG5, REG6 and REG7 Disabled

155

260

420

REG1, REG2 and REG5 Enabled. REG3,

REG4, REG6 and REG7 Disabled

Supply Current

µA

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 Enabled

Shutdown Supply Current

Oscillator Frequency

All Regulators Disabled

8

2

18

µA

MHz

V

1.8

1.4

2.2

Logic High Input Voltage¹

Logic Low Input Voltage

Leakage Current

0.4

1

V

_nIRQ= V_nRSTO= 4.2V

_BATFalling

µA

V

LBI Threshold Voltage

LBI Hysteresis Threshold

Low Level Output Voltage²

nRSTO Delay

1.03

1.2

1.31

V_BATRising

I_SINK= 5mA

200

mV

V

0.35

260^ꢂ

160

20

ms

°C

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

Temperature rising

ꢀ: PWRHLD, PWREN, EXTON are logic inputs.

2: nLBO, nPBSTAT, nIRQ, nRSTO are open drain outputs.

3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms.

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ACT8935

Rev 4, 17-Sep-13

STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS

(V_VP1= V_VP2= V_VP3= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

Operating Voltage Range

UVLO Threshold

CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

Input Voltage Rising

2.5

2.6

100

65

0

2.7

V

UVLO Hysteresis

Input Voltage Falling

Regulator Enabled

mV

µA

Quiescent Supply Current

Shutdown Current

90

1

V

_VP= 5.5V, Regulator Disabled

ꢀ

_OUT≥ 1.2V, I_OUT= 10mA

-1%

-2%

V_NOM

1%

2%

Output Voltage Accuracy

V

ꢀ

_OUT< 1.2V, I_OUT= 10mA

_VP= Max(V_NOM¹+1, 3.2V) to 5.5V

I

_OUT= 10mA to IMAX²

Line Regulation

0.15

0.0017

93

%/V

%/mA

%V_NOM

MHz

kHz

Load Regulation

Power Good Threshold

Power Good Hysteresis

V

_OUTRising

_OUTFalling

2

_OUT≥ 20% of V_NOM

_OUT= 0V

1.8

2

2.2

Oscillator Frequency

500

400

75

Soft-Start Period

Minimum On-Time

REG1

µs

ns

Maximum Output Current

Current Limit

0.9

1.2

A

1.4

0.18

0.16

0

1.7

1

PMOS On-Resistance

NMOS On-Resistance

SW1 Leakage Current

REG2

I

_SW1= -100mA

_SW1= 100mA

ꢀ

I

ꢀ

V

_VP1= 5.5V, V_SW1= 0 or 5.5V

µA

Maximum Output Current

Current Limit

0.7

0.9

A

1.1

0.21

0.16

0

1.3

1

PMOS On-Resistance

NMOS On-Resistance

SW2 Leakage Current

REG3

I

_SW2= -100mA

_SW2= 100mA

ꢀ

I

ꢀ

V

_VP2= 5.5V, V_SW2= 0 or 5.5V

µA

Maximum Output Current

Current Limit

0.9

1.2

A

1.4

0.18

0.16

0

1.7

PMOS On-Resistance

I

_SW3= -100mA

I_SW3= 100mA

_VP3= 5.5V, V_SW3= 0 or 5.5V

ꢀ

NMOS On-Resistance

SW3 Leakage Current

ꢀ

V

1

µA

ꢀ: V_NOMrefers to the nominal output voltage level for V_OUTas defined by the Ordering Information section.

2: IMAX Maximum Output Current.

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ACT8935

Rev 4, 17-Sep-13

LOW-NOISE LDO ELECTRICAL CHARACTERISTICS

(V_INL= 3.6V, C_OUT4= C_OUT5= C_OUT6= C_OUT7= 1.5µF, T_A= 25°C, LOWIQ[-] = [0], unless otherwise specified.)

PARAMETER

TEST CONDITIONS

MIN

2.5

TYP

MAX

5.5

UNIT

Operating Voltage Range

V

ꢀ

V

_OUT≥ 1.2V, T_A= 25°C, I_OUT= 10mA

_OUT< 1.2V, T_A= 25°C, I_OUT= 10mA

_INL= Max (V_OUT+ 0.5V, 3.6V) to 5.5V

-1%

-2%

V_NOM

2%

Output Voltage Accuracy

Line Regulation

V

ꢀ

4%

0.05

0.5

LOWIQ[ ] = [0]

mV/V

V_INL= Max (V_OUT+ 0.5V, 3.6V) to 5.5V

LOWIQ[ ] = [1]

Load Regulation

I_OUT= 1mA to IMAX^ꢃ

0.08

75

65

37

31

0

V/A

dB

f = 1kHz, I_OUT= 20mA, V_OUT= 1.2V

f = 10kHz, I_OUT= 20mA, V_OUT= 1.2V

Regulator Enabled, LOWIQ[ ] = [0]

Regulator Enabled, LOWIQ[ ] = [1]

Regulator Disabled

Power Supply Rejection Ratio

60

52

1

Supply Current per Output

µA

Soft-Start Period

V_OUT= 2.9V

V_OUTRising

V_OUTFalling

140

89

3

µs

Power Good Threshold

Power Good Hysteresis

%V_NOM

I

_OUT= 20mA, f = 10Hz to 100kHz, V_OUT=

Output Noise

50

µV_RMS

1.2V

Discharge Resistance

REG4

LDO Disabled, DIS[ ] = 1

1.5

kꢀ

Dropout Voltage^ꢁ

Maximum Output Current

Current Limit^ꢂ

I_OUT= 80mA, V_OUT> 3.1V

90

140

90

180

mV

mA

µF

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT4Range

REG5

20

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 80mA, V_OUT> 3.1V

280

mV

mA

µF

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT5Range

REG6

20

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 80mA, V_OUT> 3.1V

180

mV

mA

µF

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT6Range

REG7

20

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 80mA, V_OUT> 3.1V

140

280

mV

mA

µF

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT7Range

20

ꢀ: V_NOMrefers to the nominal output voltage level for V_OUTas defined by the Ordering Information section.

2: IMAX Maximum Output Current.

3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the

regulation voltage (for 3.1V output voltage or higher).

ꢃ: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.

Under heavy overload conditions the output current limit folds back by 30% (typ)

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ACT8935

Rev 4, 17-Sep-13

ActivePath^TMCHARGER ELECTRICAL CHARACTERISTICS

(V_CHGIN= 5.0V, T_A= 25°C, unless otherwise specified.)

PARAMETER

ActivePath

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHGIN Operating Voltage Range

CHGIN UVLO Threshold

CHGIN UVLO Hysteresis

CHGIN OVP Threshold

4.35

3.1

6.0

3.9

V

CHGIN Voltage Rising

3.5

0.5

6.6

0.4

35

CHGIN Voltage Falling

CHGIN Voltage Rising

CHGIN Voltage Falling

V_CHGIN< V_UVLO

V

6.0

7.2

V

CHGIN OVP Hysteresis

V

70

µA

V_CHGIN< V_BAT+ 50mV, V_CHGIN> V_UVLO

100

200

CHGIN Supply Current

V

_CHGIN> V_BAT+ 150mV, V_CHGIN> V_UVLO

1.3

2.0

mA

Charger disabled, I_VSYS= 0mA

I_VSYS= 100mA

CHGIN to VSYS On-Resistance

CHGIN to VSYS Current Limit

0.3

2

ꢀ

ACIN = VSYS

1.5

80

A

ACIN = GA, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

90

450

100

500

mA

400

VSYS REGULATION

VSYS Regulated Voltage

nSTAT OUTPUT

I_VSYS= 10mA

V_nSTAT= 2V

4.45

4

4.6

8

4.8

V

nSTAT Sink current

12

1

mA

µA

nSTAT Leakage Current

ACIN AND CHGLEV INPUTS

CHGLEV Logic High Input Voltage

CHGLEV Logic Low Input Voltage

CHGLEV Leakage Current

ACIN Voltage Thresholds

ACIN Hysteresis Voltage

ACIN Leakage Current

TH INPUT

V_nSTAT= 4.2V

1.4

V

0.4

1

V_CHGLEV= 4.2V

µA

V

ACIN voltage rising

ACIN voltage falling

1.03

1.2

1.31

200

mV

µA

V

_ACIN= 4.2V

1

TH Pull-Up Current

V_CHGIN> V_BAT+ 100mV, Hysteresis = 50mV

Hot Detect NTC Thermistor

91

102

110

µA

V

V_THUpper Temperature Voltage

2.44

2.51

2.58

Threshold (V_THH

)

V_THLower Temperature Voltage

Cold Detect NTC Thermistor

Upper and Lower Thresholds

0.47

0.50

30

0.53

V

Threshold (V_THL

)

V_THHysteresis

mV

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ACT8935

Rev 4, 17-Sep-13

ActivePath^TMCHARGER ELECTRICAL CHARACTERISTICS CONT’D

(V_CHGIN= 5.0V, T_A= 25°C, unless otherwise specified.)

PARAMETER

CHARGER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BAT Reverse Leakage Current V_CHGIN= 0V, V_BAT= 4.2V, I_VSYS= 0mA

BAT to VSYS On-Resistance

8

µA

70

mꢀ

Fast Charge

ISET Pin Voltage

1.2

0.13

4.2

V

Precondition

T_A= -20°C to 70°C

4.179

4.170

4.221

V

Charge Termination Voltage

V_TERM

T_A= -40°C to 85°C

4.230

1

ACIN = VSYS, CHGLEV = VSYS -10%

I_CHG

+10%

ACIN = VSYS, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

-10%

400

80

I

_CHG/5

+10%

mA

V_BAT= 3.8V

R_ISET= 6.8K

Charge Current

450

500

ACIN = GA, CHGLEV = GA

ACIN = VSYS, CHGLEV = VSYS

ACIN = VSYS, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

ACIN = GA, CHGLEV = GA

90

10% I_CHG

45

100

V_BAT= 2.7V

Precondition Charge Current

mA

R_ISET= 6.8K

45

Precondition Threshold Voltage V_BATVoltage Rising

Precondition Threshold

2.75

2.85

3.0

V

_BATVoltage Falling

150

mV

Hysteresis

ACIN = VSYS, CHGLEV = VSYS

10% I_CHG

ACIN = VSYS, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

ACIN = GA, CHGLEV = GA

10% I_CHG

45

END-OF-CHARGE Current

Threshold

V_BAT= 4.15V

mA

45

Charge Restart Threshold

Precondition Safety Timer

Total Safety Timer

V_TERM- V_BAT, V_BATFalling

PRETIMO[ ] = 10

190

205

80

220

mV

min

hr

TOTTIMO[ ] = 10

5

Thermal Regulation Threshold

100

°C

ꢀ: R_ISET(kꢀ) = 2336 × (1V/I_CHG(mA)) - 0.205

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

V_REFvs. Temperature

Frequency vs. Temperature

0.84

0.42

0

2.5

2

1.5

1

0.5

0

-0.42

-0.84

-0.5

-1

Typical V_REF=1.2V

Typical Oscillator Frequency=2MHz

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80 85

Temperature (°C)

PBIN Startup Sequence

PWRHLD Startup Sequence

CH1

CH2

CH3

CH4

CH5

REG3/PWRSTAT[ ] = 0

CH1: V_PBIN, 5V/div

CH2: V_OUT3, 1V/div

CH3: V_OUT5, 1V/div

CH4: V_OUT1, 1.5V/div

CH5: V_OUT2, 3V/div

TIME: 2ms/div

CH1: V_PWRHRD, 5V/div

CH2: V_OUT5, 1V/div

CH3: V_OUT1, 1.5V/div

CH4: V_OUT2, 3V/div

TIME: 2ms/div

PWREN Sequence

CH1

CH2

CH3

CH4

CH5

CH1: V_PWREN, 5V/div

CH2: V_OUT3, 1V/div

CH3: V_OUT4, 1V/div

CH4: V_OUT6, 2.5V/div

CH5: V_OUT7, 3V/div

TIME: 2ms/div

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Push-Button Response (First Power-Up)

Manual Reset Response

CH1

CH2

CH3

CH1: V_PBIN, 1V/div

CH1: V_PBIN, 2V/div

CH2: V_nPBSTAT, 2V/div

CH3:V_nRSTO, 2V/div

TIME: 100ms/div

PBIN Resistor = 50kꢀ

CH2: V_nPBSTAT, 2V/div

PBIN Resistor = 0ꢀ

CH3: V_nRSTO, 2V/div

TIME: 100ms/div

REG1 Efficiency vs. Output Current

REG2 Efficiency vs. Output Current

100

80

60

40

20

0

100

80

60

40

20

0

V_OUT= 1.8V

V_OUT= 3.3V

V_IN= 5.0V

V_IN= 3.6V

V_IN= 4.2V

1

10

100

1000

1

10

100

1000

Output Current (mA)

REG3 Efficiency vs. Output Current

100

V_OUT= 1.2V

80

60

40

20

0

V_IN= 5.0V

V_IN= 3.6V

V_IN= 4.2V

1

10

100

1000

Output Current (mA)

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

REG1 Output Voltage vs. Temperature

REG2 Output Voltage vs. Temperature

1.815

1.809

1.803

1.797

1.791

1.785

3.310

3.306

3.302

3.298

3.294

3.290

V_OUT1= 1.8V

I_LOAD= 100mA

V_OUT2= 3.3V

I_LOAD= 100mA

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

REG2 MOSFET Resistance

REG3 Output Voltage vs. Temperature

1.210

1.206

1.202

1.198

1.194

1.190

350

300

250

200

150

100

50

I_LOAD= 100mA

V_OUT3= 1.2V

I_LOAD= 100mA

PMOS

NMOS

0

3.0

3.5

4.0

4.5

5.0

5.5

-40

-20

0

20

40

60

80

100

120

Input Voltage (V)

Temperature (°C)

REG1, 3 MOSFET Resistance

350

I_LOAD= 100mA

300

250

200

150

100

50

PMOS

NMOS

0

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Output Voltage vs. Output Current

3.70

3.50

3.30

3.10

2.90

2.70

2.50

2.30

2.10

1.300

1.260

1.220

1.180

1.140

1.180

REG7

REG4, REG5

REG6

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Output Current (mA)

Dropout Voltage vs. Output Current

160

140

250

200

150

100

50

120

REG5

100

80

60

40

20

0

REG4

V_IN= 3.3V

0

20

40

60

80

100 120 140 160

0

20

40

60

80

100 120 140 160

Output Current (mA)

Dropout Voltage vs. Output Current

180

160

140

120

100

80

300

250

200

150

100

50

REG6

REG7

60

40

20

V_IN= 3.3V

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Current (mA)

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Output Voltage vs. Temperature

Region of Stable C_OUTESR vs. Output Current

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0

1

REG7

REG6

0.1

Stable ESR

REG4, REG5

0.01

0

50

100

150

-40

-20

0

20

40

60

80

100

120

Output Current (mA)

Temperature (°C)

LDO Output Voltage Noise

CH1

CH1: V_OUTx, 200µV/div (AC COUPLED)

TIME: 200ms/div

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

VSYS Voltage vs. CHGIN Voltage

VSYS Voltage vs. VSYS Current

6.0

5.0

4.0

3.0

2.0

1.0

0

5.2

5.0

4.8

4.6

4.4

4.2

4.0

ACIN/CHGLEV = 01

ACIN/CHGLEV = 11

V_VSYS= 4.6V

0

2

4

6

8

10

0

500

1000

1500

2000

2500

CHGIN Voltage (V)

VSYS Current (mA)

Charger Current vs. Battery Voltage

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V_CHGIN= 5V

ACIN = 0

CHGLEV = 1

450mA USB

V_BATFalling

V_BATRising

V_CHGIN= 5V

ACIN = 0

V_BATFalling

CHGLEV = 0

V_BATRising

90mA USB

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Battery Voltage (V)

Charger Current vs. Battery Voltage

DCCC and Battery Supplement Modes

1200

1000

800

600

400

200

0

R_ISET= 2.4kꢀ

V_CHGIN= 5V

CH4

CH3

CH2

ACIN/CHGLEV = 11

V_BAT= 3.5V

V_VSYS= 4.6V

_VSYS= 0-1.8A

I_CHARGE= 1000mA

_CHGIN= 5.1V-3A

I

V_BATFalling

V_BATRising

CH1

V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

CH1: I_VSYS, 1.00A/div

CH2: I_BAT, 1.00A/div

CH3: V_BAT, 1.00V/div

CH4: V_VSYS, 1V/div

TIME: 200ms/div

Battery Voltage (V)

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ACT8935

Rev 4, 17-Sep-13

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

VAC Applied

VAC Removed

CH4

CH3

CH2

CH3

CH2

CH1

V_CHGIN= 5V

V_BAT= 3.5V

R_VSYS= 100ꢀ

ACIN/CHGLEV = 01

V_CHGIN= 5V

V_BAT= 3.5V

R_VSYS= 100ꢀ

ACIN/CHGLEV = 01

CH1: I_BAT, 400mA/div

CH2: V_BAT, 1V/div

CH3: V_VSYS, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

CH1: I_BAT, 200mA/div

CH2: V_VSYS, 2V/div

CH3: V_BAT, 1V/div

CH4: V_CHGIN, 5V/div

TIME: 100ms/div

VAC Applied

VAC Removed

CH4

CH3

CH2

CH3

CH2

CH1

V_CHGIN= 5V

V_BAT= 3.97V

V_CHGIN= 5V

V_BAT= 3.97V

CH1: I_BAT, 1A/div

CH2: V_BAT, 2V/div

CH3: V_VSYS, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

CH1: I_BAT, 1A/div

CH2: V_VSYS, 2V/div

CH3: V_BAT, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

R_VSYS= 47ꢀ

ACIN/CHGLEV = 11

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ACT8935

Rev 4, 17-Sep-13

APPLICATION INFORMATION

Interfacing with the SiRF Prima^TM/Atlas IV^TM

The ACT8935 is optimized for use in applications

using the SiRF Prima^TMand Atlas IV^TMprocessors,

supporting both the power domains as well as the

signal interface for these processors.

the ACT8935 pin names and the Prima/Atlas IV pin

names are provided. When this is done, the

Prima/Atlas IV pin names are located after the

ACT8935 pin names, and are italicized and located

inside parentheses. For example, PWREN

(X_PWR_EN) refers to the logic signal applied to

the ACT8935's PWREN input, identifying that it is

driven from the Prima/Atlas IV's X_PWR_EN

output. Likewise, REG2 (VDD_IO) refers to

ACT8935's OUT2 pin, identifying that it is

connected to the Prima/Atlas IV's VDD_IO power

domain.

While the ACT8935 supports many possible

configurations for powering these processors, one

of the most common configurations is detailed in

this datasheet. In general, this document refers to

the ACT8935 pin names and functions. However, in

cases where the description of interconnections

between these devices benefits by doing so, both

Table 2:

ACT8935 and SiRF Power Domains

SiRF POWER DOMAIN

VDDIO_MEM

VDD_IO

ACT8935 CHANNEL

REG1

TYPE

DC/DC

LDO

DEFAULT VOLTAGE

CURRENT CAPABILITY

900mA

1.8V

3.3V

1.2V

REG2

700mA

VDD_PDN/VDD_TSC

VDD_PLL

REG3

900mA

REG4

150mA

VDD_PRE

REG5

LDO

150mA

VREF_ADC

VDDA_TSC

REG6

LDO

2.5V

3.3V

150mA

VDD2V5_USB

VDD3V3_USB

REG7

Table 3:

ACT8935 and SiRF Power Modes

POWER MODE

CONTROL STATE

POWER DOMAIN STATE

QUIESCENT CURRENT

PWRHLD is asserted, PWREN is REG1, REG2, REG3, REG4, REG5,

ALL ON

420µA

asserted, PWRDS[ ] is 0

REG6 and REG7 are on

PWRHLD is asserted, PWREN is

de-asserted, PWRDS[ ] is 0

REG1, REG2 and REG5 are on.

REG3, REG4, REG6 and REG7 are off

SLEEP

260µA

155µA

PWRHLD is asserted, PWREN is

de-asserted, PWRDS[ ] is 1

REG1 is on. REG2, REG3, REG4,

REG5, REG6 and REG7 are off

DEEP-SLEEP

Table 4:

ACT8935 and SiRF Signal Interface

ACT8935

PWREN

SCL

DIRECTION

SiRF Prima / Atlas IV

X_PWR_EN

X_SCL_0

SDA

X_SDA_0

EXTON

nRSTO

nIRQ

X_RTC_Alarm

X_Reset_B

X_GPIO[1]¹

X_GPIO[0]²

X_GPIO[4] ^ꢂ

X_VIP_PXD[6]^ꢃ

GPIO⁵

nPBSTAT

nLBO

CHGLEV

PWRHLD

1, 2, ꢂ, ꢃ: Typical connections shown, actual connections may vary.

5: Optional connection for power hold control.

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ACT8935

Rev 4, 17-Sep-13

Table 5:

Control Pins

PIN NAME

IF PWRSTAT[ ] = 0

IF PWRSTAT[ ] = 1

PBIN

REG1, REG2, REG3, REG5

REG1, REG2, REG5

EXTON

PWRHLD

PWREN

REG1, REG2, REG5

REG3, REG4, REG6, REG7

Manual Reset Function

Control Signals

The second major function of the PBIN input is to

provide a manual-reset input for the processor. To

manually-reset the processor, drive PBIN directly to

VSYS through a low impedance (less than 2.5kꢀ).

When this occurs, nRSTO immediately asserts low,

then remains asserted low until the PBIN input is

de-asserted and the reset time-out period expires.

Enable Inputs

The ACT8935 features a variety of control inputs,

which are used to enable and disable outputs

depending upon the desired mode of operation.

PWREN, PWRHLD, and EXTON are logic inputs,

while PBIN is a unique, multi-function input. Refer

to Table 5 for a description of which channels are

controlled by each input.

nPBSTAT Output

nPBSTAT is an open-drain output that reflects the

state of the PBIN input; nPBSTAT is asserted low

whenever PBIN is asserted, and is high-Z

otherwise. This output is typically used as an

interrupt signal to the processor, to initiate a

software-programmable routine such as operating

mode selection or to open a menu. Connect

nPBSTAT to an appropriate supply voltage

(typically OUT2) through a 10kꢀ or greater resistor.

PBIN Multi-Function Input

ACT8935 features the PBIN multi-function pin,

which combines system enable/disable control with

a hardware reset function. Select either of the two

pin functions by asserting this pin, either through a

direct connection to VSYS, or through a 50kꢀ

resistor to VSYS, as shown in Figure 2.

Figure 2:

nRSTO Output

PBIN Input

nRSTO is an open-drain output which asserts low

upon startup or when manual reset is asserted via

the PBIN input. When asserted on startup, nRSTO

remains low until reset time-out period expires after

OUT2 reaches its power-OK threshold. When

asserted due to manual-reset, nRSTO immediately

asserts low, then remains asserted low until the

PBIN input is de-asserted and the reset time-out

period expires.

Connect a 10kꢀ or greater pull-up resistor from

nRSTO to an appropriate voltage supply (typically

OUT2) .

Enable / Wake-Up

nIRQ Output

The most common application for PBIN is to drive it

to VSYS through a 50kꢀ resistor. In this case, PBIN

initiates system enable, if the system is disabled, or

is used to initiate a wake up routine from SLEEP

mode.

nIRQ is an open-drain output that asserts low any

time an interrupt is generated. Connect a 10kꢀ or

greater pull-up resistor from nIRQ to an appropriate

voltage supply. nIRQ is typically used to drive the

interrupt input of the system processor.

In order to initiate a wake up routine or any other

function that is initiated through push-button

assertion, the processor should monitor the

ACT8935's nPBSTAT output. See the nPBSTAT

Output section for more information.

Many of the ACT8935's functios support interrupt-

generation as a result of various conditions. These

are typically masked by default, but may be

unmasked via the I²C interface. For more

information about the available fault conditions,

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unmasked via the I²C interface. For more

information about the available fault conditions,

refer to the appropriate sections of this datasheet.

PWRHLD, holding REG1, REG2, and REG5, and

assert PWREN (X_PWR_EN), enabling REG4,

REG6, REG7 and holding REG3 to ensure that the

system remains powered after PBIN is released.

Note that under some conditions a false interrupt

may be generated upon initial startup. For this

reason, it is recommended that the interrupt service

routine check and validate nSYSLEVMSK[-] and

nFLTMSK[-] bits before processing an interrupt

generated by these bits. These interrupts may be

validated by nSYSSTAT[-], OK[-] bits.

The logic required to control the Prima and Atlas IV

processors requires that REG3 is enabled when

PBIN is asserted during power-up, but then operate

independently of PBIN during SLEEP mode. For

this reason, the ACT8935 features the

REG3/PWRSTAT[-] bit, which controls how REG3

responds when the PBIN input is asserted. The

required functionality may be achieved either by

setting PWRSTAT[-] to 1 during the boot sequence

or, alternatively, as part of the process of entering

SLEEP mode.

Push-Button Control

The ACT8935 is designed to initiate a system

enable sequence when the PBIN multi-function

input is asserted. Once this occurs, a power-on

sequence commences, as described below. The

power-on sequence must complete and the

microprocessor must take control (by asserting

PWREN or PWRHLD) before PBIN is de-asserted.

If the microprocessor is unable to complete its

power-up routine successfully before the user

releases the push-button, the ACT8935

automatically shuts the system down. This provides

protection against accidental or momentary

assertions of the push-button. If desired, longer

“push-and-hold” times can be implemented by

simply adding an additional time delay before

asserting PWREN or PWRHLD.

Once the power-up routine is completed, the

system remains enabled after the push-button is

released as long as either PWRHLD or PWREN are

asserted high. If the processor does not assert

PWRHLD or PWREN before the user releases the

push-button, the boot-up sequence is terminated

and all regulators are disabled. This provides

protection against "false-enable", when the push-

button is accidentally depressed, and also ensures

that the system remains enabled only if the

processor successfully completes the boot-up

sequence.

Alternatively, an enable sequence may initiate as a

result of asserting the EXTON input. EXTON

enables the ACT8935 in an identical manner as

PBIN, but does not assert nPBSTAT. EXTON is

normally driven by the Prima/Atlas IV's RTC Alarm

signal in order to enable or wake the system from

SLEEP, DEEP-SLEEP, or shut down modes.

Control Sequences

The ACT8935 features

a

variety of control

sequences that are optimized for supporting system

enable and disable, as well as both SLEEP and

DEEP-SLEEP modes of the SiRF Prima and Atlas

IV processors.

Enable Sequence

A typical enable sequence initiates as a result of

asserting PBIN, and begins by enabling REG3 and

REG5. When REG5 reaches its power-OK

threshold, REG1 and REG2 are enabled and

nRSTO is asserted low, resetting the

microprocessor. If REG5 is above its power-OK

threshold when the reset timer expires, nRSTO is

de-asserted, allowing the microprocessor to begin

its boot sequence.

During the boot sequence, the processor should

read the DSRDY[ ] bit; if the value of DSRDY[ ] is 0

then the software should proceed with a typical

enable sequence, whereas if the value of DSRDY[-]

is 1 then the software should proceed with a “wake

from DEEP-SLEEP” routine. See the DEEP-SLEEP

Sequence section for more information. During the

boot sequence, the microprocessor must assert

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ACT8935

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Figure 3:

Power Enable Sequence

Power Up Sequence

PBIN

nPBSTAT

260ms

nRSTO

PWREN

PWRHLD

OUT3

OUT5

93% of regulation

8ms

OUT1

OUT2

OUT4, OUT6, OUT7

REG3/PWRSTAT[ ]

SDREQ[ ]

DEEP-SLEEP Mode Sequence

SLEEP Mode Sequence

The ACT8935 supports Prima/Atlas IV DEEP-

SLEEP mode operation. Once a successful power-

up routine has been completed, DEEP-SLEEP

mode may be initiated through a variety of software-

controlled mechanisms.

The ACT8935 supports Prima/Atlas IV SLEEP

mode operation. Once a successful power-up

routine has been completed, SLEEP mode may be

initiated through a variety of software-controlled

mechanisms.

DEEP-SLEEP mode is typically initiated when the

user presses the push-button during normal

operation. Pressing the push-button asserts, the

nPBSTAT output, which interrupts the processor. In

response to this interrupt the processor should first

set the DSRDY[ ] bit to 1, then set the PWRDS[-] bit

to 1, disabling REG2, REG3, REG4, REG5, REG6,

and REG7.

The Prima and Atlas IV processors require that

REG3 is enabled by PBIN, but then operate

independently of PBIN in SLEEP mode. Therefore,

it is important that REG3/PWRSTAT[-] be set to 1

prior to entering SLEEP mode. This may be done

as part of the boot sequence or as part of the

sequence to enter SLEEP mode.

SLEEP mode is typically initiated when the user

presses the push-button during normal operation.

Pressing the push-button asserts, the nPBSTAT

output, which interrupts the processor. In response

to this interrupt the processor should de-assert

PWREN (X_PWR_EN), disabling REG3, REG4,

REG6 and REG7. PWRHLD should remain

asserted during SLEEP mode so that REG1, REG2

and REG5 remain enabled.

Waking from DEEP-SLEEP mode is initiated when

the user presses the push-button again. Asserting

PBIN clears the PWRDS[-] bit to 0, enabling REG3

and REG5. Once REG5 reaches regulation, REG2

is enabled and the nRSTO timer begins. Once the

reset timer period expires the nRSTO output is de-

asserted and the processor initiates a boot-up

sequence, during which it should determine the

system status by reading the DSRDY[-] bit; if the

value of DSRDY[-] is 0 then the software should

proceed with a typical enable sequence, whereas if

the value of DSRDY[-] is 1 then the software should

proceed with a “wake from DEEP-SLEEP” routine.

To complete the wake process, the processor should

assert PWRHLD to ensure that the system remains

enabled after the push-button is released, and assert

PWREN to enable REG4, REG6, and REG7, then set

DSRDY[-] to 0 to complete a full wake-up routine.

Waking from SLEEP mode is initiated when the

user presses the push-button again, which asserts

nPBSTAT. Processors should respond by asserting

PWREN (X_PWR_EN), which enables REG3,

REG4, REG6 and REG7, so that normal operation

may resume.

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ACT8935

Rev 4, 17-Sep-13

Figure 4:

Sleep Mode Sequence

Figure 5:

Deep Sleep Mode Sequence

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ACT8935

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completely software-controlled, but typically

involved initiating various “clean-up” processes

before clear SDREQ[-] bit to 0, disabling all

regulators and shutting the system down.

Disable Sequence

As with the enable sequence, a typical disable

sequence is initiated when the user presses the

push-button, which interrupts the processor via the

nPBSTAT output. The actual disable sequence is

Figure 6:

Power Disable Sequence

Shutdown Sequence

PBIN

nPBSTAT

nRSTO

PWREN

PWRHLD

OUT3

OUT5

OUT1

OUT2

OUT4, OUT6, OUT7

SDREQ[ ]

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ACT8935

Rev 4, 17-Sep-13

FUNCTIONAL DESCRIPTION

I²C Interface

below the SYSLEV[-] voltage threshold:

1) If nSYSMODE[-] = 1 (default case), when system

The ACT8935 features an I²C interface that allows

advanced programming capability to enhance

overall system performance. To ensure

voltage level interrupt is unmasked

(nSYSLEVMSK[ ]=1) and V_VSYSfalls below the

programmable threshold, the ACT8935 asserts

nIRQ, providing a software “under-voltage alarm”.

The response to this interrupt is controlled by the

CPU, but will typically initiate a controlled shutdown

sequence either or alert the user that the battery is

low. In this case the interrupt is cleared when V_VSYS

rises up again above the SYSLEV rising threshold

and nSYSSTAT[-] is read via I²C.

compatibility with

a

wide range of system

processors, the I²C interface supports clock speeds

of up to 400kHz (“Fast-Mode” operation) and uses

standard I²C commands. I²C write-byte commands

are used to program the ACT8935, and I²C read-

byte commands are used to read the ACT8935’s

internal registers. The ACT8935 always operates as

a slave device, and is addressed using a 7-bit slave

address followed by an eighth bit, which indicates

whether the transaction is a read-operation or a

write-operation, [1011011x].

2) If nSYSMODE[-] = 0, when V_VSYSfalls below the

programmable threshold the ACT8935 shuts down,

immediately disabling all regulators. This option is

useful for implementing a programmable “under-

voltage lockout” function that forces the system off

when the battery voltage falls below the SYSLEV

threshold voltage. Since this option does not

support a controlled shutdown sequence, it is

generally used as a "fail-safe" to shut the system

down when the battery voltage is too low.

SDA is a bi-directional data line and SCL is a clock

input. The master device initiates a transaction by

issuing a START condition, defined by SDA

transitioning from high to low while SCL is high.

Data is transferred in 8-bit packets, beginning with

the MSB, and is clocked-in on the rising edge of

SCL. Each packet of data is followed by an

“Acknowledge” (ACK) bit, used to confirm that the

data was transmitted successfully.

Table 6:

SYSLEV Falling Threshold

For more information regarding the I²C 2-wire serial

interface, go to the NXP website: http://www.nxp.com.

SYSLEV Falling Threshold

SYSLEV[3:0]

(Hysteresis = 200mV)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Voltage Monitor and Interrupt

Programmable System Voltage Monitor

The ACT8935 features a programmable system-

voltage monitor, which monitors the voltage at

VSYS and compares it to

a programmable

threshold voltage. The programmable voltage

threshold is programmed by SYSLEV[3:0], as

shown in Table 6.

SYSLEV[ ] is set to 3.0V by default. There is a

200mV rising hysteresis on SYSLEV[ ] threshold

such that V_VSYSneeds to be 3.2V(typ) or higher in

order to power up the IC.

The nSYSSTAT[-] bit reflects the output of an

internal voltage comparator that monitors V_VSYS

relative to the SYSLEV[-] voltage threshold, the

value of nSYSTAT[-] = 1 when V_VSYSis lower than

the SYSLEV[-] voltage threshold, and nSYSTAT[-] =

0 when V_VSYSis higher than the SYSLEV[-] voltage

threshold. Note that the SYSLEV[-] voltage

threshold is defined for falling voltages, and that the

comparator produces about 200mV of hysteresis at

VSYS. As a result, once V_VSYSfalls below the

SYSLEV threshold, its voltage must increase by

more than about 200mV to clear that condition.

Precision Voltage Detector

The LBI input connects to one input of a precision

voltage comparator, which can be used to monitor a

system voltage such as the battery voltage. An

external resistive-divider network can be used to set

voltage monitoring thresholds, as shown in

Functional Block Diagram. The output of the

comparator is present at the nLBO open-drain

output.

After the IC is powered up, the ACT8935 responds

in one of two ways when the voltage at VSYS falls

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ACT8935

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Thermal Shutdown

The ACT8935 integrates thermal shutdown

protection circuitry to prevent damage resulting

from excessive thermal stress, as may be

encountered under fault conditions. This circuitry

disables all regulators if the ACT8935 die

temperature exceeds 160°C, and prevents the

regulators from being enabled until the IC

temperature drops by 20°C (typ).

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ACT8935

Rev 4, 17-Sep-13

STEP-DOWN DC/DC REGULATORS

Despite the advantages of ceramic capacitors, care

must be taken during the design process to ensure

stable operation over the full operating voltage and

temperature range. Ceramic capacitors are

available in a variety of dielectrics, each of which

exhibits different characteristics that can greatly

affect performance over their temperature and

voltage ranges.

General Description

The ACT8935 features three synchronous, fixed-

frequency, current-mode PWM step down

converters that achieve peak efficiencies of up to

97%. REG1 and REG3 are capable of supplying up

to 900mA of output current, while REG2 supports

up to 700mA. These regulators operate with a fixed

frequency of 2MHz, minimizing noise in sensitive

applications and allowing the use of small external

components.

Two of the most common dielectrics are Y5V and

X5R. Whereas Y5V dielectrics are inexpensive and

can provide high capacitance in small packages,

their capacitance varies greatly over their voltage

and temperature ranges and are not recommended

for DC/DC applications. X5R and X7R dielectrics

are more suitable for output capacitor applications,

as their characteristics are more stable over their

operating ranges, and are highly recommended.

100% Duty Cycle Operation

Each regulator is capable of operating at up to

100% duty cycle. During 100% duty-cycle

operation, the high-side power MOSFET is held on

continuously, providing a direct connection from the

input to the output (through the inductor), ensuring

the lowest possible dropout voltage in battery

powered applications.

Inductor Selection

REG1, REG2, and REG3 utilize current-mode

control and a proprietary internal compensation

scheme to simultaneously simplify external

component selection and optimize transient

performance over their full operating range. These

devices were optimized for operation with 2.2μH

inductors, although inductors in the 1.5μH to 3.3μH

range can be used. Choose an inductor with a low

DC-resistance, and avoid inductor saturation by

choosing inductors with DC ratings that exceed the

maximum output current by at least 30%.

Synchronous Rectification

REG1, REG2, and REG3 each feature integrated n-

channel synchronous rectifiers, maximizing

efficiency and minimizing the total solution size and

cost by eliminating the need for external rectifiers.

Soft-Start

When enabled, each output voltages tracks an

internal 400μs soft-start ramp, minimizing input

current during startup and allowing each regulator

to power up in a smooth, monotonic manner that is

independent of output load conditions.

Configuration Options

Output Voltage Programming

Compensation

By default, each regulator powers up and regulates

to its default output voltage. Once the system is

enabled, each regulator's output voltage may be

independently programmed to a different value,

typically in order to minimize the power

consumption of the microprocessor during some

operating modes. Program the output voltages via

the I²C serial interface by writing to the regulator's

VSET[-] register as shown in Table 8.

Each buck regulator utilizes current-mode control

and a proprietary internal compensation scheme to

simultaneously simplify external component

selection and optimize transient performance over

its full operating range. No compensation design is

required; simply follow a few simple guidelines

described below when choosing external

components.

Input Capacitor Selection

Enable / Disable Control

The input capacitor reduces peak currents and

noise induced upon the voltage source. A 4.7μF

ceramic capacitor is recommended for each

regulator in most applications.

During normal operation, each buck may be

enabled or disabled via the I²C interface by writing

to that regulator's ON[ ] bit. The regulator accept

rising or falling edge of ON[ ] bit as on/off signal. To

enable the regulator, clear ON[ ] to 0 first then set to

1. To disable the regulator, set ON[ ] to 1 first then

clear it to 0.

Output Capacitor Selection

For most applications, 22μF ceramic output

capacitors are recommended for REG1 and REG3,

while 15μF ceramic output capacitor is

recommended for REG2.

PWRSTAT Control Bit (REG3)

PWRSTAT[-] is a control bit which configures

REG3's behavior with respect to the PBIN input.

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ACT8935

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The Prima and Atlas IV processors require that

REG3 enable with PBIN, but then operate

independently of PBIN when implementing sleep

modes. PWRSTAT[ ] provides a convenient means

of doing so; PWRSTAT defaults to 0, in which case

REG3 is enabled when PBIN is asserted. Set

PWRSTAT[-] to 1, making REG3's enable state

independent of PBIN, prior to entering SLEEP

mode.

OK[ ] and Output Fault Interrupt

Each DC/DC features a power-OK status bit that

can be read by the system microprocessor via the

I²C interface. If an output voltage is lower than the

power-OK threshold, typically 7% below the

programmed regulation voltage, that regulator's

OK[ ] bit will be 0.

If a DC/DC's nFLTMSK[-] bit is set to 1, the

ACT8935 will interrupt the processor if that DC/DC's

output voltage falls below the power-OK threshold.

In this case, nIRQ will assert low and remain

asserted until either the regulator is turned off or

back in regulation, and the OK[ ] bit has been read

via I²C.

REG1, REG2, REG3 Turn-on Delay

Each of REG1, REG2 and REG3 features a

programmable Turn-on Delay which help ensure a

reliable qualification. This delay is programmed by

DELAY[2:0], as shown in Table 7.

Table 7:

PCB Layout Considerations

REGx/DELAY[ ] Turn-On Delay

High switching frequencies and large peak currents

make PC board layout an important part of step-

down DC/DC converter design. A good design

minimizes excessive EMI on the feedback paths

and voltage gradients in the ground plane, both of

which can result in instability or regulation errors.

DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 ms

2 ms

4 ms

Step-down DC/DCs exhibit discontinuous input

current, so the input capacitors should be placed as

close as possible to the IC, and avoiding the use of

via if possible. The inductor, input filter capacitor,

and output filter capacitor should be connected as

close together as possible, with short, direct, and

wide traces. The ground nodes for each regulator's

power loop should be connected at a single point in

a star-ground configuration, and this point should

be connected to the backside ground plane with

multiple via. The output node for each regulator

should be connected to its corresponding OUTx pin

through the shortest possible route, while keeping

sufficient distance from switching nodes to prevent

noise injection. Finally, the exposed pad should be

directly connected to the backside ground plane

using multiple via to achieve low electrical and

thermal resistance.

8 ms

16 ms

32 ms

64 ms

128 ms

Operating Mode

By default, REG1, REG2, and REG3 each operate

in fixed-frequency PWM mode at medium to heavy

loads, while automatically transitioning to

proprietary power-saving mode at light loads in

order to maximize standby battery life. In

applications where low noise is critical, force fixed-

frequency PWM operation across the entire load

current range, at the expense of light-load

efficiency, by setting the MODE[ ] bit to 1.

a

Table 8:

REGx/VSET[ ] Output Voltage Setting

REGx/VSET[5:3]

REGx/VSET[2:0]

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.250

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.500

2.600

2.700

2.800

2.900

3.000

3.100

3.200

3.300

3.400

3.500

3.600

3.700

3.800

3.900

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ACT8935

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LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS

or falling edge of ON[ ] bit as on/off signal. To

enable the regulator, clear ON[ ] to 0 first then set to

1. To disable the regulator, set ON[ ] to 1 first then

clear it to 0.

General Description

REG4, REG5, REG6, and REG7 are low-noise,

low-dropout linear regulators (LDOs) that are each

capable of supplying up to 150mA. Each LDO has

been optimized to achieve low noise and high-

PSRR, achieving more than 65dB PSRR at

frequencies up to 10kHz.

REG4, REG5, REG6, REG7 Turn-on Delay

Each of REG4, REG5, REG6 and REG7 features a

programmable Turn-on Delay which help ensure a

reliable qualification. This delay is programmed by

DELAY[2:0], as shown in Table 7.

Output Current Limit

Each LDO contains current-limit circuitry featuring a

current-limit fold-back function. During normal and

moderate overload conditions, the regulators can

support more than their rated output currents.

During extreme overload conditions, however, the

current limit is reduced by approximately 30%,

reducing power dissipation within the IC.

Output Discharge

Each of the ACT8935’s LDOs features an optional

output discharge function, which discharges the

output to ground through a 1.5kꢀ resistance when

the LDO is disabled. This feature may be enabled

or disabled by setting DIS[-]; set DIS[-] to 1 to

enable this function, clear DIS[-] to 0 to disable it.

Compensation

Low-Power Mode

The LDOs are internally compensated and require

very little design effort, simply select input and

output capacitors according to the guidelines below.

Each of ACT8935's LDOs features a LOWIQ[-] bit

which, when set to 1, reduces the LDO's quiescent

current by about 16%, saving power and extending

battery lifetime.

Input Capacitor Selection

Each LDO requires a small ceramic input capacitor

to supply current to support fast transients at the

input of the LDO. Bypassing each INL pin to GA

with 1μF. High quality ceramic capacitors such as

X7R and X5R dielectric types are strongly

recommended.

OK[ ] and Output Fault Interrupt

Each LDO features a power-OK status bit that can

be read by the system microprocessor via the

interface. If an output voltage is lower than the

power-OK threshold, typically 11% below the

programmed regulation voltage, the value of that

regulator's OK[-] bit will be 0.

Output Capacitor Selection

Each LDO requires a small 1.5μF ceramic output

capacitor for stability. For best performance, each

output capacitor should be connected directly

between the output and GA pins, as close to the

output as possible, and with a short, direct

connection. High quality ceramic capacitors such as

X7R and X5R dielectric types are strongly

recommended.

If a LDO's nFLTMSK[-] bit is set to 1, the ACT8935

will interrupt the processor if that LDO's output

voltage falls below the power-OK threshold. In this

case, nIRQ will assert low and remain asserted until

either the regulator is turned off or back in

regulation, and the OK[-] bit has been read via I²C.

PCB Layout Considerations

The ACT8935’s LDOs provide good DC, AC, and

noise performance over a wide range of operating

conditions, and are relatively insensitive to layout

considerations. When designing a PCB, however,

careful layout is necessary to prevent other circuitry

from degrading LDO performance.

Configuration Options

Output Voltage Programming

By default, each LDO powers up and regulates to

its default output voltage. Once the system is

enabled, each output voltage may be independently

programmed to a different value by writing to the

regulator's VSET[-] register via the I²C serial

interface as shown in Table 8.

A good design places input and output capacitors

as close to the LDO inputs and output as possible,

and utilizes a star-ground configuration for all

regulators to prevent noise-coupling through

ground. Output traces should be routed to avoid

close proximity to noisy nodes, particularly the SW

nodes of the DC/DCs.

Enable / Disable Control

During normal operation, each LDO may be

enabled or disabled via the I²C interface by writing

to that LDO's ON[ ] bit. The regulator accept rising

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ACT8935

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REFBP is a noise-filtered reference, and internally

has a direct connection to the linear regulator

controller. Any noise injected into REFBP will

directly affect the outputs of the linear regulators,

and therefore special care should be taken to

ensure that no noise is injected to the outputs via

REFBP. As with the LDO output capacitors, the

REFBP bypass capacitor should be placed as close

to the IC as possible, with short, direct connections

to the star-ground. Avoid the use of via whenever

possible. Noisy nodes, such as from the DC/DCs,

should be routed as far away from REFBP as

possible.

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ACT8935

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ActivePath^TMCHARGER

In an input over-voltage condition this circuit limits

V_VSYSto 4.6V, protecting any circuitry connected to

VSYS from the over-voltage condition, which may

exceed this circuitry's voltage capability. This circuit

is capable of withstanding input voltages of up to

12V.

General Description

The ACT8935 features an advanced battery

charger that incorporates the patent-pending

ActivePath architecture for system power selection.

This combination of circuits provides a complete,

advanced battery-management system that

automatically selects the best available input

supply, manages charge current to ensure system

power availability, and provides a complete, high-

accuracy (±0.5%), thermally regulated, full-featured

single-cell linear Li+ charger that can withstand

input voltages of up to 12V.

Table 9:

Input Over-Voltage Protection Setting

OVPSET[1]

OVPSET[0]

OVP THRESHOLD

0

1

0

1

0

1

6.6V

7.0V

7.5V

8.0V

ActivePath Architecture

The ActivePath architecture performs three

important functions:

Input Supply Overload Protection

1) System Configuration Optimization

2) Input Protection

The ActivePath circuitry monitors and limits the total

current drawn from the input supply to a value set

by the ACIN and CHGLEV inputs, as well as the

resistor connected to ISET. Drive ACIN to a logic-

low for “USB Mode”, which limits the input current to

either 100mA, when CHGLEV is driven to a logic-

low, or 450mA, when CHGLEV is driven to a logic-

high. Drive ACIN to a logic-high for “AC-Mode”,

which limits the input current to 2A, typically.

3) Battery-Management

System Configuration Optimization

The ActivePath circuitry monitors the state of the

input supply, the battery, and the system, and

automatically reconfigures itself to optimize the

power system. If a valid input supply is present,

ActivePath powers the system from the input while

charging the battery in parallel. This allows the

battery to charge as quickly as possible, while

supplying the system. If a valid input supply is not

present, ActivePath powers the system from the

battery. Finally, if the input is present and the

system current requirement exceeds the capability

of the input supply, ActivePath allows system power

to be drawn from both the battery and the input

supply.

Input Under Voltage Lockout

If the input voltage applied to CHGIN falls below

3.5V (typ), an input under-voltage condition is

detected and the charger is disabled. Once an input

under-voltage condition is detected, a new charge

cycle will initiate when the input exceeds the under-

voltage threshold by at least 500mV.

Battery Management

The ACT8935 features a full-featured, intelligent

charger for Lithium-based cells, and was designed

specifically to provide a complete charging solution

with minimum system design effort.

Input Protection

Input Over-Voltage Protection

The ActivePath circuitry features input over-voltage

protection circuitry. This circuitry disables charging

when the input voltage exceeds the voltage set by

OVPSET[-] as shown in table 13, but stands off the

input voltage in order to protect the system. Note

that the adjustable OVP threshold is intended to

provide the charge cycle with adjustable immunity

against upward voltage transients on the input, and

is not intended to allow continuous charging with

input voltages above the charger's normal operating

voltage range. Independent of the OVPSET[-]

setting, the charge cycle is not allowed to resume

until the input voltage falls back into the charger's

normal operating voltage range (i.e. below 6.0V).

The core of the charger is a CC/CV (Constant-

Current/Constant-Voltage), linear-mode charge

controller. This controller incorporates current and

voltage sense circuitry, an internal 70mꢀ power

MOSFET, thermal-regulation circuitry,

a

full-

featured state machine that implements charge

control and safety features, and circuitry that

eliminates the reverse blocking diode required by

conventional charger designs.

The charge termination voltage is highly accurate

(±0.5%), and features a selection of charge safety

time-out periods that protect the system from

operation with damaged cells. Other features

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ACT8935

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include pin-programmable fast-charge current and

one current-limited nSTAT output that can directly

drive LED indicator or provide a logic-level status

a logic-high, or 100mA, if CHGLEV is driven to a

logic-low.

The ACT8935's charge current settings are

summarized in Table 10.

signal to the host microprocessor.

Note that the actual charge current may be limited

to a current lower than the programmed fast charge

current due to the ACT8935’s internal thermal

regulation loop. See the Thermal Regulation section

for more information.

Dynamic Charge Current Control (DCCC)

The ACT8935's ActivePath charger features

dynamic charge current control (DCCC) circuitry,

which acts to ensure that the system remains

powered while operating within the maximum output

capability of the power adapter. The DCCC circuitry

continuously monitors V_VSYS, and if the voltage at

VSYS drops by more than 200mV, the DCCC

circuitry automatically reduces charge current in

order to prevent V_VSYSfrom continuing to drop.

Charger Input Interrupts

In order to ease input supply detection and

eliminate the size and cost of external detection

circuitry, the charger has the ability to generate

interrupts based upon the status of the input supply.

This function is capable of generating an interrupt

when the input is connected, disconnected, or both.

An interrupt is generated any time the input supply

is connected when INSTAT[ ] bit is set to 1 and the

INCON[-] bit is set to 1, and an interrupt is

generated any time the input supply is disconnected

when INSTAT[ ] bit is set to 1 and the INDIS[ ] bit is

set to 1.

Charge Current Programming

The ACT8935's ActivePath charger features a

flexible charge current-programming scheme that

combines the convenience of internal charge

current programming with the flexibility of resistor

based charge current programming. Current limits

and charge current programming are managed as a

function of the ACIN and CHGLEV pins, in

combination with R^ISET, the resistance connected to

the ISET pin.

INDAT[-] indicates the status of the CHGIN input

supply. A value of 1 indicates that a valid CHGIN

input (CHGIN UVLO Threshold<V_CHGIN<CHGIN

OVP Threshold) is present, a value of 0 indicates a

valid input is not present.

ACIN is a logic input that configures the current-limit

of ActivePath's linear regulator as well as that of the

battery charger. ACIN features a precise 1.2V logic

threshold, so that the input voltage detection

threshold may be adjusted with a simple resistive

voltage divider. This input also allows a simple, low-

cost dual-input charger switch to be implemented

with just a few, low-cost components.

When an interrupt is generated by the input supply,

reading the INSTAT[ ] returns a value of 1.

INSTAT [ ] is automatically cleared to 0 upon

reading. When no interrupt is generated by the

input supply, reading the INSTAT[ ] returns a value

of 0.

When the voltage at ACIN is above the 1.2V

threshold, the charger operates in “AC-Mode” with a

charge current programmed by R^ISET, and the RISET

is given by:

When responding to an Input Status Interrupt, it is

often useful to know the state of the ACIN input. For

example, in

a

dual-input charger application

knowing the state of the ACIN input can identify

which type of input supply has been connected. The

state of the ACIN input can be read at any time by

reading the ACINSTAT[-] bit, where a value of 1

indicates that the voltage at ACIN is above the 1.2V

threshold (indicating that a wall-cube has been

attached), and a value of 0 indicates that the

voltage is below this threshold (indicating that ACIN

input is not valid and USB supply input is selected).

R_ISET(kꢀ) = 2336 × (1V/I_CHG(mA)) - 0.205

With a given R_ISETthen charge current will reduce 5

times when CHGLEV is driven low.

When ACIN is below the 1.2V threshold, the

charger operates in “USB-Mode”, with a maximum

CHGIN input current and charge current defined by

the CHGLEV input; 450mA, if CHGLEV is driven to

Table 10:

ACIN and CHGLEV Inputs

CHARGE CURRENT

PRECONDITION CHARGE CURRENT

(mA)

ACIN

CHGLEV

(mA)

0

1

0

1

0

1

90

45

450

45

I

_CHG/5

I_CHG

10% × I_CHG

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Figure 7:

Typical Li+ charge profile and ACT8935 charge states

A: PRECONDITION State

B: FAST-CHARGE State

C: TOP-OFF State

D: END-OF-CHARGE State

Figure 8:

Charger State Diagram

TEMP NOT OK

ANY STATE

(V_CHGIN< V_BAT) OR (V_CHGIN< V_CHGINUVLO)

OR (V_CHGIN> V_OVP) OR (SUSCHG[ ] = 1)

SUSPEND

TEMP-FAULT

(V_CHGIN> V_BAT) AND (V_CHGIN> V_CHGINUVLO)

AND (V_CHGIN< V_OVP) AND (SUSCHG[ ] = 0)

TEMP OK

PRECONDITION

TIME-OUT-FAULT

PRECONDITION

Time-out

(V_BAT> 2.85V) AND

(T_QUAL= 32ms)

Total Time-out

FAST-CHARGE

(V_BAT= V_TERM) AND

(T_QUAL= 32ms)

(V_BAT< V_TERM- 205mV )

AND (T_QUAL= 32ms)

TOP-OFF

(I_BAT< 10% x I_CHG) OR (Total

Time-out) AND (T_QUAL= 32ms)

END-OF-CHARGE

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minimizing battery current drain and allowing the

cell to “relax”. The charger continues to monitor the

cell voltage, and re-initiates a charging sequence if

the cell voltage drops to 205mV (typ) below the

charge termination voltage.

Charge-Control State Machine

PRECONDITION State

new charging cycle begins with the

A

PRECONDITION state, and operation continues in

this state until V^BATexceeds the Precondition

Threshold Voltage. When operating in

PRECONDITION state, the cell is charged at 10%

of the programmed maximum fast-charge constant

SUSPEND State

The state-machine jumps to the SUSPEND state

any time the battery is removed, and any time the

input voltage either falls below the CHGIN UVLO

threshold or exceeds the OVP threshold. Once

none of these conditions are present, a new charge

cycle initiates.

current, I_CHG

.

Once V^BATreaches the Precondition Threshold

Voltage, the state machine jumps to the FAST-

CHARGE state. If V^BATdoes not reach the

Precondition Threshold Voltage before the

Precondition Time-out period expires, then the state

machine jumps to the TIME-OUT-FAULT state in

order to prevent charging a damaged cell. See the

Charge Safety Timers section for more information.

A charging cycle may also be suspended manually

by setting the SUSPEND[ ] bit. In this case, initiate

a new charging sequence by clearing SUSPEND[ ]

to 0.

State Machine Interrupts

FAST-CHARGE State

The charger features the ability to generate

interrupts when the charger state machine

transitions, based upon the status of the CHG_ bits.

Set CHGEOCIN[ ] bit to 1 and CHGSTAT[ ] bit to 1

to generate an interrupt when the charger state

machine goes into the END-OF-CHARGE (EOC)

state. Set CHGEOCOUT[ ] bit to 1 and CHGSTAT[ ]

bit to 1 to generate an interrupt when the charger

state machine exits the EOC state.

In the FAST-CHARGE state, the charger operates

in constant-current (CC) mode and regulates the

charge current to the current set by R^ISET. Charging

continues in CC mode until V^BATreaches the charge

termination voltage (V^TERM), at which point the state-

machine jumps to the TOP-OFF state. If V_BATdoes

not reach V^TERMbefore the total time out period

expires then the state-machine will jump to the

“EOC” state and will re-initiate a new charge cycle

after 32ms “relax”. See the Current Limits and

Charge Current Programming sections for more

information about setting the maximum charge

current.

CHGDAT[ ] indicates the status of the charger state

machine. A value of 1 indicates that the charger

state machine is in END-OF-CHARGE state, a

value of 0 indicates the charger state machine is in

other states.

When an interrupt is generated by the charger state

machine, reading the CHGSTAT[ ] returns a value

of 1. CHGSTAT[ ] is automatically cleared to 0 upon

reading. When no interrupt is generated by the

charger state machine, reading the CHGSTAT[ ]

returns a value of 0.

TOP-OFF State

In the TOP-OFF state, the cell charges in constant-

voltage (CV) mode. In CV mode operation, the

charger regulates its output voltage to the 4.20V

charge termination voltage, and the charge current

is naturally reduced as the cell approaches full

charge. Charging continues until the charge current

drops to END-OF-CHARGE current threshold, at

which point the state machine jumps to the END-

OF-CHARGE (EOC) state.

For additional information about the charge cycle,

CSTATE[0:1] may be read at any time via I²C to

determine the current charging state.

Table 11:

If the state-machine does not jump out of the TOP-

OFF state before the Total-Charge Time-out period

expires, the state machine jumps to the EOC state

and will re-initiate a new charge cycle if V_BATfalls

below termination voltage 205mV (typ). For more

information about the charge safety timers, see the

Charging Safety Times section.

Charging Status Indication

CSTATE[0] CSTATE[1] STATE MACHINE STATUS

1

0

PRECONDITION State

FAST-CHARGE/

TOP-OFF State

END-OF-CHARGE (EOC) State

0

1

0

END-OF-CHARGE State

In the END-OF-CHARGE (EOC) state, the charger

SUSPEND/DISABLED/

FAULT State

presents

a

high-impedance to the battery,

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Table 13:

Thermal Regulation

Total Safety Timer Setting

The charger features an internal thermal regulation

loop that monitors die temperature and reduces

charging current as needed to ensure that the die

temperature does not exceed the thermal regulation

threshold of 110°C. This feature protects against

excessive junction temperature and makes the

device more accommodating to aggressive thermal

designs. Note, however, that attention to good

thermal designs is required to achieve the fastest

possible charge time by maximizing charge current.

TOTAL TIME-OUT

PERIOD

TOTTIMO[1] TOTTIMO[0]

0

1

0

1

0

1

3 hrs

4 hrs

5 hrs

Disabled

Charge Status Indicator

Charge Safety Timers

The charger provides a charge-status indicator

output, nSTAT. nSTAT is an open-drain output

which sinks current when the charger is in an

active-charging state, and is high-Z otherwise.

nSTAT features an internal 8mA current limit, and is

capable of directly driving a LED without the need

of a current-limiting resistor or other external

circuitry. To drive an LED, simply connect the LED

between nSTAT pin and an appropriate supply,

such as VSYS. For a logic-level charge status

indication, simply connect a resistor from nSTAT to

an appropriate voltage supply.

The charger features programmable charge safety

timers which help ensure a safe charge by

detecting potentially damaged cells. These timers

are programmable via the PRETIMO[1:0] and

TOTTIMO[1:0] bits, as shown in Table 11 and Table

13. Note that in order to account for reduced charge

current resulting from DCCC operation in thermal

regulation mode, the charge time-out periods are

extended proportionally to the reduction in charge

current. As a result, the actual safety period may

exceed the nominal timer period.

Charger Timer Interrupts

Table 14:

The charger features the ability to generate

interrupts based upon the status of the charge

Charging Status Indication

STATE

PRECONDITION

FAST-CHARGE

TOP-OFF

nSTAT

Active

High-Z

timers. Set the TIMRPRE[

]

bit to

1

and

TIMRSTAT[ ] bit to 1 to generate an interrupt when

the Precondition Timer expires. Set the TIMRTOT[ ]

bit to 1 and TIMRSTAT[ ] bit to 1 to generate an

interrupt when the Total-Charge Timer expires.

TIMRDAT[ ] indicates the status of the charge

timers. A value of 1 indicates a precondition time-

out or a total charge time-out occurs, a value of 0

indicates other cases.

END-OF-CHARGE

SUSPEND

TEMPERATURE FAULT

TIME-OUT-FAULT

When an interrupt is generated by the charge

timers, reading the TIMRSTAT[ ] returns a value of

1. TIMRSTAT[ ] is automatically cleared to 0 upon

reading. When no interrupt is generated by the

charge timers, reading the TIMRSTAT[ ] returns a

value of 0.

Reverse-Current Protection

The charger includes internal reverse-current

protection circuitry that eliminates the need for

blocking diodes, reducing solution size and cost as

well as dropout voltage relative to conventional

battery chargers. When the voltage at CHGIN falls

below V^BAT, the charger automatically reconfigures

its power switch to minimize current drawn from the

battery.

Table 12:

PRECONDITION Safety Timer Setting

PRECONDITION

PRETIMO[1] PRETIMO[0]

TIME-OUT PERIOD

Battery Temperature Monitoring

0

1

0

1

0

1

40 mins

60 mins

80 mins

Disabled

In a typical application, the TH pin is connected to

the battery pack's thermistor input, as shown in

Figure 9. The charger continuously monitors the

temperature of the battery pack by injecting a

102μA (typ) current into the thermistor (via the TH

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pin) and sensing the voltage at TH. The voltage at

TH is continuously monitored, and charging is

suspended if the voltage at TH exceeds either of

the internal V^THHand VTHL thresholds of 0.5V and

2.51V, respectively.

Figure 9:

Simple Configuration

The net resistance (from TH to GA) required to

cross the thresholds are given by:

102μA × R^NOM× kHOT = 0.5V → RNOM × kHOT ≈ 5kꢀ

102μA × R^NOM× kCOLD = 2.51V → RNOM × kCOLD ≈

25kꢀ

where R^NOMis the nominal thermistor resistance at

room temperature, and k^HOTand kCOLD represent the

ratios of the thermistor's resistance at the desired

hot and cold thresholds, respectively, to the

resistance at 25°C.

Battery Temperature Interrupts

In order to ease detecting the status of the battery

temperature, the charger features the ability to

generate interrupts based upon the status of the

battery temperature. Set the TEMPOUT[ ] bit to 1

and TEMPSTAT[ ] bit to 1 to generate an interrupt

when battery temperature goes out of the valid

temperature range. Set the TEMPIN[ ] bit to 1 and

TEMPSTAT[ ] bit to 1 to generate an interrupt when

battery temperature returns to the valid range.

TEMPDAT[ ] indicates the status of the battery

temperature. A value of 1 indicates the battery

temperature is inside of the valid range, a value of 0

indicates the battery is outside of the valid range.

When an interrupt is generated by the battery

temperature event, reading the TEMPSTAT[ ]

returns a value of 1. TEMPSTAT[ ] is automatically

cleared to 0 upon reading. When no interrupt is

generated by the battery temperature event,

reading the TEMPSTAT[ ] returns a value of 0.

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ACT8935

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TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS

DIMENSION IN

MILLIMETERS

DIMENSION IN

INCHES

SYMBOL

MIN

MAX

MIN

MAX

A

A1

A2

b

0.700

0.800

0.028

0.031

0.200 REF

0.008 REF

0.000

0.150

4.900

3.450

0.050

0.250

5.100

3.750

0.000

0.006

0.193

0.136

0.002

0.010

0.201

0.148

D

E

D2

E2

e

0.400 BSC

0.016 BSC

L

0.300

0.500

0.012

0.020

R

0.300

0.012

Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each

product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use

as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of

the use of any product or circuit described in this datasheet, nor does it convey any patent license.

Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact

sales@active-semi.com or visit http://www.active-semi.com.

is a registered trademark of Active-Semi.

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Mouser Electronics

Authorized Distributor

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Active-Semi:

ACT8935


型号：	ACT8935QJ1E2-T
厂家：	ACTIVE-SEMI, INC
描述：	Advanced PMU for SiRF PrimaTM and Atlas IVTM
文件：	总46页 (文件大小：710K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ACT8935QJ1E2-T [ACTIVE-SEMI]

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