ACT8937QJ206-T_技术文档

®

ACT8937

Rev 0, 21-Sep-10

Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors

FEATURES

GENERAL DESCRIPTION

The ACT8937 is a complete, cost effective, highly-

efficient ActivePMU^TMpower management solution,

optimized for the unique power, voltage-

sequencing, and control requirements of the

Samsung S5PC100, S5PC110 and S5PV210

processors.

• Optimized for Samsung S5PC100, S5PC110 and

S5PV210 Processors

• Three Step-Down DC/DC Converters

• Four Low-Dropout Linear Regulators

• Integrated ActivePath^TMCharger

• I²C^TMSerial Interface

• Advanced Enable/Disable Sequencing Controller

• Minimal External Components

This device features three step-down DC/DC

converters and four low-noise, low-dropout linear

regulators, along with a complete battery charging

solution featuring the advanced ActivePath^TM

system-power selection function.

• Tiny 5×5mm TQFN55-40 Package

− 0.75mm Package Height

The three DC/DC converters utilize

a high-

efficiency, fixed-frequency (2MHz), current-mode

PWM control architecture that requires a minimum

number of external components. Two DC/DCs are

capable of supplying up to 1100mA of output

current, while the third supports up to 1200mA. All

four low-dropout linear regulators are high-

performance, low-noise, regulators that supply up to

150mA, 150mA, 250mA, and 250mA, respectively.

− Pb-Free and RoHS Compliant

The ACT8937 is available in a compact, Pb-Free

and RoHS-compliant TQFN55-40 package.

TYPICAL APPLICATION DIAGRAM

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I²C^TMis a trademark of NXP.

®

ACT8937

Rev 0, 21-Sep-10

TABLE OF CONTENTS

General Information.....................................................................................................................................p. 01

Functional Block Diagram............................................................................................................................p. 03

Ordering Information....................................................................................................................................p. 04

Pin Configuration .........................................................................................................................................p. 04

Pin Descriptions...........................................................................................................................................p. 05

Absolute Maximum Ratings.........................................................................................................................p. 07

I²C Interface Electrical Characteristics ........................................................................................................p. 08

Global Register Map....................................................................................................................................p. 09

Register and Bit Descriptions ......................................................................................................................p. 10

System Control Electrical Characteristics....................................................................................................p. 15

Step-Down DC/DC Electrical Characteristics..............................................................................................p. 16

Low-Noise LDO Electrical Characteristics...................................................................................................p. 17

ActivePath^TMCharger Electrical Characteristics..........................................................................................p. 18

Typical Performance Characteristics...........................................................................................................p. 20

System control information ..........................................................................................................................p. 27

Interfacing with the Samsung S5PV210 ..........................................................................................p. 27

Control Signals.................................................................................................................................p. 28

Push-Button Control.........................................................................................................................p. 29

Control Sequences...........................................................................................................................p. 29

Functional Description .................................................................................................................................p. 32

I²C Interface .....................................................................................................................................p. 32

Housekeeping Functions..................................................................................................................p. 32

Step-Down DC/DC Regulators ....................................................................................................................p. 33

General Description..........................................................................................................................p. 33

100% Duty Cycle Operation.............................................................................................................p. 33

Synchronous Rectification................................................................................................................p. 33

Soft-Start ..........................................................................................................................................p. 33

Compensation ..................................................................................................................................p. 33

Configuration Options.......................................................................................................................p. 33

OK[ ] and Output Fault Interrupt.......................................................................................................p. 34

PCB Layout Considerations.............................................................................................................p. 34

Low-Noise, Low-Dropout Linear Regulators................................................................................................p. 35

General Description..........................................................................................................................p. 35

Output Current Limit.........................................................................................................................p. 35

Compensation ..................................................................................................................................p. 35

Configuration Options.......................................................................................................................p. 35

OK[ ] and Output Fault Interrupt.......................................................................................................p. 35

PCB Layout Considerations.............................................................................................................p. 35

ActivePath^TMCharger ..................................................................................................................................p. 37

General Description..........................................................................................................................p. 37

ActivePath Architecture....................................................................................................................p. 37

System Configuration Optimization..................................................................................................p. 37

Input Protection ................................................................................................................................p. 37

Battery Management........................................................................................................................p. 37

Charge Current Programming..........................................................................................................p. 38

Charge-Control State Machine.........................................................................................................p. 40

Thermal Regulation..........................................................................................................................p. 41

Charge Safety Timers ......................................................................................................................p. 41

Charge Status Indicator....................................................................................................................p. 41

Reverse-Current Protection .............................................................................................................p. 41

Battery Temperature Monitoring ......................................................................................................p. 41

TQFN55-40 Package Outline and Dimensions ...........................................................................................p. 43

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®

ACT8937

Rev 0, 21-Sep-10

FUNCTIONAL BLOCK DIAGRAM

Active- Semi

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®

ACT8937

Rev 0, 21-Sep-10

ORDERING INFORMATION^ꢀꢁ

V_OUT1

V_OUT2/V_STBY2

V_OUT3/V_STBY3

V_OUT4V_OUT5V_OUT6V_OUT7

PROCESSOR

PART NUMBER_ꢂ

ACT8937QJ2PQ-T

3.3V

1.3V/1.2V

1.35V/1.2V

1.2V

1.1V

1.2V

1.1V

1.2V

1.1V

3.3V

S5PC100

S5PC110

S5PV210

ACT8937QJ21C-T

ACT8937QJ206-T

3.3V

1.8V

1.1V/1.1V

1.25V/1.25V

S5PC110

S5PV210

1.1V

3.3V

ꢀ: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means

semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.

ꢁ: Standard product options are identified in this table. Contact factory for custom options. Minimum order quantity is 12,000 units.

ꢃ: To select V_STBYxas a output regulation voltage of REGx. Drive VSEL to a logic high. The V_STBYxcan be set by software via I²C

interface, refer to appropriate sections of this datasheet for V_STBYxsetting.

ꢂ: ACT8937QJ2PQ-T is optimized for S5PC100, ACT8937QJ21C-T and ACT8937QJ206-T are optimized for S5PC110 and S5PV210.

ACT8937QJ_ _ _-T

Active-Semi

Product Number

Package Code

Pin Count

Option Code

Tape and Reel

PIN CONFIGURATION

TOP VIEW

REFBP

OUT1

GA

BAT

nSTAT

SDA

OUT4

OUT5

INL

Active- Semi

SCL

VSEL

TH

ACT8937

OUT7

OUT6

nPBIN

PWRHLD

ISET

CHGLEV

ACIN

EP

Thin - QFN (TQFN55-40)

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®

ACT8937

Rev 0, 21-Sep-10

PIN DESCRIPTIONS

NAME

DESCRIPTION

Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is

discharged to GA in shutdown.

1

REFBP

Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the

internal feedback network to the output voltage.

2

3

4

5

6

7

8

OUT1

GA

Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3

together at a single point as close to the IC as possible.

Output Voltage for REG4. Capable of delivering up to 150mA of output current. Connect a 1.5µF

ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ when disabled.

OUT4

OUT5

INL

Output Voltage for REG5. Capable of delivering up to 150mA of output current. Connect a 1.5µF

ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ when disabled.

Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic

capacitor placed as close as possible to the IC.

Output Voltage for REG7. Capable of delivering up to 250mA of output current. Connect a 2.2µF

ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ when disabled.

OUT7

OUT6

Output Voltage for REG6. Capable of delivering up to 250mA of output current. Connect a 2.2µF

ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ when disabled.

Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN

directly to GA to assert a manual reset condition. Refer to the nPBIN Input section for more

information. nPBIN is internally pulled up to VSYS through a 35kꢀ resistor.

9

nPBIN

10

11

PWRHLD Power Hold Input. Refer to the Control Sequences section for more information.

nRSTO

nIRQ

Active Low Reset Output. See the nRSTO Output section for more information.

Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or a

charger interrupt occurs. See the nIRQ Output section for more information.

12

13

Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the

nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.

nPBSTAT

Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the

IC as possible.

14

15

16

GP3

SW3

VP3

Switching Node Output for REG3. Connect this pin to the switching end of the inductor.

Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as

possible to the IC.

Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the

internal feedback network to the output voltage.

17

18

19

OUT3

PWREN Power Enable Input. Refer to the Control Sequences section for more information.

Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than

nLBO

1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information.

Low Battery Input. The input voltage will be compared to 1.2V and output of this comparison

drives nLBO. See the Precision Voltage Detector section for more information.

20

LBI

21

22

ACIN

AC Input Supply Detection. See the Charge Current Programming section for more information.

CHGLEV Charge Current Selecting Input. See the Charge Current Programming section for more information.

Charge Current Set. Program the maximum charge current by connecting a resistor (R_ISET) between

ISET and GA. See the Charge Current Programming section for more information.

23

24

ISET

Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102µA current

internally. See the Battery Temperature Monitoring section for more information.

TH

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ACT8937

Rev 0, 21-Sep-10

PIN DESCRIPTIONS CONT’D

NAME

DESCRIPTION

Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.

Drive to logic high to select secondary output voltage. See the Output Voltage Programming

section for more information.

25

VSEL

26

27

SCL

SDA

Clock Input for I²C Serial Interface.

Data Input for I²C Serial Interface. Data is read on the rising edge of SCL.

Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it

to directly drive an indicator LED without additional external components. See the Charge Status

Indicator section for more information.

28

nSTAT

29, 30

31, 32

BAT

Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)

System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.

VSYS

Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to

the IC as possible. The battery charger is automatically enabled when a valid voltage is present

on CHGIN .

33

34

CHGIN

OUT2

Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the

internal feedback network to the output voltage.

Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as

possible to the IC.

35

36

37

38

39

VP2

SW2

GP12

SW1

VP1

Switching Node Output for REG2. Connect this pin to the switching end of the inductor.

Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as

close to the IC as possible.

Switching Node Output for REG1. Connect this pin to the switching end of the inductor.

Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as

possible to the IC.

40

NC

EP

No Connect. Not internally connected.

EP

Exposed Pad. Must be soldered to ground on PCB.

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ACT8937

Rev 0, 21-Sep-10

ABSOLUTE MAXIMUM RATINGS^ꢀ

PARAMETER

VALUE

UNIT

V

VP1, VP2 to GP12

VP3 to GP3

-0.3 to +6

BAT, VSYS, INL to GA

V

CHGIN to GA

t < 1ms and duty cycle <1%

Steady State

-0.3 to +18

-0.3 to +14

V

SW1, OUT1 to GP12

SW2, OUT2 to GP12

SW3, OUT3 to GP3

-0.3 to (V_VP1+ 0.3)

-0.3 to (V_VP2+ 0.3)

-0.3 to (V_VP3+ 0.3)

V

nPBIN, ACIN, CHGLEV, ISET, TH, nSTAT, SCL, SDA, REFBP, PWRHLD, PWREN,

VSEL, nLBO, LBI, nPBSTAT, nIRQ, nRSTO to GA

-0.3 to +6

V

OUT4, OUT5, OUT6, OUT7 to GA

GP12, GP3 to GA

-0.3 to (V_INL+ 0.3)

-0.3 to +0.3

-40 to 85

V

Operating Ambient Temperature

Maximum Junction Temperature

°C

125

Maximum Power Dissipation

2.7

W

TQFN55-40 (Thermal Resistance θ_JA= 30^oC/W)

Storage Temperature

-65 to 150

300

°C

Lead Temperature (Soldering, 10 sec)

ꢀ: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may

affect device reliability.

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ACT8937

Rev 0, 21-Sep-10

I²C INTERFACE ELECTRICAL CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

SCL, SDA Input Low

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_VSYS= 3.1V to 5.5V, T_A= -40ºC to 85ºC

0.35

SCL, SDA Input High

SDA Leakage Current

SCL Leakage Current

SDA Output Low

V

_VSYS= 3.1V to 5.5V, T_A= -40ºC to 85ºC

1.55

V

1

µA

V

8

18

I

_OL= 5mA

0.35

SCL Clock Period, t_SCL

SDA Data Setup Time, t_SU

SDA Data Hold Time, t_HD

Start Setup Time, t_ST

Stop Setup Time, t_SP

1.5

100

300

100

µs

ns

For Start Condition

For Stop Condition

Figure 1:

I²C Compatible Serial Bus Timing

t_SCL

SCL

t_ST

t_HD

t_SU

t_SP

SDA

Start

condition

Stop

condition

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ACT8937

Rev 0, 21-Sep-10

GLOBAL REGISTER MAP

BITS

OUTPUT ADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

NAME

DEFAULT^ꢀ

NAME

TRST nSYSMODE nSYSLEVMSK nSYSSTAT SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]

SYS

0x00

0x01

0x20

0x21

0x22

0x30

0x31

0x32

0x40

0x41

0x42

0x50

0x51

0x54

0x55

0x60

0x61

0x64

0x65

0x70

0x71

0x78

0x79

0x7A

0

1

0

R

0

1

Reserved Reserved

Reserved

SCRATCH SCRATCH SCRATCH SCRATCH

SYS

DEFAULT^ꢀ

0

NAME

Reserved Reserved

VSET1[5]

VSET1[4]

VSET1[3]

VSET1[2]

VSET1[1]

VSET1[0]

REG1

REG2

REG3

REG4

REG5

REG6

REG7

APCH

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

VSET2[4]

1

VSET2[3]

1

0

VSET2[2]

0

VSET2[1]

0

1

Reserved Reserved

VSET2[5]

VSET2[0]

0

ON

0

PHASE

0

1

NAME

MODE

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

R

Reserved Reserved

VSET1[5]

VSET1[4]

VSET1[3]

VSET1[2]

VSET1[1]

VSET1[0]

0

1

VSET2[4]

1

0

VSET2[3]

0

1

VSET2[2]

1

0

VSET2[1]

0

NAME

Reserved Reserved

VSET2[5]

VSET2[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

ON

0

PHASE

0

MODE

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

0

1

0

R

NAME

Reserved Reserved

VSET1[5]

VSET1[4]

VSET1[3]

VSET1[2]

VSET1[1]

VSET1[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

VSET2[4]

1

VSET2[3]

1

0

VSET2[2]

0

VSET2[1]

0

1

Reserved Reserved

VSET2[5]

VSET2[0]

0

ON

0

PWRSTAT

0

1

NAME

MODE

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

VSET[4]

1

VSET[3]

0

1

VSET[2]

1

0

VSET[1]

0

R

Reserved Reserved

VSET[5]

VSET[0]

0

ON

0

DIS

1

0

NAME

LOWIQ

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

VSET[4]

1

VSET[3]

0

1

VSET[2]

1

0

VSET[1]

0

R

Reserved Reserved

VSET[5]

VSET[0]

0

ON

0

DIS

1

0

NAME

LOWIQ

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

VSET[4]

1

0

VSET[3]

0

VSET[2]

1

0

VSET[1]

0

R

Reserved Reserved

VSET[5]

VSET[0]

0

ON

0

DIS

1

0

NAME

LOWIQ

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

VSET[4]

1

VSET[3]

1

VSET[2]

0

VSET[1]

0

R

Reserved Reserved

VSET[5]

VSET[0]

0

ON

0

DIS

1

NAME

LOWIQ

DELAY[2]²DELAY[1]²DELAY[0]²nFLTMSK

OK

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

Reserved

0

1

Reserved

1

0

Reserved

0

Reserved

0

Reserved

0

R

Reserved

0

Reserved Reserved

0

1

NAME

SUSCHG Reserved TOTTIMO[1] TOTTIMO[0] PRETIMO[1] PRETIMO[0] OVPSET[1] OVPSET[0]

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

1

0

CHGSTAT

0

1

TIMRDAT

R

0

TEMPDAT

R

0

INDAT

R

0

TIMRSTAT TEMPSTAT

INSTAT

CHGDAT

0

R

NAME

TIMRTOT TEMPIN

INCON

CHGEOCIN TIMRPRE TEMPOUT

INDIS

0

CHGEOCOUT

DEFAULT^ꢀ

NAME

DEFAULT^ꢀ

0

CSTATE[0]

R

0

CSTATE[1]

R

0

Reserved

R

0

Reserved

R

Reserved Reserved

Reserved ACINSTAT

0

R

ꢀ: Default values of ACT8937QJ21C-T.

2: Regulator turn-on delay bits. Automatically cleared to default values when the input power is removed or falls below the system

UVLO.

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ACT8937

Rev 0, 21-Sep-10

REGISTER AND BIT DESCRIPTIONS

Table 1:

Global Register Map

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Reset Timer Setting. Defines the reset timeout threshold. See

nRSTO Output section for more information.

SYS

0x00

[7]

TRST

R/W

SYSLEV Mode Select. Defines the response to the SYSLEV

voltage detector, 1: Generate an interrupt when VSYS falls below

the programmed SYSLEV threshold, 0: automatic shutdown

when VSYS falls below the programmed SYSLEV threshold.

SYS

0x00

[6] nSYSMODE

R/W

System Voltage Level Interrupt Mask. Disabled interrupt by

default, set to 1 to enable this interrupt. See the Programmable

System Voltage Monitor section for more information

SYS

0x00

[5] nSYSLEVMSK R/W

System Voltage Status. Value is 1 when VSYS is higher than the

SYSLEV voltage threshold, value is 0 when VSYS is lower than

the system voltage detection threshold.

[4]

nSYSSTAT

R

System Voltage Detect Threshold. Defines the SYSLEV voltage

threshold. See the Programmable System Voltage Monitor

section for more information.

SYS

0x00

0x01

0x20

0x21

[3:0]

[7:4]

SYSLEV

-

R/W

R

Reserved.

Scratchpad Bits. Non-functional bits, maybe be used by user to

store system status information. Volatile bits, which are cleared

upon system shutdown.

SYS

[3:0] SCRATCH

REG1

[7:6]

[5:0]

[7:6]

[5:0]

-

Reserved.

Primary Output Voltage Selection. Valid when VSEL is driven low.

See the Output Voltage Programming section for more

information.

VSET1

-

R/W

R

Reserved.

Secondary Output Voltage Selection. Valid when VSEL is driven

high. See the Output Voltage Programming section for more

information.

VSET2

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit

to 0 to disable the regulator.

REG1

0x22

[7]

[6]

ON

R/W

Regulator Phase Control. Set bit to 1 for regulator to operate

180° out of phase with the oscillator, clear bit to 0 for regulator to

operate in phase with the oscillator.

PHASE

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-savings

mode under light-load conditions.

REG1

0x22

[5]

MODE

R/W

Regulator Turn-On Delay Control. See the REG1, REG2, REG3

Turn-on Delay section for more information.

REG1

0x22

[4:2]

[1]

DELAY

R/W

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG1

REG2

0x22

0x30

[0]

OK

-

R

[7:6]

Reserved.

Primary Output Voltage Selection. Valid when VSEL is driven low.

See the Output Voltage Programming section for more

information.

REG2

0x30

0x31

[5:0]

[7:6]

VSET1

-

R/W

R

Reserved.

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ACT8937

Rev 0, 21-Sep-10

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Secondary Output Voltage Selection. Valid when VSEL is

driven high. See the Output Voltage Programming section for

more information.

REG2

0x31

0x32

[5:0]

[7]

VSET2

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

ON

R/W

Regulator Phase Control. Set bit to 1 for regulator to operate

180° out of phase with the oscillator, clear bit to 0 for regulator

to operate in phase with the oscillator.

[6]

PHASE

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-

savings mode under light-load conditions.

REG2

0x32

[5]

MODE

R/W

Regulator Turn-On Delay Control. See the REG1, REG2,

REG3 Turn-on Delay section for more information.

REG2

0x32

[4:2]

[1]

DELAY

R/W

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG2

REG3

0x32

0x40

[0]

OK

-

R

[7:6]

Reserved.

Primary Output Voltage Selection. Valid when VSEL is driven

low. See the Output Voltage Programming section for more

information.

REG3

0x40

0x41

[5:0]

[7:6]

[5:0]

VSET1

-

R/W

R

Reserved.

Secondary Output Voltage Selection. Valid when VSEL is

driven high. See the Output Voltage Programming section for

more information.

VSET2

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

REG3

0x42

[7]

[6]

ON

R/W

Configures regulator behavior with respect to the nPBIN input.

Set bit to 0 to enable regulator when nPBIN is asserted.

PWRSTAT

Regulator Mode Select. Set bit to 1 for fixed-frequency PWM

under all load conditions, clear bit to 0 to transit to power-

savings mode under light-load conditions.

REG3

0x42

[5]

MODE

R/W

Regulator Turn-On Delay Control. See the REG1, REG2,

REG3 Turn-on Delay section for more information.

REG3

0x42

[4:2]

[1]

DELAY

R/W

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG3

REG4

0x42

0x50

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator, clear

bit to 0 to disable the regulator.

REG4

0x51

[7]

[6]

ON

R/W

Output Discharge Control. When activated, discharges LDO

output to GA through 1.5kꢀ when in shutdown. Set bit to 1 to

enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG4

0x51

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

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ACT8937

Rev 0, 21-Sep-10

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG4

REG5

0x51

0x54

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG5

0x55

[7]

[6]

ON

R/W

Output Discharge Control. When activated, discharges LDO

output to GA through 1.5kꢀ when in shutdown. Set bit to 1 to

enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG5

0x55

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6 , REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG5

REG6

0x55

0x60

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG6

0x61

[7]

[6]

ON

R/W

Output Discharge Control. When activated, discharges LDO

output to GA through 1.5kꢀ when in shutdown. Set bit to 1 to

enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG6

0x61

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG6

REG7

0x61

0x64

[0]

OK

-

R

[7:6]

[5:0]

Reserved.

Output Voltage Selection. See the Output Voltage

Programming section for more information.

VSET

R/W

Regulator Enable Bit. Set bit to 1 to enable the regulator,

clear bit to 0 to disable the regulator.

REG7

0x65

[7]

[6]

ON

R/W

Output Discharge Control. When activated, discharges LDO

output to GA through 1.5kꢀ when in shutdown. Set bit to 1 to

enable output voltage discharge in shutdown, clear bit to 0 to

disable this function.

DIS

LDO Low-IQ Mode Control. Set bit to 1 for low-power

operating mode, clear bit to 0 for normal mode.

REG7

0x65

[5]

[4:2]

[1]

LOWIQ

DELAY

R/W

Regulator Turn-On Delay Control. See the REG4, REG5,

REG6, REG7 Turn-on Delay section for more information.

Regulator Fault Mask Control. Set bit to 1 enable to fault-

interrupts, clear bit to 0 to disable fault-interrupts.

nFLTMSK

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ACT8937

Rev 0, 21-Sep-10

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Regulator Power-OK Status. Value is 1 when output voltage

exceeds the power-OK threshold, value is 0 otherwise.

REG7

APCH

0x65

0x70

[0]

OK

-

R

[7:0]

R/W

Reserved.

Charge Suspend Control Input. Set bit to 1 to suspend

charging, clear bit to 0 to allow charging to resume.

APCH

0x71

[7]

[6]

SUSCHG

-

R/W

Reserved.

Total Charge Timeout Selection. See the Charge Safety

Timers section for more information.

[5:4]

TOTTIMO

Precondition Charge Timeout Selection. See the Charge

Safety Timers section for more information.

APCH

0x71

0x78

[3:2]

[1:0]

[7]

PRETIMO

OVPSET

R/W

Input Over-Voltage Protection Threshold Selection. See the

Input Over-Voltage Protection section for more information.

Charge Timeout Interrupt Status. See the Charge Safety

Timers section for more information.

TIMRSTAT

TEMPSTAT

INSTAT

Temperature Interrupt Status. See the Battery Temperature

Monitoring section for more information.

[6]

Input Voltage Interrupt Status. See the Charge Current

Programming section for more information.

[5]

Charge State Interrupt Status. See the State Machine

Interrupts section for more information.

[4]

CHGSTAT

Charge Timer Interrupt Status. Value is 1 when precondition

timeout or total charge timeout fault occurs. Value is 0 in

other case.

APCH

0x78

[3]

[2]

[1]

TIMRDAT

TEMPDAT

INDAT

R

Temperature Status. Value is 1 when battery temperature is

outside of valid range. Value is 0 when battery temperature

is inside of valid range.

Input Voltage Status. Value is 1 when a valid input at

CHGIN is present. Value is 0 when a valid input at CHGIN

is not present.

Charge State Status. Value is 1 when in END-OF-CHARGE

State. Value is 0 when in other state.

APCH

0x78

0x79

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

CHGDAT

TIMRTOT

TEMPIN

R

Charge Timer Interrupt Control. See the Charge Safety

Timers section for more information.

R/W

Temperature Interrupt Control. See the Battery Temperature

Monitoring section for more information.

Input Voltage Interrupt Control. See the Charge Current

Programming section for more information.

INCON

Charge State Interrupt Control. See the State Machine

Interrupts section for more information.

CHGEOCIN

TIMRPRE

TEMPOUT

INDIS

Charge Timer Interrupt Control. See the Charge Safety

Timers section for more information.

Temperature Interrupt Control. See the Battery Temperature

Monitoring section for more information.

Input Voltage Interrupt Control. See the Charge Current

Programming section for more information.

Charge State Interrupt Control. See the State Machine

Interrupts section for more information.

APCH

0x79

0x7A

[0] CHGEOCOUT

[7:6]

R/W

R

-

Reserved.

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ACT8937

Rev 0, 21-Sep-10

REGISTER AND BIT DESCRIPTIONS CONT’D

OUTPUT ADDRESS BIT

NAME

ACCESS

DESCRIPTION

Charge State. Values indicate the current charging state. See

the State Machine Interrupts section for more information.

APCH

0x7A

[5:4]

[3:2]

CSTATE

-

R

Reserved.

ACIN Status. Indicates the state of the ACIN input, typically in

order to identify the type of input supply connected. Value is

1 when ACIN is above the 1.2V precision threshold, value is

0 when ACIN is below this threshold.

APCH

0x7A

[1]

[0]

ACINSTAT

-

R

Reserved.

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ACT8937

Rev 0, 21-Sep-10

SYSTEM CONTROL ELECTRICAL CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

Input Voltage Range

TEST CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

UVLO Threshold Voltage

UVLO Hysteresis

VSYS Rising

2.2

2.45

200

2.65

V

VSYS Falling

mV

REG1 and REG5 Enabled. REG2, REG3,

REG4, REG6 and REG7 Disabled

190

340

420

REG1, REG2, REG3, REG4 and REG5

Enabled. REG6 and REG7 Disabled

Supply Current

µA

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 Enabled

Shutdown Supply Current

Oscillator Frequency

All Regulators Disabled

8

2

18

µA

MHz

V

1.8

1.4

2.2

Logic High Input Voltage¹

Logic Low Input Voltage

Leakage Current

0.4

1

V

_nIRQ= V_nRSTO= 4.2V

µA

V

LBI Threshold Voltage

LBI Hysteresis Threshold

Low Level Output Voltage²

nRSTO Delay

VBAT Falling

VBAT Rising

I_SINK= 5mA

1.03

1.2

1.31

200

mV

V

0.35

260^ꢃ

160

20

ms

°C

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

Temperature rising

ꢀ: PWRHLD, PWREN, VSEL are logic inputs

2: nLBO, nPBSTAT, nIRQ, nRSTO are open drain outputs

3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms.

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ACT8937

Rev 0, 21-Sep-10

STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS

(V_VP1= V_VP2= V_VP3= 3.6V, T_A= 25°C, unless otherwise specified.)

PARAMETER

Operating Voltage Range

UVLO Threshold

CONDITIONS

MIN

2.7

TYP

MAX

5.5

UNIT

V

Input Voltage Rising

2.5

2.6

100

65

0

2.7

V

UVLO Hysteresis

Input Voltage Falling

Regulator Enabled

mV

µA

Quiescent Supply Current

Shutdown Current

90

1

V

_VP= 5.5V, Regulator Disabled

ꢀ

V_OUT≥ 1.2V, I_OUT= 10mA

-1%

-2%

V_NOM

1%

2%

Output Voltage Accuracy

V

ꢀ

V_OUT< 1.2V, I_OUT= 10mA

Line Regulation

V

_VP= Max(V_NOM¹+1, 3.2V) to 5.5V

0.15

0.0017

93

%/V

%/mA

%V_NOM

MHz

kHz

Load Regulation

I

_OUT= 10mA to IMAX²

Power Good Threshold

Power Good Hysteresis

V

_OUTRising

_OUTFalling

2

_OUT≥ 20% of V_NOM

_OUT= 0V

1.8

2

2.2

Oscillator Frequency

500

400

75

Soft-Start Period

Minimum On-Time

REG1

µs

ns

Maximum Output Current

Current Limit

1.1

A

1.55

1.80

0.16

0

2.05

1

PMOS On-Resistance

NMOS On-Resistance

SW1 Leakage Current

REG2

I

_SW1= -100mA

_SW1= 100mA

ꢀ

I

ꢀ

V

_VP1= 5.5V, V_SW1= 0 or 5.5V

µA

Maximum Output Current

Current Limit

1.1

A

1.55

1.80

0.16

0

2.05

1

PMOS On-Resistance

NMOS On-Resistance

SW2 Leakage Current

REG3

I

_SW2= -100mA

_SW2= 100mA

ꢀ

I

ꢀ

V

_VP2= 5.5V, V_SW2= 0 or 5.5V

µA

Maximum Output Current

Current Limit

1.2

A

1.55

1.80

0.16

0

2.05

PMOS On-Resistance

I

_SW3= -100mA

I_SW3= 100mA

_VP3= 5.5V, V_SW3= 0 or 5.5V

ꢀ

NMOS On-Resistance

SW3 Leakage Current

ꢀ

V

1

µA

ꢀ: V_NOMrefers to the nominal output voltage level for V_OUTas defined by the Ordering Information section.

2: IMAX Maximum Output Current.

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ACT8937

Rev 0, 21-Sep-10

LOW-NOISE LDO ELECTRICAL CHARACTERISTICS

(V_INL= 3.6V, C_OUT4= C_OUT5= 1.5µF, C_OUT6= C_OUT7= 2.2µF, LOWIQ[ ] = [0], T_A= 25°C, unless otherwise specified.)

PARAMETER

TEST CONDITIONS

MIN

2.5

TYP

MAX

5.5

UNIT

Operating Voltage Range

V

ꢀ

V

_OUT≥ 1.2V, T_A= 25°C, I_OUT= 10mA

-1%

-2%

V_NOM

2%

Output Voltage Accuracy

Line Regulation

V

ꢀ

V_OUT< 1.2V, T_A= 25°C, I_OUT= 10mA

4%

V

_INL= Max(V_OUT+ 0.5V, 3.6V) to 5.5V

0.05

LOWIQ[ ] = [0]

mV/V

V_INL= Max(V_OUT+ 0.5V, 3.6V) to 5.5V

LOWIQ[ ] = [1]

0.5

Load Regulation

I_OUT= 1mA to IMAX²

0.08

75

65

37

31

0

V/A

dB

f = 1kHz, I_OUT= 20mA, V_OUT=1.2V

f = 10kHz, I_OUT= 20mA, V_OUT=1.2V

Regulator Enabled, LOWIQ[ ] = [0]

Regulator Enabled, LOWIQ[ ] = [1]

Regulator Disabled

Power Supply Rejection Ratio

60

52

1

Supply Current per Output

µA

Soft-Start Period

V_OUT= 2.9V

V_OUTRising

V_OUTFalling

140

89

3

µs

%

Power Good Threshold

Power Good Hysteresis

I

_OUT= 20mA, f = 10Hz to 100kHz, V_OUT=

Output Noise

50

µV_RMS

1.2V

Discharge Resistance

REG4

LDO Disabled, DIS[ ] = 1

1.5

kꢀ

Dropout Voltage^ꢃ

Maximum Output Current

Current Limit^ꢂ

I_OUT= 80mA, V_OUT> 3.1V

90

180

mV

mA

µF

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT4Range

REG5

20

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 80mA, V_OUT> 3.1V

140

280

mV

mA

150

200

1.5

V_OUT= 95% of regulation voltage

Stable C_OUT5Range

20

µF

REG6

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 120mA, V_OUT> 3.1V

90

180

mV

mA

µF

250

300

2.2

V_OUT= 95% of regulation voltage

Stable C_OUT6Range

REG7

20

Dropout Voltage

Maximum Output Current

Current Limit

I_OUT= 120mA, V_OUT> 3.1V

140

280

mV

mA

µF

250

300

2.2

V_OUT= 95% of regulation voltage

Stable C_OUT7Range

20

ꢀ: V_NOMrefers to the nominal output voltage level for V_OUTas defined by the Ordering Information section.

2: IMAX Maximum Output Current.

3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the

regulation voltage (for 3.1V output voltage or higher).

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ACT8937

Rev 0, 21-Sep-10

ActivePath^TMCHARGER ELECTRICAL CHARACTERISTICS

(V_CHGIN= 5.0V, T_A= 25°C, unless otherwise specified.)

PARAMETER

ActivePath

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHGIN Operating Voltage Range

CHGIN UVLO Threshold

CHGIN UVLO Hysteresis

CHGIN OVP Threshold

4.35

3.1

6.0

3.9

V

CHGIN Voltage Rising

3.5

0.5

6.6

0.4

35

CHGIN Voltage Falling

CHGIN Voltage Rising

CHGIN Voltage Falling

V_CHGIN< V_UVLO

V

6.0

7.2

V

CHGIN OVP Hysteresis

V

70

µA

V_CHGIN< V_BAT+ 50mV, V_CHGIN> V_UVLO

100

200

CHGIN Supply Current

V

_CHGIN> V_BAT+ 150mV, V_CHGIN> V_UVLO

1.3

2.0

mA

Charger disabled, I_VSYS= 0mA

I_VSYS= 100mA

CHGIN to VSYS On-Resistance

CHGIN to VSYS Current Limit

0.3

2

ꢀ

ACIN = VSYS

1.5

80

A

ACIN = GA, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

90

450

100

500

mA

400

VSYS REGULATION

VSYS Regulated Voltage

nSTAT OUTPUT

I_VSYS= 10mA

V_nSTAT= 2V

4.45

4

4.6

8

4.8

V

nSTAT Sink current

12

1

mA

µA

nSTAT Leakage Current

ACIN AND CHGLEV INPUTS

CHGLEV Logic High Input Voltage

CHGLEV Logic Low Input Voltage

CHGLEV Leakage Current

ACIN Voltage Thresholds

ACIN Hysteresis voltage threshold

ACIN Leakage Current

TH INPUT

V_nSTAT= 4.2V

1.4

V

0.4

1

V_CHGLEV= 4.2V

µA

V

ACIN voltage rising

ACIN voltage falling

1.03

1.2

1.31

200

mV

µA

V

_ACIN= 4.2V

1

TH Pull-Up Current

V_CHGIN> V_BAT+ 100mV, Hysteresis = 50mV

Hot Detect NTC Thermistor

91

102

110

µA

V

V_THUpper Temperature Voltage

2.44

2.51

2.58

Threshold (V_THH

)

V_THLower Temperature Voltage

Cold Detect NTC Thermistor

Upper and Lower Thresholds

0.47

0.50

30

0.53

V

Threshold (V_THL

)

V_THHysteresis

mV

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ACT8937

Rev 0, 21-Sep-10

ActivePath^TMCHARGER ELECTRICAL CHARACTERISTICS CONT’D

(V_CHGIN= 5.0V, T_A= 25°C, unless otherwise specified.)

PARAMETER

CHARGER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BAT Reverse Leakage Current

BAT to VSYS On-Resistance

V

_CHGIN= 0V, V_BAT= 4.2V, I_VSYS= 0mA

8

µA

70

mꢀ

Fast Charge

1.2

0.13

4.2

ISET Pin Voltage

V

Precondition

T_A= -20°C to 70°C

T_A= -40°C to 85°C

4.179

4.170

4.221

V

Charge Termination Voltage

4.230

1

ACIN = VSYS, CHGLEV = VSYS -10%

I_CHG

+10%

ACIN = VSYS, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

ACIN = GA, CHGLEV = GA

ACIN = VSYS, CHGLEV = VSYS

ACIN = VSYS, CHGLEV = GA

ACIN = GA, CHGLEV = VSYS

ACIN = GA, CHGLEV = GA

-10%

400

80

I

_CHG/5

+10%

mA

V_BAT= 3.8V

_ISET= 6.8K

Charge Current

R

450

500

90

100

10% I_CHG

45

V_BAT= 2.7V

R_ISET= 6.8K

Precondition Charge Current

Precondition Threshold Voltage

mA

45

V

_BATVoltage Rising

_BATVoltage Falling

ACIN = VSYS, CHGLEV = VSYS

2.75

2.85

3.0

V

Precondition Threshold

Hysteresis

V

150

mV

10% I_CHG

ACIN = VSYS, CHGLEV = GA

END-OF-CHARGE Current

Threshold

V_BAT= 4.15V

mA

ACIN = GA, CHGLEV =

VSYS

45

ACIN = GA, CHGLEV = GA

45

205

80

Charge Restart Threshold

Precondition Safety Timer

Total Safety Timer

V

_VSYS- V_BAT, V_BATFalling

190

220

V

min

hr

PRETIMO[ ] = 10

TOTTIMO[ ] = 10

5

Thermal Regulation Threshold

100

°C

ꢀ: R_ISET(kꢀ) = 2336 × (1V/I_CHG(mA)) - 0.205

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ACT8937

Rev 0, 21-Sep-10

TYPICAL PERFORMANCE CHARACTERISTICS

(V_VSYS= 3.6V, T_A= 25°C, unless otherwise specified.)

Frequency vs. Temperature

V_REFvs. Temperature

0.84

0.42

0

2.5

2

1.5

1

0.5

0

-0.42

-0.84

-0.5

-1

Typical V_REF=1.2V

Typical Oscillator Frequency=2MHz

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80 85

Temperature (°C)

PWRHLD holding OUT1 & OUT5 after

nPBIN is released

PWREN Sequence

CH1

CH2

CH3

CH2

CH3

CH4

CH5

CH6

CH4

CH1: V_PWREN, 5V/div

CH2: V_OUT2, 1V/div

CH3: V_OUT3, 1V/div

CH4: V_OUT4, 1V/div

CH5: V_OUT6, 1V/div

CH6: V_OUT7, 2V/div

TIME: 4ms/div

CH1: V_nPBIN, 2V/div

CH2: V_OUT5, 1V/div

CH3: V_OUT1, 2V/div

CH4: V_PWRHLD,2V/div

TIME: 100ms/div

nPBIN Startup Sequence

CH1

CH2

CH1

CH2

CH3

CH4

CH5

CH6

CH1: V_nPBIN, 5V/div

CH2: V_OUT5, 1V/div

CH3: V_OUT2, 1V/div

CH4: V_OUT3, 1V/div

CH5: V_OUT4, 1V/div

TIME: 2ms/div

CH2: V_OUT5, 1V/div

CH3: V_OUT2, 1V/div

CH4: V_OUT1, 2V/div

CH5: V_OUT6, 1V/div

CH6: V_OUT7, 2V/div

TIME: 4ms/div

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ACT8937

Rev 0, 21-Sep-10

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Push-Button Response (First Power-Up)

Manual Reset Response

CH1

CH2

CH1

CH2

CH3

CH1: V_nPBIN, 2V/div

CH2: V_nPBSTAT, 2V/div

CH3:V_nRSTO, 2V/div

TIME: 100ms/div

nPBIN Resistor = 50kꢀ

CH2: V_nPBSTAT, 2V/div

nPBIN Resistor = 0ꢀ

CH3: V_nRSTO, 2V/div

TIME: 100ms/div

REG1 Efficiency vs. Output Current

REG2 Efficiency vs. Output Current

100

80

60

40

20

0

100

80

60

40

20

0

V_OUT= 1.2V

V_IN= 3.6V

V_OUT= 3.3V

V_IN= 5.0V

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

V_IN= 4.2V

1

10

100

1000

1

10

100

1000

Output Current (mA)

REG3 Efficiency vs. Output Current

100

V_OUT= 1.35V

V_IN= 3.6V

80

60

40

20

0

V_IN= 5.0V

V_IN= 4.2V

1

10

100

1000

Output Current (mA)

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TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

REG1 Output Voltage vs. Temperature

REG2 Output Voltage vs. Temperature

3.310

3.306

3.302

3.298

3.294

3.290

1.310

1.306

1.302

1.298

1.294

1.290

V_OUT1= 3.3V

I_LOAD= 100mA

V_OUT2= 1.3V

I_LOAD= 100mA

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

REG1, 2, 3 MOSFET Resistance

REG3 Output Voltage vs. Temperature

1.360

1.356

1.352

1.348

1.344

1.340

350

300

250

200

150

100

50

I_LOAD= 100mA

V_OUT3= 1.35V

I

_LOAD= 100mA

PMOS

NMOS

0

3.0

3.5

4.0

4.5

5.0

5.5

-40

-20

0

20

40

60

80

100

120

Input Voltage (V)

Temperature (°C)

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ACT8937

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TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Output Voltage vs. Output Current

1.90

1.70

1.50

1.30

1.10

0.90

0.70

0.50

0.30

3.70

3.50

3.30

3.10

2.90

2.70

2.50

2.30

2.10

REG7

REG6

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Output Current (mA)

Output Voltage vs. Output Current

Dropout Voltage vs. Output Current

1.300

1.260

1.220

1.180

1.140

1.100

160

140

120

REG4, REG5

100

80

60

40

20

0

REG4

V_IN= 3.3V

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100 120 140 160

Output Current (mA)

Dropout Voltage vs. Output Current

180

160

140

120

100

80

250

200

150

100

50

REG6

REG5

60

40

20

V_IN= 3.3V

0

50

100

150

200

250

300

0

20

40

60

80

100 120 140 160

Output Current (mA)

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ACT8937

Rev 0, 21-Sep-10

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

Dropout Voltage vs. Output Current

Output Voltage vs. Temperature

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0

300

250

200

150

100

50

REG7

REG4, REG5, REG6

V_IN= 3.3V

0

50

100

150

200

250

300

-40

-20

0

20

40

60

80

100

120

Output Current (mA)

Temperature (°C)

LDO Output Voltage Noise

Region of Stable C_OUTESR vs. Output Current

1

CH1

0.1

Stable ESR

0.01

CH1: V_OUTx, 200µV/div (AC COUPLED)

TIME: 200ms/div

0

50

100

150

200

250

Output Current (mA)

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ACT8937

Rev 0, 21-Sep-10

TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

VSYS Voltage vs. CHGIN Voltage

VSYS Voltage vs. VSYS Current

6.0

5.0

4.0

3.0

2.0

1.0

0

5.2

5.0

4.8

4.6

4.4

4.2

4.0

ACIN/CHGLEV = 01

ACIN/CHGLEV = 11

VSYS = 4.6V

0

2

4

6

8

10

0

500

1000

1500

2000

2500

CHGIN Voltage (V)

VSYS Current (mA)

Charger Current vs. Battery Voltage

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V_CHGIN= 5V

ACIN = 0

CHGLEV = 1

450mA USB

V_BATFalling

V_BATRising

V_CHGIN= 5V

ACIN = 0

V_BATFalling

CHGLEV = 0

V_BATRising

90mA USB

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Battery Voltage (V)

Charger Current vs. Battery Voltage

DCCC and Battery Supplement Modes

1200

1000

800

600

400

200

0

R_ISET= 2.4kꢀ

V_CHGIN= 5V

CH4

CH3

CH2

ACIN/CHGLEV = 11

V_BAT= 3.5V

V_VSYS= 4.6V

_VSYS= 0-1.8A

I_CHARGE= 1000mA

_CHGIN= 5.1V-3A

I

V_BATFalling

V_BATRising

CH1

V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

CH1: I_VSYS, 1.00A/div

CH2: I_BAT, 1.00A/div

CH3: V_BAT, 1.00V/div

CH4: V_VSYS, 1V/div

TIME: 200ms/div

Battery Voltage (V)

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TYPICAL PERFORMANCE CHARACTERISTICS CONT’D

(T_A= 25°C, unless otherwise specified.)

VAC Applied

VAC Removed

CH4

CH3

CH2

CH3

CH2

CH1

V_CHGIN= 5V

V_BAT= 3.5V

R_VSYS= 100ꢀ

ACIN/CHGLEV = 01

V_CHGIN= 5V

V_BAT= 3.5V

R_VSYS= 100ꢀ

ACIN/CHGLEV = 01

CH1: V_BAT, 1V/div

CH2: I_BAT, 400mA/div

CH3: V_VSYS, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

CH1: I_BAT, 200mA/div

CH2: V_BAT, 1V/div

CH3: V_VSYS, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 100ms/div

VAC Applied

VAC Removed

CH4

CH3

CH2

CH3

CH2

CH1

V_CHGIN= 5V

V_BAT= 3.97V

V_CHGIN= 5V

V_BAT= 3.97V

CH1: I_BAT, 1A/div

CH2: V_BAT, 2V/div

CH3: V_VSYS, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

CH1: I_BAT, 1A/div

CH2: V_VSYS, 2V/div

CH3: V_BAT, 2V/div

CH4: V_CHGIN, 5V/div

TIME: 40ms/div

R_VSYS= 47ꢀ

ACIN/CHGLEV = 11

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ACT8937

Rev 0, 21-Sep-10

SYSTEM CONTROL INFORMATION

Interfacing with the Samsung S5PC100, S5PC110 and S5PV210 Processors

The ACT8937 is optimized for use in applications

using the S5PC100, S5PC110 and S5PV210

processors, supporting both the power domains as

well as the signal interface for these processors.

between these devices benefits by doing so, both

the ACT8937 pin names and the Samsung

processor pin names are provided. When this is

done, the S5PV210 pin names are located after the

ACT8937 pin names, and are italicized and located

inside parentheses. For example, PWREN

(XPWRRGTON) refers to the logic signal applied to

the ACT8937's PWREN input, identifying that it is

driven from the S5PV210's XPWRRGTON output.

Likewise, OUT1 (VDD_IO) refers to ACT8937's

OUT1 pin, identifying that it is connected to the

S5PV210's VDD_IO power domain.

The following paragraphs describe how to design

ACT8937 with S5PV210 Processor, but the design

guidelines are directly applicable to S5PC100 and

S5PC110 as well.

While the ACT8937 supports many possible

configurations for powering these processors, one

of the most common configurations is detailed in

this datasheet. In general, this document refers to

the ACT8937 pin names and functions. However, in

cases where the description of interconnections

Table 2:

ACT8937 and Samsung S5PV210 Power Domains

POWER DOMAIN

VDD_IO

ACT8937 CHANNEL

REG1

TYPE

DC/DC

LDO

DEFAULT VOLTAGE

CURRENT CAPABILITY

1100mA

3.3V

1.1V/1.V

1.25V/1.25V

1.1V

VDD_INT

REG2

1100mA

VDD_ARM

REG3

1200mA

VDD_xPLL

REG4

150mA

VDD_Alive

REG5

LDO

1.1V

150mA

VDD_UOTG_D

VDD_UOTG_A

REG6

LDO

1.1V

250mA

REG7

LDO

3.3V

250mA

Table 3:

ACT8937 and Samsung S5PV210Power Modes

POWER

QUIESCENT

CURRENT

CONTROL STATE

MODE

POWER DOMAIN STATE

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 are all on

ALL ON

PWRHLD is asserted, PWREN is asserted

420µA

PWRHLD is asserted, PWREN is asserted,

REG6 and REG7 are disabled after system

boots up.

REG1, REG2, REG3, REG4 and

REG5 are on. REG6 and REG7 are off

NORMAL

340µA

PWRHLD is asserted, PWREN is de-asserted, REG1 and REG5 are on. REG2, REG3,

SLEEP

190µA

<18µA

REG6 and REG7 are disabled as default

REG4, REG6 and REG7 are off

PWRHLD is de-asserted, PWREN is de-

asserted

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 are all off

ALL OFF

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Table 4:

ACT8937 and Samsung S5PV210 Signal Interface

ACT8937

PWREN

SCL

DIRECTION

SAMSUNG S5V210

XPWRRGTON

Xi2cSCL[0]

Xi2cSDA[0]

DVS_GPIO^ꢀ

XnRESET

SDA

VSEL

nRSTO

nIRQ

XEINT0^ꢁ

nPBSTAT

nLBO

XEINT1^ꢃ

XnBATF

PWRHLD

Power hold GPIO^ꢂ

1: Optional connection for DVS control.

2, ꢃ: Typical connections shown, actual connections may vary.

ꢂ: Optional connection for power hold control.

Table 5:

Control Pins

PIN NAME

nPBIN

OUTPUT

REG1, REG2, REG3, REG4, REG5, REG6, REG7

REG1, REG5

PWRHLD

PWREN

REG2, REG3, REG4, REG6, REG7

nPBSTAT Output

Control Signals

nPBSTAT is an open-drain output that reflects the

state of the nPBIN input; nPBSTAT is asserted low

whenever nPBIN is asserted, and is high-Z

otherwise. This output is typically used as an

interrupt signal to the processor, to initiate a

software-programmable routine such as operating

mode selection or to open a menu. Connect

nPBSTAT to an appropriate supply voltage

(typically OUT1) through a 10kꢀ or greater resistor.

Enable Inputs

The ACT8937 features a variety of control inputs,

which are used to enable and disable outputs

depending upon the desired mode of operation.

PWREN, PWRHLD are logic inputs, while nPBIN is

a unique, multi-function input. Refer to Table 5 for a

description of which channels are controlled by

each input.

Figure 2:

nPBIN Multi-Function Input

nPBIN Input

ACT8937 features the nPBIN multi-function pin,

which combines system enable/disable control with

a hardware reset function. Select either of the two

pin functions by asserting this pin, either through a

direct connection to GA, or through a 50kꢀ resistor

to GA, as shown in Figure 2.

Manual Reset Function

The second major function of the nPBIN input is to

provide a manual-reset input for the processor. To

manually-reset the processor, drive nPBIN directly

to GA through a low impedance (less than 2.5kꢀ).

When this occurs, nRSTO immediately asserts low,

then remains asserted low until the nPBIN input is

de-asserted and the reset timeout period expires.

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nRSTO Output

Control Sequences

nRSTO is an open-drain output which asserts low

upon startup or when manual reset is asserted via

the nPBIN input. When asserted on startup, nRSTO

remains low until reset timeout period expires after

OUT5 reaches its power-OK threshold. When

asserted due to manual-reset, nRSTO immediately

asserts low, then remains asserted low until the

nPBIN input is de-asserted and the reset timeout

period expires.

The ACT8937 features

a

variety of control

sequences that are optimized for supporting system

enable and disable, as well as SLEEP mode of the

Samsung S5PC100, S5PC110 and S5PV210

processors.

Enabling/Disabling Sequence

A typical enable sequence is initiated whenever the

following conditions occurs:

1) nPBIN is asserted low via 50Kꢀ resistance, or

Connect a 10kꢀ or greater pull-up resistor from

nRSTO to an appropriate voltage supply (typically

OUT1).

2) A valid input voltage is present at CHGIN^ꢀ.

The enable sequence begins by enabling REG5.

When REG5 reaches its power-OK threshold,

nRSTO is asserted low, resetting the

microprocessor. REG2, REG3 and REG4 are

enabled after REG5 reaches its power-OK

threshold for 8ms². When REG2 reaches its power-

OK threshold for 8ms², REG1 and REG6 are

enabled. When REG2 reaches its power-OK

threshold for 16ms², REG7 is enabled. If REG5 is

above its power-OK threshold when the reset timer

expires, nRSTO is de-asserted, allowing the

microprocessor to begin its boot sequence.

nIRQ Output

nIRQ is an open-drain output that asserts low any

time an interrupt is generated. Connect a 10kꢀ or

greater pull-up resistor from nIRQ to an appropriate

voltage supply. nIRQ is typically used to drive the

interrupt input of the system processor.

Many of the ACT8937's functions support interrupt-

generation as a result of various conditions. These

are typically masked by default, but may be

unmasked via the I²C interface. For more

information about the available fault conditions,

refer to the appropriate sections of this datasheet.

During the boot sequence, the microprocessor must

assert PWRHLD, holding REG1 and REG5, and

assert PWREN(XPWRRGTON), holding REG2,

REG3, REG4, REG6 and REG7 to ensure that the

system remains powered after nPBIN is released.

REG6 and REG7 can also be enabled/disabled via

I²C after microprocessor completes its boot

sequence.

Note that under some conditions a false interrupt

may be generated upon initial startup. For this

reason, it is recommended that the interrupt service

routine check and validate nSYSLEVMSK[-] and

nFLTMSK[-] bits before processing an interrupt

generated by these bits. These interrupts may be

validated by nSYSSTAT[-], OK[-] bits.

Once the power-up routine is completed, the

system remains enabled after the push-button is

released as long as either PWRHLD or PWREN are

asserted high. If the processor does not assert

PWRHLD before the user releases the push-button,

the boot-up sequence is terminated and all

regulators are disabled. This provides protection

against "false-enable", when the pushbutton is

accidentally depressed, and also ensures that the

system remains enabled only if the processor

successfully completes the boot-up sequence. To

disable REG6 (or REG7) via I²C after the power-up,

Push-Button Control

The ACT8937 is designed to initiate a system

enable sequence when the nPBIN multi-function

input is asserted. Once this occurs, a power-on

sequence commences, as described below. The

power-on sequence must complete and the

microprocessor must take control (by asserting

PWREN or PWRHLD) before nPBIN is de-asserted.

If the microprocessor is unable to complete its

power-up routine successfully before the user lets

the push-button go off, the ACT8937 automatically

shuts the system down. This provides protection

against accidental or momentary assertions of the

push-button. If desired, longer “push-and-hold”

times can be easily implemented by simply adding

an additional time delay before asserting PWREN

or PWRHLD.

the software needs

to

set

register

bit

REG6.ON[ ] (or REG7.ON[ ]) to “1” first, then set it

back to “0” to turn off the regulator.

As with the enable sequence, a typical disable

sequence is initiated when the user presses the

push-button, which interrupts the processor via the

nPBSTAT output. The actual disable sequence is

completely software-controlled, but typically

ꢀ: Applicable only for ACT8937QJ2XX.

2: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.

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involved initiating various “clean-up” processes

before the processor finally de-asserts PWRHLD,

which disables REG1 and REG5 after push-button

is released. Since the processor loses power of

VDD_IO and VDD_Alive, it automatically de-asserts

PWREN (XPWRRGTON), and hence shuts the

system down by disabling REG2, REG3, REG4,

REG6 and REG7.

interrupt the processor should de-assert

PWREN(XPWRRGTON), disabling REG2, REG3,

REG4, REG6 and REG7. PWRHLD should remain

asserted during SLEEP mode so that REG1 and

REG5 remain enabled.

Waking up from SLEEP mode is typically initiated

when the user presses the push-button again,

which enables REG2, REG3, REG4, REG6 and

REG7 and asserts nPBSTAT. Processors should

respond by asserting PWREN(XPWRRGTON),

which holds REG2, REG3, REG4, REG6 and REG7

so that normal operation may resume. An external

interrupt , for instance a charger interrupt or a RTC

interrupt, can also initiate a wake up sequence.

When an external interrupt is sent to the processor,

the processor should response by getting itself

ready to wake up from SLEEP mode first, then

assert PWREN(XPWRRGTON), which enables

REG2, REG3, REG4, REG6 and REG7 so that the

normal operation may resume.

SLEEP Mode Sequence

The ACT8937 supports Samsung S5PC100,

S5PC110 and S5PV210 processors’ SLEEP mode

operation. Once a successful power-up routine has

been completed, SLEEP mode may be initiated

through

a

variety of software-controlled

mechanisms.

SLEEP mode is typically initiated when the user

presses the push-button during normal operation.

Pressing the push-button asserts the nPBIN input,

which asserts the nPBSTAT output, which

interrupts the processor. In response to this

Figure 3:

Enable/Disable Sequence

ꢀ

ꢀ: Applicable only for ACT8937QJ2XX.

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Figure 4:

Sleep Mode and Wake up Sequence (from Push Button)

ꢀ

Figure 5:

Sleep Mode and Wake up Sequence (from External Interrupt)

ꢀ

ꢀ: Applicable only for ACT8937QJ2XX.

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ACT8937

Rev 0, 21-Sep-10

FUNCTIONAL DESCRIPTION

I²C Interface

controlled by the CPU, but will typically initiate a

controlled shutdown sequence either or alert the

user that the battery is low. In this case the interrupt

is cleared when nSYSSTAT[-] is read via I²C.

The ACT8937 features an I²C interface that allows

advanced programming capability to enhance overall

system performance. To ensure compatibility with a

wide range of system processors, the I²C interface

supports clock speeds of up to 400kHz (“Fast-Mode”

operation) and uses standard I²C commands. I²C

write-byte commands are used to program the

ACT8937, and I²C read-byte commands are used to

read the ACT8937’s internal registers. The ACT8937

always operates as a slave device, and is addressed

using a 7-bit slave address followed by an eighth bit,

which indicates whether the transaction is a read-

operation or a write-operation, [1011011x].

2) If nSYSMODE[-] = 0, when VSYS falls below the

programmable threshold the ACT8937 shuts down,

immediately disabling all regulators. This option is

useful for implementing a programmable “under-

voltage lockout” function that forces the system off

when the battery voltage falls below the SYSLEV

threshold voltage. Since this option does not support

a controlled shutdown sequence, it is generally used

as a "fail-safe" to shut the system down when the

battery voltage is too low.

Table 6:

SDA is a bi-directional data line and SCL is a clock

input. The master device initiates a transaction by

issuing a START condition, defined by SDA

transitioning from high to low while SCL is high. Data

is transferred in 8-bit packets, beginning with the

MSB, and is clocked-in on the rising edge of SCL.

Each packet of data is followed by an “Acknowledge”

(ACK) bit, used to confirm that the data was

transmitted successfully.

SYSLEV Falling Threshold

SYSLEV[3:0]

(Hysteresis = 200mV)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

For more information regarding the I²C 2-wire serial

interface, go to the NXP website: http://www.nxp.com.

Housekeeping Functions

Programmable System Voltage Monitor

The ACT8937 features a programmable system-

voltage monitor, which monitors the voltage at VSYS

and compares it to a programmable threshold

voltage. The programmable voltage threshold is

programmed by SYSLEV[3:0], as shown in Table 6.

The nSYSSTAT[-] bit reflects the output of an

internal voltage comparator that monitors VSYS

relative to the SYSLEV[-] voltage threshold, the

value of nSYSTAT[-] = 1 when VSYS is higher than

the SYSLEV[-] voltage threshold, and nSYSTAT[-] =

0 when VSYS is lower than the SYSLEV[-] voltage

threshold. Note that the SYSLEV[-] voltage threshold

is defined for falling voltages, and that the

comparator produces about 200mV of hysteresis at

VSYS. As a result, once VSYS falls below the

SYSLEV threshold, its voltage must increase by

more than about 200mV to clear that condition.

Precision Voltage Detector

The LBI input connects to one input of a precision

voltage comparator, which can be used to monitor a

system voltage such as the battery voltage. An

external resistive-divider network can be used to set

voltage monitoring thresholds, as shown in

Functional Block Diagram. The output of the

comparator is present at the nLBO open-drain

output.

Thermal Shutdown

The ACT8937 responds in one of two ways when the

voltage at VSYS falls below the SYSLEV[-] voltage

threshold:

The ACT8937 integrates thermal shutdown

protection circuitry to prevent damage resulting from

excessive thermal stress, as may be encountered

under fault conditions. This circuitry disables all

regulators if the ACT8937 die temperature exceeds

160°C, and prevents the regulators from being

enabled until the IC temperature drops by 20°C (typ).

1) If nSYSMODE[-] = 1 (default case), when VSYS

falls below the programmable threshold the

ACT8937 asserts nIRQ, providing a software “under-

voltage alarm”. The response to this interrupt is

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ACT8937

Rev 0, 21-Sep-10

STEP-DOWN DC/DC REGULATORS

must be taken during the design process to ensure

stable operation over the full operating voltage and

temperature range. Ceramic capacitors are available

in a variety of dielectrics, each of which exhibits

different characteristics that can greatly affect

performance over their temperature and voltage

ranges.

General Description

The ACT8937 features three synchronous, fixed-

frequency, current-mode PWM step down converters

that achieve peak efficiencies of up to 97%. REG1

and REG2 are capable of supplying up to 1100mA of

output current, while REG3 supports up to 1200mA.

These regulators operate with a fixed frequency of

2MHz, minimizing noise in sensitive applications and

allowing the use of small external components.

Two of the most common dielectrics are Y5V and

X5R. Whereas Y5V dielectrics are inexpensive and

can provide high capacitance in small packages, their

capacitance varies greatly over their voltage and

temperature ranges and are not recommended for

DC/DC applications. X5R and X7R dielectrics are

more suitable for output capacitor applications, as

their characteristics are more stable over their

operating ranges, and are highly recommended.

100% Duty Cycle Operation

Each regulator is capable of operating at up to 100%

duty cycle. During 100% duty-cycle operation, the

high-side power MOSFET is held on continuously,

providing a direct connection from the input to the

output (through the inductor), ensuring the lowest

possible dropout voltage in battery powered

applications.

Inductor Selection

REG1, REG2, and REG3 utilize current-mode control

and a proprietary internal compensation scheme to

simultaneously simplify external component selection

and optimize transient performance over their full

operating range. These devices were optimized for

operation with 2.2μH inductors, although inductors in

the 1.5μH to 3.3μH range can be used. Choose an

inductor with a low DC-resistance, and avoid inductor

saturation by choosing inductors with DC ratings that

exceed the maximum output current by at least 30%.

Synchronous Rectification

REG1, REG2, and REG3 each feature integrated n-

channel synchronous rectifiers, maximizing efficiency

and minimizing the total solution size and cost by

eliminating the need for external rectifiers.

Soft-Start

When enabled, each output voltages tracks an

internal 400μs soft-start ramp, minimizing input

current during startup and allowing each regulator to

power up in a smooth, monotonic manner that is

independent of output load conditions.

Configuration Options

Output Voltage Programming

By default, each regulator powers up and regulates to

its default output voltage. Output voltage is selectable

by setting VSEL pin that when VSEL is low, output

voltage is programmed by VSET1[-] bits, and when

VSEL is high, output voltage is programmed by

VSET2[-] bits. However, once the system is enabled,

each regulator's output voltage may be independently

programmed to a different value, typically in order to

minimize the power consumption of the

microprocessor during some operating modes.

Program the output voltages via the I²C serial

interface by writing to the regulator's VSET1[-]

register if VSEL is low or VSET2[-] register if VSEL is

high as shown in Table 8.

Compensation

Each buck regulator utilizes current-mode control and

a proprietary internal compensation scheme to

simultaneously simplify external component selection

and optimize transient performance over its full

operating range. No compensation design is

required; simply follow a few simple guidelines

described below when choosing external

components.

Input Capacitor Selection

The input capacitor reduces peak currents and noise

induced upon the voltage source. A 4.7μF ceramic

capacitor is recommended for each regulator in most

applications.

Enable / Disable Control

During normal operation, each buck may be enabled

or disabled via the I²C interface by writing to that

regulator's ON[ ] bit. To enable the regulator set ON[ ]

to 1, to disable the regulator clear ON[ ] to 0.

Output Capacitor Selection

For most applications, 22μF ceramic output

capacitors are recommended for REG1, REG2 and

REG3.

Despite the advantages of ceramic capacitors, care

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ACT8937

Rev 0, 21-Sep-10

interface. If an output voltage is lower than the power-

OK threshold, typically 7% below the programmed

regulation voltage, that regulator's OK[ ] bit will be 0.

REG1, REG2, REG3 Turn-on Delay

Each of REG1, REG2 and REG3 features a

programmable Turn-on Delay which help ensure a

reliable qualification. This delay is programmed by

DELAY[2:0], as shown in Table 7.

If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8937

will interrupt the processor if that DC/DC's output

voltage falls below the power-OK threshold. In this

case, nIRQ will assert low and remain asserted until

the OK[ ] bit has been read via I²C.

Table 7:

REGx/DELAY[ ] Turn-On Delay

DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY

PCB Layout Considerations

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 ms

2 ms

High switching frequencies and large peak currents

make PC board layout an important part of step-down

DC/DC converter design. A good design minimizes

excessive EMI on the feedback paths and voltage

gradients in the ground plane, both of which can

result in instability or regulation errors.

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

Step-down DC/DCs exhibit discontinuous input

current, so the input capacitors should be placed as

close as possible to the IC, and avoiding the use of

via if possible. The inductor, input filter capacitor, and

output filter capacitor should be connected as close

together as possible, with short, direct, and wide

traces. The ground nodes for each regulator's power

loop should be connected at a single point in a star-

ground configuration, and this point should be

connected to the backside ground plane with multiple

via. The output node for each regulator should be

connected to its corresponding OUTx pin through the

shortest possible route, while keeping sufficient

distance from switching nodes to prevent noise

injection. Finally, the exposed pad should be directly

connected to the backside ground plane using

multiple via to achieve low electrical and thermal

resistance.

Operating Mode

By default, REG1, REG2, and REG3 each operate in

fixed-frequency PWM mode at medium to heavy

loads, while automatically transitioning to

a

proprietary power-saving mode at light loads in order

to maximize standby battery life. In applications

where low noise is critical, force fixed-frequency

PWM operation across the entire load current range,

at the expense of light-load efficiency, by setting the

MODE[ ] bit to 1.

OK[ ] and Output Fault Interrupt

Each DC/DC features a power-OK status bit that can

be read by the system microprocessor via the I²C

Table 8:

REGx/VSET[ ] Output Voltage Setting

REGx/VSET[5:3]

REGx/VSET[2:0]

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.250

1.300

1.350

1.400

1.450

1.500

1.550

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.500

2.600

2.700

2.800

2.900

3.000

3.100

3.200

3.300

3.400

3.500

3.600

3.700

3.800

3.900

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ACT8937

Rev 0, 21-Sep-10

LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS

to that LDO's ON[ ] bit. To enable the LDO set ON[ ]

to 1, to disable the LDO clear ON[ ] to 0.

General Description

REG4, REG5, REG6, and REG7 are low-noise,

low-dropout linear regulators (LDOs) that supply up

to 150mA, 150mA, 250mA, and 250mA,

respectively. Each LDO has been optimized to

achieve low noise and high-PSRR, achieving more

than 65dB PSRR at frequencies up to 10kHz.

REG4, REG5, REG6, REG7 Turn-on Delay

Each of REG4, REG5, REG6 and REG7 features a

programmable Turn-on Delay which help ensure a

reliable qualification. This delay is programmed by

DELAY[2:0], as shown in Table 7.

Output Current Limit

Output Discharge

Each LDO contains current-limit circuitry featuring a

current-limit fold-back function. During normal and

moderate overload conditions, the regulators can

support more than their rated output currents.

During extreme overload conditions, however, the

current limit is reduced by approximately 30%,

reducing power dissipation within the IC.

Each of the ACT8937’s LDOs features an optional

output discharge function, which discharges the

output to ground through a 1.5kꢀ resistance when

the LDO is disabled. This feature may be enabled

or disabled by setting DIS[-] via; set DIS[-] to 1 to

enable this function, clear DIS[-] to 0 to disable it.

Low-Power Mode

Compensation

Each of ACT8937's LDOs features a LOWIQ[-] bit

which, when set to 1, reduces the LDO's quiescent

current by about 16%, saving power and extending

battery lifetime.

The LDOs are internally compensated and require

very little design effort, simply select input and

output capacitors according to the guidelines below.

Input Capacitor Selection

OK[ ] and Output Fault Interrupt

Each LDO requires a small ceramic input capacitor

to supply current to support fast transients at the

input of the LDO. Bypassing each INL pin to GA

with 1μF. High quality ceramic capacitors such as

X7R and X5R dielectric types are strongly

recommended.

Each LDO features a power-OK status bit that can

be read by the system microprocessor via the

interface. If an output voltage is lower than the

power-OK threshold, typically 11% below the

programmed regulation voltage, the value of that

regulator's OK[-] bit will be 0.

Output Capacitor Selection

If a LDO's nFLTMSK[-] bit is set to 1, the ACT8937

will interrupt the processor if that LDO's output

voltage falls below the power-OK threshold. In this

case, nIRQ will assert low and remain asserted until

the OK[-] bit has been read via I²C.

Each LDO requires

a small ceramic output

capacitor for stability. Capacitance value is 1.5μF

for REG4 and REG5, 2.2μF for REG6 and REG7.

For best performance, each output capacitor should

be connected directly between the output and GA

pins, as close to the output as possible, and with a

short, direct connection. High quality ceramic

capacitors such as X7R and X5R dielectric types

are strongly recommended.

PCB Layout Considerations

PCB Layout Considerations The ACT8937’s LDOs

provide good DC, AC, and noise performance over

a wide range of operating conditions, and are

relatively insensitive to layout considerations. When

designing a PCB, however, careful layout is

necessary to prevent other circuitry from degrading

LDO performance.

Configuration Options

Output Voltage Programming

By default, each LDO powers up and regulates to

its default output voltage. Once the system is

enabled, each output voltage may be independently

programmed to a different value by writing to the

regulator's VSET[-] register via the I²C serial

interface as shown in Table 8.

A good design places input and output capacitors

as close to the LDO inputs and output as possible,

and utilizes a star-ground configuration for all

regulators to prevent noise-coupling through

ground. Output traces should be routed to avoid

close proximity to noisy nodes, particularly the SW

nodes of the DC/DCs.

Enable / Disable Control

During normal operation, each LDO may be

enabled or disabled via the I²C interface by writing

REFBP is a filtered reference noise, and internally

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ACT8937

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has a direct connection to the linear regulator

controller. Any noise injected onto REFBP will

directly affect the outputs of the linear regulators,

and therefore special care should be taken to

ensure that no noise is injected to the outputs via

REFBP. As with the LDO output capacitors, the

REFBP bypass capacitor should be placed as close

to the IC as possible, with short, direct connections

to the star-ground. Avoid the use of via whenever

possible. Noisy nodes, such as from the DC/DCs,

should be routed as far away from REFBP as

possible.

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ACT8937

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ActivePath^TMCHARGER

General Description

In an input over-voltage condition this circuit limits

VSYS to 4.6V, protecting any circuitry connected to

VSYS from the over-voltage condition, which may

exceed this circuitry's voltage capability. This circuit

is capable of withstanding input voltages of up to

12V.

The ACT8937 features an advanced battery

charger that incorporates the patent-pending

ActivePath architecture for system power selection.

This combination of circuits provides a complete,

advanced battery-management system that

automatically selects the best available input

supply, manages charge current to ensure system

power availability, and provides a complete, high-

accuracy (±0.5%), thermally regulated, full-featured

single-cell linear Li+ charger that can withstand

input voltages of up to 12V.

Table 9:

Input Over-Voltage Protection Setting

OVPSET[1]

OVPSET[0]

OVP THRESHOLD

0

1

0

1

0

1

6.6V

7.0V

7.5V

8.0V

ActivePath Architecture

The ActivePath architecture performs three

important functions:

Input Supply Overload Protection

1) System Configuration Optimization

2) Input Protection

The ActivePath circuitry monitors and limits the total

current drawn from the input supply to a value set

by the ACIN and CHGLEV inputs, as well as the

resistor connected to ISET. Drive ACIN to a logic-

low for “USB Mode”, which limits the current to

either 100mA, when CHGLEV is driven to a logic-

low, or 500mA, when CHGLEV is driven to a logic-

high. Drive ACIN to a logic-high for “AC-Mode”,

which limits the input current to 2A, typically.

3) Battery-Management

System Configuration Optimization

The ActivePath circuitry monitors the state of the

input supply, the battery, and the system, and

automatically reconfigures itself to optimize the

power system. If a valid input supply is present,

ActivePath powers the system from the input while

charging the battery in parallel. This allows the

battery to charge as quickly as possible, while

supplying the system. If a valid input supply is not

present, ActivePath powers the system from the

battery. Finally, if the input is present and the

system current requirement exceeds the capability

of the input supply, ActivePath allows system power

to be drawn from both the battery and the input

supply.

Input Under Voltage Lockout

If the input voltage applied to CHGIN falls below

3.5V (typ), an input under-voltage condition is

detected and the charger is disabled. Once an input

under-voltage condition is detected, a new charge

cycle will initiate when the input exceeds the under-

voltage threshold by at least 500mV.

Battery Management

The ACT8937 features a full-featured, intelligent

charger for Lithium-based cells, and was designed

specifically to provide a complete charging solution

with minimum system design effort.

Input Protection

Input Over-Voltage Protection

The core of the charger is a CC/CV (Constant-

Current/Constant-Voltage), linear-mode charge

controller. This controller incorporates current and

voltage sense circuitry, an internal 70mꢀ power

The ActivePath circuitry features input over-voltage

protection circuitry. This circuitry disables charging

when the input voltage exceeds the voltage set by

OVPSET[-] as shown in Table 9, but stands off the

input voltage in order to protect the system. Note

that the adjustable OVP threshold is intended to

provide the charge cycle with adjustable immunity

against upward voltage transients on the input, and

is not intended to allow continuous charging with

input voltages above the charger's normal operating

voltage range. Independent of the OVPSET[-]

setting, the charge cycle is not allowed to continue

until the input voltage falls back into the charger's

normal operating voltage range (i.e. below 6.0V).

MOSFET, thermal-regulation circuitry,

a

full-

featured state-machine that implements charge

control and safety features, and circuitry that

eliminates the reverse blocking diode required by

conventional charger designs.

The charge termination voltage is highly accurate

(±0.5%), and features a selection of charge safety

timeout periods that protect the system from

operation with damaged cells. Other features

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ACT8937

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include pin-programmable fast-charge current and

one current-limited nSTAT output that can directly

drive LED indicator or provide a logic-level status

charge current defined by the CHGLEV input;

500mA, if CHGLEV is driven to a logic-high, or

100mA, if CHGLEV is driven to a logic-low.

signal to the host microprocessor.

The ACT8937's charge current settings are

summarized in Table 10.

Dynamic Charge Current Control (DCCC)

Note that the actual charge current may be limited

to a current lower than the programmed fast charge

current due to the ACT8937’s internal thermal

regulation loop. See the Thermal Regulation section

for more information.

The ACT8937's ActivePath charger features

dynamic charge current control (DCCC) circuitry,

which acts to ensure that the system remains

powered while operating within the maximum output

capability of the power adapter. The DCCC circuitry

continuously monitors VSYS, and if the voltage at

VSYS drops by more than 200mV, the DCCC

circuitry automatically reduces charge current in

order to prevent VSYS from continuing to drop.

In order to ease input supply detection and

eliminate the size and cost of external detection

circuitry, the charger has the ability to generate

interrupts based upon the status of the input supply.

This function is capable of generating an interrupt

when the input is connected, disconnected, or both.

An interrupt is generated any time the input supply

is connected when INSTAT[ ] bit is set to 1 and the

INCON[-] bit is set to 1, and an interrupt is

generated any time the input supply is disconnected

when INSTAT[ ] bit is set to 1 and the INDIS[ ] bit is

set to 1.

Charge Current Programming

The ACT8937's ActivePath charger features a

flexible charge current-programming scheme that

combines the convenience of internal charge

current programming with the flexibility of resistor

based charge current programming. Current limits

and charge current programming are managed as a

function of the ACIN and CHGLEV pins, in

combination with R^ISET, the resistance connected to

the ISET pin.

The status of the input may be read at any time by

reading the INDAT[-] bit, where a value of 1

indicates that the valid input (V_CHGIN

UVLO<V_CHGIN<V_OVP) is present, and a value of 0

indicates that a valid input is not present. Reading

the INSTAT[-] bit indicates when the input has

generated an interrupt; this bit will normally return a

value of 0, but will return value of 1 when an input

interrupt has been generated then the interrupt is

automatically cleared to 0 upon reading.

ACIN is a logic input that configures the current-limit

of ActivePath's linear regulator as well as that of the

battery charger. ACIN features a precise 1.2V logic

threshold, so that the input voltage detection

threshold may be adjusted with a simple resistive

voltage divider. This input also allows a simple, low-

cost dual-input charger switch to be implemented

with just a few, low-cost components.

When responding to an Input Status Interrupt, it is

often useful to know the state of the ACIN input. For

When the voltage at ACIN is above the 1.2V

threshold, the charger operates in “AC-Mode” with a

charge current programmed by R^ISET, and the RISET

is given by:

example, in

a

dual-input charger application

knowing the state of the ACIN input can identify

which type of input supply has been connected. The

state of the ACIN input can be read at any time by

reading the ACINSTAT[-] bit, where a value of 1

indicates that the voltage at ACIN is above the 1.2V

threshold (indicating that a wall-cube has been

attached), and a value of 0 indicates that the

voltage is below this threshold (indicating that ACIN

input is not valid and USB supply input is selected).

R

_ISET(kꢀ) = 2336 × (1V/I_CHG(mA)) - 0.205

With a given R_ISETthen charge current will reduce 5

times when CHGLEV is driven low.

When ACIN is below the 1.2V threshold, the

charger operates in “USB-Mode”, with a maximum

Table 10:

ACIN and CHGLEV Inputs

CHARGE CURRENT

PRECONDITION CHARGE CURRENT

(mA)

ACIN

CHGLEV

(mA)

0

1

0

1

0

1

90mA

45mA

450mA

I

_CHG/5

I_CHG

10% × I_CHG

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ACT8937

Rev 0, 21-Sep-10

Figure 6:

Typical Li+ charge profile and ACT8937 charge states

A: PRECONDITION State

B: FAST-CHARGE State

C: TOP-OFF State

D: END-OF-CHARGE State

Figure 7:

Charger State Diagram

TEMP NOT OK

ANY STATE

(V_CHGIN< V_BAT) OR (V_CHGIN< V_CHGINUVLO)

OR (V_CHGIN> V_OVP) OR (SUSCHG[ ] = 1)

SUSPEND

TEMP-FAULT

(V_CHGIN> V_BAT) AND (V_CHGIN> V_CHGINUVLO)

AND (V_CHGIN< V_OVP) AND (SUSCHG[ ] = 0)

TEMP OK

PRECONDITION

TIMEOUT-FAULT

PRECONDITION

Timeout

(V_BAT> 2.85V) AND

(T_QUAL= 32ms)

Total Timeout

FAST-CHARGE

(V_BAT= V_TERM) AND

(T_QUAL= 32ms)

(V_BAT< V_TERM- 205mV )

AND (T_QUAL= 32ms)

TOP-OFF

(I_BAT< 10% x I_CHG) OR (Total

Time-out) AND (T_QUAL= 32ms)

END-OF-CHARGE

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ACT8937

Rev 0, 21-Sep-10

presents

a

high-impedance to the battery,

Charge-Control State Machine

minimizing battery current drain and allowing the

cell to “relax”. The charger continues to monitor the

cell voltage, and re-initiates a charging sequence if

the cell voltage drops to 205mV (typ) below the

charge termination voltage.

PRECONDITION State

new charging cycle begins with the

A

PRECONDITION state, and operation continues in

this state until V^BATexceeds the Precondition

Threshold Voltage. When operating in

PRECONDITION state, the cell is charged at 10%

of the programmed maximum fast-charge constant

current, I_CHG[-].

SUSPEND State

The state-machine jumps to the SUSPEND state

any time the battery is removed, and any time the

input voltage falls below either the UVLO threshold

or exceeds the OVP threshold. Once none of these

conditions are present, a new charge cycle initiates.

Once V^BATreaches the Precondition Threshold

Voltage, the state machine jumps to the FAST-

CHARGE state. If V^BATdoes not reach the

Precondition Threshold Voltage before the

Precondition Timeout period expires, then the state

machine jumps to the TIMEOUT-FAULT state in

order to prevent charging a damaged cell. See the

Charge Safety Timers section for more information.

A charging cycle may also be suspended manually

by setting the SUSPEND[ ] bit. In this case, initiate

a new charging sequence by clearing SUSPEND[ ]

to 0.

State Machine Interrupts

FAST-CHARGE State

The charger features the ability to generate

interrupts when the charger state machine

transitions, based upon the status of the CHG_ bits.

An interrupt may be generated when the state

machine transitions to END-OF-CHARGE (EOC)

state by setting the CHGEOCIN[ ] bit to

1 and CHGSTAT[ ] bit to 1. An interrupt may be

generated when machine transitions get out END-

OF-CHARGE (EOC) state by setting the

CHGEOCOUT[ ] bit to 1 and CHGSTAT[ ] bit to 1.

In the FAST-CHARGE state, the charger operates

in constant-current (CC) mode and regulates the

charge current to the current set by R^ISET. Charging

continues in CC mode until V^BATreaches the charge

termination voltage (V^TERM), at which point the state-

machine jumps to the TOP-OFF state. If V_BATdoes

not reach V^TERMbefore the total time out period

expires then the state-machine will jump to the

“EOC” state and will re-initiate a new charge cycle

after 32ms “relax”. See the Current Limits and

Charge Current Programming sections for more

information about setting the maximum charge

current.

The status of the charge state machine may be

read at any time by reading the CHGDAT[-] bit,

where a value of 0 indicates no interrupt generated,

and a value of 1 indicates interrupt generated.

Reading the CHGSTAT[-] bit indicates when a state

machine transition has generated an interrupt; this

bit will normally return a value of 0, but will return

value of 1 when a state transition occurs then the

interrupt is automatically cleared to 0 upon reading.

TOP-OFF State

In the TOP-OFF state, the cell charges in constant-

voltage (CV) mode. In CV mode operation, the

charger regulates its output voltage to the 4.20V

charge termination voltage, and the charge current

is naturally reduced as the cell approaches full

charge. Charging continues until the charge current

drops to END-OF-CHARGE current threshold, at

which point the state machine jumps to the END-

OF-CHARGE (EOC) state.

For additional information about the charge cycle,

CSTATE[1:0] may be read at any time via I²C to

determine the current charging state.

Table 11:

Charging Status Indication

If the state-machine does not jump out of the TOP-

OFF state before the Total-Charge Timeout period

expires, the state machine jumps to the EOC state

and will re-initiate a new charge cycle if V_BATfalls

below termination voltage 205mV (typ). For more

information about the charge safety timers, see the

Charging Safety Times section.

CSTATE[1] CSTATE[0] STATE MACHINE STATUS

0

1

0

1

0

1

PRECONDITION State

FAST-CHARGE State

TOP-OFF State

END-OF-CHARGE State

END-OF-CHARGE (EOC) State

In the END-OF-CHARGE (EOC) state, the charger

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I²C^TMis a trademark of NXP.

®

ACT8937

Rev 0, 21-Sep-10

Table 13:

Thermal Regulation

Total Safety Timer Setting

The charger features an internal thermal regulation

loop that monitors die temperature and reduces

charging current as needed to ensure that the die

temperature does not exceed the thermal regulation

threshold of 110°C. This feature protects against

excessive junction temperature and makes the

device more accommodating to aggressive thermal

designs. Note, however, that attention to good

thermal designs is required to achieve the fastest

possible charge time by maximizing charge current.

TOTAL TIMEOUT

PERIOD

TOTTIMO[1] TOTTIMO[0]

0

1

0

1

0

1

3 hrs

4 hrs

5 hrs

Disabled

Charge Status Indicator

Charge Safety Timers

The charger provides a charge-status indicator

output, nSTAT. nSTAT is an open-drain output

which sinks current when the charger is in an

active-charging state, and is high-Z otherwise.

nSTAT features an internal 8mA current limit, and is

capable of directly driving a LED without the need

of a current-limiting resistor or other external

circuitry. To drive an LED, simply connect the LED

between nSTAT pin and an appropriate supply,

such as VSYS. For a logic-level charge status

indication, simply connect a resistor from nSTAT to

an appropriate voltage supply.

The charger features programmable charge safety

timers which help ensure a safe charge by

detecting potentially damaged cells. These timers

are programmable via the PRETIMO[1:0] and

TOTTIMO[1:0] bits, as shown in Table 12 and Table

13. Note that in order to account for reduced charge

current resulting from DCCC operation, the charge

timeout periods are extended proportionally to the

reduction in charge current. As a result, the actual

safety period may exceed the nominal timer period.

The charger features the ability to generate

interrupts based upon the status of the charge

timers, based upon the status of the TIMR_ bits.

Generate interrupts when the Precondition Timer

expires by setting the TIMRPRE[ ] bit to 1 and

TIMRSTAT[ ] bit to 1, generate interrupts when the

Total-Charge Timer expires by setting the

TIMRTOT[ ] bit to 1 and TIMRSTAT[ ] bit to 1.

Table 14:

Charging Status Indication

STATE

PRECONDITION

FAST-CHARGE

TOP-OFF

nSTAT

Active

High-Z

The status of the charge timers may be read at any

time by reading the TIMRDAT[ ] bit, where a value

of 0 indicates that neither charge timer has expired,

and a value of 1 indicates that one of the charge

timers has expired. Reading the TIMRSTAT[-] bit

indicates when a charge timers has generated an

interrupt; this bit will normally return a value of 0,

but will return value of 1 when a charge-timer

interrupt has been generated then the interrupt is

automatically cleared to 0 upon reading.

END-OF-CHARGE

SUSPEND

TEMPERATURE FAULT

TIMEOUT-FAULT

Reverse-Current Protection

The charger includes internal reverse-current

protection circuitry that eliminates the need for

blocking diodes, reducing solution size and cost as

well as dropout voltage relative to conventional

battery chargers. When the voltage at CHGIN falls

below V^BAT, the charger automatically reconfigures

its power switch to minimize current drawn from the

battery.

Table 12:

PRECONDITION Safety Timer Setting

PRECONDITION

PRETIMO[1] PRETIMO[0]

TIMEOUT PERIOD

0

1

0

1

0

1

40 mins

60 mins

80 mins

Disabled

Battery Temperature Monitoring

In a typical application, the TH pin is connected to

the battery pack's thermistor input, as shown in

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- 41 -

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePMU^TMand ActivePath^TMare trademarks of Active-Semi.

I²C^TMis a trademark of NXP.

®

ACT8937

Rev 0, 21-Sep-10

Figure 8. The charger continuously monitors the

temperature of the battery pack by injecting a

102μA (typ) current into the thermistor (via the TH

pin) and sensing the voltage at TH. The voltage at

TH is continuously monitored, and charging is

suspended if the voltage at TH exceeds either of

the internal VTHH and VTHL thresholds of 0.5V and

2.51V, respectively.

Figure 8:

Simple Configuration

The net resistance (from TH to GA) required to

cross the thresholds are given by:

102μA × RNOM × kHOT = 0.5V → RNOM × kHOT

≈ 5kꢀ

102μA × RNOM × kCOLD = 2.51V → RNOM ×

kCOLD ≈ 25kꢀ

where RNOM is the nominal thermistor resistance

at room temperature, and kHOT and kCOLD

represent the ratios of the thermistor's resistance at

the desired hot and cold thresholds, respectively, to

the resistance at 25°C.

In order to ease detecting the status of the battery

temperature, the charger features the ability to

generate interrupts based upon the status of the

battery temperature. Generate an interrupt when

battery temperature goes out of the valid

temperature range by setting the TEMPOUT[ ] bit to

1 and TEMPSTAT[ ] bit to 1. Generated an interrupt

when battery temperature returns to the valid range

by setting the TEMPIN[ ] bit to 1 and TEMPSTAT[ ]

bit to 1.

The status of the battery temperature may be read

at any time by reading the TEMPDAT[-] bit, where a

value of 1 indicates that battery temperature is

within the valid range, and a value of 0 indicates

that battery temperature has exceeded either of the

thresholds. Reading the TEMPSTAT[-] bit indicates

when the battery temperature has generated an

interrupt; this bit will normally return a value of 0,

but will return value of 1 when a cell-temperature

interrupt has been generated then the interrupt is

automatically cleared to 0 upon reading.

Innovative Power^TM

- 42 -

www.active-semi.com

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePMU^TMand ActivePath^TMare trademarks of Active-Semi.

I²C^TMis a trademark of NXP.

®

ACT8937

Rev 0, 21-Sep-10

TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS

DIMENSION IN

MILLIMETERS

DIMENSION IN

INCHES

SYMBOL

MIN

MAX

MIN

MAX

A

A1

A2

b

0.700

0.800

0.028

0.031

0.200 REF

0.008 REF

0.000

0.150

4.900

3.450

0.050

0.250

5.100

3.750

0.000

0.006

0.193

0.136

0.002

0.010

0.201

0.148

D

E

D2

E2

e

0.400 BSC

0.016 BSC

L

0.300

0.500

0.012

0.020

R

0.300

0.012

Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each

product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use

as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of

the use of any product or circuit described in this datasheet, nor does it convey any patent license.

Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact

sales@active-semi.com or visit http://www.active-semi.com.

®

is a registered trademark of Active-Semi.

Innovative Power^TM

- 43 -

www.active-semi.com

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePMU^TMand ActivePath^TMare trademarks of Active-Semi.

I²C^TMis a trademark of NXP.


型号：	ACT8937QJ206-T
厂家：	ACTIVE-SEMI, INC
描述：	Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors PC
文件：	总44页 (文件大小：975K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ACT8937QJ206-T [ACTIVE-SEMI]

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