ADS4616A4A-7 [ADATA]
Synchronous DRAM(512K X 16 Bit X 2 Banks); 同步DRAM （ 512K ×16位×2组）
| 型号： | ADS4616A4A-7 |
| 厂家： | 
ADATA Technology Co., Ltd. |
| 描述： | Synchronous DRAM(512K X 16 Bit X 2 Banks) |
| 文件： | 总8页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A-Data
ADS4616A4A
512K x 16 Bit x 2 Banks
Synchronous DRAM
General Description
Features
•Single 3.3V +/- 0.3V power supply
The ADS4616A4A are two-bank Synchronous
DRAMs organized as 524,288 words x 16 bits x 2
banks,
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
-Burst Length (1,2,4,8, & full page)
-Burst Type (sequential & Interleave)
•2 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:50-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
200Mhz
166Mhz
143Mhz
Interface
Package
ADS4616A4A-5
ADS4616A4A -6
ADS4616A4A -7
LVTTL
LVTTL
LVTTL
400mil 50pin TSOPII
400mil 50pin TSOPII
400mil 50pin TSOPII
Pin Assignment
V
DD
1
2
Vss
50
49
48
47
DQ0
DQ15
DQ14
3
DQ1
VSSQ
Vss
Q
4
DQ2
5
DQ13
DQ12
46
45
44
6
DQ3
VDDQ
7
VDD
Q
8
DQ11
43
42
DQ4
DQ5
9
DQ10
VSSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SSQ
V
41
40
39
DQ9
DQ6
DQ8
VDDQ
DQ7
VDDQ
38
37
36
35
NC
LDQM
/WE
UDQM
CLK
/CAS
/RAS
CKE
34
NC
A9
/CS
33
32
31
(BS)A11
A10
A0
A8
A7
A6
30
29
A1
A5
A4
A2
28
27
26
A3
V
SS
VDD
50-pin plastic TSOP II 400 mil
Rev 1 December, 2001
1
A-Data
ADS4616A4A
Pin Description
PIN
NAME
FUNCTION
CLK
CKE
System Clock
Active on the positive edge to sample all inputs.
Clock Enable
Chip Select
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A10 Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A10
Column address : A0~A7
DQ0~DQ15 Data
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
L(U)DQM Data Mask
/RAS
/CAS
/WE
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Column Address Strobe
Write Enable
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
Clock
Generator
CKE
Bank B
Address
Address
Buffer
&
Bank A
Mode
Register
Refresh
Counter
Amplifier
DQM
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
DQ
Data Control Circuit
/WE
Rev 1 December, 2001
2
A-Data
ADS4616A4A
Absolute Maximum Ratings
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-0.3~ 4.6
-0.3~ 4.6
-55 ~ +150
1
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
V
℃
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
Max
Unit
V
Note
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VDD+0.3
V
1
VIL
0.8
-
V
2
VOH
-
-
-
-
V
IOH=-2mA
VOL
0.4
5
V
IOL=2mA
IIL
-5
uA
uA
3
4
IOL
-5
5
Note : 1. VIH (max)=V
+2.0V with a pulse width < 3ns
DDH
2.VIL(min)=V
-2.0V with a pulse < 3ns and – 1.5V with a pulse < 5ns
SSQ
3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≦ VOUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
AC input high / low level voltage
Symbol
VIH / VIL
Vtrip
Value
1.4 / 1.4
1.4
Unit
V
Note
Input timing measurement reference level voltage
Input rise / fall time
V
TR / tF
Voutfef
CL
1
ns
V
Output timing measurement reference level
Output load capacitance for access time measurement
1.4
50
pF
Rev 1 December, 2001
3
A-Data
ADS4616A4A
Capacitance
TA=25℃, f-=1Mhz, VDD=3.3V
Parameter
Pin
Symbol
C11
Min
2.5
2.5
Max
4
Unit
pF
Input capacitance
CLK
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
C12
5
pF
Data input / output capacitance DQM
CI/O
4
6.5
pF
Output load circuit
1.4 V
50 ohms
Z= 50 ohms
Output
30 pF
DC Characteristics I
Parameter
Symbol
Min
-5
Max
Unit
uA
uA
V
Note
Input leakage current
Output leakage current
Output high voltage
Output low voltage
I
I
LI
5
5
1
2
LO
-5
V
V
OH
OL
2.4
-
-
I
OH = -2mA
0.4
V
IOL = 2mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.DOUT is disabled, VOUT = 0 to 3.6.
Rev 1 December, 2001
4
A-Data
ADS4616A4A
DC Characteristics II
Speed
-6
Parameter
Symbol
Test condition
Unit
mA
Note
1
-5
-7
Burst length=1, One bank active
Operating Current
IDD1
70
60
50
tRC≧tRC(min),IOL=0mA
Precharge standby
current in power
down mode
CKE≦VIL(max), tCK=min
CKE≦VIL(max), tCK=∞
IDD2P
1
1
mA
mA
mA
IDD2PS
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
Precharge standby
current in Non power
down mode
IDD2N changed one time during 2clks.
All other pins ≧VDD-0.2V or ≦
0.2V
35
30
25
CKE≧VIH(min), tCK=∞
IDD2NS
8
Input signals are stable.
Active standby
current in power
down mode
CKE≦VIL(max), tCK=min
IDD3P
45
40
35
CKE≧VIH(min), /CS≧VIH(min),
Active standby
tCK=min input signals are
current in Non power IDD3N changed one time during 2clks.
3
mA
mA
All other pins ≧VDD-0.2V or ≦
0.2V
down mode
tCK≧tCK(min),IOL=0 mA
All banks active
Burst mode operating
current
IDD4
120
60
110
100
50
1
2
tRRC≧tRRC(min), All banks
active
Auto refresh current IDD5
Self refresh current IDD6
55
mA
uA
CKE≦0.2V
200
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1 December, 2001
5
A-Data
ADS4616A4A
AC Characteristics
-5
-6
-7
Parameter
Symbol
Unit Note
Min Max Min Max Min Max
System clock /CAS Latency = 3 tCK3
Cycle time
5
7
6
8
2
2
-
7
10
2
1000
1000
1000 ns
/CAS Latency = 2 tCK2
Clock high pulse width
Clock low pulse width
tCHW
tCLW
2
-
-
-
-
-
ns
ns
1
1
2
-
2
Access time /CAS Latency = 3 tAC3
-
4.5
4.5
5
-
5
ns
2
form clock
/CAS Latency = 2 tAC2
tRC
-
-
5.5
-
-
5.5
-
54
60
65
Row cycle time
-
-
ns
ns
/RAS to /CAS delay
/RAS active time
tRCD
tRAS
tRP
14
18
-
20
-
40 100K 42 100K 45 100K ns
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
Address hold time
14
10
1
-
-
18
12
1
-
-
20
14
1
-
-
-
-
-
-
-
-
-
ns
ns
tRRD
tCCD
tOH
-
-
CLK
ns
1.5
1.5
1
-
2
-
2.5
1.5
1
tDS
-
1.5
1
-
ns
1
1
1
1
tDH
-
-
ns
tAS
1.5
1
-
1.5
1
-
1.5
1
ns
tAH
-
-
ns
Power down exit time
Refresh time
tPDE
tREF
5
-
5
-
5
CLK
64
64
64 ms
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1 December, 2001
6
A-Data
ADS4616A4A
Command Truth-Table
Command
Mode Register Set
No Operation
Bank Active
CKEn-1 CKEn
/CS
L
/RAS
/CAS
/WE
L
A10
X
A9-A0
H
H
H
X
X
X
L
H
L
L
H
H
V
X
L
H
X
L
H
V
Read
L
H
H
H
X
X
L
L
H
H
L
L
L
H
L
V
V
Read with Auto Precharge
Write
H
L
H
H
Write with Auto Precharge
Precharge All Bank
X
X
X
X
L
L
H
H
L
L
Precharge select Bank
L
Burst Stop
DQM
H
H
H
H
X
L
X
X
Entry
L
L
H
L
L
X
H
H
X
H
Self Refresh
Exit
X
X
H
L
H
Entry
H
L
X
X
Precharge
X
X
Power down
Exit
L
H
Entry
H
L
L
L
X
X
Clock Suspend
Exit
Rev 1 December, 2001
7
A-Data
ADS4616A4A
Package Information
500
266
255
MILLIMETER
NOM.
INCH
NOM.
SYMBOL
MIN.
MAX.
1.20
0.15
1.05
0.45
0.21
MIN.
MAX.
0.047
0.006
0.041
0.018
0.008
A
A1
A2
B
0.05
0.95
0.30
0.12
0.10
1.00
0.002
0.037
0.012
0.005
0.039
c
D
HE
E
e
L
21.08 BSC
11.76
10.16
0.830 BSC
0.463
0.400
11.56
10.03
0.80 BSC
0.40
11.96
10.29
0.460
0.395
0.0315
0.016
0.471
0.405
0.50
0.60
0.020
0.024
L1
S
0.80 REF
0.71 REF
0.031 REF
0.028 REF
0 °
-
5 °
0 °
-
5 °
θ
400mil 50pin TSOP II Package
Rev 1 December, 2001
8
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