ADS6632A4A [ADATA]
Synchronous DRAM(512K X 32 Bit X 4 Banks); 同步DRAM ( 512K ×32位×4银行)型号: | ADS6632A4A |
厂家: | ADATA Technology Co., Ltd. |
描述: | Synchronous DRAM(512K X 32 Bit X 4 Banks) |
文件: | 总8页 (文件大小:596K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
A-Data
ADS6632A4A
512K x 32 Bit x 4 Banks
Synchronous DRAM
General Description
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
The ADS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
-CAS Latency (2 & 3)
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:86-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
200Mhz
183Mhz
166Mhz
Interface
Package
ADS6632A4A-5
LVTTL
LVTTL
LVTTL
400mil 86pin TSOPII
400mil 86pin TSOPII
400mil 86pin TSOPII
ADS6632A4A-5.5
ADS6632A4A-6
Pin Assignment
V
DD
V
S S
1
2
3
4
5
6
7
8
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
DQ0
DQ15
V
DDQ
DQ1
DQ2
V
S SQ
DQ14
DQ13
V
S S Q
DQ3
DQ4
V
DDQ
DQ12
DQ11
V
DDQ
DQ5
DQ6
V
S SQ
9
DQ10
DQ9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
V
S S Q
DQ7
NC
V
DDQ
DQ8
N C
V
DD
V
S S
DQM 0
WE
DQM 1
N C
N C
CLK
CKE
A9
CA S 1 8
RA S 1 9
CS
2 0
NC
21
22
23
24
25
26
27
28
29
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
39
4 0
4 1
4 2
4 3
A8
BA0
BA1
A10/AP
A0
A7
A6
A5
A4
A1
A3
A2
DQM 3
DQM 2
V
S S
V
DD
N C
DQ31
NC
DQ16
V
DDQ
V
SSQ
DQ30
DQ29
DQ17
DQ18
V
S S Q
V
DDQ
DQ28
DQ27
DQ19
DQ20
V
DDQ
V
SSQ
DQ26
DQ25
DQ21
DQ22
V
S S Q
V
DDQ
DQ24
DQ23
V
S S
V
DD
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1
A-Data
ADS6632A4A
Pin Description
PIN
NAME
FUNCTION
CLK
CKE
System Clock
Active on the positive edge to sample all inputs.
Clock Enable
Chip Select
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11 Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
DQ0~DQ31 Data
DQM0~3 Data Mask
/RAS
/CAS
/WE
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Column Address Strobe
Write Enable
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
Clock
Generator
Bank3
Bank2
CKE
Bank1
Address
Address
Buffer
&
Bank0
Mode
Register
Refresh
Counter
Amplifier
DQM
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
Data Control Circuit
DQ
/WE
Rev 1.0 April, 2001
2
A-Data
ADS6632A4A
Absolute Maximum Ratings
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
V
℃
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
3.0
VDD+0.3
V
1
VIL
0
-
0.8
-
V
2
VOH
V
IOH=-2mA
VOL
-
0.4
5
V
IOL=2mA
IIL
-5
-
uA
uA
3
4
IOL
-5
-
5
Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable.
2.VIL(min)=-1.5V AC for pulse width ≦ 10ns acceptable.
3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≦ VOUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
AC input high / low level voltage
Symbol
VIH / VIL
Vtrip
Value
2.4 / 0.4
1.4
Unit
V
Note
Input timing measurement reference level voltage
Input rise / fall time
V
TR / tF
Voutfef
CL
1
Ns
V
Output timing measurement reference level
Output load capacitance for access time measurement
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for ADS6632A4A5.
1.4
30
pF
2
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
3
A-Data
ADS6632A4A
Capacitance
TA=25℃, f-=1Mhz, VDD=3.3V
Parameter
Pin
Symbol
Cl1
Min
Max
4
Unit
Input capacitance
CLK
2.5
2.5
pF
pF
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2
5
Data input / output capacitance DQM
CI/O
4
6.5
pF
Output load circuit
3.3 V
1200 ohms
V
OH(DC) = 2.4V,IOH= -2mA
Output
V
OL(DC) = 0.4V,IOL= 2mA
50 pF
870 ohms
DC Characteristics I
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
Min
Max
1
Unit
uA
Note
I
I
LI
-1
-1.5
2.4
-
1
2
LO
1.5
-
uA
V
V
OH
OL
V
V
I
OH = -2mA
0.4
IOL = 2mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.DOUT is disabled, VOUT = 0 to 3.6.
Rev 1.0 April, 2001
4
A-Data
ADS6632A4A
DC Characteristics II
Speed
-5.5
Parameter
Symbol
Test condition
Unit
mA
Note
1
-5
-6
Burst length=1, One bank active
Operating Current
IDD1
210
200
190
tRC≧tRC(min),IOL=0mA
Precharge standby
current in power down
mode
CKE≦VIL(max), tCK=min
CKE≦VIL(max), tCK=∞
IDD2P
2
2
mA
IDD2PS
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
0.2V
Precharge standby
current in Non power
down mode
IDD2N
15
mA
mA
CKE≧VIH(min), tCK=∞
Input signals are stable.
IDD2NS
12
CKE≦VIL(max), tCK=min
CKE≦VIL(max), tCK=∞
IDD3P
6
5
Active standby current
in power down mode
IDD3PS
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
0.2V
Active standby current IDD3N
in Non power down
mode
30
mA
mA
CKE≧VIH(min), tCK=∞
Input signals are stable.
tCK≧tCK(min),IOL=0 mA
All banks active
IDD3NS
20
Burst mode operating
IDD4
280
250
270
260
230
1
2
current
tRRC≧tRRC(min), All banks
active
Auto refresh current IDD5
240
1
mA
mA
CKE≦0.2V
Self refresh current
IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1.0 April, 2001
5
A-Data
ADS6632A4A
AC Characteristics
-5
-5.5
Max
-6
Parameter
Symbol
Unit
ns
Note
Min
5
Max
Min
5.5
10
Min
6
Max
System clock
Cycle time
/CAS Latency = 3 tCK3
/CAS Latency = 2 tCK2
1000
1000
1000
10
2
10
2.5
2.5
-
Clock high pulse width
Clock low pulse width
tCHW
tCLW
-
-
2.25
2.25
-
-
-
-
ns
ns
1
1
2
-
Access time form /CAS Latency = 3 tAC3
-
4.5
6
-
5
6
-
5.5
ns
ns
2
clock
/CAS Latency = 2 tAC2
-
-
-
6
Operation
tRC
55
55
15
40
15
10
1
55
60
60
18
42
18
12
1
-
/RAS cycle time
Auto Refresh
tRRC
tRCD
tRAS
tRP
-
55
-
-
/RAS to /CAS delay
-
16.5
-
-
ns
ns
/RAS active time
100K 38.5 100K
100K
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
-
-
16.5
11
1
-
-
-
-
ns
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tOH
ns
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
ns
Write command to data – in delay
Data – in to precharge command
Data – in active command
DQM to data – out Hi-Z
DQM to data – in mask
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
0
-
0
-
0
-
1
-
1
-
1
-
5
-
5
-
5
-
2
-
2
-
2
-
0
-
0
-
0
-
1.5
1.5
1
-
2
-
2
-
tDS
-
1.5
1
-
1.5
1
-
ns
1
1
1
1
1
1
1
1
tDH
-
-
-
ns
tAS
1.5
1
-
1.5
1
-
1.5
1
-
ns
Address hold time
tAH
-
-
-
ns
CKE setup time
tCKS
tCKH
tCS
1.5
1
-
1.5
1
-
1.5
1
-
ns
CKE hold time
-
-
-
ns
Command setup time
Command hold time
CLK to data output in low Z-time
MRS to new command
Power down exit time
Self refresh exit time
Refresh time
1.5
1
-
1.5
1
-
1.5
1
-
ns
tCH
-
-
-
ns
tOLZ
tMRD
tPDE
tSRE
tREF
1
-
1
-
1
-
ns
2
-
2
-
2
-
CLK
CLK
CLK
ms
1
-
1
-
1
-
1
-
1
-
1
-
3
-
64
-
64
-
64
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
6
A-Data
ADS6632A4A
Command Truth-Table
Command
CKEn-1 CKEn
/CS
L
/RAS
/CAS
/WE
L
DQM ADDR A10/AP
BA
Mode Register Set
H
H
H
H
X
X
X
X
L
X
H
L
L
X
H
H
X
X
X
X
OP code
H
X
No Operation
X
L
H
Bank Active
Read
L
H
RA
V
V
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Auto Precharge
Write
H
L
H
H
X
X
X
V
Write with Auto Precharge
Precharge All Bank
H
H
X
V
X
X
L
L
H
H
L
L
Precharge select Bank
Burst Stop
DQM
L
X
X
X
H
H
H
H
H
X
L
X
V
X
X
Auto Refresh
Entry
H
L
L
L
L
L
H
H
X
H
X
H
X
L
Self Refresh
Exit
X
X
X
H
L
X
H
X
H
X
X
H
X
H
X
L
H
L
X
X
H
L
Entry
H
Precharge
H
Power down
Exit
L
H
X
L
H
H
H
H
L
X
V
X
V
X
V
Entry
H
L
L
X
X
Clock Suspend
Exit
H
X
Rev 1.0 April, 2001
7
A-Data
ADS6632A4A
Package Information
Symbol
Min
Dimension in mm
Dimension in inch
Norm
Max
1.20
0.15
1.05
0.27
0.23
0.21
0.16
Min
Norm
Max
0.047
0.006
0.011
0.018
0.009
0.008
0.006
A
A1
A2
b
0.05
0.95
0.17
0.17
0.12
0.10
0.10
1.00
0.002
0.037
0.007
0.007
0.005
0.004
0.004
0.039
b1
c
0.20
0.008
c1
D
0.127
0.005
22.22 BSC
0.61 REF
11.76 BSC
10.16 BSC
0.50
0.875 BSC
0.024 REF
0.463 BSC
0.400 BSC
ZD
E
E1
L
0.40
0.60
0.016
0.020
0.024
L1
e
0.80 REF
0.50 BSC
0.031 REF
0.020 BSC
R1
R2
0.12
0.12
0
0.005
0.005
0
0.25
8
0.010
8
1
2
3
0
0
10
10
15
15
20
20
10
10
15
15
20
20
400mil 86pin TSOP II Package
Rev 1.0 April, 2001
8
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