ADS7029QDCURQ1 [TI]
超低功耗、超小型 8 位 2MSPS SAR ADC | DCU | 8 | -40 to 125;
| 型号： | ADS7029QDCURQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低功耗、超小型 8 位 2MSPS SAR ADC | DCU | 8 | -40 to 125 |
| 文件： | 总30页 (文件大小：1108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7029-Q1
ZHCSFX9 –JANUARY 2017
ADS7029-Q1小型低功耗 8 位、2MSPS SAR ADC
1 特性
2 应用
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
•
•
•
•
•
•
车用信息娱乐
车用传感器
液位传感器
超声波流量计
电机控制
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模型 (HBM) 静电放电 (ESD) 分类
等级 ±2000V
便携式医疗设备
器件带电器件模型 (CDM) 静电放电 (ESD) 分类
等级 ±1000V
3 说明
•
•
超低功耗：
ADS7029-Q1器件是一款符合汽车类 Q100 标准的 8
位、2MSPS 模数转换器 (ADC)。此器件支持宽范围的
模拟输入电压（2.35V 至 3.6V），并且包括一个基于
电容器且内置采样保持电路的 SAR ADC。串行外设接
口 (SPI) 兼容串口由 CS 和 SCLK 信号控制。输入信
号在 CS 下降沿进行采样，SCLK 用于转换和串行数据
输出。此器件支持宽范围的数字电源（1.65V 至
3.6V），可直接连接到各类主机控制器。ADS7029-
Q1符合 JESD8-7A 标准的标称 DVDD 范围（1.65V 至
1.95V）。
–
2MSPS、AVDD 为 3V 时的功耗为 1.11 mW
（最大值）
–
1kSPS、AVDD 为 3V 时的功耗低于 1µW
微型封装：
8 引脚超薄小外形尺寸 (VSSOP) 封
装：2.30mm × 2.00mm
–
•
•
吞吐量为 2MSPS 且零延迟
宽工作电压范围：
–
–
–
AVDD：2.35V 至 3.6V
DVDD：1.65V 至 3.6V（与 AVDD 无关）
温度范围：-40°C 至 +125°C
ADS7029-Q1采用 8 引脚微型超薄小外形尺寸
(VSSOP) 封装，额定工作温度范围为 –40°C 至 +125°
C。ADS7029-Q1采样速率较快，采用微型封装并具有
低功耗特性，适用于空间受限的汽车类快速扫描 标准
的理想选择。
•
性能优异：
–
–
8 位分辨率且无丢码 (NMC)
±0.2 最低有效位 (LSB) 微分非线性
(DNL)；±0.25 最低有效位 (LSB) 积分非线性
(INL)
器件信息(1)
–
–
信噪比 (SNR) 为 49dB（3V AVDD 时）
部件名称
封装
封装尺寸（标称值）
总谐波失真 (THD) 为 -70dB（3V AVDD 时）
超薄小外形尺寸封装
(VSSOP)(8)
ADS7029-Q1
2.30mm x 2.00mm
•
•
•
•
单极输入范围：0V 至 AVDD
集成偏移校准
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
兼容 SPI 的串行接口：32MHz
符合 JESD8-7A 标准的数字 I/O
典型应用
AVDD
AVDD used as
Reference for device
OPA_AVDD
R
AVDD
+
AINP
+
VIN+
ADS7029-Q1
œ
C
AINM
GND
OPA_AVSS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS811
ADS7029-Q1
ZHCSFX9 –JANUARY 2017
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 12
7.1 Digital Voltage Levels ............................................. 12
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
10 Power Supply Recommendations ..................... 23
10.1 AVDD and DVDD Supply Recommendations....... 23
10.2 Estimating Digital Power Consumption................. 23
10.3 Optimizing Power Consumed by the Device ........ 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 文档支持................................................................ 25
12.2 接收文档更新通知 ................................................. 25
12.3 社区资源................................................................ 25
12.4 商标....................................................................... 25
12.5 静电放电警告......................................................... 25
12.6 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
7
8
4 修订历史记录
日期
修订版本
注释
2017 年 1 月
*
最初发布。
2
Copyright © 2017, Texas Instruments Incorporated
ADS7029-Q1
www.ti.com.cn
ZHCSFX9 –JANUARY 2017
5 Pin Configuration and Functions
DCU Package
8-Pin Leaded VSSOP
Top View
DVDD
SCLK
SDO
CS
1
2
3
4
8
7
6
5
GND
AVDD
AINP
AINM
Not to scale
Pin Functions
NAME
AINM
NO.
5
I/O
DESCRIPTION
Analog input
Analog input
Supply
Analog signal input, negative
Analog signal input, positive
AINP
AVDD
CS
6
7
Analog power-supply input, also provides the reference voltage to the ADC
4
Digital input
Supply
Chip-select signal, active low
DVDD
GND
SCLK
SDO
1
Digital I/O supply voltage
8
Supply
Ground for power supply, all analog and digital signals are referred to this pin
2
Digital input
Digital output
Serial clock
3
Serial data out
Copyright © 2017, Texas Instruments Incorporated
3
ADS7029-Q1
ZHCSFX9 –JANUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–60
MAX
3.9
UNIT
V
AVDD to GND
DVDD to GND
3.9
V
AINP to GND
AVDD + 0.3
0.3
V
AINM to GND
V
Digital input voltage to GND
Storage temperature, Tstg
DVDD + 0.3
150
V
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.35
1.65
–40
NOM
MAX
3.6
UNIT
AVDD
DVDD
TA
Analog supply voltage range
Digital supply voltage range
Operating free-air temperature
V
V
3.6
125
°C
6.4 Thermal Information
ADS7029-Q1
THERMAL METRIC(1)
DCU (VSSOP)
8 PINS
181.8
50.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
73.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.0
ψJB
73.9
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
ADS7029-Q1
www.ti.com.cn
ZHCSFX9 –JANUARY 2017
6.5 Electrical Characteristics
at TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 2 MSPS, and VAINM = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage span(1)
0
–0.1
–0.1
AVDD
AVDD + 0.1
0.1
V
V
AINP to GND
AINM to GND
Absolute input
voltage range
CS
Sampling capacitance
15
8
pF
SYSTEM PERFORMANCE
Resolution
Bits
Bits
LSB(2)
NMC
INL
No missing codes
8
–0.5
–0.4
Integral nonlinearity
Differential nonlinearity
Offset error
AVDD = 3 V
±0.25
±0.2
±0.5
±25
0.5
0.4
DNL
EO
AVDD = 3 V
LSB
LSB
dVOS/dT
EG
Offset error drift with temperature
Gain error
ppm/°C
%FS
AVDD = 3 V
±0.2
±25
Gain error drift with temperature
No calibration
ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time
Maximum throughput rate
DYNAMIC CHARACTERISTICS
120
ns
32-MHz SCLK, AVDD = 2.35 V to 3.6 V
2
MHz
SNR
Signal-to-noise ratio(3)
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
At –3 dB, AVDD = 3 V
48.5
48.5
49
–70
49
dB
dB
THD
Total harmonic distortion(3)(4)
Signal-to-noise and distortion(3)
Spurious-free dynamic range(3)
Full-power bandwidth
SINAD
SFDR
BW(fp)
dB
75
dB
25
MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
VIL
High-level input voltage(5)
Low-level input voltage(5)
0.65 × DVDD
DVDD + 0.3
0.35 × DVDD
DVDD
V
V
–0.3
At Isource = 500 µA
At Isource = 2 mA
At Isink = 500 µA
At Isink = 2 mA
0.8 × DVDD
VOH
High-level output voltage(5)
Low-level output voltage(5)
V
V
DVDD – 0.45
DVDD
0
0
0.2 × DVDD
0.45
VOL
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
IAVDD
IDVDD
PD
Analog supply voltage
Digital I/O supply voltage
Analog supply current
Digital supply current
Power dissipation
2.35
1.65
3
3
3.6
3.6
V
V
At 2 MSPS with AVDD = 3 V
AVDD = 3 V, no load, no transitions
At 2 MSPS with AVDD = 3 V
335
10
370
µA
µA
mW
1.005
1.11
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
(4) Calculated on the first nine harmonics of the input frequency.
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Digital Voltage Levels section for
more details.
Copyright © 2017, Texas Instruments Incorporated
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ZHCSFX9 –JANUARY 2017
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6.6 Timing Requirements
all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF
(unless otherwise specified)
MIN
120
0.016
41.67
0.45
0.45
30
TYP
MAX
UNIT
ns
tACQ
Acquisition time
fSCLK
SCLK frequency
24
MHz
ns
tSCLK
SCLK period
tPH_CK
tPL_CK
tPH_CS
tSU_CSCK
tD_CKCS
SCLK high time
0.55
0.55
tSCLK
tSCLK
ns
SCLK low time
CS high time
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
12
ns
10
ns
6.7 Switching Characteristics
all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF
(unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fTHROUGHP
UT
Throughput
2
MSPS
tCYCLE
Cycle time
0.5
µs
ns
ns
tCONV
Conversion time
8.5 × tSCLK + tSU_CSCK
10
tDV_CSDO
Delay time: CS falling to data enable
Delay time: SCLK falling to (next)
data valid on DOUT
tD_CKDO
AVDD = 2.35 V to 3.6 V
25
ns
ns
Delay time: CS rising to DOUT going
to tri-state
tDZ_CSDO
5
Sample
N+1
Sample
N
tCYCLE
tCONV
tACQ
tSU_CSCK
CS
1
0
2
3
4
5
6
7
8
9
10
SCLK
SDO
D4
D3
0
D6
D5
D2
D1
D0
D7
Data for Sample N
Figure 1. Timing Diagram
6
Copyright © 2017, Texas Instruments Incorporated
ADS7029-Q1
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ZHCSFX9 –JANUARY 2017
6.8 Typical Characteristics
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
200
400
600
800
1000
0
200
400
600
800
1000
Input Frequency (kHz)
Input Frequency (kHz)
D001
D002
SNR = 49.65 dB, THD = –73.26 dB, fIN = 2 kHz,
AVDD = 3 V
SNR = 49.19 dB, THD = –71.25 dB, fIN = 250 kHz,
AVDD = 3 V
Figure 2. Typical FFT
Figure 3. Typical FFT
52
8
52
49
46
43
40
8
49
46
43
40
7.75
7.5
7.25
7
7.75
7.5
7.25
7
SNR
SINAD
ENOB
SNR
SINAD
ENOB
-40
-7
26
59
92
125
2
33
64
95
126
157
188
219
250
Free-Air Temperature (èC)
Input Frequency (kHz)
D003
D004
fIN = 2 kHz, AVDD = 3 V
AVDD = 3 V
Figure 4. SNR and SINAD vs Temperature
Figure 5. SNR and SINAD vs Input Frequency
-65
-67
-69
-71
-73
-75
52
50.5
49
47.5
46
44.5
43
41.5
40
SNR
SINAD
2.35
2.6
2.85
3.1
3.35
3.6
-40
-7
26
59
92
125
Reference Voltage (V)
Free-Air Temperature (èC)
D005
D006
fIN = 2 kHz
fIN = 2 kHz, AVDD = 3 V
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
Figure 7. THD vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
67
65
63
61
59
57
-75
-73
-71
-69
-67
-65
-40
-7
26
59
92
125
0
50
100
150
200
250
Free-Air Temperature (èC)
Input Frequency (kHz)
D007
D008
fIN = 2 kHz, AVDD = 3 V
AVDD = 3 V
Figure 8. SFDR vs Temperature
Figure 9. THD vs Input Frequency
-65
-68
-71
-74
-77
-80
85
82
79
76
73
70
0
50
100
150
200
250
2.35
2.6
2.85
3.1
3.35
3.6
Input Frequency (kHz)
Reference Voltage (V)
D009
D010
fIN = 2 kHz, AVDD = 3 V
Figure 10. SFDR vs Input Frequency
Figure 11. THD vs Reference Voltage (AVDD)
90
86
82
78
74
70
70000
60000
50000
40000
30000
20000
10000
0
2.35
2.6
2.85
3.1
3.35
3.6
126
127
128
Reference Voltage (V)
Code
D011
D012
fIN = 2 kHz, AVDD = 3 V
Mean code = 127, sigma = 0, AVDD = 3 V
Figure 12. SFDR vs Reference Voltage (AVDD)
Figure 13. DC Input Histogram
8
Copyright © 2017, Texas Instruments Incorporated
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ZHCSFX9 –JANUARY 2017
Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
0.5
0.5
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
64
128
192
256
0
64
128
192
256
Code
Code
D017
D018
AVDD = 2.35 V
AVDD = 2.35 V
Figure 14. Typical DNL
Figure 15. Typical INL
0.5
0.3
0.5
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
64
128
192
256
0
64
128
192
256
Code
Code
D019
D020
AVDD = 3 V
AVDD = 3 V
Figure 16. Typical DNL
Figure 17. Typical INL
0.5
0.3
0.5
0.3
Maximum
Minimum
Maximum
Minimum
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40
-7
26
59
92
125
2.35
2.6
2.85
3.1
3.35
3.6
Free-Air Temperature (èC)
Reference Voltage (V)
D021
D022
AVDD = 3 V
Figure 18. DNL vs Temperature
Figure 19. DNL vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
0.5
0.5
Maximum
Minimum
Maximum
Minimum
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40
-7
26
59
92
125
2.35
2.6
2.85
3.1
3.35
3.6
Free-Air Temperature (èC)
Reference Voltage (V)
D023
D024
AVDD = 3 V
Figure 20. INL vs Temperature
Figure 21. INL vs Reference Voltage (AVDD)
400
375
350
325
300
0.4
0.3
0.2
0.1
0
-40
-7
26
59
92
125
100
600
1100
1600
2000
Free-Air Temperature (èC)
Throughput (Ksps)
D025
D026
AVDD = 3 V
AVDD = 3 V
Figure 22. AVDD Supply Current vs Temperature
Figure 23. AVDD Supply Current vs Throughput
0.45
0.4
8
7.9
7.8
7.7
7.6
7.5
0.35
0.3
0.25
2.35
2.6
2.85
3.1
3.35
3.6
0
500
1000
1500
2000
Supply Voltage (V)
Sampling rate (kSPS)
D027
D029
fSample = 2 MSPS
AVDD = DVDD = 3.3 V
Figure 25. ENOB vs Sampling Rate
Figure 24. AVDD Supply Current vs Supply Voltage
10
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ZHCSFX9 –JANUARY 2017
Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
50
49.75
49.5
49.25
49
50
49.8
49.6
49.4
49.2
49
48.8
48.6
48.4
48.2
48
48.75
48.5
48.25
48
0
500
1000
1500
2000
0
500
1000
1500
2000
Sampling rate (kSPS)
Sampling rate (kSPS)
D030
D031
AVDD = DVDD = 3.3 V
AVDD = DVDD = 3.3 V
Figure 26. SNR vs Sampling Rate
Figure 27. SINAD vs Sampling Rate
-72
-71.5
-71
-70.5
-70
0
500
1000
Sampling rate (kSPS)
1500
2000
D032
AVDD = DVDD = 3.3 V
Figure 28. THD vs Sampling Rate
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 29 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
VIL
DVDD = 1.65 V to 1.95 V
-0.3V
Figure 29. Digital Voltage Levels as per the JESD8-7A Standard
8 Detailed Description
8.1 Overview
The ADS7029-Q1 is an ultra-low-power, miniature analog-to-digital converter (ADC) that supports a wide analog
input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples
the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock
provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM
pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are
reconnected across the AINP and AINM pins and the ADS7029-Q1 enters acquisition phase.
The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up
or during normal operation; see the Offset Calibration section for more details.
The device also provides a simple serial interface to the host controller and operates over a wide range of digital
power supplies. The ADS7029-Q1 requires only a 24-MHz SCLK for supporting a throughput of 2 MSPS. The
digital interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram
section provides a block diagram of the device.
12
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8.2 Functional Block Diagram
DVDD
AVDD
GND
Offset
Calibration
AINP
AINM
CS
SCLK
SDO
CDAC
Comparator
Serial
Interface
œ
SAR
8.3 Feature Description
8.3.1 Reference
The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 30. The AVDD pin is
recommended to be decoupled with a 3.3-µF, low equivalent series resistance (ESR) ceramic capacitor.. The
AVDD pin functions as a switched capacitor load to the source powering AVDD. The decoupling capacitor
provides the instantaneous charge required by the internal circuit and helps in maintaining a stable dc voltage on
the AVDD pin. The AVDD pin is recommended to be powered with a low output impedance and low-noise
regulator (such as the TPS73230).
3.3 µF
DVDD
AVDD
GND
Offset
Calibration
AINP
AINM
CS
SCLK
SDO
CDAC
Comparator
Serial
Interface
œ
SAR
Figure 30. Reference for the Device
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Feature Description (continued)
8.3.2 Analog Input
The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and
converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input
and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario,
there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground.
In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The
AINP input is capable of accepting signals from 0 V to AVDD. Figure 31 represents the equivalent analog input
circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling
capacitor. The sampling switch is represented by an RS (typically 50 Ω) resistor in series with an ideal switch and
CS (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD
and ground.
AVDD
R
s
50 ꢀ
AINP
C
S
15 pF
AVDD
R
S
50 ꢀ
AINM
C
S
Figure 31. Equivalent Input Circuit for the Sampling Stage
The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for
the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by
Equation 1:
FSR = VREF = AVDD
(1)
14
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Feature Description (continued)
8.3.3 ADC Transfer Function
The device output is in straight binary format. The device resolution for a single-ended input can be computed by
Equation 2:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD and
N = 8
(2)
Figure 32 and Table 1 show the ideal transfer characteristics for the device.
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
V
REF
V
REF
VREF œ 1 LSB
+ 1LSB
1 LSB
2
2
Single-Ended Analog Input
(AINP œ AINM)
Figure 32. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE (AINP – AINM)
≤1 LSB
CODE
NFSC
DESCRIPTION
IDEAL OUTPUT CODE (HEX)
Negative full-scale code
00
01
80
81
FF
1 LSB to 2 LSBs
NFSC + 1
MC
—
Mid code
(VREF / 2) to (VREF / 2) + 1 LSB
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
≥ VREF – 1 LSB
MC + 1
PFSC
—
Positive full-scale code
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8.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 33 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 12 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 14 SCLKs. A CS rising edge ends the frame and brings the serial data bus to tri-state. For acquisition of
the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is
completed. For details on timing specifications, see the Timing Requirements table.
The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains
low during the first serial transfer frame after power-up. For further details, see the Offset Calibration section.
Sample
N+1
Sample
N
tCYCLE
tCONV
tACQ
tSU_CSCK
CS
1
0
2
3
4
5
6
7
8
9
10
SCLK
D4
D3
0
D6
D5
D2
D1
D0
D7
SDO
Data for Sample N
Figure 33. Serial Interface Timing Diagram
16
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8.4 Device Functional Modes
8.4.1 Offset Calibration
The ADS7029-Q1 includes a feature to calibrate the device internal offset. During offset calibration, the analog
input pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset
calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be
accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, it is
recommended to calibrate the offset on power-up in order to bring the offset error within the specified limits. If the
operating temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during
normal operation. Figure 34 shows the offset calibration process.
Normal Operation
With Uncalibarted
Data Capture(1)
offset
Device
Power Up
Data Capture(1)
Normal Operation
With Calibarted
offset
Calibration during Normal Operation(2)
(1) See the Timing Requirements section for timing specifications.
(2) See the Offset Calibration During Normal Operation section for details.
(3) See the Offset Calibration on Power-Up section for details.
(4) The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 34. Offset Calibration
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the
CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains
low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first
sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up,
the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 35
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
MIN
TYP
MAX
UNIT
MHz
ns
fCLK-CAL
SCLK frequency for calibration
12
tPOWERUP-CAL Calibration time at power-up
15 × tSCLK
120
tACQ
Acquisition time
ns
tPH_CS
tSU_CSCK
tD_CKCS
CS high time
tACQ
12
ns
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
ns
10
ns
Start
Power-up
Calibration
Sample
#1
tPH_CS
tACQ
tPOWERUP-CAL
CS
tD_CKCS
tSU_CSCK
1
2
15
16
SCLK(fCLK-CAL
)
SDO
Figure 35. Offset Calibration on Power-Up Timing Diagram
18
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8.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 10 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 10th
SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 36 shows the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MIN
TYP
MAX
UNIT
MHz
ns
fCLK-CAL
tCAL
SCLK frequency for calibration
Calibration time during normal operation
Acquisition time
12
15 × tSCLK
120
tACQ
ns
tPH_CS
tSU_CSCK
tD_CKCS
CS high time
tACQ
12
ns
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
ns
10
ns
Sample
N+1
Sample
N
tPH_CS
tACQ
tCONV
tCAL
CS
tSU_CSCK
tD_CKCS
16
18
32
1
0
2
3
4
9
10
17
31
SCLK(fCLK-CAL
)
0
D7
D6
D1
SDO
D0
Data for Sample N
Figure 36. Offset Calibration During Normal Operation Timing Diagram
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a SAR ADC are the input driver and the
reference driver circuits. This section details some general principles for designing the input driver circuit,
reference driver circuit, and provides some application circuits designed for the ADS7029-Q1.
9.2 Typical Application
OPA_VDD
AVDD
33 ꢀ
œ
VDD
VIN
+
OPA365-Q1
TI Device
+
œ
VSOURCE
1 nF
GND
GND
Device: 12-Bit , 2-MSPS,
Single-Ended Input
Input Driver
Copyright © 2016, Texas Instruments Incorporated
Figure 37. Single-Supply DAQ with the ADS7029-Q1
9.2.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7029-
Q1 with SNR greater than 49 dB and THD less than –70 dB for input frequencies of 2 kHz at a throughput of
2 MSPS.
9.2.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge
kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
20
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Typical Application (continued)
9.2.2.1 Low Distortion Charge Kickback Filter Design
Figure 38 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and
connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input
pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this
transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched
capacitor load can create stability issues.
RF
Charge Kickback Filter
RFLT
SAR ADC
RIN
VIN
-
+
SW
CSH
VCM
CFLT
f-3dB
=
1
2 Πx RFLT x CFLT
Figure 38. Charge Kickback Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the SNR of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also
helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter
capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection
and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition
process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC
sampling capacitance. For this device, the input sampling capacitance is equal to 15 pF. Thus, the value of CFLT
is greater than 300 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-
temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, a
SPICE simulation is strongly recommended to be performed to confirm that the amplifier has more than 40°
phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some
amplifiers can require more bandwidth than others to drive similar filters.
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Typical Application (continued)
9.2.2.2 Input Amplifier Selection
To achieve a SINAD greater than 49 dB, the operational amplifier must have high bandwidth in order to settle the
input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the
total system noise below 20% of the input-referred noise of the ADC. For the application circuit illustrated in
Figure 37, the OPA365-Q1 is selected for its high bandwidth (50 MHz) and low noise (4.5 nV/√Hz).
For a step-by-step design procedure for a low-power, small form-factor digital acquisition (DAQ) circuit based on
similar SAR ADCs, see the Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and
Ultra-Small Form Factor TI Precision Design.
9.2.2.3 Reference Circuit
The analog supply voltage of the device is also used as a voltage reference for conversion. The AVDD pin is
recommended to be decoupled with a 3.3-µF, low-ESR ceramic capacitor.
9.2.3 Application Curve
Figure 39 shows the FFT plot for the ADS7029-Q1 with a 2-kHz input frequency used for the circuit in Figure 37.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
200
400 600
Frequency (kHz)
800
1000
D001
SNR = 70.6 dB, THD = –86 dB, SINAD = 70.2 dB, number of samples = 32768
Figure 39. Test Results for the ADS7029-Q1 and OPA365-Q1 for a 2-kHz Input
22
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10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The ADS7029-Q1 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins individually with 3.3-µF ceramic decoupling capacitors, as shown in Figure 40.
AVDD
DVDD
AVDD
GND
3.3 mF
3.3 mF
DVDD
Figure 40. Power-Supply Decoupling
10.2 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO
line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on
every rising edge of the data output and is discharged on every falling edge of the data output. The current
consumed by the device from the DVDD supply can be calculated by Equation 3:
IDVDD = C × V × f
where:
•
•
•
C = Load capacitance on the SDO line
V = DVDD supply voltage and
f = Number of transitions on the SDO output
(3)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on SDO change at every SCLK. SDO data changing at
every SCLK results in an output code of AAh or 55h. For an output code of AAh or 55h at a 2-MSPS throughput,
the frequency of transitions on the SDO output is 8 MHz.
For the current consumption to remain at the lowest possible value, keep the DVDD supply at the lowest
permissible value and keep the capacitance on the SDO line as low as possible.
10.3 Optimizing Power Consumed by the Device
•
Keep the analog supply voltage (AVDD) as close as possible to the analog input voltage. Set AVDD to be
greater than or equal to the analog input voltage of the device.
•
•
•
Keep the digital supply voltage (DVDD) at the lowest permissible value.
Reduce the load capacitance on the SDO output.
Run the device at the optimum throughput. Power consumption reduces with throughput.
Copyright © 2017, Texas Instruments Incorporated
23
ADS7029-Q1
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11 Layout
11.1 Layout Guidelines
Figure 41 shows a board layout example for the ADS7029-Q1.
Some of the key considerations for an optimum layout with this device are:
•
•
•
Use a ground plane underneath the device and partition the printed circuit board (PCB) into analog and digital
sections.
Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
The power sources to the device must be clean and well-bypassed. Use 2.2-μF ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins.
•
•
•
Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
Connect ground pins to the ground plane using short, low-impedance path.
Place the fly-wheel RC filters components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance
precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical
properties over voltage, frequency, and temperature changes.
11.2 Layout Example
Digital
Pins
Analog
Pins
GND
AINM
5
6
CS
4
3
SDO
RFLT
ADS7049-Q1
2
SCLK
DVDD
GND
AVDD
7
8
2.2 …F
GND
1
2.2 …F
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Example Layout
24
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ADS7029-Q1
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ZHCSFX9 –JANUARY 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《TPS732xx 具有反向电流保护功能的无电容 NMOS、250mA 低压降稳压器》
《专为低功耗和超小型特性进行优化的三项 12 位数据采集参考设计》TI 高精度设计
OPAx314 3MHz、低功耗、低噪声、RRIO、1.8V CMOS运算放大器
《OPAx365-Q1 50MHz 低失真、高 CMRR、轨到轨 I/O 单电源运算放大器》
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7029QDCURQ1
ACTIVE
VSSOP
DCU
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
17TT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
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EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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