5962-01-385-6686_技术文档

Very Fast, Complete

10- or 12-Bit A/D Converters

a

AD578/AD579

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Complete 12-Bit ADC with Reference and Clock

Fast Conversion: 3 ␮s Max

Buried Zener Reference for Long-Term Stability and

Low Gain TC: ؎30 ppm/؇C Max (AD578)

؎40 ppm/؇C Max (AD579)

AD578/AD579

(AD578)

BIT 12

(AD578)

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

1

2

3

4

5

6

7

8

9

32

–15V

31 +15V

100⍀

20k⍀

30 ANALOG GND

20k⍀

5k⍀

29

28

ZERO ADJ

5k⍀

Max Nonlinearity: <؎0.012%

20V SPAN INPUT

No Missing Codes over Temperature

Low Power: 555 mW (AD578); 775 mW (AD579)

Available to MIL-STD-883

Positive-True Parallel or Serial Logic Outputs

Short Cycle Capability

Precision 10 V Reference for External Applications

Adjustable Internal Clock

Z Models for ؎12 V Supplies

27 10V SPAN INPUT

10k⍀

26

25

BIPOLAR OFFSET

GAIN (REF IN)

24 REF OUT

BIT 4

BIT 3 10

BIT 2 11

BIT 1 12

BIT 1 13

23 SERIAL OUT

22

SERIAL OUT

21 CONVERT START

20 EOC

SHORT

14

15

19 CLOCK IN

18 CLOCK OUT

17 CLOCK ADJ

CYCLE

DIGITAL

GND

SAR

CLOCK

+5V 16

COMPARATOR

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD578 and AD579 are high speed 12-bit and 10-bit

successive approximation ADCs that include an internal clock,

reference, and comparator. Their hybrid design utilizes MSI

digital and linear ICs in conjunction with a 12-bit or 10-bit

monolithic, monotonic DAC to provide superior performance

and versatility with IC size, price, and reliability.

1. Both the AD578 and AD579 are complete ADCs. No

external components are required to perform a conversion.

2. The fast conversion rates—3 µs for the AD578 and 1.8 µs for

the AD579—make them ideal candidates for high speed data

acquisition systems requiring high throughput.

3. The internal buried Zener reference is laser trimmed to high

initial accuracy and low TC and is available externally.

Important performance characteristics of the AD578 include

1/2 LSB₁₂linearity error maximum at +25°C, maximum gain

temperature coefficient of 30 ppm/°C, and maximum conver-

sion time of 3 µs at a typical power dissipation of 555 mW. The

10-bit AD579 provides 1/2 LSB₁₀maximum linearity error at

1.8 µs maximum and 775 mW typical P_D.

4. Precision thin-film scaling resistors on the DAC provide for

excellent thermal tracking.

5. Short cycle and external clock capabilities are provided for

applications requiring faster conversion speeds and/or lower

resolution.

Both the AD578 and AD579 include scaling resistors that provide

analog input signal ranges of 5 V, 10 V, and 0 V to +10 V.

Both are contained in 32-lead ceramic side-brazed DIP pack-

ages and are available with MIL-STD-883 Class B processing.

The serial output function is no longer supported on this

product after date code 9623.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(Typical @ 25؇C, ؎15 V and +5 V, unless otherwise noted.)

AD578/AD579–SPECIFICATIONS

Parameter

AD578J

AD578K

AD578L

RESOLUTION

12 Bits

ANALOG INPUTS

Voltage Ranges

Bipolar

5.0 V, 10 V

0 V to +10 V, 0 V to +20 V

5.0 V, 10 V

0 V to +10 V, 0 V to +20 V

5.0 V, 10 V

0 V to +10 V, 0 V to +20 V

Unipolar

Input Impedance

0 V to +10 V, 5 V

10 V, 0 V to +20 V

5 kΩ

10 kΩ

5 kΩ

10 kΩ

5 kΩ

10 kΩ

DIGITAL INPUTS

Convert Command¹

Clock Input

1 LSTTL Load

TRANSFER CHARACTERISTICS

Gain Error^{2, 3}

0.1% FSR, 0.25% FSR max

1/2 LSB max

0.1% FSR, 0.25% FSR max

1/2 LSB max

0.1% FSR, 0.25% FSR max

1/2 LSB max

Unipolar Offset³

Bipolar Error^{3, 4}

Linearity Error, 25°C

T_MINto T_MAX

3/4 LSB

DIFFERENTIAL LINEARITY ERROR

(Minimum resolution for which no

missing codes are guaranteed)

25°C

12 Bits

T_MINto T_MAX

POWER SUPPLY SENSITIVITY

+15 V 10%

–15 V 10%

0.005%/%∆V_Smax

+5 V 10%

TEMPERATURE COEFFICIENTS

Gain

15 ppm/°C typ

30 ppm/°C max

3 ppm/°C typ

10 ppm/°C max

8 ppm/°C typ

20 ppm/°C max

2 ppm/°C typ

15 ppm/°C typ

30 ppm/°C max

3 ppm/°C typ

10 ppm/°C max

8 ppm/°C typ

20 ppm/°C max

2 ppm/°C typ

15 ppm/°C typ

30 ppm/°C max

3 ppm/°C typ

10 ppm/°C max

8 ppm/°C typ

20 ppm/°C max

2 ppm/°C typ

Unipolar Offset

Bipolar Offset

Differential Linearity

CONVERSION TIME^{5, 6, 7}(max)

6.0 µs

4.5 µs

3 µs

PARALLEL OUTPUTS

Unipolar Code

Bipolar Code

Binary

Offset Binary/Twos Complement

2 LSTTL Loads

Offset Binary/Twos Complement

2 LSTTL Loads

Offset Binary/Twos Complement

2 LSTTL Loads

Output Drive

SERIAL OUTPUTS (NRZ FORMAT)

Unipolar Code

Bipolar Code

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Output Drive

END OF CONVERSION (EOC)

Output Drive

Logic l During Conversion

8 LSTTL Loads

Logic l During Conversion

8 LSTTL Loads

Logic l During Conversion

8 LSTTL Loads

INTERNAL CLOCK⁷

Output Drive

2 LSTTL Loads

INTERNAL REFERENCE

Voltage

Drift

10.000 100 mV

12 ppm/°C, 20 ppm/°C max

1 mA max

10.000 100 mV

12 ppm/°C, 20 ppm/°C max

1 mA max

10.000 100 mV

12 ppm/°C, 20 ppm/°C max

1 mA max

External Current

POWER SUPPLY REQUIREMENTS⁸

Range for Rated Accuracy

+4.75 to +5.25 and 13.5 to 16.5 +4.75 to +5.25 and 13.5 to 16.5 +4.75 to +5.25 and 13.5 to 16.5

Supply Current

+15 V

–15 V

+5 V

5 mA typ, 8 mA max

22 mA typ, 35 mA max

30 mA typ, 40 mA max

555 mW typ

5 mA typ, 8 mA max

22 mA typ, 35 mA max

30 mA typ, 40 mA max

555 mW typ

5 mA typ, 8 mA max

22 mA typ, 35 mA max

30 mA typ, 40 mA max

555 mW typ

Power Dissipation

TEMPERATURE RANGE

Operating

Storage

0°C to +70°C

–65°C to +150°C

0°C to +70°C

–65°C to +150°C

0°C to +70°C

–65°C to +150°C

See Page 3 for notes.

–2–

REV. C

AD578/AD579

Parameter

AD578SD⁹

AD578TD⁹

RESOLUTION

12 Bits

ANALOG INPUTS

Voltage Ranges

Bipolar

5.0 V, 10 V

0 V to +10 V, 0 V to +20 V

5.0 V, 10 V

0 V to +10 V, 0 V to +20 V

Unipolar

Input Impedance

0 V to +10 V, 5 V

10 V, 0 V to +20 V

5 kΩ

10 kΩ

5 kΩ

10 kΩ

DIGITAL INPUTS

Convert Command¹

Clock Input

1 LSTTL Load

TRANSFER CHARACTERISTICS

Gain Error^{2, 3}

0.1% FSR, 0.25% FSR max

1/2 LSB max

0.1% FSR, 0.25% FSR max

1/2 LSB max

Unipolar Offset³

Bipolar Error^{3, 4}

Linearity Error, 25°C

T_MINto T_MAX

3/4 LSB max

DIFFERENTIAL LINEARITY ERROR

(Minimum resolution for which no

missing codes are guaranteed)

25°C

12 Bits

T_MINto T_MAX

POWER SUPPLY SENSITIVITY

+15 V 10%

–15 V 10%

0.005%/%∆V_Smax

+5 V 10%

TEMPERATURE COEFFICIENTS

Gain

15 ppm/°C typ

50 ppm/°C max

3 ppm/°C typ

15 ppm/°C max

8 ppm/°C typ

25 ppm/°C max

2 ppm/°C typ

15 ppm/°C typ

30 ppm/°C max

3 ppm/°C typ

10 ppm/°C max

8 ppm/°C typ

20 ppm/°C max

2 ppm/°C typ

Unipolar Offset

Bipolar Offset

Differential Linearity

CONVERSION TIME^{5, 6, 7}(max)

6.0 µs

4.5 µs

PARALLEL OUTPUTS

Unipolar Code

Bipolar Code

Binary

Offset Binary/Twos Complement

2 LSTTL Loads

Offset Binary/Twos Complement

2 LSTTL Loads

Output Drive

SERIAL OUTPUTS (NRZ FORMAT)

Unipolar Code

Bipolar Code

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Output Drive

END OF CONVERSION (EOC)

Output Drive

Logic l During Conversion

8 LSTTL Loads

Logic l During Conversion

8 LSTTL Loads

INTERNAL CLOCK⁷

Output Drive

2 LSTTL Loads

INTERNAL REFERENCE

Voltage

Drift

10.000 100 mV

12 ppm/°C, 20 ppm/°C max

1 mA max

10.000 100 mV

12 ppm/°C, 20 ppm/°C max

1 mA max

External Current

POWER SUPPLY REQUIREMENTS⁸

Range for Rated Accuracy

Supply Current +15 V

–15 V

+4.75 to +5.25 and 13.5 to 16.5

5 mA typ, 8 mA max

22 mA typ, 35 mA max

30 mA typ, 40 mA max

555 mW typ

+4.75 to +5.25 and 13.5 to 16.5

5 mA typ, 8 mA max

22 mA typ, 35 mA max

30 mA typ, 40 mA max

555 mW typ

+5 V

Power Dissipation

TEMPERATURE RANGE

Operating

Storage

–55°C to +125°C

–65°C to +150°C

–55°C to +125°C

–65°C to +150°C

NOTES

¹Positive pulse 200 ns wide (min) leading edge (0 to 1) resets outputs. Trailing edge initiates conversion.

²With 50 Ω, 1% fixed resistor in place of gain adjust potentiometer.

³Adjustable to 0.

⁴With 50 Ω, 1% resistor between REF OUT and BIPOLAR OFFSET (Pins 24 and 26).

⁵Conversion time is defined as the time between the falling edge of convert start and the falling edge of the EOC.

⁶Each grade is specified at the conversion speed shown.

⁷Externally adjustable by a resistor or capacitor (see Figure 6).

⁸For Z models, order AD578ZJ, AD578ZK, or AD578ZL ( 11.6 V to 16.5 V).

⁹Available to MIL-STD-883, Level B. See ADI Military Products Databook for detailed specifications.

S

pecifications subject to change without notice.

REV. C

–3–

AD578/AD579

Parameter

AD579JN

AD579KN

RESOLUTION

10 Bits

ANALOG INPUTS

Voltage Ranges

Bipolar

±5.0 V, ±10 V

0 V to +10 V, 0 V to +20 V

±5.0 V, ±10 V

0 V to +10 V, 0 V to +20 V

Unipolar

Input Impedance

0 V to +10 V, ±5 V

±10 V, 0 V to +20 V

5 kW (±20%)

10 kW (±20%)

5 kW (±20%)

10 kW (±20%)

DIGITAL INPUTS

Convert Command¹

Clock Input

1 LSTTL Load

TRANSFER CHARACTERISTICS

Gain Error^{2, 3}

±0.1% FSR, ±0.25% FSR max

±1/2 LSB max

±0.1% FSR, ±0.25% FSR max

±1/2 LSB max

Unipolar Offset³

Bipolar Error^{3, 4}

Linearity Error, 25∞C

T_MINto T_MAX

±3/4 LSB

DIFFERENTIAL LINEARITY ERROR

(Minimum resolution for which no

missing codes are guaranteed)

25∞C

10 Bits

T_MINto T_MAX

POWER SUPPLY SENSITIVITY

+15 V ± 10%

0.005%/%DV_Smax

0.001%/%DV_Smax

0.005%/%DV_Smax

0.001%/%DV_Smax

–15 V ± 10%

+5 V ± 10%

Z Versions

+12 V ± 5%

–12 V ± 5%

0.007%/%DV_Smax

TEMPERATURE COEFFICIENTS

Gain

±25 ppm/∞C typ

±40 ppm/∞C max

±5 ppm/∞C typ

±15 ppm/∞C max

±8 ppm/∞C typ

±20 ppm/∞C max

±2 ppm/∞C typ

±25 ppm/∞C typ

±40 ppm/∞C max

±5 ppm/∞C typ

±15 ppm/∞C max

±8 ppm/∞C typ

±20 ppm/∞C max

±2 ppm/∞C typ

Unipolar Offset

Bipolar Offset

Differential Linearity

CONVERSION TIME^{5, 6}(max)

T_MINto T_MAX

2.2 ms

2.4 ms

1.8 ms

2.0 ms

PARALLEL OUTPUTS

Unipolar Code

Bipolar Code

Binary

Offset Binary/Twos Complement

2 LSTTL Loads

Offset Binary/Twos Complement

2 LSTTL Loads

Output Drive

SERIAL OUTPUTS (NRZ FORMAT)

Unipolar Code

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Bipolar Code

Output Drive

END OF CONVERSION (EOC)

Output Drive

Logic 1 During Conversion

8 LSTTL Loads

Logic 1 During Conversion

8 LSTTL Loads

INTERNAL CLOCK⁷

Output Drive

2 LSTTL Loads

INTERNAL REFERENCE

Voltage

Temperature Coefficient

External Current

10.000 ± 100 mV typ

±15 ppm/∞C

±1 mA max

10.000 ± 100 mV typ

±15 ppm/∞C

±1 mA max

POWER SUPPLY REQUIREMENTS

Range for Rated Accuracy

Z Models⁸

+4.75 to +5.25 and ±13.5 to ±16.5

+4.75 to +5.25 and ±11.4 to ±16.5

5 mA typ, 8 mA max

22 mA typ, 35 mA max

100 mA typ, 150 mA max

775 mW typ

+4.75 to +5.25 and ±13.5 to ±16.5

+4.75 to +5.25 and ±11.4 to ±16.5

5 mA typ, 8 mA max

22 mA typ, 35 mA max

100 mA typ, 150 mA max

775 mW typ

Supply Current

+15 V

–15 V

+5 V

Power Dissipation

TEMPERATURE RANGE

Operating

Storage

0∞C to +70∞C

–65∞C to +150∞C

0∞C to +70∞C

–65∞C to +150∞C

NOTES

¹Positive pulse 200 ns wide (min) leading edge (0 to 1) resets outputs. Trailing edge initiates conversion.

²With 50 W, 1% fixed resistor in place of gain adjust potentiometer.

³Adjustable to zero.

⁴With 50 W, 1% resistor between REF OUT and BIPOLAR OFFSET (Pins 24 and 26).

⁵Conversion time is defined as the time between the falling edge of convert start and the falling edge of the EOC.

(Continued on page 5)

REV. C

–4–

AD578/AD579

Parameter

AD579TD⁹

RESOLUTION

10 Bits

ANALOG INPUTS

Voltage Ranges

Bipolar

±5.0 V, ±10 V

0 V to +10 V, 0 V to +20 V

Unipolar

Input Impedance

0 V to +10 V, ±5 V

±10 V, 0 V to +20 V

5 kW (±20%)

10 kW (±20%)

DIGITAL INPUTS

Convert Command¹

Clock Input

1 LSTTL Load

TRANSFER CHARACTERISTICS

Gain Error^{2, 3}

±0.1% FSR, ±0.25% FSR max

±1/2 LSB max

Unipolar Offset³

Bipolar Error^{3, 4}

Linearity Error, 25∞C

T_MINto T_MAX

±3/4 LSB

DIFFERENTIAL LINEARITY ERROR

(Minimum resolution for which no

missing codes are guaranteed)

25∞C

10 Bits

T_MINto T_MAX

POWER SUPPLY SENSITIVITY

+15 V ± 10%

0.005%/%DV_Smax

0.001%/%DV_Smax

–15 V ± 10%

+5 V ± 10%

Z Versions

+12 V ± 5%

–12 V ± 5%

0.007%/%DV_Smax

TEMPERATURE COEFFICIENTS

Gain

±25 ppm/∞C typ

±40 ppm/∞C max

±5 ppm/∞C typ

±15 ppm/∞C max

±8 ppm/∞C typ

±20 ppm/∞C max

±2 ppm/∞C typ

Unipolar Offset

Bipolar Offset

Differential Linearity

CONVERSION TIME^{5, 6}(max)

T_MINto T_MAX

1.8 ms

2.0 ms

PARALLEL OUTPUTS

Unipolar Code

Bipolar Code

Binary

Offset Binary/Twos Complement

2 LSTTL Loads

Output Drive

SERIAL OUTPUTS (NRZ FORMAT)

Unipolar Code

Bipolar Code

Binary/Complementary Binary

Offset Binary/Comp. Offset Binary

2 LSTTL Loads

Output Drive

END OF CONVERSION (EOC)

Output Drive

Logic 1 During Conversion

8 LSTTL Loads

INTERNAL CLOCK⁷

Output Drive

2 LSTTL Loads

INTERNAL REFERENCE

Voltage

Temperature Coefficient

External Current

10.000 ± 100 mV typ

±15 ppm/∞C

±1 mA max

POWER SUPPLY REQUIREMENTS

Range for Rated Accuracy

Z Models⁸

+4.75 to +5.25 and ±13.5 to ±16.5

+4.75 to +5.25 and ±11.4 to ±16.5

5 mA typ, 8 mA max

22 mA typ, 35 mA max

100 mA typ, 150 mA max

775 mW typ

Supply Current

+15 V

–15 V

+5 V

Power Dissipation

TEMPERATURE RANGE

Operating

Storage

–55∞C to +125∞C

–65∞C to +150∞C

NOTES (continued)

⁶Each grade is specified at the conversion speed shown.

⁷Externally adjustable by a resistor or capacitor. See Figure 8 for appropriate connections.

⁸For Z models, order AD579ZJN, AD579ZKN, or AD579ZTD.

⁹Available to MIL-STD-883, Level B. See ADI Military Products Databook for detailed specifications.

Specifications subject to change without notice.

REV. C

–5–

AD578/AD579

ORDERING GUIDE¹

Conversion

Speed

Temperature

Range

Package

Option²

Model

Resolution

AD578JN (JD)

AD578KN (KD)

AD578LN (LD)

AD578SD

12 Bits

10 Bits

6.0 ms

4.5 ms

3.0 ms

6.0 ms

4.5 ms

6.0 ms

4.5 ms

2.2 ms

1.8 ms

0∞C to +70∞C

DH-32B

–55∞C to +125∞C

0∞C to +70∞C

–55∞C to +125∞C

AD578TD

AD578SD/883B

AD578TD/883B

AD579JN

AD579KN

AD579TD

AD579TD/883B

NOTES

¹For ±12 V operation Z Version, order AD578ZTD.

²DH = Side Brazed Ceramic DIP.

200ns, min

THEORY OF OPERATION

CONVERT

START

The AD578 is a complete pretrimmed 12-bit ADC that requires

no external components to provide the successive approximation

analog-to-digital conversion function. A block diagram of the

AD578/AD579 is shown in Figure 1.

200ns

80ns

CLOCK

160ns

10ns

100ns

EOC

AD578/AD579

(AD578)

BIT 1

1

2

3

4

5

6

7

8

9

32

–15V

BIT 12

(AD578)

BIT 11

31 +15V

BIT 2

BIT 3

100⍀

20k⍀

30 ANALOG GND

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

20k⍀

5k⍀

29

28

ZERO ADJ

5k⍀

20V SPAN INPUT

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

27 10V SPAN INPUT

10k⍀

26

25

BIPOLAR OFFSET

GAIN (REF IN)

24 REF OUT

BIT 4

BIT 3 10

BIT 2 11

BIT 1 12

BIT 1 13

23 SERIAL OUT

22

SERIAL OUT

21 CONVERT START

20 EOC

SHORT

14

15

19 CLOCK IN

18 CLOCK OUT

17 CLOCK ADJ

CYCLE

DIGITAL

GND

SAR

CLOCK

BIT 10

BIT 11

+5V 16

COMPARATOR

Figure 1. AD578/AD579 Functional Block Diagram and

Pinout

BIT 12

SERIAL

OUT

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

When the control section is commanded to initiate a conversion,

it enables the clock and resets the successive approximation regis-

ter (SAR). The SAR, timed by the clock, sequences through the

conversion cycle and returns an end-of-convert flag to the control

section. The control section disables the clock and brings the

output status flag low. The data bits are valid on the falling

edge of the clock pulse starting with t₁and ending with t₁₂

(Figures 2a and 2b) and accurately represent the input signal to

within ±1/2 LSB.

CLOCK

INTERNAL: CONNECT CLOCK OUT (18) TO CLOCK IN (19)

EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19)

CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH

MINIMUM PERIOD,T OF 100ns.

MIN

NOTE

THE RISING EDGE OF CONVERT START PULSE RESETS THE MSB TO ZERO,

AND THE LSBs TO ONE.THE TRAILING EDGE INITIATES CONVERSION.

Figure 2a. AD578 Timing Diagram

REV. C

–6–

AD578/AD579

200ns, min

UNIPOLAR CALIBRATION

CONVERT

START

CONVERSION TIME

70ns

100ns

The AD578/AD579 are intended to have a nominal 1/2 LSB

offset so that the exact analog input for a given code will be in

the middle of that code (halfway between the transitions to the

codes above and below it). Thus, when properly calibrated, the

first transition (from 0000 0000 0000 to 0000 0000 0001) will

occur for an input level of +1/2 LSB.

125ns

~15ns

GATED

CLOCK

t₁t₂t₃t₄t₅t₆t₇t₈t₉t₁₀

t₀

100ns

CONVERSION IN PROGRESS

PARALLEL DATA VALID

EOC

25ns

75ns

BIT 1

(MSB)

If Pin 26 is connected to Pin 30, the unit will behave in this

manner, within specifications. Refer to Table I, Table II, and

Figure 3 for further clarification. If the offset trim (R1) is used,

it should be trimmed as above, although a different offset can be

set for a particular system requirement. This circuit will give

approximately 25 mV of offset trim range.

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

The full-scale trim is done by applying a signal 1 1/2 LSB

below the nominal full scale. Trim R2 to give the last transition

(1111 1111 1110 to 1111 1111 11111).

+15V

R1

ZERO ADJ

10k⍀

–15V

0V TO +20V

20V IN

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

SERIAL

CLOCK

ANALOG INPUTS

BITS 1–12 (AD578)

10V IN

BITS 1–10 (AD579)

0V TO +10V

INTERNAL: CONNECT CLOCK OUT (18) TO CLOCK IN (19)

EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19)

CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH

AD578/AD579

MINIMUM PERIOD,T

OF 100ns.

MIN

BIP OFF

Figure 2b. AD579 Timing Diagram

CLK OUT

CLK IN

REF IN

The temperature-compensated buried Zener reference provides the

primary voltage reference to the DAC and guarantees excellent

stability with both time and temperature. The reference is

trimmed to 10 V 1.0%; it is buffered and can supply up to

1 mA to an external load in addition to the current required to

drive the reference input resistor (0.5 mA) and bipolar offset

resistor (1 mA). The thin-film application resistors are trimmed

to match the full-scale output current of the DAC. Two 5 kΩ

input scaling resistors allow either a 10 V or a 20 V span. The

10 kΩ bipolar offset resistor is grounded for unipolar operation

or connected to the 10 V reference for bipolar operation.

R2

100⍀

REF OUT

+

6.8␮F

DIG GND

ANA GND

Figure 3. Unipolar Input Connections

Table I. AD578 Digital Output Codes vs. Analog Input for Unipolar and Bipolar Ranges

Digital Output Code

Analog Input—Volts

(Center of Quantization Interval)

(Binary for Unipolar Ranges;

Offset Binary for Bipolar Ranges)

0 V to +10 V

Range

0 V to +20 V

Range

–5 V to +5 V

Range

–10 V to +10 V

Range

B1

(MSB)

B12

(LSB)

+9.9976

+19.9951

+4.9976

+9.9951

1 1 1 1 1 1 1 1 1 1 1 1

+9.9952

+19.9902

+4.9952

+9.9902

1 1 1 1 1 1 1 1 1 1 1 0

•

+5.0024

+5.0000

•

+10.0049

+10.0000

•

+0.0024

+0.0000

•

+0.0049

+0.0000

•

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0 0 0

•

+0.0024

+0.0000

+0.0051

+0.0000

–4.9976

–5.0000

–9.9951

–10.0000

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

REV. C

–7–

AD578/AD579

Table II. AD579 Digital Output Codes vs. Analog Input for Unipolar and Bipolar Ranges

Digital Output Code

(Binary for Unipolar Ranges;

Analog Input—Volts

(Center of Quantization Interval)

Offset Binary for Bipolar Ranges)

0 V to +10 V

Range

0 V to +20 V

Range

–5 V to +5 V

Range

–10 V to +10 V

Range

B1

(MSB)

B12

(LSB)

+9.9902

+9.9804

+19.9804

+19.9609

+4.9902

+4.9804

+9.9804

+9.9609

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

∑

+10.0195

+10.0000

∑

+5.0097

+5.0000

∑

+0.0097

+0.0000

∑

+0.0195

+0.0000

∑

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0 0 0

∑

+0.0097

+0.0000

+0.0195

+0.0000

–4.9902

–5.0000

–9.9804

–10.0000

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

BIPOLAR OPERATION

LAYOUT CONSIDERATIONS

The connections for bipolar ranges are shown in Figure 4. Again,

as for the unipolar ranges, if the offset and gain specifications

are sufficient, the 100 W trimmer shown can be replaced by a

50 W ± 1% fixed resistor. The analog input is applied as for the

unipolar ranges. Bipolar calibration is similar to unipolar calibra-

tion. First, a signal 1/2 LSB above negative full scale is applied,

and R1 is trimmed to give the first transition (0000 0000 0000

to 0000 0000 0001). A signal 1 1/2 LSB below positive full

scale is applied and R2 trimmed to give the last transition

(1111 1111 1110 to 1111 1111 1111).

Many data acquisition components have two or more ground pins

that are not connected together within the device. These grounds

are usually referred to as the logic power return, analog com-

mon (analog power return), and analog signal ground. These

grounds must be tied together at one point, usually at the system

power supply ground. Ideally, a single solid ground would be

desirable. However, since current flows through the ground

wires and etch stripes of the circuit cards, and since these paths

have resistance and inductance, hundreds of millivolts can be

generated between the system ground point and the ground pin

of the AD578 or AD579. Separate ground returns should be

provided to minimize the current flow in the path from sensitive

points to the system ground point. In this way, supply currents

and logic-gate return currents are not summed into the same

return path as analog signals, where they would cause measure-

ment errors.

ZERO ADJ

؎10V

20V IN

ANALOG INPUTS

BITS 1–12 (AD578)

10V IN

BITS 1–10 (AD579)

–15V

؎5V

+5V

0.1␮F

10␮F

AD578/AD579

+

ANALOG

COMMON

BIP OFF

R1

10␮F

DIG

COM

100⍀

10␮F

+

CLK OUT

CLK IN

REF IN

+15V

R2

100⍀

REF OUT

Figure 5. Basic Bypassing Practice

+

6.8␮F

Each of the AD578 or AD579 supply terminals should be capaci-

tively decoupled as close to the ADC as possible. A large value

capacitor such as 10 mF in parallel with a 0.1 mF capacitor is

usually sufficient. Analog supplies are bypassed to the analog

power return pin and the logic supply is bypassed to the digital

GND pin.

DIG GND

ANA GND

Figure 4. Bipolar Input Connections

To minimize noise, the reference output (Pin 24) should be

decoupled by a 6.8 mF capacitor to Pin 30.

REV. C

–8–

AD578/AD579

CLOCK RATE CONTROL

J GRADE

K,T GRADES

The internal clock is preset to a nominal conversion time of 5.6 µs

(AD578) or 4.8 µs (AD579). It can be adjusted for either faster

or slower conversion rates. For faster conversions, connect the

appropriate 1% resistor between Pins 17 and 18 and short Pin 18

to Pin 19 (see Figures 6, 7, and 8).

2.2␮s

CONVERSION

RATE

1.8␮s

CONVERSION

RATE

649⍀

422⍀

1%

For slower conversions (AD578 only), connect a capacitor

between Pins 15 and 17.

Figure 8. AD579 Clock Rate Control Connection

Note that the No Missing Code operation is not guaranteed

when operating in this mode if a particular grade’s conversion

speed specification is exceeded.

Short Cycle Input—A short cycle input, Pin 14, permits the

timing cycle to be terminated after any number of desired bits

has been converted, allowing shorter conversion times in appli-

cations not requiring the full 10-bit (AD579) or 12-bit (AD578)

resolution. Short cycle pin connections and associated conver-

sion times are summarized in Tables III and IV.

3␮s

CONVERSION

RATE

6␮s

CONVERSION

RATE

4.5␮s

CONVERSION

RATE

L GRADE

K,T GRADES

J, S GRADES

TO SLOW

CONVERSION,

USE C

FROM

FIGURE 7

Table III. AD578 Short Cycle Connections

825⍀

؎1%

3.32⍀

؎1%

Connect

Pin 14 to

Conversion Speed

(␮s)

For Resolution Bit

Figure 6. AD578 Clock Rate Control Connection

12

10

8

Pin 16

Pin 2

Pin 4

3

2.5

2

CAPACITANCE – pF

1000

680

330

13.0

10.0

8.0

Table IV. AD579 Short Cycle Connections

CAPACITOR

RESISTOR

Connect

Pin 14 to

Conversion Speed

(␮s)

For Resolution Bit

10

8

Pin 2

Pin 4

1.8

1.5

6.0

4.0

2.0

External Clock—An external clock may be connected directly

to the clock input, Pin 19. When operating in this mode, the

convert start should be held high for a minimum of one clock

period in order to reset the SAR and synchronize the conversion

cycle. A positive-going pulse width of 100 ns to 200 ns will provide

a continuous string of conversions that start on the first rising

edge of the external clock after the EOC output has gone low.

1.5

10k

200

2k

RESISTANCE – ⍀

Figure 7. AD578 Conversion Times vs. R or C Values

External Buffer Amplifier—In applications where the AD578 or

AD579 is to be driven from high impedance sources or directly

from an analog multiplexer, a fast slewing, wideband op amp like

the AD711 should be used (see Figure 9).

V

GND

SS

DD

+5V +15V –15V

+V

AD711

–V

OUT

ANALOG INPUT

0V TO 10V

S1

AD7506

S16

DATA BITS

1 TO 12

A0 A1 A2 A3

EN

AD578

OR

AD579

Figure 9. Input Buffer

REV. C

–9–

AD578/AD579

OUTLINE DIMENSIONS

32-Lead Side Brazed Ceramic DIP [SBDIP/H]

(DH-32B)

Dimensions shown in inches and (millimeters)

0.005 (0.13) MIN

32

0.080 (2.03) MAX

17

1

16

0.605 (15.37)

0.580 (14.73)

1.640 (41.66)

1.584 (40.23)

PIN 1

0.230 (5.84)

MAX

0.060 (1.52)

0.040 (1.02)

0.012 (0.31)

0.009 (0.23)

0.610 (15.49)

0.590 (14.99)

0.180 (4.57)

MIN

0.175 (4.46)

0.125 (3.18)

0.020 (0.51)

0.016 (0.41)

0.055 (1.40)

0.045 (1.14)

0.100 (2.54)

BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. C

–10–

AD578/AD579

Revision History

Location

Page

10/03—Data Sheet changed from REV. B to REV. C

Change analog-to-digital converter to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal

Replaced OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3/03—Data Sheet changed from REV. A to REV. B

Added text to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Reformatted SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Renumbered Figures 6–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

REV. C

–11–

–12–


型号：	5962-01-385-6686
厂家：	ADI
描述：	IC,A/D CONVERTER,SINGLE,12-BIT,HYBRID,DIP,32PIN 光电二极管转换器
文件：	总12页 (文件大小：368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962-01-385-6686 [ADI]

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