5962-87719012A [ADI]
Programmable Gain Instrumentation Amplifier; 可编程增益仪表放大器器
| 型号： | 5962-87719012A |
| 厂家： | 
ADI |
| 描述： | Programmable Gain Instrumentation Amplifier |
| 文件： | 总15页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable Gain
Instrumentation Amplifier
a
AD625
FUNCTIONAL BLOCK DIAGRAM
FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% Max
Low Gain TC: 5 ppm/ꢁC Max
Low Nonlinearity: 0.001% Max
Low Offset Voltage: 25 ꢂV
Low Noise 4 nV/√Hz (at 1 kHz) RTI
Gain Bandwidth Product: 25 MHz
16-Lead Ceramic or Plastic DIP Package,
20-Terminal LCC Package
50ꢀ
AD625
–
–
–INPUT
+
+
–GAIN
SENSE
10kꢀ
SENSE
–GAIN
DRIVE
10kꢀ
10kꢀ
–
V
OUTPUT
B
+
+GAIN
DRIVE
10kꢀ
Standard Military Drawing Available
MlL-Standard Parts Available
Low Cost
REFERENCE
+GAIN
SENSE
+
+
50ꢀ
–
–
+INPUT
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application: 1) Circuits re-
quiring nonstandard gains (i.e., gains not easily achievable with
devices such as the AD524 and AD624). 2) Circuits requiring a
low cost, precision software programmable gain amplifier.
1. The AD625 affords up to 16-bit precision for user selected
fixed gains from 1 to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be config-
ured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
For low noise, high CMRR, and low drift the AD625JN is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
1 to 10,000. The error contribution of the AD625JN is less than
0.05% gain error and under 5 ppm/°C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
A software programmable gain amplifier (SPGA) can be config-
ured with the addition of a CMOS multiplexer (or other switch
network), and a suitable resistor network. Because the ON
resistance of the switches is removed from the signal path, an
AD625 based SPGA will deliver 12-bit precision, and can be
programmed for any set of gains between 1 and 10,000, with
completely user selected gain steps.
5. The proprietary design of the AD625 provides input voltage
noise of 4 nV/√Hz at 1 kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25 µV/°C, output offset drift below
15 µV/°C, and a maximum nonlinearity of 0.001% at G = 1. All
grades exhibit excellent ac performance; a 25 MHz gain band-
width product, 5 V/µs slew rate and 15 µs settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial (–40°C to +85°C) temperature range, two grades (J,
K) for commercial (0°C to +70°C) temperature range, and one
(S) grade rated over the extended (–55°C to +125°C) tempera-
ture range.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(typical @ VS = ꢃ15 V, RL = 2 kꢀ and TA = + 25ꢁC, unless otherwise noted)
AD625–SPECIFICATIONS
AD625A/J/S
AD625B/K
Typ
AD625C
Typ
Model
Min Typ
Max
Min
Max
+ 1
10,000
0.03
Min
Max
+ 1
110,000
0.02
Unit
GAIN
Gain Equation
2 RF
RG
2 RF
RG
2 RF
RG
+ 1
Gain Range
1
10,000
0.05
1
1
Gain Error1
.035
ꢃ
0.02
ꢃ
0.01
ꢃ
%
Nonlinearity, Gain = 1-256
Gain>256
0.005
0.01
0.002
0.008
0.001
0.005
%
%
ppm/°C
Gain vs. Temp. Gain<10001
5
5
5
GAIN SENSE INPUT
Gain Sense Current
vs. Temperature
300
5
150
500
20
500
150
2
75
250
15
250
50
2
50
100
10
100
nA
nA/°C
nA
Gain Sense Offset Current
vs. Temperature
2
15
1
10
2
10
nA/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the
Input vs. Supply
G = 1
50
1
4
200
2/2
5
25
0.25
2
50
0.50/1
3
10
0.1
1
25
0.25
2
µV
µV/°C
mV
20
50/50
10
25/40
10
15
µV/°C
70
85
95
75
95
100
75
90
105
110
85
80
95
110
115
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
100
110
120
105
120
140
100 110
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
30
50
2
ꢃ
ꢃ
50
20
50
1
ꢃ
ꢃ
25
15
10
50
1
ꢃ
ꢃ
15
5
nA
pA/°C
nA
35
20
20
20
pA/°C
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
1
4
1
4
1
4
1
4
1
4
1
4
GΩ
pF
GΩ
pF
Input Voltage Range
Differ. Input Linear (VDL
2
)
10
10
10
V
G
G
G
12V –
×VD
12V –
×VD
12V –
×VD
Common-Mode Linear (VCM
)
(
)
(
)
(
)
2
2
2
Common-Mode Rejection Ratio dc to
60 Hz with 1 kΩ Source Imbalance
G = 1
70
90
75
95
75
90
85
80
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
105
115
125
100
110
120
115
125
140
100 105
110 115
105
110
OUTPUT RATING
10 V
10 V
10 V
@ 5 mA
@ 5 mA
@ 5 mA
DYNAMIC RESPONSE
Small Signal –3 dB
G = 1 (RF = 20 kΩ)
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%, 20 V Step
650
400
150
25
650
400
150
25
650
400
150
25
kHz
kHz
kHz
kHz
V/µs
5.0
5.0
5.0
G = 1 to 200
G = 500
G = 1000
15
35
75
15
35
75
15
35
75
µs
µs
µs
–2–
REV. D
AD625
AD625A/J/S
Typ
AD625B/K
Typ
AD625C
Typ
Model
Min
Max
Min
Max
Min
Max
Unit
NOISE
Voltage Noise, 1 kHz
R.T.I.
R.T.O.
R.T.I., 0.1 Hz to 10 Hz
4
75
4
75
4
75
nV/√Hz
nV/√Hz
G = 1
G = 10
G = 100
G = 1000
10
10
10
µV p-p
µV p-p
µV p-p
µV p-p
1.0
0.3
0.2
1.0
0.3
0.2
1.0
0.3
0.2
Current Noise
0.1 Hz to 10 Hz
60
60
60
pA p-p
SENSE INPUT
RIN
IIN
Voltage Range
Gain to Output
10
30
10
30
10
30
kΩ
µA
V
10
10
10
10
10
10
1
0.01
0.01
1
0.01
0.01
1
0.01
%
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
20
30
20
30
20
30
kΩ
µA
V
1
1
1
0.01
%
TEMPERATURE RANGE
Specified Performance
J/K Grades
A/B/C Grades
S Grade
Storage
0
+70
+85
+125
+150
0
–40
+70
+85
°C
°C
°C
°C
–40
–55
–65
–40
–65
+85
–65
+150
+150
POWER SUPPLY
Power Supply Range
Quiescent Current
6 to 18
3.5
6 to 18
3.5
6 to 18
3.5
V
mA
5
5
5
NOTES
1Gain Error and Gain TC are for the AD625 only. Resistor Network errors will add to the specified errors.
2VDL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at other gains = 10 V/G. VD = actual differential input voltage.
Example: G = 10, VD = 0.50; VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are
used to calculate outgoing quality levels.
REV. D
–3–
AD625
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 450 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (D, E) . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . . –65°C to +125°C
AD625J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD625A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD625S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
AD625AD
AD625BD
AD625BD/+
AD625CD
AD625SD
AD625SD/883B
AD625SE/883B
AD625JN
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
0°C to +70°C
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
20-Terminal Leadless Chip Carrier
16-Lead Plastic DIP
16-Lead Plastic DIP
Die
D-16
D-16
D-16
D-16
D-16
D-16
E-20A
N-16
N-16
AD625KN
0°C to +70°C
AD625ACHIPS
AD625SCHIPS
5962-87719012A*
5962-8771901EA*
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Die
20-Terminal Leadless Chip Carrier
16-Lead Ceramic DIP
E-20A
D-16
*Standard Military Drawing Available
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD625 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONNECTIONS
Leadless Chip Carrier (E) Package
Ceramic DIP (D) and Plastic DIP (N) Packages
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+INPUT
–INPUT
+GAIN SENSE
RTI NULL
–GAIN SENSE
RTO NULL
–V
S
+V
10kꢀ
10kꢀ
S
3
2
1 20 19
AD625
TOP VIEW
(Not to Scale)
RTI NULL
RTO NULL
–GAIN DRIVE
+GAIN DRIVE
18
RTO NULL
4
5
RTI NULL
RTI NULL
17 RTO NULL
NC
SENSE
AD625
TOP VIEW
16
15
14
NC
NC 6
+GAIN DRIVE 7
NC 8
REFERENCE
V
OUT
(Not to Scale)
–GAIN NULL
SENSE
–V
+V
S
S
NC = NO CONNECT
9
10 11 12 13
NC = NO CONNECT
–4–
REV. D
Typical Performance Characteristics–AD625
20
15
10
5
20
15
10
5
30
20
10
0
25ꢁC
0
0
0
5
10
15
20
0
5
10
15
20
10
100
1k
10k
SUPPLY VOLTAGE – ꢃV
SUPPLY VOLTAGE – ꢃV
LOAD RESISTANCE – ꢀ
Figure 2. Output Voltage Swing
vs. Supply Voltage
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
Figure 3. Output Voltage Swing
vs. Load Resistance
30
–160
–140
G = 1000
1000
100
10
G = 1, 100
G = 100
–120
20
G = 10
–100
BANDWIDTH
LIMITED
G = 500
G = 1
–80
–60
–40
10
G = 100
1
–20
G = 1000
0
0
1k
10k
100k
1M
0
10
100
1k
10k 100k
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 5. Large Signal Frequency
Response
Figure 4. CMRR vs. Frequency
RTI, Zero to 1 kΩ Source Imbal-
ance
Figure 6. Gain vs. Frequency
160
–1
0
160
–V = –15V dc+
S
+V = +15V dc+
S
140
120
100
80
140
120
100
80
1V p-p SINEWAVE
G = 500
G = 100
1V p-p SINEWAVE
G = 500
G = 100
1
2
G = 1
G = 1
3
60
4
60
40
5
40
20
6
20
0
7
0
10
100
1k
10k
100k
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
10
100
1k
10k
100k
FREQUENCY – Hz
WARM-UP TIME – Minutes
FREQUENCY – Hz
Figure 8. Negative PSRR vs.
Frequency
Figure 7. Offset Voltage, RTI, Turn
On Drift
Figure 9. Positive PSRR vs.
Frequency
REV. D
–5–
AD625
40
+V
30
S
20
10
V
OUT
0
AD625
10V
–10
–20
–30
–V
S
–40
–125
–75
–25
25
75
125
TEMPERATURE – ꢁC
Figure 12. Gain Overrange Recovery
Figure 10. Input Bias Current vs.
Temperature
Figure 11. Overrange and Gain
Switching Test Circuit (G = 8, G = 1)
100k
10k
1k
8.0
6.0
4.0
2.0
0
1000
100
10
1
G = 1
G = 10
G = 100, 1000
100
10
G = 1000
10k
0.1
1
10
100
1k
10k
100k
1
10
100
1k
100k
0
5
10
15
20
FREQUENCY – Hz
FREQUENCY – Hz
SUPPLY VOLTAGE – ꢃV
Figure 15. Input Current Noise
Figure 13. Quiescent Current vs.
Supply Voltage
Figure 14. RTI Noise Spectral
Density vs. Gain
+V
S
–V
S
AD625
DUT
16.2kꢀ
1ꢂF
+V
S
1ꢂF
AD712
1/2
1/2
AD712
9.09kꢀ
16.2kꢀ
1ꢂF
–V
S
G = 1, 10, 100
G = 1000
1.62Mꢀ
100ꢀ
1kꢀ
1.82kꢀ
Figure 18. Low Frequency Voltage
Noise, G = 1000 (System
Gain = 100,000)
Figure 16. Low Frequency Voltage
Noise, G = 1 (System Gain = 1000)
Figure 17. Noise Test Circuit
–6–
REV. D
AD625
–12 TO 12
–8 TO 8
G = 1
G = 1000
G = 100
G = 100
–4 TO 4
OUTPUT
STEP – V
4 TO –4
G = 1000
8 TO –8 G = 1
12 TO –12
0
10
20
30
40
50
60
70
SETTLING TIME – ꢂS
Figure 21. Large Signal Pulse
Figure 19. Large Signal Pulse
Response and Settling Time, G = 100
Response and Settling Time, G = 1
Figure 20. Settling Time to 0.01%
10kꢀ 1kꢀ 10kꢀ
1%
10T 1%
V
OUT
INPUT
20V p-p
+V
S
100kꢀ
0.1%
AD625
1kꢀ 500ꢀ 200ꢀ
0.1% 0.1% 0.1%
–V
S
Figure 23. Settling Time Test Circuit
Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000
Figure 22. Large Signal Pulse
Response and Settling Time, G = 10
REV. D
–7–
AD625
THEORY OF OPERATION
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-to-
back Zener diodes and smaller resistors, as shown in Figure
26b, provides adequate protection. Figure 26c shows low cost
FETs with a maximum ON resistance of 300 Ω configured to offer
input protection with minimal degradation to noise, (5.2 nV/√Hz
compared to normal noise performance of 4 nV/√Hz).
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (Q1–Q4) provides additional gain to A1 and
A2. Feedback from the outputs of A1 and A2 forces the collec-
tor currents of Q1–Q4 to be constant, thereby, impressing the
input voltage across RG. This creates a differential voltage at the
outputs of A1 and A2 which is given by the gain (2RF/RG + 1)
times the differential portion of the input voltage. The unity
gain subtracter, A3, removes any common-mode signal from the
output voltage yielding a single ended output, VOUT, referred to
the potential at the reference pin.
During differential overload conditions, excess current will flow
through the gain sense lines (Pins 2 and 15). This will have no
effect in fixed gain applications. However, if the AD625 is being
used in an SPGA application with a CMOS multiplexer, this
current should be taken into consideration. The current capa-
bilities of the multiplexer may be the limiting factor in allowable
overflow current. The ON resistance of the switch should be
included as part of RG when calculating the necessary input
protection resistance.
The value of RG is the determining factor of the transconduc-
tance of the input preamp stage. As RG is reduced for larger
gains the transconductance increases. This has three important
advantages. First, this approach allows the circuit to achieve a
very high open-loop gain of (3 × 108 at programmed gains ≥ 500)
thus reducing gain related errors. Second, the gain-bandwidth
product, which is determined by C3, C4, and the input trans-
conductance, increases with gain, thereby, optimizing frequency
response. Third, the input voltage noise is reduced to a value
determined by the collector current of the input transistors
(4 nV/√Hz).
+VS
FD333
FD333
1.4kꢀ
+IN
RF
RG
RF
VOUT
AD625
1.4kꢀ
–IN
FD333
FD333
–VS
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two consid-
erations when applying input protection for the AD625; 1) that
continuous input current must be limited to less than 10 mA
and 2) that input voltages must not exceed either supply by
more than one diode drop (approximately 0.6 V @ 25°C).
Figure 26a. Input Protection Circuit
+V
S
FD333
FD333
500ꢀ
+IN
R
F
Under differential overload conditions there is (RG + 100) Ω in
series with two diode drops (approximately 1.2 V) between the
plus and minus inputs, in either direction. With no external protec-
tion and RG very small (i.e., 40 Ω), the maximum overload
voltage the AD625 can withstand, continuously, is approximately
2.5 V. Figure 26a shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
1N5837A
V
OUT
R
G
AD625
1N5837A
R
F
500ꢀ
–IN
FD333
FD333
–V
S
+V
S
Figure 26b. Input Protection Circuit for G > 5
+
V
–
50ꢂA
50ꢂA
B
+V
S
FD333
A1
A2
FD333
10kꢀ
C3
C4
SENSE
+IN
2kꢀ
10kꢀ
R
R
F
2N5952
V
O
V
OUT
AD625
G
GAIN
DRIVE
GAIN
10kꢀ
50ꢀ
10kꢀ
DRIVE
REF
R
F
50ꢀ
R
R
F
F
+IN
Q1, Q3
Q2, Q4
–IN
–IN
R
G
2kꢀ
FD333
GAIN
GAIN
2N5952
SENSE SENSE
FD333
50ꢂA
50ꢂA
–V
S
–V
S
Figure 26c. Input Protection Circuit
Figure 25. Simplified Circuit of the AD625
–8–
REV. D
AD625
RTO NOISE
RTO OFFSET VOLTAGE
Any resistors in series with the inputs of the AD625 will degrade
the noise performance. For this reason the circuit in Figure 26b
should be used if the gains are all greater than 5. For gains less
than 5, either the circuit in Figure 26a or in Figure 26c can be
used. The two 1.4 kΩ resistors in Figure 26a will degrade the
noise performance to:
300
200
100
3
2
4kTRext +(4 nV/ Hz)2 = 7.9 nV/ Hz
10k 20k 30k 40k 50k 60k
10k 20k 30k 40k 50k 60k
FEEDBACK RESISTANCE – ꢀ
FEEDBACK RESISTANCE – ꢀ
RESISTOR PROGRAMMABLE GAIN AMPLIFIER
In the resistor-programmed mode (Figure 27), only three exter-
nal resistors are needed to select any gain from 1 to 10,000.
Depending on the application, discrete components or a
pretrimmed network can be used. The gain accuracy and gain
TC are primarily determined by the external resistors since the
AD625C contributes less than 0.02% to gain error and under
5 ppm/°C gain TC. The gain sense current is insensitive to
common-mode voltage, making the CMRR of the resistor pro-
grammed AD625 independent of the match of the two feedback
resistors, RF.
RTO OFFSET VOLTAGE DRIFT
6
BANDWIDTH
1M
10kꢀ
5
4
3
2
100k
10k
20kꢀ
50kꢀ
1
10k 20k 30k 40k 50k 60k
FEEDBACK RESISTANCE – ꢀ
1
10
100
1k
FEEDBACK RESISTANCE – ꢀ
Selecting Resistor Values
Figure 28. RTO Noise, Offset, Drift and Bandwidth vs.
Feedback Resistance Normalized to 20 kΩ
As previously stated each RF provides feedback to the input
stage and sets the unity gain transconductance. These feedback
resistors are provided by the user. The AD625 is tested and
specified with a value of 20 kΩ for RF. Since the magnitude of
RTO errors increases with increasing feedback resistance, values
much above 20 kΩ are not recommended (values below 10 kΩ
for RF may lead to instability). Refer to the graph of RTO noise,
offset, drift, and bandwidth (Figure 28) when selecting the
feedback resistors. The gain resistor (RG) is determined by the
formula RG = 2 RF/(G – l).
Table I. Common Gains Nominally Within ꢃ0.5% Error
Using Standard 1% Resistors
GAIN
RF
RG
1
2
5
10
20
20 kΩ
∞
19.6 kΩ
20 kΩ
39.2 kΩ
10 kΩ
4.42 kΩ
2.1 kΩ
806 Ω
402 Ω
205 Ω
78.7 Ω
39.2 Ω
13.3 kΩ
5.62 kΩ
2.67 kΩ
1.27 kΩ
634 Ω
316 Ω
154 Ω
76.8 Ω
38.3 Ω
20 kΩ
20 kΩ
19.6 kΩ
20 kΩ
2R
F
G =
+1
R
G
50
R
F
R
R
F
G
+INPUT
–INPUT
100
200
500
1000
4
8
16
32
64
128
256
512
1024
20.5 kΩ
19.6 kΩ
19.6 kΩ
20 kΩ
1
16
+GAIN
SENSE
–GAIN
SENSE
2
3
4
5
6
7
8
15
14
13
12
11
10
9
RTI NULL
+V
RTO
NULL
S
19.6 kΩ
20 kΩ
RTO
NULL
RTI NULL
A1
A2
+GAIN DRIVE
–GAIN DRIVE
19.6 kΩ
20 kΩ
NC
10kꢀ
10kꢀ
V
OUT
REF
20 kΩ
10kꢀ
10kꢀ
A3
19.6 kΩ
19.6 kΩ
19.6 kΩ
+V
S
–V
S
AD625
Figure 27. AD625 in Fixed Gain Configuration
A list of standard resistors which can be used to set some com-
mon gains is shown in Table I.
SENSE TERMINAL
The sense terminal is the feedback point for the AD625 output
amplifier. Normally it is connected directly to the output. If
heavy load currents are to be drawn through long leads, voltage
drops through lead resistance can cause errors. In these in-
stances the sense terminal can be wired to the load thus putting
For single gain applications, only one offset null adjust is neces-
sary; in these cases the RTI null should be used.
REV. D
–9–
AD625
GND V
V
DD SS
the I × R drops “inside the loop” and virtually eliminating this
error source.
Typically, IC instrumentation amplifiers are rated for a full 10
volt output swing into 2 kΩ. In some applications, however, the
need exists to drive more current into heavier loads. Figure 29
shows how a high-current booster may be connected “inside the
loop” of an instrumentation amplifier. By using an external
power boosting circuit, the power dissipated by the AD625 will
remain low, thereby, minimizing the errors induced by self-
heating. The effects of nonlinearities, offset and gain inaccura-
cies of the buffer are reduced by the loop gain of the AD625’s
output amplifier.
+IN
A
A
E
0
+V
S
1
SENSE
N
AD7502
V
AD625
OUT
REFERENCE
–V
S
–IN
+VS
V
S
V
39kꢀ
REF
VIN
+
+V
S
SENSE
X1
0.01ꢂF
AD589
1.2V
RF
R3
R
FB
R5
2kꢀ
20kꢀ
+V
RG
RF
MSB
S
AD625
DATA
INPUTS
C
1
RI
LSB
CS
OUT 1
OUT 2
AD7524
8-BIT DAC
1/2
R4
10kꢀ
1/2
VIN
–
AD712
REFERENCE
AD712
–VS
WR
5kꢀ
–V
S
Figure 29. AD625 /Instrumentation Amplifier with Output
Current Booster
Figure 30. Software Controllable Offset
REFERENCE TERMINAL
An instrumentation amplifier can be turned into a voltage-to-
current converter by taking advantage of the sense and reference
terminals as shown in Figure 31.
The reference terminal may be used to offset the output by up
to 10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. However, it must be
remembered that the total output swing is 10 volts, from
ground, to be shared between signal and reference offset.
VIN+
SENSE
RF
+VX
–
The AD625 reference terminal must be presented with nearly
zero impedance. Any significant resistance, including those
caused by PC layouts or other connection techniques, will in-
crease the gain of the noninverting signal path, thereby, upset-
ting the common-mode rejection of the in-amp. Inadvertent
thermocouple connections created in the sense and reference
lines should also be avoided as they will directly affect the out-
put offset voltage and output offset voltage drift.
RG
RF
AD625
R1
IL
VIN
–
AD711
LOAD
Figure 31. Voltage-to-Current Converter
In the AD625 a reference source resistance will unbalance the
CMR trim by the ratio of 10 kΩ/RREF. For example, if the refer-
ence source impedance is 1 Ω, CMR will be reduced to 80 dB
(10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to
provide the low impedance reference point as shown in Figure
30. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A1, the
forced current IL will largely flow through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the In-Amp.
The circuit of Figure 30 also shows a CMOS DAC operating in
the bipolar mode and connected to the reference terminal to
provide software controllable offset adjustments. The total offset
range is equal to (VREF/2 × R5/R4), however, to be symmetri-
cal about 0 V R3 = 2 × R4.
The offset per bit is equal to the total offset range divided by 2N,
where N = number of bits of the DAC. The range of offset for
Figure 30 is 120 mV, and the offset is incremented in steps of
0.9375 mV/LSB.
INPUT AND OUTPUT OFFSET VOLTAGE
Offset voltage specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but this requires extra
circuitry.
–10–
REV. D
AD625
Offset voltage and offset voltage drift each have two compo-
nents: input and output. Input offset is that component of offset
that is generated at the input stage. Measured at the output it is
directly proportional to gain, i.e., input offset as measured at the
output at G = 100 is 100 times greater than that measured at
G = 1. Output offset is generated at the output and is constant
for all gains.
in distributed stray capacitances. In many applications shielded
cables are used to minimize noise. This technique can create
+V
S
+INPUT
SENSE
R
R
F
V
OUT
100ꢀ
AD711
AD625
G
The input offset and drift are multiplied by the gain, while the
output terms are independent of gain, therefore, input errors
dominate at high gains and output errors dominate at low gains.
The output offset voltage (and drift) is normally specified at
G = 1 (where input effects are insignificant), while input offset
(and drift) is given at a high gain (where output effects are negli-
gible). All input-related parameters are specified referred to the
input (RTI) which is to say that the effect on the output is “G”
times larger. Offset voltage vs. power supply is also specified as
an RTI error.
R
F
–INPUT
REFERENCE
–V
S
Figure 32. Common-Mode Shield Driver
common-mode rejection errors unless the shield is properly
driven. Figures 32 and 33 show active data guards which are
configured to improve ac common-mode rejection by “boot-
strapping” the capacitances of the input cabling, thus minimiz-
ing differential phase shift.
By separating these errors, one can evaluate the total error inde-
pendent of the gain. For a given gain, both errors can be com-
bined to give a total error referred to the input (RTI) or output
(RTO) by the following formula:
+INPUT
+V
S
AD712
100ꢀ
100ꢀ
SENSE
R
R
F
Total Error RTI = input error + (output error/gain)
V
AD625
OUT
G
Total Error RTO = (Gain × input error) + output error
R
F
–V
S
REFERENCE
The AD625 provides for both input and output offset voltage
adjustment. This simplifies nulling in very high precision appli-
cations and minimizes offset voltage effects in switched gain
applications. In such applications the input offset is adjusted
first at the highest programmed gain, then the output offset is
adjusted at G = 1. If only a single null is desired, the input offset
null should be used. The most additional drift when using only
the input offset null is 0.9 µV/°C, RTO.
–INPUT
–V
S
Figure 33. Differential Shield Driver
GROUNDING
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have two or
more ground pins. These grounds must eventually be tied to-
gether at one point. It would be convenient to use a single
ground line, however, current through ground wires and pc runs
of the circuit card can cause hundreds of millivolts of error.
Therefore, separate ground returns should be provided to mini-
mize the current flow from the sensitive points to the system
ground (see Figure 34). Since the AD625 output voltage is
developed with respect to the potential on the reference termi-
nal, it can solve many grounding problems.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance.
In an instrumentation amplifier, degradation of common-mode
rejection is caused by a differential phase shift due to differences
STATUS
ANALOG
OUT
AD7502
AD583
SAMPLE
AND
HOLD
AD574A
INPUT
AD625
SIGNAL
A/D
CONVERTER
+VS
HOLD
CAP
–VS
VLOGIC
–VS +VS
+VS
–VS
+VS –VS
DIGITAL
COMMON
ANALOG POWER
GROUND
Figure 34. Basic Grounding Practice for a Data Acquisition System
–11–
REV. D
AD625
GROUND RETURNS FOR BIAS CURRENTS
high thermoelectric potential (about 35 µV°C). This means that
care must be taken to insure that all connections (especially
those in the input circuit of the AD625) remain isothermal. This
includes the input leads (1, 16) and the gain sense lines (2, 15).
These pins were chosen for symmetry, helping to desensitize the
input circuit to thermal gradients. In addition, the user should
also avoid air currents over the circuitry since slowly fluctuating
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. There must be a direct return path
for these currents, otherwise they will charge external capaci-
tances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying “floating” input sources such as
transformers, or ac-coupled sources, there must be a dc path
from each input to ground as shown in Figure 35.
GND VDD VSS
+VS
SENSE
RF
+VS
VOUT
RG
RF
AD625
15 16
LOAD
AD7502
REFERENCE
VOUT
10
TO POWER
SUPPLY
GROUND
AD625
9
–VS
14
+
VIN
–
0.1ꢂF LOW
LEAKAGE
13
1kꢀ
11
Figure 35a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
–VS
12
AD711
+VS
SENSE
RF
VDD
VOUT
RG
RF
AD625
VSS
AD7510DIKD
LOAD
GND
REFERENCE
200ꢂs
ZERO PULSE
TO POWER
SUPPLY
GROUND
–VS
A1
A2
A3
A4
Figure 36. Auto-Zero Circuit
Figure 35b. Ground Returns for Bias Currents with
Thermocouple Input
thermocouple voltages will appear as “flicker” noise. In SPGA
applications relay contacts and CMOS mux leads are both
potential sources of additional thermocouple errors.
+VS
The base emitter junction of an input transistor can rectify out
of band signals (i.e., RF interference). When amplifying small
signals, these rectified voltages act as small dc offset errors. The
AD625 allows direct access to the input transistors’ bases and
emitters enabling the user to apply some first order filtering to
these unwanted signals. In Figure 37, the RC time constant
should be chosen for desired attenuation of the interfering signals.
In the case of a resistive transducer, the capacitance alone work-
ing against the internal resistance of the transducer may suffice.
SENSE
RF
VOUT
RG
RF
AD625
LOAD
REFERENCE
TO POWER
SUPPLY
GROUND
–VS
100kꢀ
100kꢀ
Figure 35c. Ground Returns for Bias Currents with AC
Coupled Inputs
R
F
R
G
R
F
R
R
FILTER
CAP
FILTER
CAP
+IN
–IN
AUTOZERO CIRCUITS
In many applications it is necessary to maintain high accuracy.
At room temperature, offset effects can be nulled by the use of
offset trimpots. Over the operating temperature range, however,
offset nulling becomes a problem. For these applications the
autozero circuit of Figure 36 provides a hardware solution.
C
C
1
16
–IN
+IN
+GAIN SENSE
–GAIN SENSE
2
3
4
5
6
7
8
15
14
13
12
11
10
9
RTI NULL
+V
RTO
NULL
RTO
NULL
RTI NULL
A1
A2
OTHER CONSIDERATIONS
–GAIN DRIVE
+GAIN DRIVE
SENSE
One of the more overlooked problems in designing ultralow-
drift dc amplifiers is thermocouple induced offset. In a circuit
comprised of two dissimilar conductors (i.e., copper, kovar), a
current flows when the two junctions are at different tempera-
tures. When this circuit is broken, a voltage known as the
“Seebeck” or thermocouple emf can be measured. Standard IC
lead material (kovar) and copper form a thermocouple with a
NC
10kꢀ
10kꢀ
10kꢀ
10kꢀ
V
OUT
REF
V
OUT
A3
+V
S
–V
S
AD625
Figure 37. Circuit to Attenuate RF Interference
–12–
REV. D
AD625
These capacitances may also be incorporated as part of the
external input protection circuit (see section on Input Protec-
tion). As a general practice every effort should be made to
match the extraneous capacitance at Pins 15 and 2, and Pins 1
and 16, to preserve high ac CMR.
AD625
–INPUT
–GAIN
SENSE
20kꢀ
–GAIN
DRIVE
C
S-OUT
15.6kꢀ
3.9kꢀ
10kꢀ
R
ON
10kꢀ
10kꢀ
SOFTWARE PROGRAMMABLE GAIN AMPLIFIER
An SPGA provides the ability to externally program precision
gains from digital inputs. Historically, the problem in systems
requiring electronic switching of gains has been the ON resis-
tance (RON) of the multiplexer, which appears in series with the
gain setting resistor RG. This can result in substantial gain errors
and gain drifts. The AD625 eliminates this problem by making
the gain drive and gain sense pins available (Pins 2, 15, 5, 12;
see Figure 39). Consequently the multiplexer’s ON resistance is
removed from the signal current path. This transforms the ON
resistance error into a small nullable offset error. To clarify this
point, an error budget analysis has been performed in Table II
based on the SPGA configuration shown in Figure 39.
C
C
OUT
C
C
975kꢀ
650kꢀ
S
I
I
I
I
S
S
OUT
C
12-BIT
DAS
–
V
S
V
IN
S-OUT
+
975kꢀ
3.9kꢀ
R
ON
OUT
S
10kꢀ
+GAIN
DRIVE
OUT
15.6kꢀ
+GAIN
SENSE
20kꢀ
+INPUT
Figure 39. SPGA with Multiplexer Error Sources
Figure 39 shows a complete SPGA feeding a 12-bit DAS with a
0 V–10 V input range. This configuration was used in the error
budget analysis shown in Table II. The gain used for the RTI
calculations is set at 16. As the gain is changed, the ON resis-
tance of the multiplexer and the feedback resistance will change,
which will slightly alter the values in the table.
AD7502
TTL/DTL TO CMOS LEVEL TRANSLATOR
V
V
A0
A1
SS
DECODER/DRIVER
DD
GND
E
N
Table II. Errors Induced by Multiplexer to an SPGA
3.9kꢀ 975ꢀ 650ꢀ 975ꢀ 3.9kꢀ
Induced
Error
Specifications
AD625C AD7520KN Calculation
Voltage Offset
Induced RTI
20kꢀ
15.6kꢀ
15.6kꢀ
20kꢀ
RTI Offset Gain Sense Switch
40 nA × 170 Ω =
6.8 µV
6.8 µV
+INPUT
–INPUT
Voltage
Offset
Current
40 nA
Resistance
170 Ω
1
2
3
4
5
6
7
16
15
14
13
12
11
10
+GAIN
–GAIN
SENSE
SENSE
RTI Offset Gain Sense Differential 60 nA × 6.8 Ω =
0.41 µV
Voltage
Current
60 nA
Switch
Resistance
6.8 Ω
0.41 µV
RTI NULL
RTO NULL
–V
+V
S
S
RTI NULL
RTO NULL
A1
A2
RTO Offset Feedback Differential 2 (0.2 nA × 20 kΩ) 0.5 µV
Voltage Resistance Leakage = 8 µV/16
Current (IS)2
+GAIN DRIVE
–GAIN DRIVE
NC
20 kΩ1
10kꢀ
10kꢀ
V
OUT
REF
+0.2 nA
10kꢀ
10kꢀ
A3
–0.2 nA
+V
S
8
9
–V
S
AD625
RTO Offset Feedback Differential 2 (1 nA × 20 kΩ)
Voltage Resistance Leakage = 40 µV/16
20 kΩ1
Current
2.5 µV
Figure 38. SPGA in a Gain of 16
2
(IOUT
)
Figure 38 shows an AD625 based SPGA with possible gains of
1, 4, 16, 64. RG equals the resistance between the gain sense
lines (Pins 2 and 15) of the AD625. In Figure 38, RG equals
the sum of the two 975 Ω resistors and the 650 Ω resistor, or
2600 Ω. RF equals the resistance between the gain sense and the
gain drive pins (Pins 12 and 15, or Pins 2 and 5), that is RF
equals the 15.6 kΩ resistor plus the 3.9 kΩ resistor, or 19.5 kΩ.
The gain, therefore equals:
+1 nA
–1 nA
Total error induced by a typical CMOS multiplexer
to an SPGA at +25°C
10.21 ꢂA
NOTES
1The resistor for this calculation is the user-provided feedback resistance (RF).
20 kΩ is recommended value (see Resistor Programmable Gain Amplifier section).
2The leakage currents (IS and IOUT) will induce an offset voltage, however, the offset
will be determined by the difference between the leakages of each “half’’ of the
differential multiplexer. The differential leakage current is multiplied by the
feedback resistance (see Note 1), to determine offset voltage. Because differential
leakage current is not a parameter specified on multiplexer data sheets, the most
extreme difference (one most positive and one most negative) was used for the
calculations in Table II. Typical performance will be much better.
2RF
2(19.5kΩ)
(2.6kΩ)
+1=
+1=16
RG
As the switches of the differential multiplexer proceed synchro-
nously, RG and RF change, resulting in the various programmed
gain settings.
**The frequency response and settling will be affected by the ON resistance and
internal capacitance of the multiplexer. Figure 40 shows the settling time vs.
ON resistance at different gain settings for an AD625 based SPGA.
**Switch resistance and leakage current errors can be reduced by using relays.
REV. D
–13–
AD625
1000
3) Begin all calculations with G0 = 1 and RF0 = 0.
RF1 = (20 kΩ – RF0) (1–1/4): RF0 = 0 ∴ RF1 = 15 kΩ
RF2 = [20 kΩ – (RF0 + RF1)] (1–4/16):
800
400
200
R
= 1kꢀ
ON
RF0 + RF1 = 15 kΩ ∴ RF2 = 3.75 kΩ
100
80
R
= 500ꢀ
ON
RF3 = [20 kΩ – (RF0 + RF1 + RF2)] (1–16/64):
RF0 + RF1 + RF2 = 18.75 kΩ ∴ RF3 = 937.5 Ω
40
20
R
= 200ꢀ
ON
4) The center resistor (RG of the highest gain setting), is deter-
mined last. Its value is the remaining resistance of the 40 kΩ
string, and can be calculated with the equation:
10
8
R
= 0ꢀ
ON
4
2
1
M
RG = (40 kΩ – 2 RF
)
∑
j
1
4
16
64
GAIN
256
1024
4096
j = 0
RG = 40 kΩ – 2 (RF + RF + RF RF )
3
+
0
1
2
40 kΩ – 39.375 kΩ = 625 Ω
Figure 40. Time to 0.01% of a 20 V Step Input for
SPGA with AD625
5) If different resistor values are desired, all the resistors in the
network can be scaled by some convenient factor. However,
raising the impedance will increase the RTO errors, lowering
the total network resistance below 20 kΩ can result in ampli-
fier instability. More information on this phenomenon is
given in the RPGA section of the data sheet. The scale factor
will not affect the unity gain feedback resistors. The resistor
network in Figure 38 has a scaling factor of 650/625 = 1.04,
if this factor is used on RF1, RF2, RF3, and RG, then the resis-
tor values will match exactly.
DETERMINING SPGA RESISTOR NETWORK VALUES
The individual resistors in the gain network can be calculated
sequentially using the formula given below. The equation deter-
mines the resistors as labeled in Figure 41. The feedback resis-
tors and the gain setting resistors are interactive, therefore; the
formula must be a series where the present term is dependent on
the preceding term(s). The formula
1
Gi
G0 = 1
RF
= (20 kΩ –
RFj ) (1 –
)
∑
i +1
6) Round off errors can be cumulative, therefore, it is advised to
carry as many significant digits as possible until all the values
have been calculated.
RF = 0
0
Gi =1
j = 0
can be used to calculate the necessary feedback resistors for any
set of gains. This formula yields a network with a total resistance
of 40 kΩ. A dummy variable (j) serves as a counter to keep a
running total of the preceding feedback resistors. To illustrate
how the formula can be applied, an example similar to the
calculation used for the resistor network in Figure 38 is exam-
ined below.
AD75xx
TO GAIN SENSE
(PIN 2)
TO GAIN SENSE
(PIN 15)
RF
2
RF
N
RF
G
RF
N
RF
2
20kꢀ
RF
20kꢀ
1
1) Unity gain is treated as a separate case. It is implemented
with separate 20 kΩ feedback resistors as shown in Figure 41.
It is then ignored in further calculations.
CONNECT IF UNITY
GAIN IS DESIRED
CONNECT IF UNITY
GAIN IS DESIRED
TO GAIN DRIVE
(PIN 5)
TO GAIN DRIVE
(PIN 12)
2) Before making any calculations it is advised to draw a resistor
network similar to the network in Figure 41. The network
will have (2 × M) + 1 resistors, where M = number of gains.
For Figure 38 M = 3 (4, 16, 64), therefore, the resistor string
will have seven resistors (plus the two 20 kΩ “side” resistors
for unity gain).
Figure 41. Resistors for a Gain Setting Network
–14–
REV. D
AD625
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Ceramic DIP (D-16)
16-Lead Plastic DIP (N-16)
0.430
(10.922)
0.755 (19.18)
0.745 (18.93)
16
9
0.040R
0.310 ꢃ0.01
7.874 ꢃ0.254)
16
9
0.26 (6.61)
0.24 (6.1)
0.290 ꢃ0.010
(7.37 ꢃ0.254)
0.265
(6.73)
1
8
1
8
0.306 (7.78)
0.294 (7.47)
PIN 1
0.17 (4.32)
MAX
0.175 (4.45)
0.12 (3.05)
PIN 1
0.800 ꢃ0.010
0.300
(7.62)
REF
0.14 (3.56)
0.12 (3.05)
20.32 ꢃ0.254
0.035 ꢃ0.01
(0.889 ꢃ0.254)
SEATING
PLANE
0.095 (2.41)
0.085 (2.159)
0.012 (0.305)
0.008 (0.203)
0.180 ꢃ0.03
(4.57 ꢃ0.762)
0.02 (0.508)
0.015 (0.381)
0.015 (2.67) 0.065 (1.66)
0.095 (2.42) 0.045 (1.15)
0.125 (3.175)
MIN
0.047 ꢃ0.007
(1.19 ꢃ0.18)
0.010 ꢃ0.002
(0.254 ꢃ0.05)
SEATING
PLANE
+0.003
0.017
–0.002
+0.076
–0.05
0.43
0.100 (254)
BSC
0.700 (17.78) BSC
20-Terminal Leadless Chip Carrier (E-20A)
0.350 ꢃ0.008
(8.89 ꢃ0.20)
0.082 ꢃ0.018
(2.085 ꢃ0.455)
SQ
0.20 ꢅ 45°
(0.51 ꢅ 45°)
REF
3
4
19
18
20
0.025 ꢃ0.003
(0.635 ꢃ0.075)
1
BOTTOM
VIEW
0.050
(1.27)
8
9
14
13
0.040 ꢅ 45°
(1.02 ꢅ 45°)
REF 3 PLCS
REV. D
–15–
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