5962-8982501PA [ADI]
IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, CDIP8, CERDIP-8, Voltage Reference;
| 型号： | 5962-8982501PA |
| 厂家： | 
ADI |
| 描述： | IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, CDIP8, CERDIP-8, Voltage Reference CD 输出元件 |
| 文件： | 总12页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Precision
10 V Reference
AD587
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Laser Trimmed to High Accuracy:
10.000 V ꢀ 5 mV (L and U Grades)
Trimmed Temperature Coefficient:
5 ppm/ꢁC Max (L and U Grades)
Noise Reduction Capability
NOISE
REDUCTION
+V
IN
2
8
R
S
Low Quiescent Current: 4 mA Max
Output Trim Capability
MIL-STD-883 Compliant Versions Available
A1
V
OUT
6
5
R
F
R
T
TRIM
R
I
AD587
4
GND
NOTE
PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.
NO CONNECTIONS TO THESE POINTS.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD587 represents a major advance in state-of-the-art
monolithic voltage references. Using a proprietary ion-implanted
buried Zener diode and laser wafer trimming of high stability
thin-film resistors, the AD587 provides outstanding performance
at low cost.
1. Laser trimming of both initial accuracy and temperature
coefficients results in very low errors over temperature without
the use of external components. The AD587L has a maximum
deviation from 10.000 V of ±8.5 mV between 0∞C and 70∞C,
and the AD587U guarantees ±14 mV maximum total error
between –55∞C and +125∞C.
2. For applications requiring higher precision, an optional fine
trim connection is provided.
3. Any system using an industry-standard pinout 10 V reference
can be upgraded instantly with the AD587.
4. Output noise of the AD587 is very low, typically 4 mV p-p.
A noise reduction pin is provided for additional noise filtering
using an external capacitor.
5. The AD587 is available in versions compliant with
MIL-STD-883. Refer to the Analog Devices Military Products
Databook or the current AD587/883B Data Sheet for detailed
specifications.
The AD587 offers much higher performance than most other
10 V references. Because the AD587 uses an industry-standard
pinout, many systems can be upgraded instantly with the AD587.
The buried Zener approach to reference design provides lower
noise and drift than band gap voltage references. The AD587
offers a noise reduction pin that can be used to further reduce
the noise level generated by the buried Zener.
The AD587 is recommended for use as a reference for 8-, 10-, 12-,
14-, or 16-bit DACs that require an external precision reference.
The device is also ideal for successive approximation or integrat-
ing ADCs with up to 14 bits of accuracy and, in general, can
offer better performance than the standard on-chip references.
The AD587J, AD587K, and AD587L are specified for operation
from 0∞C to 70∞C, and the AD587U is specified for –55∞C to
+125∞C operation. All grades are available in 8-lead CERDIP.
The J and K versions are also available in an 8-lead SOIC package
for surface-mount applications, while the J, K, and L grades also
come in an 8-lead PDIP.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(T = 25ꢁC, V = 15 V, unless otherwise noted.)
AD587–SPECIFICATIONS
A
IN
AD587J
Typ
AD587K
Typ
AD587L/AD587U
Parameter
Min
Max
Min
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
9.990
10.010 9.995
10.005 9.995
10.005
V
OUTPUT VOLTAGE DRIFT1
0∞C to 70∞C
–55∞C to +125∞C
20
20
10
10
5
5
ppm/∞C
GAIN ADJUSTMENT
+3
–1
+3
–1
+3
–1
%
LINE REGULATION1
13.5 V £ +VIN £ 36 V
TMIN to TMAX
±100
±100
±100
±100
±100
±100
mV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
TMIN to TMAX
mV/mA
Sourcing –10 mA < IOUT < 0 mA2
TMIN to TMAX
±100
±100
±100
QUIESCENT CURRENT
POWER DISSIPATION
2
4
2
4
2
4
mA
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
Spectral Density, 100 Hz
4
100
4
100
4
100
mV p-p
nV/÷Hz
LONG-TERM STABILITY
±15
±15
±15
ppm/1000 Hr.
SHORT-CIRCUIT
CURRENT-TO-GROUND
30
70
70
30
70
70
30
70
70
mA
mA
∞C
SHORT-CIRCUIT
CURRENT-TO-VIN
30
30
30
TEMPERATURE RANGE
Specified Performance (J, K, L)
0
+70
+85
+125
+125
0
+70
+85
+125
+125
0
+70
+85
+125
+125
Operating Performance (J, K, L)3 –40
–40
–55
–55
–40
–55
–55
Specified Performance (U)
–55
–55
Operating Performance (U)3
NOTES
1Specification is guaranteed for all packages and grades. CERDIP packaged parts are 100% production tested.
2Load regulation (sinking) specification for SOIC (R) package is ±200 mV/mA.
3The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance
outside their specified temperature range.
Specifications subject to change without notice.
ORDERING GUIDE
Initial
Error
Temperature
Coefficient
Temperature
Range
Package
Option*
Model
AD587JQ
AD587JR
AD587JR-REEL
AD587JR-REEL7 10 mV
AD587JN
AD587KQ
AD587KR
AD587KR-REEL
10 mV
10 mV
10 mV
20 ppm/∞C
20 ppm/∞C
20 ppm/∞C
20 ppm/∞C
20 ppm/∞C
10 ppm/∞C
10 ppm/∞C
10 ppm/∞C
10 ppm/∞C
10 ppm/∞C
5 ppm/∞C
5 ppm/∞C
5 ppm/∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
0∞C to 70∞C
–55∞C to +125∞C
Q-8
R-8
R-8
R-8
N-8
Q-8
R-8
R-8
R-8
N-8
Q-8
N-8
Q-8
10 mV
5 mV
5 mV
5 mV
AD587KR-REEL7 5 mV
AD587KN
AD587LQ
AD587LN
AD587UQ
5 mV
5 mV
5 mV
5 mV
*N = PDIP; Q = CERDIP; R = SOIC.
–2–
REV. E
AD587
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
+VIN to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Power Dissipation (25∞C) . . . . . . . . . . . . . . . . . . . . . 500 mW
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300∞C
Package Thermal Resistance
NOISE
*
1
2
3
4
8
7
6
5
TP
+V
REDUCTION
*
TP
IN
AD587
TOP VIEW
(Not to Scale)
*
V
OUT
TP
GND
TRIM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22∞C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110∞C/W
JC
JA
*
TP DENOTES FACTORYTEST POINT.
NO CONNECTIONS SHOULD BE MADE
TOTHESE PINS.
Output Protection: Output safe for indefinite short to ground
and momentary short to +VIN.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD587 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
AD587
THEORY OF OPERATION
NOISE PERFORMANCE AND REDUCTION
The AD587 consists of a proprietary buried Zener diode refer-
ence, an amplifier to buffer the output, and several high stability
thin-film resistors as shown in the block diagram in Figure 1.
This design results in a high precision monolithic 10 V output
reference with initial offset of 5 mV or less. The temperature
compensation circuitry provides the device with a temperature
coefficient of under 5 ppm/∞C.
The noise generated by the AD587 is typically less than 4 mV p-p
over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is
approximately 200 mV p-p. The dominant source of this noise is
the buried Zener, which contributes approximately 100 nV/÷Hz.
In comparison, the op amp’s contribution is negligible. Figure 3
shows the 0.1 Hz to 10 Hz noise of a typical AD587. The noise
measurement is made with a band-pass filter made of a 1-pole
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
low-pass filter with a corner frequency at 12.6 Hz to create a
filter with a 9.922 Hz bandwidth.
NOISE
REDUCTION
+V
IN
2
8
R
S
A1
V
OUT
6
5
R
F
R
T
TRIM
R
I
AD587
4
GND
NOTE
PINS 1, 3 AND 7 ARE INTERNALTEST POINTS.
NO CONNECTIONSTOTHESE POINTS.
Figure 1. Functional Block Diagram
Figure 3. 0.1 Hz to 10 Hz Noise
A capacitor can be added at the NOISE REDUCTION pin
(Pin 8) to form a low-pass filter with RS to reduce the noise
contribution of the Zener to the circuit.
If further noise reduction is desired, an external capacitor may
be added between the NOISE REDUCTION pin and ground, as
shown in Figure 2. This capacitor, combined with the 4 kW RS
and the Zener resistances, forms a low-pass filter on the output of
the Zener cell. A 1 mF capacitor will have a 3 dB point at 40 Hz,
and will reduce the high frequency (to 1 MHz) noise to about
160 mV p-p. Figure 4 shows the 1 MHz noise of a typical AD587
both with and without a 1 mF capacitor.
APPLYING THE AD587
The AD587 is simple to use in virtually all precision reference
applications. When power is applied to Pin 2, and Pin 4 is
grounded, Pin 6 provides a 10 V output. No external components
are required; the degree of desired absolute accuracy is achieved
simply by selecting the required device grade. The AD587 requires
less than 4 mA quiescent current from an operating supply of 15 V.
Fine trimming may be desired to set the output level to exactly
10.000 V (calibrated to a main system reference). System calibra-
tion may also require a reference voltage that is slightly different
from 10.000 V, for example, 10.24 V for binary applications. In
either case, the optional trim circuit shown in Figure 2 can offset
the output by as much as 300 mV with minimal effect on other
device characteristics.
+V
IN
2
V
IN
OPTIONAL
NOISE
REDUCTION
CAPACITOR
NOISE
REDUCTION
Figure 4. Effect of 1 mF Noise Reduction Capacitor
V
8
6
5
OUTPUT
O
on Broadband Noise
AD587
C
1ꢃF
N
10kꢂ
TRIM
TURN-ON TIME
GND
4
Upon application of power (cold start), the time required for the
output voltage to reach its final value within a specified error
band is defined as the turn-on settling time. Two components
normally associated with this are the time for the active circuits
to settle, and the time for the thermal gradients on the chip to
stabilize. Figure 5 shows the turn-on characteristics of the AD587.
It shows the settling to be about 60 ms to 0.01%. Note the absence
of any thermal tails when the horizontal scale is expanded to
1 ms/cm in Figure 5b.
Figure 2. Optional Fine Trim Configuration
–4–
REV. E
AD587
Output turn-on time is modified when an external noise reduc-
tion capacitor is used. When present, this capacitor acts as an
additional load to the internal Zener diode’s current source,
resulting in a somewhat longer turn-on time. In the case of a
1 mF capacitor, the initial turn-on time is approximately 400 ms
to 0.01% (see Figure 5c).
DYNAMIC PERFORMANCE
The output buffer amplifier is designed to provide the AD587
with static and dynamic load regulation superior to less complete
references.
Many ADCs and DACs present transient current loads to the
reference, and poor reference response can degrade the converter’s
performance.
Figures 6b and 6c display the characteristics of the AD587 output
amplifier driving a 0 mA to 10 mA load.
V
OUT
7.0V
1kW
10V
0V
V
L
AD587
a. Electrical Turn-On
Figure 6a. Transient Load Test Circuit
b. Extended Time Scale
Figure 6b. Large-Scale Transient Response
c. Turn-On with 1 mF CN
Figure 5. Turn-On Characteristics
Figure 6c. Fine Scale Setting for Transient Load
REV. E
–5–
AD587
In some applications, a varying load may be both resistive and
capacitive in nature, or the load may be connected to the AD587
by a long capacitive cable.
TEMPERATURE PERFORMANCE
The AD587 is designed for precision reference applications
where temperature performance is critical. Extensive temperature
testing ensures that the device’s high level of performance is
maintained over the operating temperature range.
Figure 7b displays the output amplifier characteristics driving a
1000 pF, 0 mA to 10 mA load.
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references
have been characterized using a maximum deviation per degree
Celsius; i.e., ppm/∞C. However, because of nonlinearities in
temperature characteristics that originated in standard Zener
references (such as “S” type characteristics), most manufacturers
have begun to use a maximum limit error band approach to
specify devices. This technique involves the measurement of the
output at three or more different temperatures to specify an
output voltage error band.
V
OUT
C
L
7.0V
1000pF
1kW
10V
0V
V
L
AD587
Figure 9 shows the typical output voltage drift for the AD587L
and illustrates the test methodology. The box in Figure 9 is
bounded on the sides by the operating temperature extremes and
on the top and the bottom by the maximum and minimum output
voltages measured over the operating temperature range. The
slope of the diagonal drawn from the lower left to the upper right
corner of the box determines the performance grade of the device.
Figure 7a. Capacitive Load Transient /Response
Test Circuit
SLOPE = T.C. =
T
T
V
– V
MAX
MIN
MAX
MIN
) ꢅ 10 ꢅ 10
MIN
6
(T
– T
MAX
10.100
V
MAX
V
MIN
10.000
Figure 7b. Output Response with Capacitive Load
LOAD REGULATION
–20
0
20
40
60
80
The AD587 has excellent load regulation characteristics. Figure 8
shows that varying the load several mA changes the output by
only a few mV.
TEMPERATURE – ꢁC
Figure 9. Typical AD587L Temperature Drift
Each AD587J, AD587K, and AD587L grade unit is tested at 0∞C,
25∞C, and 70∞C. Each AD587U grade unit is tested at –55∞C,
+25∞C, and +125∞C. This approach ensures that the variations
of output voltage that occur as the temperature changes within
the specified range will be contained within a box whose diagonal
has a slope equal to the maximum specified drift. The position
of the box on the vertical scale will change from device to device
as initial error and the shape of the curve vary. The maximum
height of the box for the appropriate temperature range and
device grade is shown in Figure 10. Duplication of these results
requires a combination of high accuracy and stable temperature
control in a test system. Evaluation of the AD587 will produce
a curve similar to that in Figure 9, but output readings may vary
depending on the test methods and equipment utilized.
ꢄV
(ꢃV)
OUT
1000
500
2
4
6
8
10 LOAD (mA)
–6
–4
–2
0
–500
–1000
Figure 8. Typical Load Regulation Characteristics
Figure 10. Maximum Output Change in mV
–6–
REV. E
AD587
NEGATIVE REFERENCE VOLTAGE FROM AN AD587
The AD587 can be used to provide a precision –10.000 V output
as shown in Figure 11. The +VIN pin is tied to at least a +3.5 V
supply, the output pin is grounded, and the AD587 ground pin is
connected through a resistor, RS, to a –15 V supply. The –10 V
output is now taken from the ground pin (Pin 4) instead of
VOUT. It is essential to arrange the output load and the supply
resistor RS so that the net current through the AD587 is between
2.5 mA and 10.0 mA. The temperature characteristics and long-
term stability of the device will be essentially the same as that of
a unit used in the standard +10 V output configuration.
The AD587 can also be used as a precision reference for multi-
ple DACs. Figure 13 shows the AD587, the AD7628 dual DAC,
and the AD712 dual op amp hooked up for single-supply opera-
tion to produce 0 V to –10 V outputs. Because both DACs are
on the same die and share a common reference and output
op amps, the DAC outputs will exhibit similar gain TCs.
+15V
+15V
0.1F
V
IN
RFB A
V
REFA
OUT A
V
OUT
DAC A
3.5V →26V
V
A =
OUT
0TO –10V
AD587
GND
AGND
RFB B
DB0
DB7
DATA
INPUTS
AD7628
AD712
2
V
IN
OUT B
18
V
V
OUT
6
DAC B
DGND
REFB
V
B =
OUT
0TO –10V
AD587
GND
4
←I
L
–10V
Figure 13. AD587 as a 10 V Reference for a CMOS Dual DAC
1nF
R
S
Precision Current Source
5V
2.5mA <
– I < 10mA
L
R
The design of the AD587 allows it to be easily configured as a
current source. By choosing the control resistor RC in Figure 14,
the user can vary the load current from the quiescent current
(2 mA typically) to approximately 10 mA.
–15V
S
Figure 11. AD587 as a Negative 10 V Reference
USING THE AD587 WITH CONVERTERS
The AD587 is an ideal reference for a wide variety of 8-, 12-,
14-, and 16-bit ADCs and DACs. Several representative examples
follow.
+V
IN
2
V
IN
10 V Reference with Multiplying CMOS DACs or ADCs
The AD587 is ideal for applications with 10-bit and 12-bit
multiplying CMOS DACs. In the standard hookup, as shown in
Figure 12, the AD587 is paired with the AD7545 12-bit multi-
plying DAC and the AD711 high speed BiFET op amp. The
amplifier DAC configuration produces a unipolar 0 V to –10 V
output range. Bipolar output applications and other operating
details can be found in the individual product data sheets.
10V
V
6
I
=
L
+ I
BIAS
OUT
R
C
R
500⍀
MIN
C
AD587
GND
4
Figure 14. Precision Current Source
+15V
R2
+15V
0.1F
10k⍀
+15V
0.1F
C1
33pF
V
IN
R
V
FB
DD
AD587
OUT1
V
V
V
OUT
REF
OUT
AD711K
0.1F
0TO
–
10V
AGND
TRIM
GND
AD7545K
DGND
DB11–DB0
–15V
Figure 12. Low Power 12-Bit CMOS DAC Application
REV. E
–7–
AD587
+V
Precision High Current Supply
IN
For higher currents, the AD587 can easily be connected to a power
PNP or power Darlington PNP device. The circuits in Figure 15a
and 15b can deliver up to 4 A to the load. The 0.1 mF capacitor
is required only if the load has a significant capacitive component.
If the load is purely resistive, improved high frequency supply
rejection results can be obtained by removing the capacitor.
220ꢂ
2N6285
0.1ꢃF
+V
IN
2
220ꢂ
+V
S
2N6285
V
OUT
V
6
OUT
AD587
+10V @ 4 AMPS
4
0.1ꢃF
2
Figure 15b. Precision High Current Voltage Source
+V
S
10V
+ I
BIAS
V
6
I
=
OUT
L
AD587
R
C
R
C
4
Figure 15a. Precision High Current Current Source
–8–
REV. E
AD587
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.005 (0.13) 0.055 (1.40)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
MIN
MAX
8
5
8
1
5
0.310 (7.87)
0.220 (5.59)
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
PIN 1
1
4
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54) BSC
0.405 (10.29) MAX
0.100 (2.54)
BSC
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.060 (1.52)
0.015 (0.38)
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.200 (5.08)
MAX
0.150 (3.81)
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
15
0
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢅ 45ꢁ
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8ꢁ
0.51 (0.0201)
0.31 (0.0122)
0ꢁ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. E
–9–
AD587
Revision History
Location
Page
7/03—Data Sheet changed from REV. D to REV. E.
Deletion of S and T grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Deletion of DIE SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
–10–
REV. E
–11–
–12–
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